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tcg-ia64: Move AREG0 to R32
[qemu.git] / tcg / ia64 / tcg-target.c
CommitLineData
477ba620
AJ		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2009-2010 Aurelien Jarno <[email protected]>
5 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
3cf246f0
RH		 26#include "tcg-be-null.h"
27
477ba620
AJ		 28/*
29 * Register definitions
30 */
31
32#ifndef NDEBUG
33static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
34 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
35 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
36 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
37 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
38 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
39 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
40 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
41 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
42};
43#endif
44
6781d08d
RH		 45#ifdef CONFIG_USE_GUEST_BASE
46#define TCG_GUEST_BASE_REG TCG_REG_R55
47#else
48#define TCG_GUEST_BASE_REG TCG_REG_R0
49#endif
255108c0
RH		 50#ifndef GUEST_BASE
51#define GUEST_BASE 0
52#endif
6781d08d 53
477ba620
AJ		 54/* Branch registers */
55enum {
56 TCG_REG_B0 = 0,
57 TCG_REG_B1,
58 TCG_REG_B2,
59 TCG_REG_B3,
60 TCG_REG_B4,
61 TCG_REG_B5,
62 TCG_REG_B6,
63 TCG_REG_B7,
64};
65
66/* Floating point registers */
67enum {
68 TCG_REG_F0 = 0,
69 TCG_REG_F1,
70 TCG_REG_F2,
71 TCG_REG_F3,
72 TCG_REG_F4,
73 TCG_REG_F5,
74 TCG_REG_F6,
75 TCG_REG_F7,
76 TCG_REG_F8,
77 TCG_REG_F9,
78 TCG_REG_F10,
79 TCG_REG_F11,
80 TCG_REG_F12,
81 TCG_REG_F13,
82 TCG_REG_F14,
83 TCG_REG_F15,
84};
85
86/* Predicate registers */
87enum {
88 TCG_REG_P0 = 0,
89 TCG_REG_P1,
90 TCG_REG_P2,
91 TCG_REG_P3,
92 TCG_REG_P4,
93 TCG_REG_P5,
94 TCG_REG_P6,
95 TCG_REG_P7,
96 TCG_REG_P8,
97 TCG_REG_P9,
98 TCG_REG_P10,
99 TCG_REG_P11,
100 TCG_REG_P12,
101 TCG_REG_P13,
102 TCG_REG_P14,
103 TCG_REG_P15,
104};
105
106/* Application registers */
107enum {
108 TCG_REG_PFS = 64,
109};
110
111static const int tcg_target_reg_alloc_order[] = {
477ba620
AJ		 112 TCG_REG_R35,
113 TCG_REG_R36,
114 TCG_REG_R37,
115 TCG_REG_R38,
116 TCG_REG_R39,
117 TCG_REG_R40,
118 TCG_REG_R41,
119 TCG_REG_R42,
120 TCG_REG_R43,
121 TCG_REG_R44,
122 TCG_REG_R45,
123 TCG_REG_R46,
124 TCG_REG_R47,
125 TCG_REG_R48,
126 TCG_REG_R49,
127 TCG_REG_R50,
128 TCG_REG_R51,
129 TCG_REG_R52,
130 TCG_REG_R53,
131 TCG_REG_R54,
132 TCG_REG_R55,
133 TCG_REG_R14,
134 TCG_REG_R15,
135 TCG_REG_R16,
136 TCG_REG_R17,
137 TCG_REG_R18,
138 TCG_REG_R19,
139 TCG_REG_R20,
140 TCG_REG_R21,
141 TCG_REG_R22,
142 TCG_REG_R23,
143 TCG_REG_R24,
144 TCG_REG_R25,
145 TCG_REG_R26,
146 TCG_REG_R27,
147 TCG_REG_R28,
148 TCG_REG_R29,
149 TCG_REG_R30,
150 TCG_REG_R31,
151 TCG_REG_R56,
152 TCG_REG_R57,
153 TCG_REG_R58,
154 TCG_REG_R59,
155 TCG_REG_R60,
156 TCG_REG_R61,
157 TCG_REG_R62,
158 TCG_REG_R63,
159 TCG_REG_R8,
160 TCG_REG_R9,
161 TCG_REG_R10,
162 TCG_REG_R11
163};
164
165static const int tcg_target_call_iarg_regs[8] = {
166 TCG_REG_R56,
167 TCG_REG_R57,
168 TCG_REG_R58,
169 TCG_REG_R59,
170 TCG_REG_R60,
171 TCG_REG_R61,
172 TCG_REG_R62,
173 TCG_REG_R63,
174};
175
af15a623
SW		 176static const int tcg_target_call_oarg_regs[] = {
177 TCG_REG_R8
477ba620
AJ		 178};
179
477ba620
AJ		 180/*
181 * opcode formation
182 */
183
184/* bundle templates: stops (double bar in the IA64 manual) are marked with
185 an uppercase letter. */
186enum {
187 mii = 0x00,
188 miI = 0x01,
189 mIi = 0x02,
190 mII = 0x03,
191 mlx = 0x04,
192 mLX = 0x05,
193 mmi = 0x08,
194 mmI = 0x09,
195 Mmi = 0x0a,
196 MmI = 0x0b,
197 mfi = 0x0c,
198 mfI = 0x0d,
199 mmf = 0x0e,
200 mmF = 0x0f,
201 mib = 0x10,
202 miB = 0x11,
203 mbb = 0x12,
204 mbB = 0x13,
205 bbb = 0x16,
206 bbB = 0x17,
207 mmb = 0x18,
208 mmB = 0x19,
209 mfb = 0x1c,
210 mfB = 0x1d,
211};
212
213enum {
214 OPC_ADD_A1 = 0x10000000000ull,
215 OPC_AND_A1 = 0x10060000000ull,
216 OPC_AND_A3 = 0x10160000000ull,
217 OPC_ANDCM_A1 = 0x10068000000ull,
218 OPC_ANDCM_A3 = 0x10168000000ull,
219 OPC_ADDS_A4 = 0x10800000000ull,
220 OPC_ADDL_A5 = 0x12000000000ull,
221 OPC_ALLOC_M34 = 0x02c00000000ull,
222 OPC_BR_DPTK_FEW_B1 = 0x08400000000ull,
223 OPC_BR_SPTK_MANY_B1 = 0x08000001000ull,
224 OPC_BR_SPTK_MANY_B4 = 0x00100001000ull,
225 OPC_BR_CALL_SPTK_MANY_B5 = 0x02100001000ull,
226 OPC_BR_RET_SPTK_MANY_B4 = 0x00108001100ull,
227 OPC_BRL_SPTK_MANY_X3 = 0x18000001000ull,
6f65c780 228 OPC_BRL_CALL_SPTK_MANY_X4 = 0x1a000001000ull,
477ba620
AJ		 229 OPC_CMP_LT_A6 = 0x18000000000ull,
230 OPC_CMP_LTU_A6 = 0x1a000000000ull,
231 OPC_CMP_EQ_A6 = 0x1c000000000ull,
232 OPC_CMP4_LT_A6 = 0x18400000000ull,
233 OPC_CMP4_LTU_A6 = 0x1a400000000ull,
234 OPC_CMP4_EQ_A6 = 0x1c400000000ull,
63975ea7 235 OPC_DEP_I14 = 0x0ae00000000ull,
c7d4475a 236 OPC_DEP_I15 = 0x08000000000ull,
477ba620
AJ		 237 OPC_DEP_Z_I12 = 0x0a600000000ull,
238 OPC_EXTR_I11 = 0x0a400002000ull,
239 OPC_EXTR_U_I11 = 0x0a400000000ull,
240 OPC_FCVT_FX_TRUNC_S1_F10 = 0x004d0000000ull,
241 OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull,
242 OPC_FCVT_XF_F11 = 0x000e0000000ull,
243 OPC_FMA_S1_F1 = 0x10400000000ull,
244 OPC_FNMA_S1_F1 = 0x18400000000ull,
245 OPC_FRCPA_S1_F6 = 0x00600000000ull,
246 OPC_GETF_SIG_M19 = 0x08708000000ull,
247 OPC_LD1_M1 = 0x08000000000ull,
248 OPC_LD1_M3 = 0x0a000000000ull,
249 OPC_LD2_M1 = 0x08040000000ull,
250 OPC_LD2_M3 = 0x0a040000000ull,
251 OPC_LD4_M1 = 0x08080000000ull,
252 OPC_LD4_M3 = 0x0a080000000ull,
253 OPC_LD8_M1 = 0x080c0000000ull,
254 OPC_LD8_M3 = 0x0a0c0000000ull,
255 OPC_MUX1_I3 = 0x0eca0000000ull,
256 OPC_NOP_B9 = 0x04008000000ull,
257 OPC_NOP_F16 = 0x00008000000ull,
258 OPC_NOP_I18 = 0x00008000000ull,
259 OPC_NOP_M48 = 0x00008000000ull,
260 OPC_MOV_I21 = 0x00e00100000ull,
261 OPC_MOV_RET_I21 = 0x00e00500000ull,
262 OPC_MOV_I22 = 0x00188000000ull,
263 OPC_MOV_I_I26 = 0x00150000000ull,
264 OPC_MOVL_X2 = 0x0c000000000ull,
265 OPC_OR_A1 = 0x10070000000ull,
266 OPC_SETF_EXP_M18 = 0x0c748000000ull,
267 OPC_SETF_SIG_M18 = 0x0c708000000ull,
268 OPC_SHL_I7 = 0x0f240000000ull,
269 OPC_SHR_I5 = 0x0f220000000ull,
270 OPC_SHR_U_I5 = 0x0f200000000ull,
271 OPC_SHRP_I10 = 0x0ac00000000ull,
272 OPC_SXT1_I29 = 0x000a0000000ull,
273 OPC_SXT2_I29 = 0x000a8000000ull,
274 OPC_SXT4_I29 = 0x000b0000000ull,
275 OPC_ST1_M4 = 0x08c00000000ull,
276 OPC_ST2_M4 = 0x08c40000000ull,
277 OPC_ST4_M4 = 0x08c80000000ull,
278 OPC_ST8_M4 = 0x08cc0000000ull,
279 OPC_SUB_A1 = 0x10028000000ull,
280 OPC_SUB_A3 = 0x10128000000ull,
281 OPC_UNPACK4_L_I2 = 0x0f860000000ull,
282 OPC_XMA_L_F2 = 0x1d000000000ull,
283 OPC_XOR_A1 = 0x10078000000ull,
284 OPC_ZXT1_I29 = 0x00080000000ull,
285 OPC_ZXT2_I29 = 0x00088000000ull,
286 OPC_ZXT4_I29 = 0x00090000000ull,
5f7b1687
RH		 287
288 INSN_NOP_M = OPC_NOP_M48, /* nop.m 0 */
289 INSN_NOP_I = OPC_NOP_I18, /* nop.i 0 */
477ba620
AJ		 290};
291
292static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1,
293 int r2, int r3)
294{
295 return opc
296 | ((r3 & 0x7f) << 20)
297 | ((r2 & 0x7f) << 13)
298 | ((r1 & 0x7f) << 6)
299 | (qp & 0x3f);
300}
301
302static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1,
303 uint64_t imm, int r3)
304{
305 return opc
306 | ((imm & 0x80) << 29) /* s */
307 | ((imm & 0x7f) << 13) /* imm7b */
308 | ((r3 & 0x7f) << 20)
309 | ((r1 & 0x7f) << 6)
310 | (qp & 0x3f);
311}
312
313static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1,
314 uint64_t imm, int r3)
315{
316 return opc
317 | ((imm & 0x2000) << 23) /* s */
318 | ((imm & 0x1f80) << 20) /* imm6d */
319 | ((imm & 0x007f) << 13) /* imm7b */
320 | ((r3 & 0x7f) << 20)
321 | ((r1 & 0x7f) << 6)
322 | (qp & 0x3f);
323}
324
325static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1,
326 uint64_t imm, int r3)
327{
328 return opc
329 | ((imm & 0x200000) << 15) /* s */
330 | ((imm & 0x1f0000) << 6) /* imm5c */
331 | ((imm & 0x00ff80) << 20) /* imm9d */
332 | ((imm & 0x00007f) << 13) /* imm7b */
333 | ((r3 & 0x03) << 20)
334 | ((r1 & 0x7f) << 6)
335 | (qp & 0x3f);
336}
337
338static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1,
339 int p2, int r2, int r3)
340{
341 return opc
342 | ((p2 & 0x3f) << 27)
343 | ((r3 & 0x7f) << 20)
344 | ((r2 & 0x7f) << 13)
345 | ((p1 & 0x3f) << 6)
346 | (qp & 0x3f);
347}
348
349static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm)
350{
351 return opc
352 | ((imm & 0x100000) << 16) /* s */
353 | ((imm & 0x0fffff) << 13) /* imm20b */
354 | (qp & 0x3f);
355}
356
357static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2)
358{
359 return opc
360 | ((b2 & 0x7) << 13)
361 | (qp & 0x3f);
362}
363
364static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2)
365{
366 return opc
367 | ((b2 & 0x7) << 13)
368 | ((b1 & 0x7) << 6)
369 | (qp & 0x3f);
370}
371
372
373static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm)
374{
375 return opc
376 | ((imm & 0x100000) << 16) /* i */
377 | ((imm & 0x0fffff) << 6) /* imm20a */
378 | (qp & 0x3f);
379}
380
381static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1,
382 int f3, int f4, int f2)
383{
384 return opc
385 | ((f4 & 0x7f) << 27)
386 | ((f3 & 0x7f) << 20)
387 | ((f2 & 0x7f) << 13)
388 | ((f1 & 0x7f) << 6)
389 | (qp & 0x3f);
390}
391
392static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1,
393 int f3, int f4, int f2)
394{
395 return opc
396 | ((f4 & 0x7f) << 27)
397 | ((f3 & 0x7f) << 20)
398 | ((f2 & 0x7f) << 13)
399 | ((f1 & 0x7f) << 6)
400 | (qp & 0x3f);
401}
402
403static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1,
404 int p2, int f2, int f3)
405{
406 return opc
407 | ((p2 & 0x3f) << 27)
408 | ((f3 & 0x7f) << 20)
409 | ((f2 & 0x7f) << 13)
410 | ((f1 & 0x7f) << 6)
411 | (qp & 0x3f);
412}
413
414static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2)
415{
416 return opc
417 | ((f2 & 0x7f) << 13)
418 | ((f1 & 0x7f) << 6)
419 | (qp & 0x3f);
420}
421
422static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2)
423{
424 return opc
425 | ((f2 & 0x7f) << 13)
426 | ((f1 & 0x7f) << 6)
427 | (qp & 0x3f);
428}
429
430static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm)
431{
432 return opc
433 | ((imm & 0x100000) << 16) /* i */
434 | ((imm & 0x0fffff) << 6) /* imm20a */
435 | (qp & 0x3f);
436}
437
438static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1,
439 int r2, int r3)
440{
441 return opc
442 | ((r3 & 0x7f) << 20)
443 | ((r2 & 0x7f) << 13)
444 | ((r1 & 0x7f) << 6)
445 | (qp & 0x3f);
446}
447
448static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1,
449 int r2, int mbtype)
450{
451 return opc
452 | ((mbtype & 0x0f) << 20)
453 | ((r2 & 0x7f) << 13)
454 | ((r1 & 0x7f) << 6)
455 | (qp & 0x3f);
456}
457
458static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1,
459 int r3, int r2)
460{
461 return opc
462 | ((r3 & 0x7f) << 20)
463 | ((r2 & 0x7f) << 13)
464 | ((r1 & 0x7f) << 6)
465 | (qp & 0x3f);
466}
467
468static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1,
469 int r2, int r3)
470{
471 return opc
472 | ((r3 & 0x7f) << 20)
473 | ((r2 & 0x7f) << 13)
474 | ((r1 & 0x7f) << 6)
475 | (qp & 0x3f);
476}
477
478static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1,
479 int r2, int r3, uint64_t count)
480{
481 return opc
482 | ((count & 0x3f) << 27)
483 | ((r3 & 0x7f) << 20)
484 | ((r2 & 0x7f) << 13)
485 | ((r1 & 0x7f) << 6)
486 | (qp & 0x3f);
487}
488
489static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1,
490 int r3, uint64_t pos, uint64_t len)
491{
492 return opc
493 | ((len & 0x3f) << 27)
494 | ((r3 & 0x7f) << 20)
495 | ((pos & 0x3f) << 14)
496 | ((r1 & 0x7f) << 6)
497 | (qp & 0x3f);
498}
499
500static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1,
501 int r2, uint64_t pos, uint64_t len)
502{
503 return opc
504 | ((len & 0x3f) << 27)
505 | ((pos & 0x3f) << 20)
506 | ((r2 & 0x7f) << 13)
507 | ((r1 & 0x7f) << 6)
508 | (qp & 0x3f);
509}
510
63975ea7
AJ		 511static inline uint64_t tcg_opc_i14(int qp, uint64_t opc, int r1, uint64_t imm,
512 int r3, uint64_t pos, uint64_t len)
513{
514 return opc
515 | ((imm & 0x01) << 36)
516 | ((len & 0x3f) << 27)
517 | ((r3 & 0x7f) << 20)
518 | ((pos & 0x3f) << 14)
519 | ((r1 & 0x7f) << 6)
520 | (qp & 0x3f);
521}
522
c7d4475a
RH		 523static inline uint64_t tcg_opc_i15(int qp, uint64_t opc, int r1, int r2,
524 int r3, uint64_t pos, uint64_t len)
525{
526 return opc
527 | ((pos & 0x3f) << 31)
528 | ((len & 0x0f) << 27)
529 | ((r3 & 0x7f) << 20)
530 | ((r2 & 0x7f) << 13)
531 | ((r1 & 0x7f) << 6)
532 | (qp & 0x3f);
533}
534
477ba620
AJ		 535static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)
536{
537 return opc
538 | ((imm & 0x100000) << 16) /* i */
539 | ((imm & 0x0fffff) << 6) /* imm20a */
540 | (qp & 0x3f);
541}
542
543static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1,
544 int r2, uint64_t imm)
545{
546 return opc
547 | ((imm & 0x1ff) << 24)
548 | ((r2 & 0x7f) << 13)
549 | ((b1 & 0x7) << 6)
550 | (qp & 0x3f);
551}
552
553static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2)
554{
555 return opc
556 | ((b2 & 0x7) << 13)
557 | ((r1 & 0x7f) << 6)
558 | (qp & 0x3f);
559}
560
561static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2)
562{
563 return opc
564 | ((ar3 & 0x7f) << 20)
565 | ((r2 & 0x7f) << 13)
566 | (qp & 0x3f);
567}
568
569static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3)
570{
571 return opc
572 | ((r3 & 0x7f) << 20)
573 | ((r1 & 0x7f) << 6)
574 | (qp & 0x3f);
575}
576
577static inline uint64_t tcg_opc_l2(uint64_t imm)
578{
579 return (imm & 0x7fffffffffc00000ull) >> 22;
580}
581
582static inline uint64_t tcg_opc_l3(uint64_t imm)
583{
584 return (imm & 0x07fffffffff00000ull) >> 18;
585}
586
6f65c780
RH		 587#define tcg_opc_l4 tcg_opc_l3
588
477ba620
AJ		 589static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3)
590{
591 return opc
592 | ((r3 & 0x7f) << 20)
593 | ((r1 & 0x7f) << 6)
594 | (qp & 0x3f);
595}
596
597static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1,
598 int r3, uint64_t imm)
599{
600 return opc
601 | ((imm & 0x100) << 28) /* s */
602 | ((imm & 0x080) << 20) /* i */
603 | ((imm & 0x07f) << 13) /* imm7b */
604 | ((r3 & 0x7f) << 20)
605 | ((r1 & 0x7f) << 6)
606 | (qp & 0x3f);
607}
608
609static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3)
610{
611 return opc
612 | ((r3 & 0x7f) << 20)
613 | ((r2 & 0x7f) << 13)
614 | (qp & 0x3f);
615}
616
617static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2)
618{
619 return opc
620 | ((r2 & 0x7f) << 13)
621 | ((f1 & 0x7f) << 6)
622 | (qp & 0x3f);
623}
624
625static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2)
626{
627 return opc
628 | ((f2 & 0x7f) << 13)
629 | ((r1 & 0x7f) << 6)
630 | (qp & 0x3f);
631}
632
633static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1,
634 int sof, int sol, int sor)
635{
636 return opc
637 | ((sor & 0x0f) << 27)
638 | ((sol & 0x7f) << 20)
639 | ((sof & 0x7f) << 13)
640 | ((r1 & 0x7f) << 6)
641 | (qp & 0x3f);
642}
643
644static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm)
645{
646 return opc
647 | ((imm & 0x100000) << 16) /* i */
648 | ((imm & 0x0fffff) << 6) /* imm20a */
649 | (qp & 0x3f);
650}
651
652static inline uint64_t tcg_opc_x2(int qp, uint64_t opc,
653 int r1, uint64_t imm)
654{
655 return opc
656 | ((imm & 0x8000000000000000ull) >> 27) /* i */
657 | (imm & 0x0000000000200000ull) /* ic */
658 | ((imm & 0x00000000001f0000ull) << 6) /* imm5c */
659 | ((imm & 0x000000000000ff80ull) << 20) /* imm9d */
660 | ((imm & 0x000000000000007full) << 13) /* imm7b */
661 | ((r1 & 0x7f) << 6)
662 | (qp & 0x3f);
663}
664
665static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm)
666{
667 return opc
668 | ((imm & 0x0800000000000000ull) >> 23) /* i */
669 | ((imm & 0x00000000000fffffull) << 13) /* imm20b */
670 | (qp & 0x3f);
671}
672
6f65c780
RH		 673static inline uint64_t tcg_opc_x4(int qp, uint64_t opc, int b1, uint64_t imm)
674{
675 return opc
676 | ((imm & 0x0800000000000000ull) >> 23) /* i */
677 | ((imm & 0x00000000000fffffull) << 13) /* imm20b */
678 | ((b1 & 0x7) << 6)
679 | (qp & 0x3f);
680}
681
477ba620
AJ		 682
683/*
684 * Relocations
685 */
686
2ba7fae2 687static inline void reloc_pcrel21b(void *pc, intptr_t target)
477ba620
AJ		 688{
689 uint64_t imm;
690 int64_t disp;
691 int slot;
692
2ba7fae2
RH		 693 slot = (intptr_t)pc & 3;
694 pc = (void *)((intptr_t)pc & ~3);
477ba620 695
2ba7fae2 696 disp = target - (intptr_t)pc;
477ba620
AJ		 697 imm = (uint64_t) disp >> 4;
698
699 switch(slot) {
700 case 0:
701 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull)
702 | ((imm & 0x100000) << 21) /* s */
703 | ((imm & 0x0fffff) << 18); /* imm20b */
704 break;
705 case 1:
706 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull)
707 | ((imm & 0x100000) >> 2) /* s */
708 | ((imm & 0x0fffe0) >> 5); /* imm20b */
709 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull)
710 | ((imm & 0x00001f) << 59); /* imm20b */
711 break;
712 case 2:
713 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull)
714 | ((imm & 0x100000) << 39) /* s */
715 | ((imm & 0x0fffff) << 36); /* imm20b */
716 break;
717 }
718}
719
720static inline uint64_t get_reloc_pcrel21b (void *pc)
721{
722 int64_t low, high;
723 int slot;
724
725 slot = (tcg_target_long) pc & 3;
726 pc = (void *)((tcg_target_long) pc & ~3);
727
728 low = (*(uint64_t *)(pc + 0));
729 high = (*(uint64_t *)(pc + 8));
730
731 switch(slot) {
732 case 0:
733 return ((low >> 21) & 0x100000) + /* s */
734 ((low >> 18) & 0x0fffff); /* imm20b */
735 case 1:
736 return ((high << 2) & 0x100000) + /* s */
737 ((high << 5) & 0x0fffe0) + /* imm20b */
738 ((low >> 59) & 0x00001f); /* imm20b */
739 case 2:
740 return ((high >> 39) & 0x100000) + /* s */
741 ((high >> 36) & 0x0fffff); /* imm20b */
742 default:
743 tcg_abort();
744 }
745}
746
2ba7fae2 747static inline void reloc_pcrel60b(void *pc, intptr_t target)
477ba620
AJ		 748{
749 int64_t disp;
750 uint64_t imm;
751
2ba7fae2 752 disp = target - (intptr_t)pc;
477ba620
AJ		 753 imm = (uint64_t) disp >> 4;
754
755 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull)
756 | (imm & 0x0800000000000000ull) /* s */
757 | ((imm & 0x07fffff000000000ull) >> 36) /* imm39 */
758 | ((imm & 0x00000000000fffffull) << 36); /* imm20b */
759 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull)
760 | ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */
761}
762
763static inline uint64_t get_reloc_pcrel60b (void *pc)
764{
765 int64_t low, high;
766
767 low = (*(uint64_t *)(pc + 0));
768 high = (*(uint64_t *)(pc + 8));
769
770 return ((high) & 0x0800000000000000ull) + /* s */
771 ((high >> 36) & 0x00000000000fffffull) + /* imm20b */
772 ((high << 36) & 0x07fffff000000000ull) + /* imm39 */
773 ((low >> 28) & 0x0000000ffff00000ull); /* imm39 */
774}
775
776
777static void patch_reloc(uint8_t *code_ptr, int type,
2ba7fae2 778 intptr_t value, intptr_t addend)
477ba620
AJ		 779{
780 value += addend;
781 switch (type) {
782 case R_IA64_PCREL21B:
783 reloc_pcrel21b(code_ptr, value);
784 break;
785 case R_IA64_PCREL60B:
786 reloc_pcrel60b(code_ptr, value);
787 default:
788 tcg_abort();
789 }
790}
791
792/*
793 * Constraints
794 */
795
796/* parse target specific constraints */
797static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
798{
799 const char *ct_str;
800
801 ct_str = *pct_str;
802 switch(ct_str[0]) {
803 case 'r':
804 ct->ct |= TCG_CT_REG;
805 tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
806 break;
807 case 'I':
808 ct->ct |= TCG_CT_CONST_S22;
809 break;
810 case 'S':
811 ct->ct |= TCG_CT_REG;
812 tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
813#if defined(CONFIG_SOFTMMU)
814 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56);
815 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57);
816#endif
817 break;
818 case 'Z':
819 /* We are cheating a bit here, using the fact that the register
820 r0 is also the register number 0. Hence there is no need
821 to check for const_args in each instruction. */
822 ct->ct |= TCG_CT_CONST_ZERO;
823 break;
824 default:
825 return -1;
826 }
827 ct_str++;
828 *pct_str = ct_str;
829 return 0;
830}
831
832/* test if a constant matches the constraint */
833static inline int tcg_target_const_match(tcg_target_long val,
834 const TCGArgConstraint *arg_ct)
835{
836 int ct;
837 ct = arg_ct->ct;
838 if (ct & TCG_CT_CONST)
839 return 1;
840 else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
841 return 1;
842 else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10)
843 return 1;
844 else
845 return 0;
846}
847
848/*
849 * Code generation
850 */
851
852static uint8_t *tb_ret_addr;
853
854static inline void tcg_out_bundle(TCGContext *s, int template,
855 uint64_t slot0, uint64_t slot1,
856 uint64_t slot2)
857{
858 template &= 0x1f; /* 5 bits */
859 slot0 &= 0x1ffffffffffull; /* 41 bits */
860 slot1 &= 0x1ffffffffffull; /* 41 bits */
861 slot2 &= 0x1ffffffffffull; /* 41 bits */
862
863 *(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template;
864 *(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18);
865 s->code_ptr += 16;
866}
867
3b6dac34 868static inline void tcg_out_mov(TCGContext *s, TCGType type,
2a534aff 869 TCGReg ret, TCGReg arg)
477ba620
AJ		 870{
871 tcg_out_bundle(s, mmI,
5f7b1687
RH		 872 INSN_NOP_M,
873 INSN_NOP_M,
477ba620
AJ		 874 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, 0, arg));
875}
876
877static inline void tcg_out_movi(TCGContext *s, TCGType type,
2a534aff 878 TCGReg reg, tcg_target_long arg)
477ba620
AJ		 879{
880 tcg_out_bundle(s, mLX,
5f7b1687 881 INSN_NOP_M,
477ba620
AJ		 882 tcg_opc_l2 (arg),
883 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg));
884}
885
477ba620
AJ		 886static void tcg_out_br(TCGContext *s, int label_index)
887{
888 TCGLabel *l = &s->labels[label_index];
889
56779034
AJ		 890 /* We pay attention here to not modify the branch target by reading
891 the existing value and using it again. This ensure that caches and
892 memory are kept coherent during retranslation. */
477ba620 893 tcg_out_bundle(s, mmB,
5f7b1687
RH		 894 INSN_NOP_M,
895 INSN_NOP_M,
477ba620
AJ		 896 tcg_opc_b1 (TCG_REG_P0, OPC_BR_SPTK_MANY_B1,
897 get_reloc_pcrel21b(s->code_ptr + 2)));
898
899 if (l->has_value) {
900 reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
901 } else {
902 tcg_out_reloc(s, (s->code_ptr - 16) + 2,
903 R_IA64_PCREL21B, label_index, 0);
904 }
905}
906
6f65c780
RH		 907static inline void tcg_out_calli(TCGContext *s, uintptr_t addr)
908{
909 /* Look through the function descriptor. */
910 uintptr_t disp, *desc = (uintptr_t *)addr;
911 tcg_out_bundle(s, mlx,
912 INSN_NOP_M,
913 tcg_opc_l2 (desc[1]),
914 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, TCG_REG_R1, desc[1]));
915 disp = (desc[0] - (uintptr_t)s->code_ptr) >> 4;
916 tcg_out_bundle(s, mLX,
917 INSN_NOP_M,
918 tcg_opc_l4 (disp),
919 tcg_opc_x4 (TCG_REG_P0, OPC_BRL_CALL_SPTK_MANY_X4,
920 TCG_REG_B0, disp));
921}
922
923static inline void tcg_out_callr(TCGContext *s, TCGReg addr)
477ba620
AJ		 924{
925 tcg_out_bundle(s, MmI,
926 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr),
927 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr),
928 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
929 TCG_REG_B6, TCG_REG_R2, 0));
930 tcg_out_bundle(s, mmB,
931 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3),
5f7b1687 932 INSN_NOP_M,
477ba620
AJ		 933 tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5,
934 TCG_REG_B0, TCG_REG_B6));
935}
936
937static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg)
938{
939 int64_t disp;
940 uint64_t imm;
941
942 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg);
943
944 disp = tb_ret_addr - s->code_ptr;
945 imm = (uint64_t)disp >> 4;
946
947 tcg_out_bundle(s, mLX,
5f7b1687 948 INSN_NOP_M,
477ba620
AJ		 949 tcg_opc_l3 (imm),
950 tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm));
951}
952
953static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg)
954{
955 if (s->tb_jmp_offset) {
956 /* direct jump method */
957 tcg_abort();
958 } else {
959 /* indirect jump method */
960 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2,
961 (tcg_target_long)(s->tb_next + arg));
962 tcg_out_bundle(s, MmI,
963 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1,
964 TCG_REG_R2, TCG_REG_R2),
5f7b1687 965 INSN_NOP_M,
477ba620
AJ		 966 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6,
967 TCG_REG_R2, 0));
968 tcg_out_bundle(s, mmB,
5f7b1687
RH		 969 INSN_NOP_M,
970 INSN_NOP_M,
477ba620
AJ		 971 tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4,
972 TCG_REG_B6));
973 }
974 s->tb_next_offset[arg] = s->code_ptr - s->code_buf;
975}
976
977static inline void tcg_out_jmp(TCGContext *s, TCGArg addr)
978{
979 tcg_out_bundle(s, mmI,
5f7b1687
RH		 980 INSN_NOP_M,
981 INSN_NOP_M,
477ba620
AJ		 982 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0));
983 tcg_out_bundle(s, mmB,
5f7b1687
RH		 984 INSN_NOP_M,
985 INSN_NOP_M,
477ba620
AJ		 986 tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
987}
988
989static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
990 TCGArg arg1, tcg_target_long arg2)
991{
992 if (arg2 == ((int16_t)arg2 >> 2) << 2) {
993 tcg_out_bundle(s, MmI,
994 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
995 TCG_REG_R2, arg2, arg1),
996 tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
5f7b1687 997 INSN_NOP_I);
477ba620
AJ		 998 } else {
999 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
1000 tcg_out_bundle(s, MmI,
1001 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
1002 TCG_REG_R2, TCG_REG_R2, arg1),
1003 tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
5f7b1687 1004 INSN_NOP_I);
477ba620
AJ		 1005 }
1006}
1007
1008static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
1009 TCGArg arg1, tcg_target_long arg2)
1010{
1011 if (arg2 == ((int16_t)arg2 >> 2) << 2) {
1012 tcg_out_bundle(s, MmI,
1013 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
1014 TCG_REG_R2, arg2, arg1),
1015 tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
5f7b1687 1016 INSN_NOP_I);
477ba620
AJ		 1017 } else {
1018 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
1019 tcg_out_bundle(s, MmI,
1020 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
1021 TCG_REG_R2, TCG_REG_R2, arg1),
1022 tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
5f7b1687 1023 INSN_NOP_I);
477ba620
AJ		 1024 }
1025}
1026
2a534aff 1027static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
a05b5b9b 1028 TCGReg arg1, intptr_t arg2)
477ba620
AJ		 1029{
1030 if (type == TCG_TYPE_I32) {
1031 tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2);
1032 } else {
1033 tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2);
1034 }
1035}
1036
2a534aff 1037static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
a05b5b9b 1038 TCGReg arg1, intptr_t arg2)
477ba620
AJ		 1039{
1040 if (type == TCG_TYPE_I32) {
1041 tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2);
1042 } else {
1043 tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2);
1044 }
1045}
1046
1047static inline void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGArg ret,
1048 TCGArg arg1, int const_arg1,
1049 TCGArg arg2, int const_arg2)
1050{
1051 uint64_t opc1, opc2;
1052
1053 if (const_arg1 && arg1 != 0) {
1054 opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1055 TCG_REG_R2, arg1, TCG_REG_R0);
1056 arg1 = TCG_REG_R2;
1057 } else {
5f7b1687 1058 opc1 = INSN_NOP_M;
477ba620
AJ		 1059 }
1060
1061 if (const_arg2 && arg2 != 0) {
1062 opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1063 TCG_REG_R3, arg2, TCG_REG_R0);
1064 arg2 = TCG_REG_R3;
1065 } else {
5f7b1687 1066 opc2 = INSN_NOP_I;
477ba620
AJ		 1067 }
1068
1069 tcg_out_bundle(s, mII,
1070 opc1,
1071 opc2,
1072 tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2));
1073}
1074
1075static inline void tcg_out_eqv(TCGContext *s, TCGArg ret,
1076 TCGArg arg1, int const_arg1,
1077 TCGArg arg2, int const_arg2)
1078{
1079 tcg_out_bundle(s, mII,
5f7b1687 1080 INSN_NOP_M,
477ba620
AJ		 1081 tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2),
1082 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1083}
1084
1085static inline void tcg_out_nand(TCGContext *s, TCGArg ret,
1086 TCGArg arg1, int const_arg1,
1087 TCGArg arg2, int const_arg2)
1088{
1089 tcg_out_bundle(s, mII,
5f7b1687 1090 INSN_NOP_M,
477ba620
AJ		 1091 tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2),
1092 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1093}
1094
1095static inline void tcg_out_nor(TCGContext *s, TCGArg ret,
1096 TCGArg arg1, int const_arg1,
1097 TCGArg arg2, int const_arg2)
1098{
1099 tcg_out_bundle(s, mII,
5f7b1687 1100 INSN_NOP_M,
477ba620
AJ		 1101 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2),
1102 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1103}
1104
1105static inline void tcg_out_orc(TCGContext *s, TCGArg ret,
1106 TCGArg arg1, int const_arg1,
1107 TCGArg arg2, int const_arg2)
1108{
1109 tcg_out_bundle(s, mII,
5f7b1687 1110 INSN_NOP_M,
477ba620
AJ		 1111 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2),
1112 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2));
1113}
1114
1115static inline void tcg_out_mul(TCGContext *s, TCGArg ret,
1116 TCGArg arg1, TCGArg arg2)
1117{
1118 tcg_out_bundle(s, mmI,
1119 tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1),
1120 tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2),
5f7b1687 1121 INSN_NOP_I);
477ba620 1122 tcg_out_bundle(s, mmF,
5f7b1687
RH		 1123 INSN_NOP_M,
1124 INSN_NOP_M,
477ba620
AJ		 1125 tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6,
1126 TCG_REG_F7, TCG_REG_F0));
1127 tcg_out_bundle(s, miI,
1128 tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6),
5f7b1687
RH		 1129 INSN_NOP_I,
1130 INSN_NOP_I);
477ba620
AJ		 1131}
1132
1133static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1134 TCGArg arg2, int const_arg2)
1135{
1136 if (const_arg2) {
1137 tcg_out_bundle(s, miI,
5f7b1687
RH		 1138 INSN_NOP_M,
1139 INSN_NOP_I,
477ba620
AJ		 1140 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1141 ret, arg1, arg2, 31 - arg2));
1142 } else {
1143 tcg_out_bundle(s, mII,
1144 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3,
1145 TCG_REG_R3, 0x1f, arg2),
1146 tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1),
1147 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret,
1148 TCG_REG_R2, TCG_REG_R3));
1149 }
1150}
1151
1152static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1153 TCGArg arg2, int const_arg2)
1154{
1155 if (const_arg2) {
1156 tcg_out_bundle(s, miI,
5f7b1687
RH		 1157 INSN_NOP_M,
1158 INSN_NOP_I,
477ba620
AJ		 1159 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1160 ret, arg1, arg2, 63 - arg2));
1161 } else {
1162 tcg_out_bundle(s, miI,
5f7b1687
RH		 1163 INSN_NOP_M,
1164 INSN_NOP_I,
477ba620
AJ		 1165 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2));
1166 }
1167}
1168
1169static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1170 TCGArg arg2, int const_arg2)
1171{
1172 if (const_arg2) {
1173 tcg_out_bundle(s, miI,
5f7b1687
RH		 1174 INSN_NOP_M,
1175 INSN_NOP_I,
477ba620
AJ		 1176 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1177 arg1, 63 - arg2, 31 - arg2));
1178 } else {
1179 tcg_out_bundle(s, mII,
5f7b1687 1180 INSN_NOP_M,
477ba620
AJ		 1181 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2,
1182 0x1f, arg2),
1183 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1184 arg1, TCG_REG_R2));
1185 }
1186}
1187
1188static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1189 TCGArg arg2, int const_arg2)
1190{
1191 if (const_arg2) {
1192 tcg_out_bundle(s, miI,
5f7b1687
RH		 1193 INSN_NOP_M,
1194 INSN_NOP_I,
477ba620
AJ		 1195 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1196 arg1, 63 - arg2, 63 - arg2));
1197 } else {
1198 tcg_out_bundle(s, miI,
5f7b1687
RH		 1199 INSN_NOP_M,
1200 INSN_NOP_I,
477ba620
AJ		 1201 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1202 arg1, arg2));
1203 }
1204}
1205
1206static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1207 TCGArg arg2, int const_arg2)
1208{
1209 if (const_arg2) {
1210 tcg_out_bundle(s, miI,
5f7b1687
RH		 1211 INSN_NOP_M,
1212 INSN_NOP_I,
477ba620
AJ		 1213 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1214 arg1, arg2, 31 - arg2));
1215 } else {
1216 tcg_out_bundle(s, mII,
1217 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1218 0x1f, arg2),
1219 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1),
1220 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1221 TCG_REG_R2, TCG_REG_R3));
1222 }
1223}
1224
1225static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1226 TCGArg arg2, int const_arg2)
1227{
1228 if (const_arg2) {
1229 tcg_out_bundle(s, miI,
5f7b1687
RH		 1230 INSN_NOP_M,
1231 INSN_NOP_I,
477ba620
AJ		 1232 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1233 arg1, arg2, 63 - arg2));
1234 } else {
1235 tcg_out_bundle(s, miI,
5f7b1687
RH		 1236 INSN_NOP_M,
1237 INSN_NOP_I,
477ba620
AJ		 1238 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1239 arg1, arg2));
1240 }
1241}
1242
1243static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1244 TCGArg arg2, int const_arg2)
1245{
1246 if (const_arg2) {
1247 tcg_out_bundle(s, mII,
5f7b1687 1248 INSN_NOP_M,
477ba620
AJ		 1249 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1250 TCG_REG_R2, arg1, arg1),
1251 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1252 TCG_REG_R2, 32 - arg2, 31));
1253 } else {
1254 tcg_out_bundle(s, miI,
5f7b1687 1255 INSN_NOP_M,
477ba620
AJ		 1256 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1257 TCG_REG_R2, arg1, arg1),
1258 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1259 0x1f, arg2));
1260 tcg_out_bundle(s, mII,
5f7b1687 1261 INSN_NOP_M,
477ba620
AJ		 1262 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3,
1263 0x20, TCG_REG_R3),
1264 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1265 TCG_REG_R2, TCG_REG_R3));
1266 }
1267}
1268
1269static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1270 TCGArg arg2, int const_arg2)
1271{
1272 if (const_arg2) {
1273 tcg_out_bundle(s, miI,
5f7b1687
RH		 1274 INSN_NOP_M,
1275 INSN_NOP_I,
477ba620
AJ		 1276 tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1277 arg1, 0x40 - arg2));
1278 } else {
1279 tcg_out_bundle(s, mII,
1280 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1281 0x40, arg2),
1282 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3,
1283 arg1, arg2),
1284 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2,
1285 arg1, TCG_REG_R2));
1286 tcg_out_bundle(s, miI,
5f7b1687
RH		 1287 INSN_NOP_M,
1288 INSN_NOP_I,
477ba620
AJ		 1289 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1290 TCG_REG_R2, TCG_REG_R3));
1291 }
1292}
1293
1294static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1295 TCGArg arg2, int const_arg2)
1296{
1297 if (const_arg2) {
1298 tcg_out_bundle(s, mII,
5f7b1687 1299 INSN_NOP_M,
477ba620
AJ		 1300 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1301 TCG_REG_R2, arg1, arg1),
1302 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1303 TCG_REG_R2, arg2, 31));
1304 } else {
1305 tcg_out_bundle(s, mII,
1306 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1307 0x1f, arg2),
1308 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1309 TCG_REG_R2, arg1, arg1),
1310 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1311 TCG_REG_R2, TCG_REG_R3));
1312 }
1313}
1314
1315static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1316 TCGArg arg2, int const_arg2)
1317{
1318 if (const_arg2) {
1319 tcg_out_bundle(s, miI,
5f7b1687
RH		 1320 INSN_NOP_M,
1321 INSN_NOP_I,
477ba620
AJ		 1322 tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1323 arg1, arg2));
1324 } else {
1325 tcg_out_bundle(s, mII,
1326 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1327 0x40, arg2),
1328 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3,
1329 arg1, arg2),
1330 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2,
1331 arg1, TCG_REG_R2));
1332 tcg_out_bundle(s, miI,
5f7b1687
RH		 1333 INSN_NOP_M,
1334 INSN_NOP_I,
477ba620
AJ		 1335 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1336 TCG_REG_R2, TCG_REG_R3));
1337 }
1338}
1339
1340static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29,
1341 TCGArg ret, TCGArg arg)
1342{
1343 tcg_out_bundle(s, miI,
5f7b1687
RH		 1344 INSN_NOP_M,
1345 INSN_NOP_I,
477ba620
AJ		 1346 tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg));
1347}
1348
1349static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg)
1350{
1351 tcg_out_bundle(s, mII,
5f7b1687 1352 INSN_NOP_M,
477ba620
AJ		 1353 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15),
1354 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1355}
1356
1357static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg)
1358{
1359 tcg_out_bundle(s, mII,
5f7b1687 1360 INSN_NOP_M,
477ba620
AJ		 1361 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31),
1362 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1363}
1364
1365static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg)
1366{
a3e28aa5 1367 tcg_out_bundle(s, miI,
5f7b1687
RH		 1368 INSN_NOP_M,
1369 INSN_NOP_I,
477ba620
AJ		 1370 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
1371}
1372
c7d4475a
RH		 1373static inline void tcg_out_deposit(TCGContext *s, TCGArg ret, TCGArg a1,
1374 TCGArg a2, int const_a2, int pos, int len)
1375{
1376 uint64_t i1 = 0, i2 = 0;
1377 int cpos = 63 - pos, lm1 = len - 1;
1378
1379 if (const_a2) {
1380 /* Truncate the value of a constant a2 to the width of the field. */
1381 int mask = (1u << len) - 1;
1382 a2 &= mask;
1383
1384 if (a2 == 0 || a2 == mask) {
1385 /* 1-bit signed constant inserted into register. */
1386 i2 = tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, ret, a2, a1, cpos, lm1);
1387 } else {
1388 /* Otherwise, load any constant into a temporary. Do this into
1389 the first I slot to help out with cross-unit delays. */
1390 i1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1391 TCG_REG_R2, a2, TCG_REG_R0);
1392 a2 = TCG_REG_R2;
1393 }
1394 }
1395 if (i2 == 0) {
1396 i2 = tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, ret, a2, a1, cpos, lm1);
1397 }
1398 tcg_out_bundle(s, (i1 ? mII : miI),
5f7b1687
RH		 1399 INSN_NOP_M,
1400 i1 ? i1 : INSN_NOP_I,
c7d4475a
RH		 1401 i2);
1402}
1403
477ba620
AJ		 1404static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1,
1405 TCGArg arg2, int cmp4)
1406{
1407 uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6;
1408
1409 if (cmp4) {
1410 opc_eq_a6 = OPC_CMP4_EQ_A6;
1411 opc_lt_a6 = OPC_CMP4_LT_A6;
1412 opc_ltu_a6 = OPC_CMP4_LTU_A6;
1413 } else {
1414 opc_eq_a6 = OPC_CMP_EQ_A6;
1415 opc_lt_a6 = OPC_CMP_LT_A6;
1416 opc_ltu_a6 = OPC_CMP_LTU_A6;
1417 }
1418
1419 switch (cond) {
1420 case TCG_COND_EQ:
1421 return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1422 case TCG_COND_NE:
1423 return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1424 case TCG_COND_LT:
1425 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1426 case TCG_COND_LTU:
1427 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1428 case TCG_COND_GE:
1429 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1430 case TCG_COND_GEU:
1431 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1432 case TCG_COND_LE:
1433 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1434 case TCG_COND_LEU:
1435 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1436 case TCG_COND_GT:
1437 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1438 case TCG_COND_GTU:
1439 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1440 default:
1441 tcg_abort();
1442 break;
1443 }
1444}
1445
6d264b38
RH		 1446static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
1447 TCGReg arg2, int label_index, int cmp4)
477ba620
AJ		 1448{
1449 TCGLabel *l = &s->labels[label_index];
477ba620 1450
6d264b38 1451 tcg_out_bundle(s, miB,
5f7b1687 1452 INSN_NOP_M,
6d264b38
RH		 1453 tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4),
1454 tcg_opc_b1(TCG_REG_P6, OPC_BR_DPTK_FEW_B1,
1455 get_reloc_pcrel21b(s->code_ptr + 2)));
477ba620
AJ		 1456
1457 if (l->has_value) {
1458 reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
1459 } else {
1460 tcg_out_reloc(s, (s->code_ptr - 16) + 2,
1461 R_IA64_PCREL21B, label_index, 0);
1462 }
1463}
1464
1465static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret,
1466 TCGArg arg1, TCGArg arg2, int cmp4)
1467{
1468 tcg_out_bundle(s, MmI,
1469 tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4),
1470 tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, 1, TCG_REG_R0),
1471 tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0));
1472}
1473
b90cf716
AJ		 1474static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret,
1475 TCGArg c1, TCGArg c2,
1476 TCGArg v1, int const_v1,
1477 TCGArg v2, int const_v2, int cmp4)
1478{
1479 uint64_t opc1, opc2;
1480
1481 if (const_v1) {
1482 opc1 = tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, v1, TCG_REG_R0);
1483 } else if (ret == v1) {
5f7b1687 1484 opc1 = INSN_NOP_M;
b90cf716
AJ		 1485 } else {
1486 opc1 = tcg_opc_a4(TCG_REG_P6, OPC_ADDS_A4, ret, 0, v1);
1487 }
1488 if (const_v2) {
1489 opc2 = tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, v2, TCG_REG_R0);
1490 } else if (ret == v2) {
5f7b1687 1491 opc2 = INSN_NOP_I;
b90cf716
AJ		 1492 } else {
1493 opc2 = tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, ret, 0, v2);
1494 }
1495
1496 tcg_out_bundle(s, MmI,
1497 tcg_opc_cmp_a(TCG_REG_P0, cond, c1, c2, cmp4),
1498 opc1,
1499 opc2);
1500}
1501
477ba620 1502#if defined(CONFIG_SOFTMMU)
477ba620
AJ		 1503/* Load and compare a TLB entry, and return the result in (p6, p7).
1504 R2 is loaded with the address of the addend TLB entry.
2174d1e1 1505 R57 is loaded with the address, zero extented on 32-bit targets. */
477ba620 1506static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
e3afa1c4 1507 TCGMemOp s_bits, uint64_t offset_rw,
477ba620
AJ		 1508 uint64_t offset_addend)
1509{
1510 tcg_out_bundle(s, mII,
5f7b1687 1511 INSN_NOP_M,
477ba620
AJ		 1512 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2,
1513 addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1),
1514 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R2,
1515 TCG_REG_R2, 63 - CPU_TLB_ENTRY_BITS,
1516 63 - CPU_TLB_ENTRY_BITS));
1517 tcg_out_bundle(s, mII,
1518 tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1519 offset_rw, TCG_REG_R2),
1520#if TARGET_LONG_BITS == 32
2174d1e1 1521 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R57, addr_reg),
477ba620 1522#else
2174d1e1 1523 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R57,
477ba620
AJ		 1524 0, addr_reg),
1525#endif
1526 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1527 TCG_REG_R2, TCG_AREG0));
1528 tcg_out_bundle(s, mII,
650a217a
RH		 1529 tcg_opc_m3 (TCG_REG_P0,
1530 (TARGET_LONG_BITS == 32
2174d1e1 1531 ? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R56,
477ba620 1532 TCG_REG_R2, offset_addend - offset_rw),
63975ea7
AJ		 1533 tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, TCG_REG_R3, 0,
1534 TCG_REG_R57, 63 - s_bits,
1535 TARGET_PAGE_BITS - s_bits - 1),
477ba620 1536 tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6,
2174d1e1 1537 TCG_REG_P7, TCG_REG_R3, TCG_REG_R56));
477ba620
AJ		 1538}
1539
e141ab52
BS		 1540/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1541 int mmu_idx) */
1542static const void * const qemu_ld_helpers[4] = {
1543 helper_ldb_mmu,
1544 helper_ldw_mmu,
1545 helper_ldl_mmu,
1546 helper_ldq_mmu,
1547};
477ba620 1548
e3afa1c4
RH		 1549static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
1550 TCGMemOp opc)
477ba620 1551{
e3afa1c4
RH		 1552 static const uint64_t opc_ld_m1[4] = {
1553 OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
1554 };
1555 static const uint64_t opc_ext_i29[8] = {
1556 OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0,
1557 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
1558 };
1559 int addr_reg, data_reg, mem_index;
1560 TCGMemOp s_bits, bswap;
477ba620
AJ		 1561
1562 data_reg = *args++;
1563 addr_reg = *args++;
1564 mem_index = *args;
e3afa1c4
RH		 1565 s_bits = opc & MO_SIZE;
1566 bswap = opc & MO_BSWAP;
477ba620
AJ		 1567
1568 /* Read the TLB entry */
1569 tcg_out_qemu_tlb(s, addr_reg, s_bits,
9349b4f9
AF		 1570 offsetof(CPUArchState, tlb_table[mem_index][0].addr_read),
1571 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
477ba620
AJ		 1572
1573 /* P6 is the fast path, and P7 the slow path */
1574 tcg_out_bundle(s, mLX,
2174d1e1
AJ		 1575 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1576 TCG_REG_R56, 0, TCG_AREG0),
477ba620
AJ		 1577 tcg_opc_l2 ((tcg_target_long) qemu_ld_helpers[s_bits]),
1578 tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1579 (tcg_target_long) qemu_ld_helpers[s_bits]));
1580 tcg_out_bundle(s, MmI,
1581 tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1582 TCG_REG_R2, 8),
1583 tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
2174d1e1 1584 TCG_REG_R3, TCG_REG_R57),
477ba620
AJ		 1585 tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1586 TCG_REG_R3, 0));
e3afa1c4 1587 if (bswap && s_bits == MO_16) {
477ba620
AJ		 1588 tcg_out_bundle(s, MmI,
1589 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1590 TCG_REG_R8, TCG_REG_R3),
1591 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1592 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1593 TCG_REG_R8, TCG_REG_R8, 15, 15));
e3afa1c4 1594 } else if (bswap && s_bits == MO_32) {
477ba620
AJ		 1595 tcg_out_bundle(s, MmI,
1596 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1597 TCG_REG_R8, TCG_REG_R3),
1598 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1599 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1600 TCG_REG_R8, TCG_REG_R8, 31, 31));
1601 } else {
1602 tcg_out_bundle(s, mmI,
1603 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1604 TCG_REG_R8, TCG_REG_R3),
1605 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
5f7b1687 1606 INSN_NOP_I);
477ba620 1607 }
e3afa1c4 1608 if (!bswap) {
477ba620 1609 tcg_out_bundle(s, miB,
2174d1e1
AJ		 1610 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1611 mem_index, TCG_REG_R0),
5f7b1687 1612 INSN_NOP_I,
477ba620
AJ		 1613 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1614 TCG_REG_B0, TCG_REG_B6));
1615 } else {
1616 tcg_out_bundle(s, miB,
2174d1e1
AJ		 1617 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1618 mem_index, TCG_REG_R0),
477ba620
AJ		 1619 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1620 TCG_REG_R8, TCG_REG_R8, 0xb),
1621 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1622 TCG_REG_B0, TCG_REG_B6));
1623 }
1624
e3afa1c4 1625 if (s_bits == MO_64) {
477ba620 1626 tcg_out_bundle(s, miI,
5f7b1687
RH		 1627 INSN_NOP_M,
1628 INSN_NOP_I,
477ba620
AJ		 1629 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
1630 data_reg, 0, TCG_REG_R8));
1631 } else {
1632 tcg_out_bundle(s, miI,
5f7b1687
RH		 1633 INSN_NOP_M,
1634 INSN_NOP_I,
e3afa1c4 1635 tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc & MO_SSIZE],
477ba620
AJ		 1636 data_reg, TCG_REG_R8));
1637 }
1638}
1639
e141ab52
BS		 1640/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1641 uintxx_t val, int mmu_idx) */
1642static const void * const qemu_st_helpers[4] = {
1643 helper_stb_mmu,
1644 helper_stw_mmu,
1645 helper_stl_mmu,
1646 helper_stq_mmu,
1647};
477ba620 1648
e3afa1c4
RH		 1649static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
1650 TCGMemOp opc)
477ba620 1651{
e3afa1c4
RH		 1652 static const uint64_t opc_st_m4[4] = {
1653 OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
1654 };
1655 int addr_reg, data_reg, mem_index;
1656 TCGMemOp s_bits;
477ba620
AJ		 1657
1658 data_reg = *args++;
1659 addr_reg = *args++;
1660 mem_index = *args;
e3afa1c4 1661 s_bits = opc & MO_SIZE;
477ba620 1662
e3afa1c4 1663 tcg_out_qemu_tlb(s, addr_reg, s_bits,
9349b4f9
AF		 1664 offsetof(CPUArchState, tlb_table[mem_index][0].addr_write),
1665 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
477ba620
AJ		 1666
1667 /* P6 is the fast path, and P7 the slow path */
1668 tcg_out_bundle(s, mLX,
2174d1e1
AJ		 1669 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1670 TCG_REG_R56, 0, TCG_AREG0),
e3afa1c4 1671 tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[s_bits]),
477ba620 1672 tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
e3afa1c4 1673 (tcg_target_long) qemu_st_helpers[s_bits]));
477ba620
AJ		 1674 tcg_out_bundle(s, MmI,
1675 tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1676 TCG_REG_R2, 8),
1677 tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
2174d1e1 1678 TCG_REG_R3, TCG_REG_R57),
477ba620
AJ		 1679 tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1680 TCG_REG_R3, 0));
1681
e3afa1c4
RH		 1682 switch (opc) {
1683 case MO_8:
1684 case MO_16:
1685 case MO_32:
1686 case MO_64:
2174d1e1 1687 tcg_out_bundle(s, mii,
477ba620
AJ		 1688 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1689 TCG_REG_R1, TCG_REG_R2),
2174d1e1
AJ		 1690 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1691 0, data_reg),
5f7b1687 1692 INSN_NOP_I);
e3afa1c4
RH		 1693 break;
1694
1695 case MO_16 | MO_BSWAP:
2174d1e1 1696 tcg_out_bundle(s, miI,
477ba620
AJ		 1697 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1698 TCG_REG_R1, TCG_REG_R2),
5f7b1687 1699 INSN_NOP_I,
477ba620 1700 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
2174d1e1
AJ		 1701 TCG_REG_R2, data_reg, 15, 15));
1702 tcg_out_bundle(s, miI,
1703 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1704 0, data_reg),
5f7b1687 1705 INSN_NOP_I,
477ba620
AJ		 1706 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1707 TCG_REG_R2, TCG_REG_R2, 0xb));
1708 data_reg = TCG_REG_R2;
e3afa1c4
RH		 1709 break;
1710
1711 case MO_32 | MO_BSWAP:
2174d1e1 1712 tcg_out_bundle(s, miI,
477ba620
AJ		 1713 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1714 TCG_REG_R1, TCG_REG_R2),
5f7b1687 1715 INSN_NOP_I,
477ba620 1716 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
2174d1e1
AJ		 1717 TCG_REG_R2, data_reg, 31, 31));
1718 tcg_out_bundle(s, miI,
1719 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1720 0, data_reg),
5f7b1687 1721 INSN_NOP_I,
477ba620
AJ		 1722 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1723 TCG_REG_R2, TCG_REG_R2, 0xb));
1724 data_reg = TCG_REG_R2;
e3afa1c4
RH		 1725 break;
1726
1727 case MO_64 | MO_BSWAP:
477ba620
AJ		 1728 tcg_out_bundle(s, miI,
1729 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1730 TCG_REG_R1, TCG_REG_R2),
2174d1e1
AJ		 1731 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1732 0, data_reg),
477ba620
AJ		 1733 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1734 TCG_REG_R2, data_reg, 0xb));
1735 data_reg = TCG_REG_R2;
e3afa1c4
RH		 1736 break;
1737
1738 default:
1739 tcg_abort();
477ba620
AJ		 1740 }
1741
d03c98d8 1742 tcg_out_bundle(s, miB,
e3afa1c4 1743 tcg_opc_m4 (TCG_REG_P6, opc_st_m4[s_bits],
d03c98d8 1744 data_reg, TCG_REG_R3),
2174d1e1
AJ		 1745 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59,
1746 mem_index, TCG_REG_R0),
d03c98d8
AJ		 1747 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1748 TCG_REG_B0, TCG_REG_B6));
477ba620
AJ		 1749}
1750
1751#else /* !CONFIG_SOFTMMU */
1752
e3afa1c4
RH		 1753static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
1754 TCGMemOp opc)
477ba620 1755{
6781d08d
RH		 1756 static uint64_t const opc_ld_m1[4] = {
1757 OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
1758 };
1759 static uint64_t const opc_sxt_i29[4] = {
1760 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
1761 };
e3afa1c4
RH		 1762 int addr_reg, data_reg;
1763 TCGMemOp s_bits, bswap;
477ba620
AJ		 1764
1765 data_reg = *args++;
1766 addr_reg = *args++;
e3afa1c4
RH		 1767 s_bits = opc & MO_SIZE;
1768 bswap = opc & MO_BSWAP;
477ba620 1769
477ba620 1770#if TARGET_LONG_BITS == 32
6781d08d
RH		 1771 if (GUEST_BASE != 0) {
1772 tcg_out_bundle(s, mII,
5f7b1687 1773 INSN_NOP_M,
6781d08d
RH		 1774 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1775 TCG_REG_R3, addr_reg),
1776 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1777 TCG_GUEST_BASE_REG, TCG_REG_R3));
1778 } else {
1779 tcg_out_bundle(s, miI,
5f7b1687 1780 INSN_NOP_M,
6781d08d
RH		 1781 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1782 TCG_REG_R2, addr_reg),
5f7b1687 1783 INSN_NOP_I);
6781d08d 1784 }
477ba620 1785
e3afa1c4
RH		 1786 if (!bswap) {
1787 if (!(opc & MO_SIGN)) {
477ba620
AJ		 1788 tcg_out_bundle(s, miI,
1789 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1790 data_reg, TCG_REG_R2),
5f7b1687
RH		 1791 INSN_NOP_I,
1792 INSN_NOP_I);
477ba620
AJ		 1793 } else {
1794 tcg_out_bundle(s, mII,
1795 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1796 data_reg, TCG_REG_R2),
5f7b1687 1797 INSN_NOP_I,
477ba620
AJ		 1798 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1799 data_reg, data_reg));
1800 }
e3afa1c4 1801 } else if (s_bits == MO_64) {
477ba620
AJ		 1802 tcg_out_bundle(s, mII,
1803 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1804 data_reg, TCG_REG_R2),
5f7b1687 1805 INSN_NOP_I,
477ba620
AJ		 1806 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1807 data_reg, data_reg, 0xb));
1808 } else {
e3afa1c4 1809 if (s_bits == MO_16) {
477ba620
AJ		 1810 tcg_out_bundle(s, mII,
1811 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1812 data_reg, TCG_REG_R2),
5f7b1687 1813 INSN_NOP_I,
477ba620
AJ		 1814 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1815 data_reg, data_reg, 15, 15));
1816 } else {
1817 tcg_out_bundle(s, mII,
1818 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1819 data_reg, TCG_REG_R2),
5f7b1687 1820 INSN_NOP_I,
477ba620
AJ		 1821 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1822 data_reg, data_reg, 31, 31));
1823 }
e3afa1c4 1824 if (!(opc & MO_SIGN)) {
477ba620 1825 tcg_out_bundle(s, miI,
5f7b1687
RH		 1826 INSN_NOP_M,
1827 INSN_NOP_I,
477ba620
AJ		 1828 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1829 data_reg, data_reg, 0xb));
1830 } else {
1831 tcg_out_bundle(s, mII,
5f7b1687 1832 INSN_NOP_M,
477ba620
AJ		 1833 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1834 data_reg, data_reg, 0xb),
1835 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1836 data_reg, data_reg));
1837 }
1838 }
1839#else
6781d08d
RH		 1840 if (GUEST_BASE != 0) {
1841 tcg_out_bundle(s, MmI,
1842 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1843 TCG_GUEST_BASE_REG, addr_reg),
1844 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1845 data_reg, TCG_REG_R2),
5f7b1687 1846 INSN_NOP_I);
6781d08d
RH		 1847 } else {
1848 tcg_out_bundle(s, mmI,
5f7b1687 1849 INSN_NOP_M,
6781d08d
RH		 1850 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1851 data_reg, addr_reg),
5f7b1687 1852 INSN_NOP_I);
6781d08d 1853 }
477ba620 1854
e3afa1c4 1855 if (bswap && s_bits == MO_16) {
477ba620 1856 tcg_out_bundle(s, mII,
5f7b1687 1857 INSN_NOP_M,
477ba620
AJ		 1858 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1859 data_reg, data_reg, 15, 15),
1860 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1861 data_reg, data_reg, 0xb));
e3afa1c4 1862 } else if (bswap && s_bits == MO_32) {
477ba620 1863 tcg_out_bundle(s, mII,
5f7b1687 1864 INSN_NOP_M,
477ba620
AJ		 1865 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1866 data_reg, data_reg, 31, 31),
1867 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1868 data_reg, data_reg, 0xb));
e3afa1c4 1869 } else if (bswap && s_bits == MO_64) {
477ba620 1870 tcg_out_bundle(s, miI,
5f7b1687
RH		 1871 INSN_NOP_M,
1872 INSN_NOP_I,
477ba620
AJ		 1873 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1874 data_reg, data_reg, 0xb));
1875 }
e3afa1c4 1876 if (opc & MO_SIGN) {
477ba620 1877 tcg_out_bundle(s, miI,
5f7b1687
RH		 1878 INSN_NOP_M,
1879 INSN_NOP_I,
477ba620
AJ		 1880 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1881 data_reg, data_reg));
1882 }
1883#endif
1884}
1885
e3afa1c4
RH		 1886static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
1887 TCGMemOp opc)
477ba620 1888{
6781d08d
RH		 1889 static uint64_t const opc_st_m4[4] = {
1890 OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
1891 };
e3afa1c4 1892 int addr_reg, data_reg;
6781d08d
RH		 1893#if TARGET_LONG_BITS == 64
1894 uint64_t add_guest_base;
1895#endif
e3afa1c4 1896 TCGMemOp s_bits, bswap;
477ba620
AJ		 1897
1898 data_reg = *args++;
1899 addr_reg = *args++;
e3afa1c4
RH		 1900 s_bits = opc & MO_SIZE;
1901 bswap = opc & MO_BSWAP;
477ba620 1902
477ba620 1903#if TARGET_LONG_BITS == 32
6781d08d
RH		 1904 if (GUEST_BASE != 0) {
1905 tcg_out_bundle(s, mII,
5f7b1687 1906 INSN_NOP_M,
6781d08d
RH		 1907 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1908 TCG_REG_R3, addr_reg),
1909 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1910 TCG_GUEST_BASE_REG, TCG_REG_R3));
1911 } else {
1912 tcg_out_bundle(s, miI,
5f7b1687 1913 INSN_NOP_M,
6781d08d 1914 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
07f59737 1915 TCG_REG_R2, addr_reg),
5f7b1687 1916 INSN_NOP_I);
6781d08d
RH		 1917 }
1918
477ba620 1919 if (bswap) {
e3afa1c4 1920 if (s_bits == MO_16) {
477ba620 1921 tcg_out_bundle(s, mII,
5f7b1687 1922 INSN_NOP_M,
477ba620
AJ		 1923 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1924 TCG_REG_R3, data_reg, 15, 15),
1925 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1926 TCG_REG_R3, TCG_REG_R3, 0xb));
1927 data_reg = TCG_REG_R3;
e3afa1c4 1928 } else if (s_bits == MO_32) {
477ba620 1929 tcg_out_bundle(s, mII,
5f7b1687 1930 INSN_NOP_M,
477ba620
AJ		 1931 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1932 TCG_REG_R3, data_reg, 31, 31),
1933 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1934 TCG_REG_R3, TCG_REG_R3, 0xb));
1935 data_reg = TCG_REG_R3;
e3afa1c4 1936 } else if (s_bits == MO_64) {
477ba620 1937 tcg_out_bundle(s, miI,
5f7b1687
RH		 1938 INSN_NOP_M,
1939 INSN_NOP_I,
477ba620
AJ		 1940 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1941 TCG_REG_R3, data_reg, 0xb));
1942 data_reg = TCG_REG_R3;
1943 }
1944 }
1945 tcg_out_bundle(s, mmI,
e3afa1c4 1946 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
477ba620 1947 data_reg, TCG_REG_R2),
5f7b1687
RH		 1948 INSN_NOP_M,
1949 INSN_NOP_I);
477ba620 1950#else
6781d08d
RH		 1951 if (GUEST_BASE != 0) {
1952 add_guest_base = tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1953 TCG_GUEST_BASE_REG, addr_reg);
1954 addr_reg = TCG_REG_R2;
1955 } else {
5f7b1687 1956 add_guest_base = INSN_NOP_M;
6781d08d
RH		 1957 }
1958
e3afa1c4 1959 if (!bswap) {
6781d08d
RH		 1960 tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI),
1961 add_guest_base,
e3afa1c4 1962 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
6781d08d 1963 data_reg, addr_reg),
5f7b1687 1964 INSN_NOP_I);
477ba620 1965 } else {
e3afa1c4 1966 if (s_bits == MO_16) {
477ba620 1967 tcg_out_bundle(s, mII,
6781d08d 1968 add_guest_base,
477ba620
AJ		 1969 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1970 TCG_REG_R3, data_reg, 15, 15),
1971 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1972 TCG_REG_R3, TCG_REG_R3, 0xb));
1973 data_reg = TCG_REG_R3;
e3afa1c4 1974 } else if (s_bits == MO_32) {
477ba620 1975 tcg_out_bundle(s, mII,
6781d08d 1976 add_guest_base,
477ba620
AJ		 1977 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1978 TCG_REG_R3, data_reg, 31, 31),
1979 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1980 TCG_REG_R3, TCG_REG_R3, 0xb));
1981 data_reg = TCG_REG_R3;
e3afa1c4 1982 } else if (s_bits == MO_64) {
477ba620 1983 tcg_out_bundle(s, miI,
6781d08d 1984 add_guest_base,
5f7b1687 1985 INSN_NOP_I,
477ba620
AJ		 1986 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1987 TCG_REG_R3, data_reg, 0xb));
1988 data_reg = TCG_REG_R3;
1989 }
1990 tcg_out_bundle(s, miI,
e3afa1c4 1991 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
6781d08d 1992 data_reg, addr_reg),
5f7b1687
RH		 1993 INSN_NOP_I,
1994 INSN_NOP_I);
477ba620
AJ		 1995 }
1996#endif
1997}
1998
1999#endif
2000
2001static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
2002 const TCGArg *args, const int *const_args)
2003{
2004 switch(opc) {
2005 case INDEX_op_exit_tb:
2006 tcg_out_exit_tb(s, args[0]);
2007 break;
2008 case INDEX_op_br:
2009 tcg_out_br(s, args[0]);
2010 break;
2011 case INDEX_op_call:
6f65c780
RH		 2012 if (likely(const_args[0])) {
2013 tcg_out_calli(s, args[0]);
2014 } else {
2015 tcg_out_callr(s, args[0]);
2016 }
477ba620
AJ		 2017 break;
2018 case INDEX_op_goto_tb:
2019 tcg_out_goto_tb(s, args[0]);
2020 break;
477ba620
AJ		 2021
2022 case INDEX_op_movi_i32:
2023 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
2024 break;
2025 case INDEX_op_movi_i64:
2026 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
2027 break;
2028
2029 case INDEX_op_ld8u_i32:
2030 case INDEX_op_ld8u_i64:
2031 tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
2032 break;
2033 case INDEX_op_ld8s_i32:
2034 case INDEX_op_ld8s_i64:
2035 tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
2036 tcg_out_ext(s, OPC_SXT1_I29, args[0], args[0]);
2037 break;
2038 case INDEX_op_ld16u_i32:
2039 case INDEX_op_ld16u_i64:
2040 tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
2041 break;
2042 case INDEX_op_ld16s_i32:
2043 case INDEX_op_ld16s_i64:
2044 tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
2045 tcg_out_ext(s, OPC_SXT2_I29, args[0], args[0]);
2046 break;
2047 case INDEX_op_ld_i32:
2048 case INDEX_op_ld32u_i64:
2049 tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
2050 break;
2051 case INDEX_op_ld32s_i64:
2052 tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
2053 tcg_out_ext(s, OPC_SXT4_I29, args[0], args[0]);
2054 break;
2055 case INDEX_op_ld_i64:
2056 tcg_out_ld_rel(s, OPC_LD8_M1, args[0], args[1], args[2]);
2057 break;
2058 case INDEX_op_st8_i32:
2059 case INDEX_op_st8_i64:
2060 tcg_out_st_rel(s, OPC_ST1_M4, args[0], args[1], args[2]);
2061 break;
2062 case INDEX_op_st16_i32:
2063 case INDEX_op_st16_i64:
2064 tcg_out_st_rel(s, OPC_ST2_M4, args[0], args[1], args[2]);
2065 break;
2066 case INDEX_op_st_i32:
2067 case INDEX_op_st32_i64:
2068 tcg_out_st_rel(s, OPC_ST4_M4, args[0], args[1], args[2]);
2069 break;
2070 case INDEX_op_st_i64:
2071 tcg_out_st_rel(s, OPC_ST8_M4, args[0], args[1], args[2]);
2072 break;
2073
2074 case INDEX_op_add_i32:
2075 case INDEX_op_add_i64:
2076 tcg_out_alu(s, OPC_ADD_A1, args[0], args[1], const_args[1],
2077 args[2], const_args[2]);
2078 break;
2079 case INDEX_op_sub_i32:
2080 case INDEX_op_sub_i64:
2081 tcg_out_alu(s, OPC_SUB_A1, args[0], args[1], const_args[1],
2082 args[2], const_args[2]);
2083 break;
2084
2085 case INDEX_op_and_i32:
2086 case INDEX_op_and_i64:
2087 tcg_out_alu(s, OPC_AND_A1, args[0], args[1], const_args[1],
2088 args[2], const_args[2]);
2089 break;
2090 case INDEX_op_andc_i32:
2091 case INDEX_op_andc_i64:
2092 tcg_out_alu(s, OPC_ANDCM_A1, args[0], args[1], const_args[1],
2093 args[2], const_args[2]);
2094 break;
2095 case INDEX_op_eqv_i32:
2096 case INDEX_op_eqv_i64:
2097 tcg_out_eqv(s, args[0], args[1], const_args[1],
2098 args[2], const_args[2]);
2099 break;
2100 case INDEX_op_nand_i32:
2101 case INDEX_op_nand_i64:
2102 tcg_out_nand(s, args[0], args[1], const_args[1],
2103 args[2], const_args[2]);
2104 break;
2105 case INDEX_op_nor_i32:
2106 case INDEX_op_nor_i64:
2107 tcg_out_nor(s, args[0], args[1], const_args[1],
2108 args[2], const_args[2]);
2109 break;
2110 case INDEX_op_or_i32:
2111 case INDEX_op_or_i64:
2112 tcg_out_alu(s, OPC_OR_A1, args[0], args[1], const_args[1],
2113 args[2], const_args[2]);
2114 break;
2115 case INDEX_op_orc_i32:
2116 case INDEX_op_orc_i64:
2117 tcg_out_orc(s, args[0], args[1], const_args[1],
2118 args[2], const_args[2]);
2119 break;
2120 case INDEX_op_xor_i32:
2121 case INDEX_op_xor_i64:
2122 tcg_out_alu(s, OPC_XOR_A1, args[0], args[1], const_args[1],
2123 args[2], const_args[2]);
2124 break;
2125
2126 case INDEX_op_mul_i32:
2127 case INDEX_op_mul_i64:
2128 tcg_out_mul(s, args[0], args[1], args[2]);
2129 break;
2130
2131 case INDEX_op_sar_i32:
2132 tcg_out_sar_i32(s, args[0], args[1], args[2], const_args[2]);
2133 break;
2134 case INDEX_op_sar_i64:
2135 tcg_out_sar_i64(s, args[0], args[1], args[2], const_args[2]);
2136 break;
2137 case INDEX_op_shl_i32:
2138 tcg_out_shl_i32(s, args[0], args[1], args[2], const_args[2]);
2139 break;
2140 case INDEX_op_shl_i64:
2141 tcg_out_shl_i64(s, args[0], args[1], args[2], const_args[2]);
2142 break;
2143 case INDEX_op_shr_i32:
2144 tcg_out_shr_i32(s, args[0], args[1], args[2], const_args[2]);
2145 break;
2146 case INDEX_op_shr_i64:
2147 tcg_out_shr_i64(s, args[0], args[1], args[2], const_args[2]);
2148 break;
2149 case INDEX_op_rotl_i32:
2150 tcg_out_rotl_i32(s, args[0], args[1], args[2], const_args[2]);
2151 break;
2152 case INDEX_op_rotl_i64:
2153 tcg_out_rotl_i64(s, args[0], args[1], args[2], const_args[2]);
2154 break;
2155 case INDEX_op_rotr_i32:
2156 tcg_out_rotr_i32(s, args[0], args[1], args[2], const_args[2]);
2157 break;
2158 case INDEX_op_rotr_i64:
2159 tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]);
2160 break;
2161
2162 case INDEX_op_ext8s_i32:
2163 case INDEX_op_ext8s_i64:
2164 tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]);
2165 break;
2166 case INDEX_op_ext8u_i32:
2167 case INDEX_op_ext8u_i64:
2168 tcg_out_ext(s, OPC_ZXT1_I29, args[0], args[1]);
2169 break;
2170 case INDEX_op_ext16s_i32:
2171 case INDEX_op_ext16s_i64:
2172 tcg_out_ext(s, OPC_SXT2_I29, args[0], args[1]);
2173 break;
2174 case INDEX_op_ext16u_i32:
2175 case INDEX_op_ext16u_i64:
2176 tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]);
2177 break;
2178 case INDEX_op_ext32s_i64:
2179 tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]);
2180 break;
2181 case INDEX_op_ext32u_i64:
2182 tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]);
2183 break;
2184
2185 case INDEX_op_bswap16_i32:
2186 case INDEX_op_bswap16_i64:
2187 tcg_out_bswap16(s, args[0], args[1]);
2188 break;
2189 case INDEX_op_bswap32_i32:
2190 case INDEX_op_bswap32_i64:
2191 tcg_out_bswap32(s, args[0], args[1]);
2192 break;
2193 case INDEX_op_bswap64_i64:
2194 tcg_out_bswap64(s, args[0], args[1]);
2195 break;
2196
c7d4475a
RH		 2197 case INDEX_op_deposit_i32:
2198 case INDEX_op_deposit_i64:
2199 tcg_out_deposit(s, args[0], args[1], args[2], const_args[2],
2200 args[3], args[4]);
2201 break;
2202
477ba620 2203 case INDEX_op_brcond_i32:
6d264b38 2204 tcg_out_brcond(s, args[2], args[0], args[1], args[3], 1);
477ba620
AJ		 2205 break;
2206 case INDEX_op_brcond_i64:
6d264b38 2207 tcg_out_brcond(s, args[2], args[0], args[1], args[3], 0);
477ba620
AJ		 2208 break;
2209 case INDEX_op_setcond_i32:
2210 tcg_out_setcond(s, args[3], args[0], args[1], args[2], 1);
2211 break;
2212 case INDEX_op_setcond_i64:
2213 tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0);
2214 break;
b90cf716
AJ		 2215 case INDEX_op_movcond_i32:
2216 tcg_out_movcond(s, args[5], args[0], args[1], args[2],
2217 args[3], const_args[3], args[4], const_args[4], 1);
2218 break;
2219 case INDEX_op_movcond_i64:
2220 tcg_out_movcond(s, args[5], args[0], args[1], args[2],
2221 args[3], const_args[3], args[4], const_args[4], 0);
2222 break;
477ba620
AJ		 2223
2224 case INDEX_op_qemu_ld8u:
e3afa1c4 2225 tcg_out_qemu_ld(s, args, MO_UB);
477ba620
AJ		 2226 break;
2227 case INDEX_op_qemu_ld8s:
e3afa1c4 2228 tcg_out_qemu_ld(s, args, MO_SB);
477ba620
AJ		 2229 break;
2230 case INDEX_op_qemu_ld16u:
e3afa1c4 2231 tcg_out_qemu_ld(s, args, MO_TEUW);
477ba620
AJ		 2232 break;
2233 case INDEX_op_qemu_ld16s:
e3afa1c4 2234 tcg_out_qemu_ld(s, args, MO_TESW);
477ba620 2235 break;
b3b0091f 2236 case INDEX_op_qemu_ld32:
477ba620 2237 case INDEX_op_qemu_ld32u:
e3afa1c4 2238 tcg_out_qemu_ld(s, args, MO_TEUL);
477ba620
AJ		 2239 break;
2240 case INDEX_op_qemu_ld32s:
e3afa1c4 2241 tcg_out_qemu_ld(s, args, MO_TESL);
477ba620
AJ		 2242 break;
2243 case INDEX_op_qemu_ld64:
e3afa1c4 2244 tcg_out_qemu_ld(s, args, MO_TEQ);
477ba620
AJ		 2245 break;
2246
2247 case INDEX_op_qemu_st8:
e3afa1c4 2248 tcg_out_qemu_st(s, args, MO_UB);
477ba620
AJ		 2249 break;
2250 case INDEX_op_qemu_st16:
e3afa1c4 2251 tcg_out_qemu_st(s, args, MO_TEUW);
477ba620
AJ		 2252 break;
2253 case INDEX_op_qemu_st32:
e3afa1c4 2254 tcg_out_qemu_st(s, args, MO_TEUL);
477ba620
AJ		 2255 break;
2256 case INDEX_op_qemu_st64:
e3afa1c4 2257 tcg_out_qemu_st(s, args, MO_TEQ);
477ba620
AJ		 2258 break;
2259
2260 default:
2261 tcg_abort();
2262 }
2263}
2264
2265static const TCGTargetOpDef ia64_op_defs[] = {
2266 { INDEX_op_br, { } },
6f65c780 2267 { INDEX_op_call, { "ri" } },
477ba620
AJ		 2268 { INDEX_op_exit_tb, { } },
2269 { INDEX_op_goto_tb, { } },
477ba620
AJ		 2270
2271 { INDEX_op_mov_i32, { "r", "r" } },
2272 { INDEX_op_movi_i32, { "r" } },
2273
2274 { INDEX_op_ld8u_i32, { "r", "r" } },
2275 { INDEX_op_ld8s_i32, { "r", "r" } },
2276 { INDEX_op_ld16u_i32, { "r", "r" } },
2277 { INDEX_op_ld16s_i32, { "r", "r" } },
2278 { INDEX_op_ld_i32, { "r", "r" } },
2279 { INDEX_op_st8_i32, { "rZ", "r" } },
2280 { INDEX_op_st16_i32, { "rZ", "r" } },
2281 { INDEX_op_st_i32, { "rZ", "r" } },
2282
2283 { INDEX_op_add_i32, { "r", "rI", "rI" } },
2284 { INDEX_op_sub_i32, { "r", "rI", "rI" } },
2285
2286 { INDEX_op_and_i32, { "r", "rI", "rI" } },
2287 { INDEX_op_andc_i32, { "r", "rI", "rI" } },
2288 { INDEX_op_eqv_i32, { "r", "rZ", "rZ" } },
2289 { INDEX_op_nand_i32, { "r", "rZ", "rZ" } },
2290 { INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
2291 { INDEX_op_or_i32, { "r", "rI", "rI" } },
2292 { INDEX_op_orc_i32, { "r", "rZ", "rZ" } },
2293 { INDEX_op_xor_i32, { "r", "rI", "rI" } },
2294
2295 { INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
2296
2297 { INDEX_op_sar_i32, { "r", "rZ", "ri" } },
2298 { INDEX_op_shl_i32, { "r", "rZ", "ri" } },
2299 { INDEX_op_shr_i32, { "r", "rZ", "ri" } },
2300 { INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
2301 { INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
2302
2303 { INDEX_op_ext8s_i32, { "r", "rZ"} },
2304 { INDEX_op_ext8u_i32, { "r", "rZ"} },
2305 { INDEX_op_ext16s_i32, { "r", "rZ"} },
2306 { INDEX_op_ext16u_i32, { "r", "rZ"} },
2307
2308 { INDEX_op_bswap16_i32, { "r", "rZ" } },
2309 { INDEX_op_bswap32_i32, { "r", "rZ" } },
2310
6d264b38 2311 { INDEX_op_brcond_i32, { "rZ", "rZ" } },
477ba620 2312 { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
b90cf716 2313 { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rI", "rI" } },
477ba620
AJ		 2314
2315 { INDEX_op_mov_i64, { "r", "r" } },
2316 { INDEX_op_movi_i64, { "r" } },
2317
2318 { INDEX_op_ld8u_i64, { "r", "r" } },
2319 { INDEX_op_ld8s_i64, { "r", "r" } },
2320 { INDEX_op_ld16u_i64, { "r", "r" } },
2321 { INDEX_op_ld16s_i64, { "r", "r" } },
2322 { INDEX_op_ld32u_i64, { "r", "r" } },
2323 { INDEX_op_ld32s_i64, { "r", "r" } },
2324 { INDEX_op_ld_i64, { "r", "r" } },
2325 { INDEX_op_st8_i64, { "rZ", "r" } },
2326 { INDEX_op_st16_i64, { "rZ", "r" } },
2327 { INDEX_op_st32_i64, { "rZ", "r" } },
2328 { INDEX_op_st_i64, { "rZ", "r" } },
2329
2330 { INDEX_op_add_i64, { "r", "rI", "rI" } },
2331 { INDEX_op_sub_i64, { "r", "rI", "rI" } },
2332
2333 { INDEX_op_and_i64, { "r", "rI", "rI" } },
2334 { INDEX_op_andc_i64, { "r", "rI", "rI" } },
2335 { INDEX_op_eqv_i64, { "r", "rZ", "rZ" } },
2336 { INDEX_op_nand_i64, { "r", "rZ", "rZ" } },
2337 { INDEX_op_nor_i64, { "r", "rZ", "rZ" } },
2338 { INDEX_op_or_i64, { "r", "rI", "rI" } },
2339 { INDEX_op_orc_i64, { "r", "rZ", "rZ" } },
2340 { INDEX_op_xor_i64, { "r", "rI", "rI" } },
2341
2342 { INDEX_op_mul_i64, { "r", "rZ", "rZ" } },
2343
2344 { INDEX_op_sar_i64, { "r", "rZ", "ri" } },
2345 { INDEX_op_shl_i64, { "r", "rZ", "ri" } },
2346 { INDEX_op_shr_i64, { "r", "rZ", "ri" } },
2347 { INDEX_op_rotl_i64, { "r", "rZ", "ri" } },
2348 { INDEX_op_rotr_i64, { "r", "rZ", "ri" } },
2349
2350 { INDEX_op_ext8s_i64, { "r", "rZ"} },
2351 { INDEX_op_ext8u_i64, { "r", "rZ"} },
2352 { INDEX_op_ext16s_i64, { "r", "rZ"} },
2353 { INDEX_op_ext16u_i64, { "r", "rZ"} },
2354 { INDEX_op_ext32s_i64, { "r", "rZ"} },
2355 { INDEX_op_ext32u_i64, { "r", "rZ"} },
2356
2357 { INDEX_op_bswap16_i64, { "r", "rZ" } },
2358 { INDEX_op_bswap32_i64, { "r", "rZ" } },
2359 { INDEX_op_bswap64_i64, { "r", "rZ" } },
2360
6d264b38 2361 { INDEX_op_brcond_i64, { "rZ", "rZ" } },
477ba620 2362 { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
b90cf716 2363 { INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rI", "rI" } },
477ba620 2364
c7d4475a
RH		 2365 { INDEX_op_deposit_i32, { "r", "rZ", "ri" } },
2366 { INDEX_op_deposit_i64, { "r", "rZ", "ri" } },
2367
477ba620
AJ		 2368 { INDEX_op_qemu_ld8u, { "r", "r" } },
2369 { INDEX_op_qemu_ld8s, { "r", "r" } },
2370 { INDEX_op_qemu_ld16u, { "r", "r" } },
2371 { INDEX_op_qemu_ld16s, { "r", "r" } },
2372 { INDEX_op_qemu_ld32, { "r", "r" } },
2373 { INDEX_op_qemu_ld32u, { "r", "r" } },
2374 { INDEX_op_qemu_ld32s, { "r", "r" } },
2375 { INDEX_op_qemu_ld64, { "r", "r" } },
2376
2377 { INDEX_op_qemu_st8, { "SZ", "r" } },
2378 { INDEX_op_qemu_st16, { "SZ", "r" } },
2379 { INDEX_op_qemu_st32, { "SZ", "r" } },
2380 { INDEX_op_qemu_st64, { "SZ", "r" } },
2381
2382 { -1 },
2383};
2384
2385/* Generate global QEMU prologue and epilogue code */
e4d58b41 2386static void tcg_target_qemu_prologue(TCGContext *s)
477ba620
AJ		 2387{
2388 int frame_size;
2389
2390 /* reserve some stack space */
da897bf5
BS		 2391 frame_size = TCG_STATIC_CALL_ARGS_SIZE +
2392 CPU_TEMP_BUF_NLONGS * sizeof(long);
477ba620
AJ		 2393 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
2394 ~(TCG_TARGET_STACK_ALIGN - 1);
da897bf5
BS		 2395 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
2396 CPU_TEMP_BUF_NLONGS * sizeof(long));
477ba620
AJ		 2397
2398 /* First emit adhoc function descriptor */
2399 *(uint64_t *)(s->code_ptr) = (uint64_t)s->code_ptr + 16; /* entry point */
2400 s->code_ptr += 16; /* skip GP */
2401
2402 /* prologue */
18d445b4 2403 tcg_out_bundle(s, miI,
477ba620 2404 tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34,
18d445b4 2405 TCG_REG_R34, 32, 24, 0),
d15de15c 2406 INSN_NOP_I,
477ba620 2407 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
18d445b4 2408 TCG_REG_B6, TCG_REG_R33, 0));
6781d08d
RH		 2409
2410 /* ??? If GUEST_BASE < 0x200000, we could load the register via
2411 an ADDL in the M slot of the next bundle. */
2412 if (GUEST_BASE != 0) {
2413 tcg_out_bundle(s, mlx,
5f7b1687 2414 INSN_NOP_M,
6781d08d
RH		 2415 tcg_opc_l2 (GUEST_BASE),
2416 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2,
2417 TCG_GUEST_BASE_REG, GUEST_BASE));
2418 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2419 }
2420
477ba620 2421 tcg_out_bundle(s, miB,
477ba620
AJ		 2422 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2423 TCG_REG_R12, -frame_size, TCG_REG_R12),
18d445b4 2424 tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22,
d15de15c 2425 TCG_REG_R33, TCG_REG_B0),
477ba620
AJ		 2426 tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
2427
2428 /* epilogue */
2429 tb_ret_addr = s->code_ptr;
2430 tcg_out_bundle(s, miI,
5f7b1687 2431 INSN_NOP_M,
477ba620 2432 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
d15de15c 2433 TCG_REG_B0, TCG_REG_R33, 0),
477ba620
AJ		 2434 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2435 TCG_REG_R12, frame_size, TCG_REG_R12));
2436 tcg_out_bundle(s, miB,
5f7b1687 2437 INSN_NOP_M,
477ba620 2438 tcg_opc_i26(TCG_REG_P0, OPC_MOV_I_I26,
18d445b4 2439 TCG_REG_PFS, TCG_REG_R34),
477ba620
AJ		 2440 tcg_opc_b4 (TCG_REG_P0, OPC_BR_RET_SPTK_MANY_B4,
2441 TCG_REG_B0));
2442}
2443
e4d58b41 2444static void tcg_target_init(TCGContext *s)
477ba620
AJ		 2445{
2446 tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32],
2447 0xffffffffffffffffull);
2448 tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64],
2449 0xffffffffffffffffull);
477ba620 2450
7221f058
RH		 2451 tcg_regset_clear(tcg_target_call_clobber_regs);
2452 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
2453 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
2454 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
2455 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
2456 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
2457 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R15);
2458 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R16);
2459 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R17);
2460 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R18);
2461 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R19);
2462 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R20);
2463 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R21);
2464 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R22);
2465 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R23);
2466 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R24);
2467 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R25);
2468 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R26);
2469 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R27);
2470 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R28);
2471 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R29);
2472 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R30);
2473 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R31);
2474 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R56);
2475 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R57);
2476 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R58);
2477 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R59);
2478 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R60);
2479 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R61);
2480 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R62);
2481 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R63);
2482
2483 tcg_regset_clear(s->reserved_regs);
477ba620
AJ		 2484 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* zero register */
2485 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* global pointer */
2486 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* internal use */
2487 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* internal use */
2488 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12); /* stack pointer */
7221f058 2489 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
d15de15c 2490 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R33); /* return address */
18d445b4 2491 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R34); /* PFS */
477ba620 2492
d15de15c 2493 /* The following 4 are not in use, are call-saved, but *not* saved
7221f058
RH		 2494 by the prologue. Therefore we cannot use them without modifying
2495 the prologue. There doesn't seem to be any good reason to use
2496 these as opposed to the windowed registers. */
2497 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R4);
2498 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R5);
2499 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6);
d15de15c 2500 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R7);
7221f058 2501
477ba620
AJ		 2502 tcg_add_target_add_op_defs(ia64_op_defs);
2503}
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