[qemu.git] / hw / char / cadence_uart.c

/*
 * Device model for Cadence UART
 *
 * Copyright (c) 2010 Xilinx Inc.
 * Copyright (c) 2012 Peter A.G. Crosthwaite ([email protected])
 * Copyright (c) 2012 PetaLogix Pty Ltd.
 * Written by Haibing Ma
 *            M.Habib
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "hw/sysbus.h"
#include "sysemu/char.h"
#include "qemu/timer.h"

#ifdef CADENCE_UART_ERR_DEBUG
#define DB_PRINT(...) do { \
    fprintf(stderr,  ": %s: ", __func__); \
    fprintf(stderr, ## __VA_ARGS__); \
    } while (0);
#else
    #define DB_PRINT(...)
#endif

#define UART_SR_INTR_RTRIG     0x00000001
#define UART_SR_INTR_REMPTY    0x00000002
#define UART_SR_INTR_RFUL      0x00000004
#define UART_SR_INTR_TEMPTY    0x00000008
#define UART_SR_INTR_TFUL      0x00000010
/* somewhat awkwardly, TTRIG is misaligned between SR and ISR */
#define UART_SR_TTRIG          0x00002000
#define UART_INTR_TTRIG        0x00000400
/* bits fields in CSR that correlate to CISR. If any of these bits are set in
 * SR, then the same bit in CISR is set high too */
#define UART_SR_TO_CISR_MASK   0x0000001F

#define UART_INTR_ROVR         0x00000020
#define UART_INTR_FRAME        0x00000040
#define UART_INTR_PARE         0x00000080
#define UART_INTR_TIMEOUT      0x00000100
#define UART_INTR_DMSI         0x00000200
#define UART_INTR_TOVR         0x00001000

#define UART_SR_RACTIVE    0x00000400
#define UART_SR_TACTIVE    0x00000800
#define UART_SR_FDELT      0x00001000

#define UART_CR_RXRST       0x00000001
#define UART_CR_TXRST       0x00000002
#define UART_CR_RX_EN       0x00000004
#define UART_CR_RX_DIS      0x00000008
#define UART_CR_TX_EN       0x00000010
#define UART_CR_TX_DIS      0x00000020
#define UART_CR_RST_TO      0x00000040
#define UART_CR_STARTBRK    0x00000080
#define UART_CR_STOPBRK     0x00000100

#define UART_MR_CLKS            0x00000001
#define UART_MR_CHRL            0x00000006
#define UART_MR_CHRL_SH         1
#define UART_MR_PAR             0x00000038
#define UART_MR_PAR_SH          3
#define UART_MR_NBSTOP          0x000000C0
#define UART_MR_NBSTOP_SH       6
#define UART_MR_CHMODE          0x00000300
#define UART_MR_CHMODE_SH       8
#define UART_MR_UCLKEN          0x00000400
#define UART_MR_IRMODE          0x00000800

#define UART_DATA_BITS_6       (0x3 << UART_MR_CHRL_SH)
#define UART_DATA_BITS_7       (0x2 << UART_MR_CHRL_SH)
#define UART_PARITY_ODD        (0x1 << UART_MR_PAR_SH)
#define UART_PARITY_EVEN       (0x0 << UART_MR_PAR_SH)
#define UART_STOP_BITS_1       (0x3 << UART_MR_NBSTOP_SH)
#define UART_STOP_BITS_2       (0x2 << UART_MR_NBSTOP_SH)
#define NORMAL_MODE            (0x0 << UART_MR_CHMODE_SH)
#define ECHO_MODE              (0x1 << UART_MR_CHMODE_SH)
#define LOCAL_LOOPBACK         (0x2 << UART_MR_CHMODE_SH)
#define REMOTE_LOOPBACK        (0x3 << UART_MR_CHMODE_SH)

#define RX_FIFO_SIZE           16
#define TX_FIFO_SIZE           16
#define UART_INPUT_CLK         50000000

#define R_CR       (0x00/4)
#define R_MR       (0x04/4)
#define R_IER      (0x08/4)
#define R_IDR      (0x0C/4)
#define R_IMR      (0x10/4)
#define R_CISR     (0x14/4)
#define R_BRGR     (0x18/4)
#define R_RTOR     (0x1C/4)
#define R_RTRIG    (0x20/4)
#define R_MCR      (0x24/4)
#define R_MSR      (0x28/4)
#define R_SR       (0x2C/4)
#define R_TX_RX    (0x30/4)
#define R_BDIV     (0x34/4)
#define R_FDEL     (0x38/4)
#define R_PMIN     (0x3C/4)
#define R_PWID     (0x40/4)
#define R_TTRIG    (0x44/4)

#define R_MAX (R_TTRIG + 1)

#define TYPE_CADENCE_UART "cadence_uart"
#define CADENCE_UART(obj) OBJECT_CHECK(UartState, (obj), TYPE_CADENCE_UART)

typedef struct {
    /*< private >*/
    SysBusDevice parent_obj;
    /*< public >*/

    MemoryRegion iomem;
    uint32_t r[R_MAX];
    uint8_t rx_fifo[RX_FIFO_SIZE];
    uint8_t tx_fifo[TX_FIFO_SIZE];
    uint32_t rx_wpos;
    uint32_t rx_count;
    uint32_t tx_count;
    uint64_t char_tx_time;
    CharDriverState *chr;
    qemu_irq irq;
    QEMUTimer *fifo_trigger_handle;
} UartState;

static void uart_update_status(UartState *s)
{
    s->r[R_SR] = 0;

    s->r[R_SR] |= s->rx_count == RX_FIFO_SIZE ? UART_SR_INTR_RFUL : 0;
    s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
    s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;

    s->r[R_SR] |= s->tx_count == TX_FIFO_SIZE ? UART_SR_INTR_TFUL : 0;
    s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
    s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;

    s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
    s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0;
    qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
}

static void fifo_trigger_update(void *opaque)
{
    UartState *s = (UartState *)opaque;

    s->r[R_CISR] |= UART_INTR_TIMEOUT;

    uart_update_status(s);
}

static void uart_rx_reset(UartState *s)
{
    s->rx_wpos = 0;
    s->rx_count = 0;
    if (s->chr) {
        qemu_chr_accept_input(s->chr);
    }
}

static void uart_tx_reset(UartState *s)
{
    s->tx_count = 0;
}

static void uart_send_breaks(UartState *s)
{
    int break_enabled = 1;

    qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
                               &break_enabled);
}

static void uart_parameters_setup(UartState *s)
{
    QEMUSerialSetParams ssp;
    unsigned int baud_rate, packet_size;

    baud_rate = (s->r[R_MR] & UART_MR_CLKS) ?
            UART_INPUT_CLK / 8 : UART_INPUT_CLK;

    ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
    packet_size = 1;

    switch (s->r[R_MR] & UART_MR_PAR) {
    case UART_PARITY_EVEN:
        ssp.parity = 'E';
        packet_size++;
        break;
    case UART_PARITY_ODD:
        ssp.parity = 'O';
        packet_size++;
        break;
    default:
        ssp.parity = 'N';
        break;
    }

    switch (s->r[R_MR] & UART_MR_CHRL) {
    case UART_DATA_BITS_6:
        ssp.data_bits = 6;
        break;
    case UART_DATA_BITS_7:
        ssp.data_bits = 7;
        break;
    default:
        ssp.data_bits = 8;
        break;
    }

    switch (s->r[R_MR] & UART_MR_NBSTOP) {
    case UART_STOP_BITS_1:
        ssp.stop_bits = 1;
        break;
    default:
        ssp.stop_bits = 2;
        break;
    }

    packet_size += ssp.data_bits + ssp.stop_bits;
    s->char_tx_time = (get_ticks_per_sec() / ssp.speed) * packet_size;
    qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}

static int uart_can_receive(void *opaque)
{
    UartState *s = (UartState *)opaque;
    int ret = MAX(RX_FIFO_SIZE, TX_FIFO_SIZE);
    uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;

    if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
        ret = MIN(ret, RX_FIFO_SIZE - s->rx_count);
    }
    if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
        ret = MIN(ret, TX_FIFO_SIZE - s->tx_count);
    }
    return ret;
}

static void uart_ctrl_update(UartState *s)
{
    if (s->r[R_CR] & UART_CR_TXRST) {
        uart_tx_reset(s);
    }

    if (s->r[R_CR] & UART_CR_RXRST) {
        uart_rx_reset(s);
    }

    s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);

    if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
        uart_send_breaks(s);
    }
}

static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
{
    UartState *s = (UartState *)opaque;
    uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
    int i;

    if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
        return;
    }

    if (s->rx_count == RX_FIFO_SIZE) {
        s->r[R_CISR] |= UART_INTR_ROVR;
    } else {
        for (i = 0; i < size; i++) {
            s->rx_fifo[s->rx_wpos] = buf[i];
            s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE;
            s->rx_count++;
        }
        timer_mod(s->fifo_trigger_handle, new_rx_time +
                                                (s->char_tx_time * 4));
    }
    uart_update_status(s);
}

static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size)
{
    if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
        return;
    }

    qemu_chr_fe_write_all(s->chr, buf, size);
}

static void uart_receive(void *opaque, const uint8_t *buf, int size)
{
    UartState *s = (UartState *)opaque;
    uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;

    if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
        uart_write_rx_fifo(opaque, buf, size);
    }
    if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
        uart_write_tx_fifo(s, buf, size);
    }
}

static void uart_event(void *opaque, int event)
{
    UartState *s = (UartState *)opaque;
    uint8_t buf = '\0';

    if (event == CHR_EVENT_BREAK) {
        uart_write_rx_fifo(opaque, &buf, 1);
    }

    uart_update_status(s);
}

static void uart_read_rx_fifo(UartState *s, uint32_t *c)
{
    if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
        return;
    }

    if (s->rx_count) {
        uint32_t rx_rpos =
                (RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE;
        *c = s->rx_fifo[rx_rpos];
        s->rx_count--;

        qemu_chr_accept_input(s->chr);
    } else {
        *c = 0;
    }

    uart_update_status(s);
}

static void uart_write(void *opaque, hwaddr offset,
                          uint64_t value, unsigned size)
{
    UartState *s = (UartState *)opaque;

    DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
    offset >>= 2;
    switch (offset) {
    case R_IER: /* ier (wts imr) */
        s->r[R_IMR] |= value;
        break;
    case R_IDR: /* idr (wtc imr) */
        s->r[R_IMR] &= ~value;
        break;
    case R_IMR: /* imr (read only) */
        break;
    case R_CISR: /* cisr (wtc) */
        s->r[R_CISR] &= ~value;
        break;
    case R_TX_RX: /* UARTDR */
        switch (s->r[R_MR] & UART_MR_CHMODE) {
        case NORMAL_MODE:
            uart_write_tx_fifo(s, (uint8_t *) &value, 1);
            break;
        case LOCAL_LOOPBACK:
            uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
            break;
        }
        break;
    default:
        s->r[offset] = value;
    }

    switch (offset) {
    case R_CR:
        uart_ctrl_update(s);
        break;
    case R_MR:
        uart_parameters_setup(s);
        break;
    }
    uart_update_status(s);
}

static uint64_t uart_read(void *opaque, hwaddr offset,
        unsigned size)
{
    UartState *s = (UartState *)opaque;
    uint32_t c = 0;

    offset >>= 2;
    if (offset >= R_MAX) {
        c = 0;
    } else if (offset == R_TX_RX) {
        uart_read_rx_fifo(s, &c);
    } else {
       c = s->r[offset];
    }

    DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
    return c;
}

static const MemoryRegionOps uart_ops = {
    .read = uart_read,
    .write = uart_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void cadence_uart_reset(DeviceState *dev)
{
    UartState *s = CADENCE_UART(dev);

    s->r[R_CR] = 0x00000128;
    s->r[R_IMR] = 0;
    s->r[R_CISR] = 0;
    s->r[R_RTRIG] = 0x00000020;
    s->r[R_BRGR] = 0x0000000F;
    s->r[R_TTRIG] = 0x00000020;

    uart_rx_reset(s);
    uart_tx_reset(s);

    s->rx_count = 0;
    s->rx_wpos = 0;
    uart_update_status(s);
}

static int cadence_uart_init(SysBusDevice *dev)
{
    UartState *s = CADENCE_UART(dev);

    memory_region_init_io(&s->iomem, OBJECT(s), &uart_ops, s, "uart", 0x1000);
    sysbus_init_mmio(dev, &s->iomem);
    sysbus_init_irq(dev, &s->irq);

    s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
            (QEMUTimerCB *)fifo_trigger_update, s);

    s->char_tx_time = (get_ticks_per_sec() / 9600) * 10;

    s->chr = qemu_char_get_next_serial();

    if (s->chr) {
        qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,
                              uart_event, s);
    }

    return 0;
}

static int cadence_uart_post_load(void *opaque, int version_id)
{
    UartState *s = opaque;

    uart_parameters_setup(s);
    uart_update_status(s);
    return 0;
}

static const VMStateDescription vmstate_cadence_uart = {
    .name = "cadence_uart",
    .version_id = 2,
    .minimum_version_id = 2,
    .minimum_version_id_old = 2,
    .post_load = cadence_uart_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(r, UartState, R_MAX),
        VMSTATE_UINT8_ARRAY(rx_fifo, UartState, RX_FIFO_SIZE),
        VMSTATE_UINT8_ARRAY(tx_fifo, UartState, RX_FIFO_SIZE),
        VMSTATE_UINT32(rx_count, UartState),
        VMSTATE_UINT32(tx_count, UartState),
        VMSTATE_UINT32(rx_wpos, UartState),
        VMSTATE_TIMER(fifo_trigger_handle, UartState),
        VMSTATE_END_OF_LIST()
    }
};

static void cadence_uart_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);

    sdc->init = cadence_uart_init;
    dc->vmsd = &vmstate_cadence_uart;
    dc->reset = cadence_uart_reset;
}

static const TypeInfo cadence_uart_info = {
    .name          = TYPE_CADENCE_UART,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(UartState),
    .class_init    = cadence_uart_class_init,
};

static void cadence_uart_register_types(void)
{
    type_register_static(&cadence_uart_info);
}

type_init(cadence_uart_register_types)
Commit	Line	Data
35548b06 PC	1	/*
	2	* Device model for Cadence UART
	3	*
	4	* Copyright (c) 2010 Xilinx Inc.
	5	* Copyright (c) 2012 Peter A.G. Crosthwaite ([email protected])
	6	* Copyright (c) 2012 PetaLogix Pty Ltd.
	7	* Written by Haibing Ma
	8	* M.Habib
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License
	12	* as published by the Free Software Foundation; either version
	13	* 2 of the License, or (at your option) any later version.
	14	*
	15	* You should have received a copy of the GNU General Public License along
	16	* with this program; if not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
83c9f4ca	19	#include "hw/sysbus.h"
dccfcd0e	20	#include "sysemu/char.h"
1de7afc9	21	#include "qemu/timer.h"
35548b06 PC	22
	23	#ifdef CADENCE_UART_ERR_DEBUG
	24	#define DB_PRINT(...) do { \
	25	fprintf(stderr, ": %s: ", __func__); \
	26	fprintf(stderr, ## __VA_ARGS__); \
	27	} while (0);
	28	#else
	29	#define DB_PRINT(...)
	30	#endif
	31
	32	#define UART_SR_INTR_RTRIG 0x00000001
	33	#define UART_SR_INTR_REMPTY 0x00000002
	34	#define UART_SR_INTR_RFUL 0x00000004
	35	#define UART_SR_INTR_TEMPTY 0x00000008
	36	#define UART_SR_INTR_TFUL 0x00000010
11a239a5 PC	37	/* somewhat awkwardly, TTRIG is misaligned between SR and ISR */
	38	#define UART_SR_TTRIG 0x00002000
	39	#define UART_INTR_TTRIG 0x00000400
35548b06 PC	40	/* bits fields in CSR that correlate to CISR. If any of these bits are set in
	41	* SR, then the same bit in CISR is set high too */
	42	#define UART_SR_TO_CISR_MASK 0x0000001F
	43
	44	#define UART_INTR_ROVR 0x00000020
	45	#define UART_INTR_FRAME 0x00000040
	46	#define UART_INTR_PARE 0x00000080
	47	#define UART_INTR_TIMEOUT 0x00000100
	48	#define UART_INTR_DMSI 0x00000200
11a239a5	49	#define UART_INTR_TOVR 0x00001000
35548b06 PC	50
	51	#define UART_SR_RACTIVE 0x00000400
	52	#define UART_SR_TACTIVE 0x00000800
	53	#define UART_SR_FDELT 0x00001000
	54
	55	#define UART_CR_RXRST 0x00000001
	56	#define UART_CR_TXRST 0x00000002
	57	#define UART_CR_RX_EN 0x00000004
	58	#define UART_CR_RX_DIS 0x00000008
	59	#define UART_CR_TX_EN 0x00000010
	60	#define UART_CR_TX_DIS 0x00000020
	61	#define UART_CR_RST_TO 0x00000040
	62	#define UART_CR_STARTBRK 0x00000080
	63	#define UART_CR_STOPBRK 0x00000100
	64
	65	#define UART_MR_CLKS 0x00000001
	66	#define UART_MR_CHRL 0x00000006
	67	#define UART_MR_CHRL_SH 1
	68	#define UART_MR_PAR 0x00000038
	69	#define UART_MR_PAR_SH 3
	70	#define UART_MR_NBSTOP 0x000000C0
	71	#define UART_MR_NBSTOP_SH 6
	72	#define UART_MR_CHMODE 0x00000300
	73	#define UART_MR_CHMODE_SH 8
	74	#define UART_MR_UCLKEN 0x00000400
	75	#define UART_MR_IRMODE 0x00000800
	76
	77	#define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH)
	78	#define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH)
	79	#define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH)
	80	#define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH)
	81	#define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH)
	82	#define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH)
	83	#define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH)
	84	#define ECHO_MODE (0x1 << UART_MR_CHMODE_SH)
	85	#define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
	86	#define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
	87
	88	#define RX_FIFO_SIZE 16
	89	#define TX_FIFO_SIZE 16
	90	#define UART_INPUT_CLK 50000000
	91
	92	#define R_CR (0x00/4)
	93	#define R_MR (0x04/4)
	94	#define R_IER (0x08/4)
	95	#define R_IDR (0x0C/4)
	96	#define R_IMR (0x10/4)
	97	#define R_CISR (0x14/4)
	98	#define R_BRGR (0x18/4)
	99	#define R_RTOR (0x1C/4)
	100	#define R_RTRIG (0x20/4)
	101	#define R_MCR (0x24/4)
	102	#define R_MSR (0x28/4)
	103	#define R_SR (0x2C/4)
	104	#define R_TX_RX (0x30/4)
	105	#define R_BDIV (0x34/4)
	106	#define R_FDEL (0x38/4)
	107	#define R_PMIN (0x3C/4)
	108	#define R_PWID (0x40/4)
	109	#define R_TTRIG (0x44/4)
	110
	111	#define R_MAX (R_TTRIG + 1)
	112
534f6ff9 AF	113	#define TYPE_CADENCE_UART "cadence_uart"
	114	#define CADENCE_UART(obj) OBJECT_CHECK(UartState, (obj), TYPE_CADENCE_UART)
	115
35548b06	116	typedef struct {
059ca2bf	117	/< private >/
534f6ff9	118	SysBusDevice parent_obj;
059ca2bf	119	/< public >/
534f6ff9	120
35548b06 PC	121	MemoryRegion iomem;
35548b06 PC	122	uint32_t r[R_MAX];
1e77c91e	123	uint8_t rx_fifo[RX_FIFO_SIZE];
2152e08a	124	uint8_t tx_fifo[TX_FIFO_SIZE];
35548b06 PC	125	uint32_t rx_wpos;
35548b06 PC	126	uint32_t rx_count;
2152e08a	127	uint32_t tx_count;
35548b06 PC	128	uint64_t char_tx_time;
	129	CharDriverState *chr;
	130	qemu_irq irq;
1246b259	131	QEMUTimer *fifo_trigger_handle;
35548b06 PC	132	} UartState;
	133
	134	static void uart_update_status(UartState *s)
	135	{
676f4c09 PC	136	s->r[R_SR] = 0;
	137
	138	s->r[R_SR] \|= s->rx_count == RX_FIFO_SIZE ? UART_SR_INTR_RFUL : 0;
	139	s->r[R_SR] \|= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
	140	s->r[R_SR] \|= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;
	141
2152e08a PC	142	s->r[R_SR] \|= s->tx_count == TX_FIFO_SIZE ? UART_SR_INTR_TFUL : 0;
	143	s->r[R_SR] \|= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
	144	s->r[R_SR] \|= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;
	145
35548b06	146	s->r[R_CISR] \|= s->r[R_SR] & UART_SR_TO_CISR_MASK;
2152e08a	147	s->r[R_CISR] \|= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0;
35548b06 PC	148	qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
	149	}
	150
	151	static void fifo_trigger_update(void *opaque)
	152	{
	153	UartState s = (UartState )opaque;
	154
	155	s->r[R_CISR] \|= UART_INTR_TIMEOUT;
	156
	157	uart_update_status(s);
	158	}
	159
35548b06 PC	160	static void uart_rx_reset(UartState *s)
	161	{
	162	s->rx_wpos = 0;
	163	s->rx_count = 0;
9121d02c PC	164	if (s->chr) {
	165	qemu_chr_accept_input(s->chr);
	166	}
35548b06 PC	167	}
	168
	169	static void uart_tx_reset(UartState *s)
	170	{
2152e08a	171	s->tx_count = 0;
35548b06 PC	172	}
	173
	174	static void uart_send_breaks(UartState *s)
	175	{
	176	int break_enabled = 1;
	177
	178	qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
	179	&break_enabled);
	180	}
	181
	182	static void uart_parameters_setup(UartState *s)
	183	{
	184	QEMUSerialSetParams ssp;
	185	unsigned int baud_rate, packet_size;
	186
	187	baud_rate = (s->r[R_MR] & UART_MR_CLKS) ?
	188	UART_INPUT_CLK / 8 : UART_INPUT_CLK;
	189
	190	ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
	191	packet_size = 1;
	192
	193	switch (s->r[R_MR] & UART_MR_PAR) {
	194	case UART_PARITY_EVEN:
	195	ssp.parity = 'E';
	196	packet_size++;
	197	break;
	198	case UART_PARITY_ODD:
	199	ssp.parity = 'O';
	200	packet_size++;
	201	break;
	202	default:
	203	ssp.parity = 'N';
	204	break;
	205	}
	206
	207	switch (s->r[R_MR] & UART_MR_CHRL) {
	208	case UART_DATA_BITS_6:
	209	ssp.data_bits = 6;
	210	break;
	211	case UART_DATA_BITS_7:
	212	ssp.data_bits = 7;
	213	break;
	214	default:
	215	ssp.data_bits = 8;
	216	break;
	217	}
	218
	219	switch (s->r[R_MR] & UART_MR_NBSTOP) {
	220	case UART_STOP_BITS_1:
	221	ssp.stop_bits = 1;
	222	break;
	223	default:
	224	ssp.stop_bits = 2;
	225	break;
	226	}
	227
	228	packet_size += ssp.data_bits + ssp.stop_bits;
	229	s->char_tx_time = (get_ticks_per_sec() / ssp.speed) * packet_size;
	230	qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
	231	}
	232
	233	static int uart_can_receive(void *opaque)
	234	{
	235	UartState s = (UartState )opaque;
d0ac820f PC	236	int ret = MAX(RX_FIFO_SIZE, TX_FIFO_SIZE);
d0ac820f PC	237	uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
35548b06	238
d0ac820f PC	239	if (ch_mode == NORMAL_MODE \|\| ch_mode == ECHO_MODE) {
	240	ret = MIN(ret, RX_FIFO_SIZE - s->rx_count);
	241	}
	242	if (ch_mode == REMOTE_LOOPBACK \|\| ch_mode == ECHO_MODE) {
	243	ret = MIN(ret, TX_FIFO_SIZE - s->tx_count);
	244	}
	245	return ret;
35548b06 PC	246	}
	247
	248	static void uart_ctrl_update(UartState *s)
	249	{
	250	if (s->r[R_CR] & UART_CR_TXRST) {
	251	uart_tx_reset(s);
	252	}
	253
	254	if (s->r[R_CR] & UART_CR_RXRST) {
	255	uart_rx_reset(s);
	256	}
	257
	258	s->r[R_CR] &= ~(UART_CR_TXRST \| UART_CR_RXRST);
	259
35548b06 PC	260	if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
	261	uart_send_breaks(s);
	262	}
	263	}
	264
	265	static void uart_write_rx_fifo(void opaque, const uint8_t buf, int size)
	266	{
	267	UartState s = (UartState )opaque;
bc72ad67	268	uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
35548b06 PC	269	int i;
	270
	271	if ((s->r[R_CR] & UART_CR_RX_DIS) \|\| !(s->r[R_CR] & UART_CR_RX_EN)) {
	272	return;
	273	}
	274
35548b06 PC	275	if (s->rx_count == RX_FIFO_SIZE) {
	276	s->r[R_CISR] \|= UART_INTR_ROVR;
	277	} else {
	278	for (i = 0; i < size; i++) {
1e77c91e	279	s->rx_fifo[s->rx_wpos] = buf[i];
35548b06 PC	280	s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE;
35548b06 PC	281	s->rx_count++;
35548b06	282	}
bc72ad67	283	timer_mod(s->fifo_trigger_handle, new_rx_time +
35548b06 PC	284	(s->char_tx_time * 4));
	285	}
	286	uart_update_status(s);
	287	}
	288
	289	static void uart_write_tx_fifo(UartState s, const uint8_t buf, int size)
	290	{
	291	if ((s->r[R_CR] & UART_CR_TX_DIS) \|\| !(s->r[R_CR] & UART_CR_TX_EN)) {
	292	return;
	293	}
	294
b52df465	295	qemu_chr_fe_write_all(s->chr, buf, size);
35548b06 PC	296	}
	297
	298	static void uart_receive(void opaque, const uint8_t buf, int size)
	299	{
	300	UartState s = (UartState )opaque;
	301	uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
	302
	303	if (ch_mode == NORMAL_MODE \|\| ch_mode == ECHO_MODE) {
	304	uart_write_rx_fifo(opaque, buf, size);
	305	}
	306	if (ch_mode == REMOTE_LOOPBACK \|\| ch_mode == ECHO_MODE) {
	307	uart_write_tx_fifo(s, buf, size);
	308	}
	309	}
	310
	311	static void uart_event(void *opaque, int event)
	312	{
	313	UartState s = (UartState )opaque;
	314	uint8_t buf = '\0';
	315
	316	if (event == CHR_EVENT_BREAK) {
	317	uart_write_rx_fifo(opaque, &buf, 1);
	318	}
	319
	320	uart_update_status(s);
	321	}
	322
	323	static void uart_read_rx_fifo(UartState s, uint32_t c)
	324	{
	325	if ((s->r[R_CR] & UART_CR_RX_DIS) \|\| !(s->r[R_CR] & UART_CR_RX_EN)) {
	326	return;
	327	}
	328
35548b06 PC	329	if (s->rx_count) {
	330	uint32_t rx_rpos =
	331	(RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE;
1e77c91e	332	*c = s->rx_fifo[rx_rpos];
35548b06 PC	333	s->rx_count--;
35548b06 PC	334
9893c80d	335	qemu_chr_accept_input(s->chr);
35548b06 PC	336	} else {
35548b06 PC	337	*c = 0;
35548b06 PC	338	}
35548b06 PC	339
35548b06 PC	340	uart_update_status(s);
	341	}
	342
a8170e5e	343	static void uart_write(void *opaque, hwaddr offset,
35548b06 PC	344	uint64_t value, unsigned size)
	345	{
	346	UartState s = (UartState )opaque;
	347
2ddef11b	348	DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
35548b06 PC	349	offset >>= 2;
	350	switch (offset) {
	351	case R_IER: /* ier (wts imr) */
	352	s->r[R_IMR] \|= value;
	353	break;
	354	case R_IDR: /* idr (wtc imr) */
	355	s->r[R_IMR] &= ~value;
	356	break;
	357	case R_IMR: /* imr (read only) */
	358	break;
	359	case R_CISR: /* cisr (wtc) */
	360	s->r[R_CISR] &= ~value;
	361	break;
	362	case R_TX_RX: /* UARTDR */
	363	switch (s->r[R_MR] & UART_MR_CHMODE) {
	364	case NORMAL_MODE:
	365	uart_write_tx_fifo(s, (uint8_t *) &value, 1);
	366	break;
	367	case LOCAL_LOOPBACK:
	368	uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
	369	break;
	370	}
	371	break;
	372	default:
	373	s->r[offset] = value;
	374	}
	375
	376	switch (offset) {
	377	case R_CR:
	378	uart_ctrl_update(s);
	379	break;
	380	case R_MR:
	381	uart_parameters_setup(s);
	382	break;
	383	}
589bfb68	384	uart_update_status(s);
35548b06 PC	385	}
35548b06 PC	386
a8170e5e	387	static uint64_t uart_read(void *opaque, hwaddr offset,
35548b06 PC	388	unsigned size)
	389	{
	390	UartState s = (UartState )opaque;
	391	uint32_t c = 0;
	392
	393	offset >>= 2;
5d40097f	394	if (offset >= R_MAX) {
2ddef11b	395	c = 0;
35548b06 PC	396	} else if (offset == R_TX_RX) {
35548b06 PC	397	uart_read_rx_fifo(s, &c);
2ddef11b PC	398	} else {
2ddef11b PC	399	c = s->r[offset];
35548b06	400	}
2ddef11b PC	401
	402	DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
	403	return c;
35548b06 PC	404	}
	405
	406	static const MemoryRegionOps uart_ops = {
	407	.read = uart_read,
	408	.write = uart_write,
	409	.endianness = DEVICE_NATIVE_ENDIAN,
	410	};
	411
823dd487	412	static void cadence_uart_reset(DeviceState *dev)
35548b06	413	{
823dd487 PC	414	UartState *s = CADENCE_UART(dev);
823dd487 PC	415
35548b06 PC	416	s->r[R_CR] = 0x00000128;
	417	s->r[R_IMR] = 0;
	418	s->r[R_CISR] = 0;
	419	s->r[R_RTRIG] = 0x00000020;
	420	s->r[R_BRGR] = 0x0000000F;
	421	s->r[R_TTRIG] = 0x00000020;
	422
	423	uart_rx_reset(s);
	424	uart_tx_reset(s);
	425
	426	s->rx_count = 0;
	427	s->rx_wpos = 0;
676f4c09	428	uart_update_status(s);
35548b06 PC	429	}
	430
	431	static int cadence_uart_init(SysBusDevice *dev)
	432	{
534f6ff9	433	UartState *s = CADENCE_UART(dev);
35548b06	434
300b1fc6	435	memory_region_init_io(&s->iomem, OBJECT(s), &uart_ops, s, "uart", 0x1000);
35548b06 PC	436	sysbus_init_mmio(dev, &s->iomem);
	437	sysbus_init_irq(dev, &s->irq);
	438
bc72ad67	439	s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
35548b06 PC	440	(QEMUTimerCB *)fifo_trigger_update, s);
35548b06 PC	441
35548b06 PC	442	s->char_tx_time = (get_ticks_per_sec() / 9600) * 10;
	443
	444	s->chr = qemu_char_get_next_serial();
	445
35548b06 PC	446	if (s->chr) {
	447	qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,
	448	uart_event, s);
	449	}
	450
	451	return 0;
	452	}
	453
	454	static int cadence_uart_post_load(void *opaque, int version_id)
	455	{
	456	UartState *s = opaque;
	457
	458	uart_parameters_setup(s);
	459	uart_update_status(s);
	460	return 0;
	461	}
	462
	463	static const VMStateDescription vmstate_cadence_uart = {
	464	.name = "cadence_uart",
2152e08a PC	465	.version_id = 2,
	466	.minimum_version_id = 2,
	467	.minimum_version_id_old = 2,
35548b06 PC	468	.post_load = cadence_uart_post_load,
	469	.fields = (VMStateField[]) {
	470	VMSTATE_UINT32_ARRAY(r, UartState, R_MAX),
1e77c91e	471	VMSTATE_UINT8_ARRAY(rx_fifo, UartState, RX_FIFO_SIZE),
2152e08a	472	VMSTATE_UINT8_ARRAY(tx_fifo, UartState, RX_FIFO_SIZE),
35548b06	473	VMSTATE_UINT32(rx_count, UartState),
2152e08a	474	VMSTATE_UINT32(tx_count, UartState),
35548b06 PC	475	VMSTATE_UINT32(rx_wpos, UartState),
35548b06 PC	476	VMSTATE_TIMER(fifo_trigger_handle, UartState),
35548b06 PC	477	VMSTATE_END_OF_LIST()
	478	}
	479	};
	480
	481	static void cadence_uart_class_init(ObjectClass klass, void data)
	482	{
	483	DeviceClass *dc = DEVICE_CLASS(klass);
	484	SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
	485
	486	sdc->init = cadence_uart_init;
	487	dc->vmsd = &vmstate_cadence_uart;
823dd487	488	dc->reset = cadence_uart_reset;
35548b06 PC	489	}
35548b06 PC	490
8c43a6f0	491	static const TypeInfo cadence_uart_info = {
534f6ff9	492	.name = TYPE_CADENCE_UART,
35548b06 PC	493	.parent = TYPE_SYS_BUS_DEVICE,
	494	.instance_size = sizeof(UartState),
	495	.class_init = cadence_uart_class_init,
	496	};
	497
	498	static void cadence_uart_register_types(void)
	499	{
	500	type_register_static(&cadence_uart_info);
	501	}
	502
	503	type_init(cadence_uart_register_types)