[qemu.git] / hw / mst_fpga.c

/*
 * PXA270-based Intel Mainstone platforms.
 * FPGA driver
 *
 * Copyright (c) 2007 by Armin Kuster <[email protected]> or
 *                                    <[email protected]>
 *
 * This code is licensed under the GNU GPL v2.
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */
#include "hw/hw.h"
#include "hw/sysbus.h"

/* Mainstone FPGA for extern irqs */
#define FPGA_GPIO_PIN	0
#define MST_NUM_IRQS	16
#define MST_LEDDAT1		0x10
#define MST_LEDDAT2		0x14
#define MST_LEDCTRL		0x40
#define MST_GPSWR		0x60
#define MST_MSCWR1		0x80
#define MST_MSCWR2		0x84
#define MST_MSCWR3		0x88
#define MST_MSCRD		0x90
#define MST_INTMSKENA	0xc0
#define MST_INTSETCLR	0xd0
#define MST_PCMCIA0		0xe0
#define MST_PCMCIA1		0xe4

#define MST_PCMCIAx_READY	(1 << 10)
#define MST_PCMCIAx_nCD		(1 << 5)

#define MST_PCMCIA_CD0_IRQ	9
#define MST_PCMCIA_CD1_IRQ	13

typedef struct mst_irq_state{
	SysBusDevice busdev;
	MemoryRegion iomem;

	qemu_irq parent;

	uint32_t prev_level;
	uint32_t leddat1;
	uint32_t leddat2;
	uint32_t ledctrl;
	uint32_t gpswr;
	uint32_t mscwr1;
	uint32_t mscwr2;
	uint32_t mscwr3;
	uint32_t mscrd;
	uint32_t intmskena;
	uint32_t intsetclr;
	uint32_t pcmcia0;
	uint32_t pcmcia1;
}mst_irq_state;

static void
mst_fpga_set_irq(void *opaque, int irq, int level)
{
	mst_irq_state *s = (mst_irq_state *)opaque;
	uint32_t oldint = s->intsetclr & s->intmskena;

	if (level)
		s->prev_level |= 1u << irq;
	else
		s->prev_level &= ~(1u << irq);

	switch(irq) {
	case MST_PCMCIA_CD0_IRQ:
		if (level)
			s->pcmcia0 &= ~MST_PCMCIAx_nCD;
		else
			s->pcmcia0 |=  MST_PCMCIAx_nCD;
		break;
	case MST_PCMCIA_CD1_IRQ:
		if (level)
			s->pcmcia1 &= ~MST_PCMCIAx_nCD;
		else
			s->pcmcia1 |=  MST_PCMCIAx_nCD;
		break;
	}

	if ((s->intmskena & (1u << irq)) && level)
		s->intsetclr |= 1u << irq;

	if (oldint != (s->intsetclr & s->intmskena))
		qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
}


static uint64_t
mst_fpga_readb(void *opaque, hwaddr addr, unsigned size)
{
	mst_irq_state *s = (mst_irq_state *) opaque;

	switch (addr) {
	case MST_LEDDAT1:
		return s->leddat1;
	case MST_LEDDAT2:
		return s->leddat2;
	case MST_LEDCTRL:
		return s->ledctrl;
	case MST_GPSWR:
		return s->gpswr;
	case MST_MSCWR1:
		return s->mscwr1;
	case MST_MSCWR2:
		return s->mscwr2;
	case MST_MSCWR3:
		return s->mscwr3;
	case MST_MSCRD:
		return s->mscrd;
	case MST_INTMSKENA:
		return s->intmskena;
	case MST_INTSETCLR:
		return s->intsetclr;
	case MST_PCMCIA0:
		return s->pcmcia0;
	case MST_PCMCIA1:
		return s->pcmcia1;
	default:
		printf("Mainstone - mst_fpga_readb: Bad register offset "
			"0x" TARGET_FMT_plx "\n", addr);
	}
	return 0;
}

static void
mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
		unsigned size)
{
	mst_irq_state *s = (mst_irq_state *) opaque;
	value &= 0xffffffff;

	switch (addr) {
	case MST_LEDDAT1:
		s->leddat1 = value;
		break;
	case MST_LEDDAT2:
		s->leddat2 = value;
		break;
	case MST_LEDCTRL:
		s->ledctrl = value;
		break;
	case MST_GPSWR:
		s->gpswr = value;
		break;
	case MST_MSCWR1:
		s->mscwr1 = value;
		break;
	case MST_MSCWR2:
		s->mscwr2 = value;
		break;
	case MST_MSCWR3:
		s->mscwr3 = value;
		break;
	case MST_MSCRD:
		s->mscrd =  value;
		break;
	case MST_INTMSKENA:	/* Mask interrupt */
		s->intmskena = (value & 0xFEEFF);
		qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
		break;
	case MST_INTSETCLR:	/* clear or set interrupt */
		s->intsetclr = (value & 0xFEEFF);
		qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
		break;
		/* For PCMCIAx allow the to change only power and reset */
	case MST_PCMCIA0:
		s->pcmcia0 = (value & 0x1f) | (s->pcmcia0 & ~0x1f);
		break;
	case MST_PCMCIA1:
		s->pcmcia1 = (value & 0x1f) | (s->pcmcia1 & ~0x1f);
		break;
	default:
		printf("Mainstone - mst_fpga_writeb: Bad register offset "
			"0x" TARGET_FMT_plx "\n", addr);
	}
}

static const MemoryRegionOps mst_fpga_ops = {
	.read = mst_fpga_readb,
	.write = mst_fpga_writeb,
	.endianness = DEVICE_NATIVE_ENDIAN,
};

static int mst_fpga_post_load(void *opaque, int version_id)
{
	mst_irq_state *s = (mst_irq_state *) opaque;

	qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
	return 0;
}

static int mst_fpga_init(SysBusDevice *dev)
{
	mst_irq_state *s;

	s = FROM_SYSBUS(mst_irq_state, dev);

	s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
	s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;

	sysbus_init_irq(dev, &s->parent);

	/* alloc the external 16 irqs */
	qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);

	memory_region_init_io(&s->iomem, &mst_fpga_ops, s,
			    "fpga", 0x00100000);
	sysbus_init_mmio(dev, &s->iomem);
	return 0;
}

static VMStateDescription vmstate_mst_fpga_regs = {
	.name = "mainstone_fpga",
	.version_id = 0,
	.minimum_version_id = 0,
	.minimum_version_id_old = 0,
	.post_load = mst_fpga_post_load,
	.fields = (VMStateField []) {
		VMSTATE_UINT32(prev_level, mst_irq_state),
		VMSTATE_UINT32(leddat1, mst_irq_state),
		VMSTATE_UINT32(leddat2, mst_irq_state),
		VMSTATE_UINT32(ledctrl, mst_irq_state),
		VMSTATE_UINT32(gpswr, mst_irq_state),
		VMSTATE_UINT32(mscwr1, mst_irq_state),
		VMSTATE_UINT32(mscwr2, mst_irq_state),
		VMSTATE_UINT32(mscwr3, mst_irq_state),
		VMSTATE_UINT32(mscrd, mst_irq_state),
		VMSTATE_UINT32(intmskena, mst_irq_state),
		VMSTATE_UINT32(intsetclr, mst_irq_state),
		VMSTATE_UINT32(pcmcia0, mst_irq_state),
		VMSTATE_UINT32(pcmcia1, mst_irq_state),
		VMSTATE_END_OF_LIST(),
	},
};

static void mst_fpga_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = mst_fpga_init;
    dc->desc = "Mainstone II FPGA";
    dc->vmsd = &vmstate_mst_fpga_regs;
}

static const TypeInfo mst_fpga_info = {
    .name          = "mainstone-fpga",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(mst_irq_state),
    .class_init    = mst_fpga_class_init,
};

static void mst_fpga_register_types(void)
{
    type_register_static(&mst_fpga_info);
}

type_init(mst_fpga_register_types)
Commit	Line	Data
7233b355 TS	1	/*
	2	* PXA270-based Intel Mainstone platforms.
	3	* FPGA driver
	4	*
	5	* Copyright (c) 2007 by Armin Kuster <[email protected]> or
	6	* <[email protected]>
	7	*
	8	* This code is licensed under the GNU GPL v2.
6b620ca3 PB	9	*
	10	* Contributions after 2012-01-13 are licensed under the terms of the
	11	* GNU GPL, version 2 or (at your option) any later version.
7233b355	12	*/
83c9f4ca PB	13	#include "hw/hw.h"
83c9f4ca PB	14	#include "hw/sysbus.h"
7233b355 TS	15
	16	/* Mainstone FPGA for extern irqs */
	17	#define FPGA_GPIO_PIN 0
	18	#define MST_NUM_IRQS 16
7233b355 TS	19	#define MST_LEDDAT1 0x10
	20	#define MST_LEDDAT2 0x14
	21	#define MST_LEDCTRL 0x40
	22	#define MST_GPSWR 0x60
	23	#define MST_MSCWR1 0x80
	24	#define MST_MSCWR2 0x84
	25	#define MST_MSCWR3 0x88
	26	#define MST_MSCRD 0x90
	27	#define MST_INTMSKENA 0xc0
	28	#define MST_INTSETCLR 0xd0
	29	#define MST_PCMCIA0 0xe0
	30	#define MST_PCMCIA1 0xe4
	31
b651fc6f DES	32	#define MST_PCMCIAx_READY (1 << 10)
	33	#define MST_PCMCIAx_nCD (1 << 5)
	34
	35	#define MST_PCMCIA_CD0_IRQ 9
	36	#define MST_PCMCIA_CD1_IRQ 13
	37
7233b355	38	typedef struct mst_irq_state{
cb380f61	39	SysBusDevice busdev;
b9441ebb	40	MemoryRegion iomem;
cb380f61	41
bb70651e	42	qemu_irq parent;
7233b355 TS	43
	44	uint32_t prev_level;
	45	uint32_t leddat1;
	46	uint32_t leddat2;
	47	uint32_t ledctrl;
	48	uint32_t gpswr;
	49	uint32_t mscwr1;
	50	uint32_t mscwr2;
	51	uint32_t mscwr3;
	52	uint32_t mscrd;
	53	uint32_t intmskena;
	54	uint32_t intsetclr;
	55	uint32_t pcmcia0;
	56	uint32_t pcmcia1;
	57	}mst_irq_state;
	58
7233b355 TS	59	static void
	60	mst_fpga_set_irq(void *opaque, int irq, int level)
	61	{
	62	mst_irq_state s = (mst_irq_state )opaque;
3e1dbc3b	63	uint32_t oldint = s->intsetclr & s->intmskena;
7233b355 TS	64
	65	if (level)
	66	s->prev_level \|= 1u << irq;
	67	else
	68	s->prev_level &= ~(1u << irq);
	69
b651fc6f DES	70	switch(irq) {
	71	case MST_PCMCIA_CD0_IRQ:
	72	if (level)
	73	s->pcmcia0 &= ~MST_PCMCIAx_nCD;
	74	else
	75	s->pcmcia0 \|= MST_PCMCIAx_nCD;
	76	break;
	77	case MST_PCMCIA_CD1_IRQ:
	78	if (level)
	79	s->pcmcia1 &= ~MST_PCMCIAx_nCD;
	80	else
	81	s->pcmcia1 \|= MST_PCMCIAx_nCD;
	82	break;
	83	}
	84
43d91709 DES	85	if ((s->intmskena & (1u << irq)) && level)
	86	s->intsetclr \|= 1u << irq;
	87
	88	if (oldint != (s->intsetclr & s->intmskena))
	89	qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
7233b355 TS	90	}
	91
	92
b9441ebb	93	static uint64_t
a8170e5e	94	mst_fpga_readb(void *opaque, hwaddr addr, unsigned size)
7233b355 TS	95	{
7233b355 TS	96	mst_irq_state s = (mst_irq_state ) opaque;
7233b355 TS	97
	98	switch (addr) {
	99	case MST_LEDDAT1:
	100	return s->leddat1;
	101	case MST_LEDDAT2:
	102	return s->leddat2;
	103	case MST_LEDCTRL:
	104	return s->ledctrl;
	105	case MST_GPSWR:
	106	return s->gpswr;
	107	case MST_MSCWR1:
	108	return s->mscwr1;
	109	case MST_MSCWR2:
	110	return s->mscwr2;
	111	case MST_MSCWR3:
	112	return s->mscwr3;
	113	case MST_MSCRD:
	114	return s->mscrd;
	115	case MST_INTMSKENA:
	116	return s->intmskena;
	117	case MST_INTSETCLR:
	118	return s->intsetclr;
	119	case MST_PCMCIA0:
	120	return s->pcmcia0;
	121	case MST_PCMCIA1:
	122	return s->pcmcia1;
	123	default:
	124	printf("Mainstone - mst_fpga_readb: Bad register offset "
b2bedb21	125	"0x" TARGET_FMT_plx "\n", addr);
7233b355 TS	126	}
	127	return 0;
	128	}
	129
	130	static void
a8170e5e	131	mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
b9441ebb	132	unsigned size)
7233b355 TS	133	{
7233b355 TS	134	mst_irq_state s = (mst_irq_state ) opaque;
7233b355 TS	135	value &= 0xffffffff;
	136
	137	switch (addr) {
	138	case MST_LEDDAT1:
	139	s->leddat1 = value;
	140	break;
	141	case MST_LEDDAT2:
	142	s->leddat2 = value;
	143	break;
	144	case MST_LEDCTRL:
	145	s->ledctrl = value;
	146	break;
	147	case MST_GPSWR:
	148	s->gpswr = value;
	149	break;
	150	case MST_MSCWR1:
	151	s->mscwr1 = value;
	152	break;
	153	case MST_MSCWR2:
	154	s->mscwr2 = value;
	155	break;
	156	case MST_MSCWR3:
	157	s->mscwr3 = value;
	158	break;
	159	case MST_MSCRD:
	160	s->mscrd = value;
	161	break;
ff2712ba	162	case MST_INTMSKENA: /* Mask interrupt */
7233b355	163	s->intmskena = (value & 0xFEEFF);
43d91709	164	qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
7233b355 TS	165	break;
	166	case MST_INTSETCLR: /* clear or set interrupt */
	167	s->intsetclr = (value & 0xFEEFF);
3e1dbc3b	168	qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
7233b355	169	break;
b651fc6f	170	/* For PCMCIAx allow the to change only power and reset */
7233b355	171	case MST_PCMCIA0:
b651fc6f	172	s->pcmcia0 = (value & 0x1f) \| (s->pcmcia0 & ~0x1f);
7233b355 TS	173	break;
7233b355 TS	174	case MST_PCMCIA1:
b651fc6f	175	s->pcmcia1 = (value & 0x1f) \| (s->pcmcia1 & ~0x1f);
7233b355 TS	176	break;
	177	default:
	178	printf("Mainstone - mst_fpga_writeb: Bad register offset "
b2bedb21	179	"0x" TARGET_FMT_plx "\n", addr);
7233b355 TS	180	}
	181	}
	182
b9441ebb BC	183	static const MemoryRegionOps mst_fpga_ops = {
	184	.read = mst_fpga_readb,
	185	.write = mst_fpga_writeb,
	186	.endianness = DEVICE_NATIVE_ENDIAN,
7233b355	187	};
7233b355	188
cb380f61	189	static int mst_fpga_post_load(void *opaque, int version_id)
7233b355 TS	190	{
	191	mst_irq_state s = (mst_irq_state ) opaque;
	192
43d91709	193	qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
7233b355 TS	194	return 0;
	195	}
	196
cb380f61	197	static int mst_fpga_init(SysBusDevice *dev)
7233b355 TS	198	{
7233b355 TS	199	mst_irq_state *s;
7233b355	200
cb380f61	201	s = FROM_SYSBUS(mst_irq_state, dev);
7233b355	202
b651fc6f DES	203	s->pcmcia0 = MST_PCMCIAx_READY \| MST_PCMCIAx_nCD;
	204	s->pcmcia1 = MST_PCMCIAx_READY \| MST_PCMCIAx_nCD;
	205
cb380f61	206	sysbus_init_irq(dev, &s->parent);
7233b355 TS	207
7233b355 TS	208	/* alloc the external 16 irqs */
cb380f61	209	qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);
7233b355	210
b9441ebb BC	211	memory_region_init_io(&s->iomem, &mst_fpga_ops, s,
b9441ebb BC	212	"fpga", 0x00100000);
750ecd44	213	sysbus_init_mmio(dev, &s->iomem);
cb380f61 DES	214	return 0;
	215	}
	216
	217	static VMStateDescription vmstate_mst_fpga_regs = {
	218	.name = "mainstone_fpga",
	219	.version_id = 0,
	220	.minimum_version_id = 0,
	221	.minimum_version_id_old = 0,
	222	.post_load = mst_fpga_post_load,
	223	.fields = (VMStateField []) {
	224	VMSTATE_UINT32(prev_level, mst_irq_state),
	225	VMSTATE_UINT32(leddat1, mst_irq_state),
	226	VMSTATE_UINT32(leddat2, mst_irq_state),
	227	VMSTATE_UINT32(ledctrl, mst_irq_state),
	228	VMSTATE_UINT32(gpswr, mst_irq_state),
	229	VMSTATE_UINT32(mscwr1, mst_irq_state),
	230	VMSTATE_UINT32(mscwr2, mst_irq_state),
	231	VMSTATE_UINT32(mscwr3, mst_irq_state),
	232	VMSTATE_UINT32(mscrd, mst_irq_state),
	233	VMSTATE_UINT32(intmskena, mst_irq_state),
	234	VMSTATE_UINT32(intsetclr, mst_irq_state),
	235	VMSTATE_UINT32(pcmcia0, mst_irq_state),
	236	VMSTATE_UINT32(pcmcia1, mst_irq_state),
	237	VMSTATE_END_OF_LIST(),
	238	},
	239	};
	240
999e12bb AL	241	static void mst_fpga_class_init(ObjectClass klass, void data)
999e12bb AL	242	{
39bffca2	243	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	244	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	245
	246	k->init = mst_fpga_init;
39bffca2 AL	247	dc->desc = "Mainstone II FPGA";
39bffca2 AL	248	dc->vmsd = &vmstate_mst_fpga_regs;
999e12bb AL	249	}
999e12bb AL	250
8c43a6f0	251	static const TypeInfo mst_fpga_info = {
39bffca2 AL	252	.name = "mainstone-fpga",
	253	.parent = TYPE_SYS_BUS_DEVICE,
	254	.instance_size = sizeof(mst_irq_state),
	255	.class_init = mst_fpga_class_init,
cb380f61 DES	256	};
cb380f61 DES	257
83f7d43a	258	static void mst_fpga_register_types(void)
cb380f61	259	{
39bffca2	260	type_register_static(&mst_fpga_info);
7233b355	261	}
83f7d43a AF	262
83f7d43a AF	263	type_init(mst_fpga_register_types)