]> Git Repo - qemu.git/blame - hw/arm/nseries.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Allow clock_gettime() monotonic clock to be utilized on more OS's
[qemu.git] / hw / arm / nseries.c
CommitLineData
7e7c5e4c
AZ		 1/*
2 * Nokia N-series internet tablets.
3 *
4 * Copyright (C) 2007 Nokia Corporation
5 * Written by Andrzej Zaborowski <[email protected]>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
fad6cb1a 17 * You should have received a copy of the GNU General Public License along
8167ee88 18 * with this program; if not, see <http://www.gnu.org/licenses/>.
7e7c5e4c
AZ		 19 */
20
21#include "qemu-common.h"
9c17d615 22#include "sysemu/sysemu.h"
83c9f4ca
PB		 23#include "hw/omap.h"
24#include "hw/arm-misc.h"
25#include "hw/irq.h"
28ecbaee 26#include "ui/console.h"
83c9f4ca
PB		 27#include "hw/boards.h"
28#include "hw/i2c.h"
29#include "hw/devices.h"
30#include "hw/flash.h"
31#include "hw/hw.h"
32#include "hw/bt.h"
33#include "hw/loader.h"
9c17d615 34#include "sysemu/blockdev.h"
83c9f4ca 35#include "hw/sysbus.h"
022c62cb 36#include "exec/address-spaces.h"
7e7c5e4c
AZ		 37
38/* Nokia N8x0 support */
39struct n800_s {
518ec134 40 struct omap_mpu_state_s *mpu;
7e7c5e4c
AZ		 41
42 struct rfbi_chip_s blizzard;
e927bb00
AZ		 43 struct {
44 void *opaque;
45 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
bc24a225 46 uWireSlave *chip;
e927bb00 47 } ts;
7e7c5e4c
AZ		 48
49 int keymap[0x80];
c4f05c8c 50 DeviceState *kbd;
7e7c5e4c 51
bdc76462 52 DeviceState *usb;
7e7c5e4c
AZ		 53 void *retu;
54 void *tahvo;
500954e3 55 DeviceState *nand;
7e7c5e4c
AZ		 56};
57
58/* GPIO pins */
e927bb00 59#define N8X0_TUSB_ENABLE_GPIO 0
7e7c5e4c
AZ		 60#define N800_MMC2_WP_GPIO 8
61#define N800_UNKNOWN_GPIO0 9 /* out */
0941041e 62#define N810_MMC2_VIOSD_GPIO 9
99570a40 63#define N810_HEADSET_AMP_GPIO 10
7e7c5e4c 64#define N800_CAM_TURN_GPIO 12
e927bb00 65#define N810_GPS_RESET_GPIO 12
7e7c5e4c
AZ		 66#define N800_BLIZZARD_POWERDOWN_GPIO 15
67#define N800_MMC1_WP_GPIO 23
0941041e 68#define N810_MMC2_VSD_GPIO 23
7e7c5e4c 69#define N8X0_ONENAND_GPIO 26
e927bb00 70#define N810_BLIZZARD_RESET_GPIO 30
7e7c5e4c
AZ		 71#define N800_UNKNOWN_GPIO2 53 /* out */
72#define N8X0_TUSB_INT_GPIO 58
e927bb00
AZ		 73#define N8X0_BT_WKUP_GPIO 61
74#define N8X0_STI_GPIO 62
7e7c5e4c 75#define N8X0_CBUS_SEL_GPIO 64
e927bb00
AZ		 76#define N8X0_CBUS_DAT_GPIO 65
77#define N8X0_CBUS_CLK_GPIO 66
78#define N8X0_WLAN_IRQ_GPIO 87
79#define N8X0_BT_RESET_GPIO 92
80#define N8X0_TEA5761_CS_GPIO 93
7e7c5e4c 81#define N800_UNKNOWN_GPIO 94
e927bb00 82#define N810_TSC_RESET_GPIO 94
7e7c5e4c 83#define N800_CAM_ACT_GPIO 95
e927bb00
AZ		 84#define N810_GPS_WAKEUP_GPIO 95
85#define N8X0_MMC_CS_GPIO 96
86#define N8X0_WLAN_PWR_GPIO 97
7e7c5e4c 87#define N8X0_BT_HOST_WKUP_GPIO 98
99570a40 88#define N810_SPEAKER_AMP_GPIO 101
7e7c5e4c
AZ		 89#define N810_KB_LOCK_GPIO 102
90#define N800_TSC_TS_GPIO 103
e927bb00
AZ		 91#define N810_TSC_TS_GPIO 106
92#define N8X0_HEADPHONE_GPIO 107
7e7c5e4c
AZ		 93#define N8X0_RETU_GPIO 108
94#define N800_TSC_KP_IRQ_GPIO 109
95#define N810_KEYBOARD_GPIO 109
96#define N800_BAT_COVER_GPIO 110
97#define N810_SLIDE_GPIO 110
98#define N8X0_TAHVO_GPIO 111
99#define N800_UNKNOWN_GPIO4 112 /* out */
e927bb00 100#define N810_SLEEPX_LED_GPIO 112
1d4e547b 101#define N800_TSC_RESET_GPIO 118 /* ? */
99570a40 102#define N810_AIC33_RESET_GPIO 118
1d4e547b 103#define N800_TSC_UNKNOWN_GPIO 119 /* out */
7e7c5e4c
AZ		 104#define N8X0_TMP105_GPIO 125
105
106/* Config */
c580d92b 107#define BT_UART 0
7e7c5e4c
AZ		 108#define XLDR_LL_UART 1
109
1d4e547b
AZ		 110/* Addresses on the I2C bus 0 */
111#define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
112#define N8X0_TCM825x_ADDR 0x29 /* Camera */
113#define N810_LP5521_ADDR 0x32 /* LEDs */
114#define N810_TSL2563_ADDR 0x3d /* Light sensor */
115#define N810_LM8323_ADDR 0x45 /* Keyboard */
116/* Addresses on the I2C bus 1 */
117#define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
118#define N8X0_MENELAUS_ADDR 0x72 /* Power management */
7e7c5e4c
AZ		 119
120/* Chipselects on GPMC NOR interface */
121#define N8X0_ONENAND_CS 0
122#define N8X0_USB_ASYNC_CS 1
123#define N8X0_USB_SYNC_CS 4
124
c580d92b
AZ		 125#define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
126
7e7c5e4c
AZ		 127static void n800_mmc_cs_cb(void *opaque, int line, int level)
128{
129 /* TODO: this seems to actually be connected to the menelaus, to
130 * which also both MMC slots connect. */
131 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
132
133 printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1);
134}
135
e927bb00 136static void n8x0_gpio_setup(struct n800_s *s)
7e7c5e4c 137{
518ec134
AF		 138 qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->mpu->mmc, 1);
139 qdev_connect_gpio_out(s->mpu->gpio, N8X0_MMC_CS_GPIO, mmc_cs[0]);
7e7c5e4c 140
518ec134 141 qemu_irq_lower(qdev_get_gpio_in(s->mpu->gpio, N800_BAT_COVER_GPIO));
7e7c5e4c
AZ		 142}
143
c580d92b
AZ		 144#define MAEMO_CAL_HEADER(...) \
145 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
146 __VA_ARGS__, \
147 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
148
149static const uint8_t n8x0_cal_wlan_mac[] = {
150 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
151 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
152 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
153 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
154 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
155 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
156};
157
158static const uint8_t n8x0_cal_bt_id[] = {
159 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
160 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
161 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
162 N8X0_BD_ADDR,
163};
164
7e7c5e4c
AZ		 165static void n8x0_nand_setup(struct n800_s *s)
166{
c580d92b 167 char *otp_region;
af5a75f4 168 DriveInfo *dinfo;
c580d92b 169
500954e3
JR		 170 s->nand = qdev_create(NULL, "onenand");
171 qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
5923ba42 172 /* Either 0x40 or 0x48 are OK for the device ID */
500954e3
JR		 173 qdev_prop_set_uint16(s->nand, "device_id", 0x48);
174 qdev_prop_set_uint16(s->nand, "version_id", 0);
175 qdev_prop_set_int32(s->nand, "shift", 1);
176 dinfo = drive_get(IF_MTD, 0, 0);
177 if (dinfo && dinfo->bdrv) {
178 qdev_prop_set_drive_nofail(s->nand, "drive", dinfo->bdrv);
179 }
180 qdev_init_nofail(s->nand);
1356b98d 181 sysbus_connect_irq(SYS_BUS_DEVICE(s->nand), 0,
518ec134
AF		 182 qdev_get_gpio_in(s->mpu->gpio, N8X0_ONENAND_GPIO));
183 omap_gpmc_attach(s->mpu->gpmc, N8X0_ONENAND_CS,
1356b98d 184 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->nand), 0));
c580d92b
AZ		 185 otp_region = onenand_raw_otp(s->nand);
186
187 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
188 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
189 /* XXX: in theory should also update the OOB for both pages */
7e7c5e4c
AZ		 190}
191
c72ddb1e
IM		 192static qemu_irq n8x0_system_powerdown;
193
194static void n8x0_powerdown_req(Notifier *n, void *opaque)
195{
196 qemu_irq_raise(n8x0_system_powerdown);
197}
198
199static Notifier n8x0_system_powerdown_notifier = {
200 .notify = n8x0_powerdown_req
201};
202
e927bb00 203static void n8x0_i2c_setup(struct n800_s *s)
7e7c5e4c 204{
697454eb 205 DeviceState *dev;
518ec134
AF		 206 qemu_irq tmp_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TMP105_GPIO);
207 i2c_bus *i2c = omap_i2c_bus(s->mpu->i2c[0]);
7e7c5e4c
AZ		 208
209 /* Attach a menelaus PM chip */
54e17933 210 dev = i2c_create_slave(i2c, "twl92230", N8X0_MENELAUS_ADDR);
0919ac78 211 qdev_connect_gpio_out(dev, 3,
518ec134 212 qdev_get_gpio_in(s->mpu->ih[0],
0919ac78 213 OMAP_INT_24XX_SYS_NIRQ));
7e7c5e4c 214
c72ddb1e
IM		 215 n8x0_system_powerdown = qdev_get_gpio_in(dev, 3);
216 qemu_register_powerdown_notifier(&n8x0_system_powerdown_notifier);
dd4427a6 217
7e7c5e4c 218 /* Attach a TMP105 PM chip (A0 wired to ground) */
54e17933 219 dev = i2c_create_slave(i2c, "tmp105", N8X0_TMP105_ADDR);
697454eb 220 qdev_connect_gpio_out(dev, 0, tmp_irq);
7e7c5e4c
AZ		 221}
222
223/* Touchscreen and keypad controller */
bc24a225 224static MouseTransformInfo n800_pointercal = {
e927bb00
AZ		 225 .x = 800,
226 .y = 480,
227 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
228};
229
bc24a225 230static MouseTransformInfo n810_pointercal = {
e927bb00
AZ		 231 .x = 800,
232 .y = 480,
233 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
234};
235
7e7c5e4c
AZ		 236#define RETU_KEYCODE 61 /* F3 */
237
238static void n800_key_event(void *opaque, int keycode)
239{
240 struct n800_s *s = (struct n800_s *) opaque;
241 int code = s->keymap[keycode & 0x7f];
242
243 if (code == -1) {
244 if ((keycode & 0x7f) == RETU_KEYCODE)
245 retu_key_event(s->retu, !(keycode & 0x80));
246 return;
247 }
248
e927bb00 249 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
7e7c5e4c
AZ		 250}
251
252static const int n800_keys[16] = {
253 -1,
254 72, /* Up */
255 63, /* Home (F5) */
256 -1,
257 75, /* Left */
258 28, /* Enter */
259 77, /* Right */
260 -1,
1d4e547b 261 1, /* Cycle (ESC) */
7e7c5e4c
AZ		 262 80, /* Down */
263 62, /* Menu (F4) */
264 -1,
265 66, /* Zoom- (F8) */
1d4e547b 266 64, /* FullScreen (F6) */
7e7c5e4c
AZ		 267 65, /* Zoom+ (F7) */
268 -1,
269};
270
e927bb00 271static void n800_tsc_kbd_setup(struct n800_s *s)
7e7c5e4c
AZ		 272{
273 int i;
274
275 /* XXX: are the three pins inverted inside the chip between the
276 * tsc and the cpu (N4111)? */
b9d38e95 277 qemu_irq penirq = NULL; /* NC */
518ec134
AF		 278 qemu_irq kbirq = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_KP_IRQ_GPIO);
279 qemu_irq dav = qdev_get_gpio_in(s->mpu->gpio, N800_TSC_TS_GPIO);
7e7c5e4c 280
22d83b14 281 s->ts.chip = tsc2301_init(penirq, kbirq, dav);
e927bb00
AZ		 282 s->ts.opaque = s->ts.chip->opaque;
283 s->ts.txrx = tsc210x_txrx;
7e7c5e4c
AZ		 284
285 for (i = 0; i < 0x80; i ++)
286 s->keymap[i] = -1;
287 for (i = 0; i < 0x10; i ++)
288 if (n800_keys[i] >= 0)
289 s->keymap[n800_keys[i]] = i;
290
291 qemu_add_kbd_event_handler(n800_key_event, s);
292
e927bb00
AZ		 293 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
294}
295
296static void n810_tsc_setup(struct n800_s *s)
297{
518ec134 298 qemu_irq pintdav = qdev_get_gpio_in(s->mpu->gpio, N810_TSC_TS_GPIO);
e927bb00
AZ		 299
300 s->ts.opaque = tsc2005_init(pintdav);
301 s->ts.txrx = tsc2005_txrx;
302
303 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
7e7c5e4c
AZ		 304}
305
1d4e547b
AZ		 306/* N810 Keyboard controller */
307static void n810_key_event(void *opaque, int keycode)
308{
309 struct n800_s *s = (struct n800_s *) opaque;
310 int code = s->keymap[keycode & 0x7f];
311
312 if (code == -1) {
313 if ((keycode & 0x7f) == RETU_KEYCODE)
314 retu_key_event(s->retu, !(keycode & 0x80));
315 return;
316 }
317
318 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
319}
320
321#define M 0
322
323static int n810_keys[0x80] = {
324 [0x01] = 16, /* Q */
325 [0x02] = 37, /* K */
326 [0x03] = 24, /* O */
327 [0x04] = 25, /* P */
328 [0x05] = 14, /* Backspace */
329 [0x06] = 30, /* A */
330 [0x07] = 31, /* S */
331 [0x08] = 32, /* D */
332 [0x09] = 33, /* F */
333 [0x0a] = 34, /* G */
334 [0x0b] = 35, /* H */
335 [0x0c] = 36, /* J */
336
337 [0x11] = 17, /* W */
338 [0x12] = 62, /* Menu (F4) */
339 [0x13] = 38, /* L */
340 [0x14] = 40, /* ' (Apostrophe) */
341 [0x16] = 44, /* Z */
342 [0x17] = 45, /* X */
343 [0x18] = 46, /* C */
344 [0x19] = 47, /* V */
345 [0x1a] = 48, /* B */
346 [0x1b] = 49, /* N */
347 [0x1c] = 42, /* Shift (Left shift) */
348 [0x1f] = 65, /* Zoom+ (F7) */
349
350 [0x21] = 18, /* E */
351 [0x22] = 39, /* ; (Semicolon) */
352 [0x23] = 12, /* - (Minus) */
353 [0x24] = 13, /* = (Equal) */
354 [0x2b] = 56, /* Fn (Left Alt) */
355 [0x2c] = 50, /* M */
356 [0x2f] = 66, /* Zoom- (F8) */
357
358 [0x31] = 19, /* R */
359 [0x32] = 29 | M, /* Right Ctrl */
360 [0x34] = 57, /* Space */
361 [0x35] = 51, /* , (Comma) */
362 [0x37] = 72 | M, /* Up */
363 [0x3c] = 82 | M, /* Compose (Insert) */
364 [0x3f] = 64, /* FullScreen (F6) */
365
366 [0x41] = 20, /* T */
367 [0x44] = 52, /* . (Dot) */
368 [0x46] = 77 | M, /* Right */
369 [0x4f] = 63, /* Home (F5) */
370 [0x51] = 21, /* Y */
371 [0x53] = 80 | M, /* Down */
372 [0x55] = 28, /* Enter */
373 [0x5f] = 1, /* Cycle (ESC) */
374
375 [0x61] = 22, /* U */
376 [0x64] = 75 | M, /* Left */
377
378 [0x71] = 23, /* I */
379#if 0
380 [0x75] = 28 | M, /* KP Enter (KP Enter) */
381#else
382 [0x75] = 15, /* KP Enter (Tab) */
383#endif
384};
385
386#undef M
387
388static void n810_kbd_setup(struct n800_s *s)
389{
518ec134 390 qemu_irq kbd_irq = qdev_get_gpio_in(s->mpu->gpio, N810_KEYBOARD_GPIO);
1d4e547b
AZ		 391 int i;
392
393 for (i = 0; i < 0x80; i ++)
394 s->keymap[i] = -1;
395 for (i = 0; i < 0x80; i ++)
396 if (n810_keys[i] > 0)
397 s->keymap[n810_keys[i]] = i;
398
399 qemu_add_kbd_event_handler(n810_key_event, s);
400
401 /* Attach the LM8322 keyboard to the I2C bus,
402 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */
518ec134 403 s->kbd = i2c_create_slave(omap_i2c_bus(s->mpu->i2c[0]),
54e17933 404 "lm8323", N810_LM8323_ADDR);
c4f05c8c 405 qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
1d4e547b
AZ		 406}
407
7e7c5e4c
AZ		 408/* LCD MIPI DBI-C controller (URAL) */
409struct mipid_s {
410 int resp[4];
411 int param[4];
412 int p;
413 int pm;
414 int cmd;
415
416 int sleep;
417 int booster;
418 int te;
419 int selfcheck;
420 int partial;
421 int normal;
422 int vscr;
423 int invert;
424 int onoff;
425 int gamma;
426 uint32_t id;
427};
428
429static void mipid_reset(struct mipid_s *s)
430{
431 if (!s->sleep)
432 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
433
434 s->pm = 0;
435 s->cmd = 0;
436
437 s->sleep = 1;
438 s->booster = 0;
439 s->selfcheck =
440 (1 << 7) | /* Register loading OK. */
441 (1 << 5) | /* The chip is attached. */
442 (1 << 4); /* Display glass still in one piece. */
443 s->te = 0;
444 s->partial = 0;
445 s->normal = 1;
446 s->vscr = 0;
447 s->invert = 0;
448 s->onoff = 1;
449 s->gamma = 0;
450}
451
e927bb00 452static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
7e7c5e4c
AZ		 453{
454 struct mipid_s *s = (struct mipid_s *) opaque;
455 uint8_t ret;
456
e927bb00 457 if (len > 9)
2ac71179 458 hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
e927bb00 459
b1503cda 460 if (s->p >= ARRAY_SIZE(s->resp))
7e7c5e4c
AZ		 461 ret = 0;
462 else
463 ret = s->resp[s->p ++];
464 if (s->pm --> 0)
465 s->param[s->pm] = cmd;
466 else
467 s->cmd = cmd;
468
469 switch (s->cmd) {
470 case 0x00: /* NOP */
471 break;
472
473 case 0x01: /* SWRESET */
474 mipid_reset(s);
475 break;
476
477 case 0x02: /* BSTROFF */
478 s->booster = 0;
479 break;
480 case 0x03: /* BSTRON */
481 s->booster = 1;
482 break;
483
484 case 0x04: /* RDDID */
485 s->p = 0;
486 s->resp[0] = (s->id >> 16) & 0xff;
487 s->resp[1] = (s->id >> 8) & 0xff;
488 s->resp[2] = (s->id >> 0) & 0xff;
489 break;
490
491 case 0x06: /* RD_RED */
492 case 0x07: /* RD_GREEN */
493 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
494 * for the bootloader one needs to change this. */
495 case 0x08: /* RD_BLUE */
496 s->p = 0;
497 /* TODO: return first pixel components */
498 s->resp[0] = 0x01;
499 break;
500
501 case 0x09: /* RDDST */
502 s->p = 0;
503 s->resp[0] = s->booster << 7;
504 s->resp[1] = (5 << 4) | (s->partial << 2) |
505 (s->sleep << 1) | s->normal;
506 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
507 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
508 s->resp[3] = s->gamma << 6;
509 break;
510
511 case 0x0a: /* RDDPM */
512 s->p = 0;
513 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
514 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
515 break;
516 case 0x0b: /* RDDMADCTR */
517 s->p = 0;
518 s->resp[0] = 0;
519 break;
520 case 0x0c: /* RDDCOLMOD */
521 s->p = 0;
522 s->resp[0] = 5; /* 65K colours */
523 break;
524 case 0x0d: /* RDDIM */
525 s->p = 0;
526 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
527 break;
528 case 0x0e: /* RDDSM */
529 s->p = 0;
530 s->resp[0] = s->te << 7;
531 break;
532 case 0x0f: /* RDDSDR */
533 s->p = 0;
534 s->resp[0] = s->selfcheck;
535 break;
536
537 case 0x10: /* SLPIN */
538 s->sleep = 1;
539 break;
540 case 0x11: /* SLPOUT */
541 s->sleep = 0;
542 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
543 break;
544
545 case 0x12: /* PTLON */
546 s->partial = 1;
547 s->normal = 0;
548 s->vscr = 0;
549 break;
550 case 0x13: /* NORON */
551 s->partial = 0;
552 s->normal = 1;
553 s->vscr = 0;
554 break;
555
556 case 0x20: /* INVOFF */
557 s->invert = 0;
558 break;
559 case 0x21: /* INVON */
560 s->invert = 1;
561 break;
562
563 case 0x22: /* APOFF */
564 case 0x23: /* APON */
565 goto bad_cmd;
566
567 case 0x25: /* WRCNTR */
568 if (s->pm < 0)
569 s->pm = 1;
570 goto bad_cmd;
571
572 case 0x26: /* GAMSET */
573 if (!s->pm)
574 s->gamma = ffs(s->param[0] & 0xf) - 1;
575 else if (s->pm < 0)
576 s->pm = 1;
577 break;
578
579 case 0x28: /* DISPOFF */
580 s->onoff = 0;
581 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
582 break;
583 case 0x29: /* DISPON */
584 s->onoff = 1;
585 fprintf(stderr, "%s: Display on\n", __FUNCTION__);
586 break;
587
588 case 0x2a: /* CASET */
589 case 0x2b: /* RASET */
590 case 0x2c: /* RAMWR */
591 case 0x2d: /* RGBSET */
592 case 0x2e: /* RAMRD */
593 case 0x30: /* PTLAR */
594 case 0x33: /* SCRLAR */
595 goto bad_cmd;
596
597 case 0x34: /* TEOFF */
598 s->te = 0;
599 break;
600 case 0x35: /* TEON */
601 if (!s->pm)
602 s->te = 1;
603 else if (s->pm < 0)
604 s->pm = 1;
605 break;
606
607 case 0x36: /* MADCTR */
608 goto bad_cmd;
609
610 case 0x37: /* VSCSAD */
611 s->partial = 0;
612 s->normal = 0;
613 s->vscr = 1;
614 break;
615
616 case 0x38: /* IDMOFF */
617 case 0x39: /* IDMON */
618 case 0x3a: /* COLMOD */
619 goto bad_cmd;
620
621 case 0xb0: /* CLKINT / DISCTL */
622 case 0xb1: /* CLKEXT */
623 if (s->pm < 0)
624 s->pm = 2;
625 break;
626
627 case 0xb4: /* FRMSEL */
628 break;
629
630 case 0xb5: /* FRM8SEL */
631 case 0xb6: /* TMPRNG / INIESC */
632 case 0xb7: /* TMPHIS / NOP2 */
633 case 0xb8: /* TMPREAD / MADCTL */
634 case 0xba: /* DISTCTR */
635 case 0xbb: /* EPVOL */
636 goto bad_cmd;
637
638 case 0xbd: /* Unknown */
639 s->p = 0;
640 s->resp[0] = 0;
641 s->resp[1] = 1;
642 break;
643
644 case 0xc2: /* IFMOD */
645 if (s->pm < 0)
646 s->pm = 2;
647 break;
648
649 case 0xc6: /* PWRCTL */
650 case 0xc7: /* PPWRCTL */
651 case 0xd0: /* EPWROUT */
652 case 0xd1: /* EPWRIN */
653 case 0xd4: /* RDEV */
654 case 0xd5: /* RDRR */
655 goto bad_cmd;
656
657 case 0xda: /* RDID1 */
658 s->p = 0;
659 s->resp[0] = (s->id >> 16) & 0xff;
660 break;
661 case 0xdb: /* RDID2 */
662 s->p = 0;
663 s->resp[0] = (s->id >> 8) & 0xff;
664 break;
665 case 0xdc: /* RDID3 */
666 s->p = 0;
667 s->resp[0] = (s->id >> 0) & 0xff;
668 break;
669
670 default:
671 bad_cmd:
672 fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd);
673 break;
674 }
675
676 return ret;
677}
678
679static void *mipid_init(void)
680{
7267c094 681 struct mipid_s *s = (struct mipid_s *) g_malloc0(sizeof(*s));
7e7c5e4c
AZ		 682
683 s->id = 0x838f03;
684 mipid_reset(s);
685
686 return s;
687}
688
e927bb00 689static void n8x0_spi_setup(struct n800_s *s)
7e7c5e4c 690{
e927bb00 691 void *tsc = s->ts.opaque;
7e7c5e4c
AZ		 692 void *mipid = mipid_init();
693
518ec134
AF		 694 omap_mcspi_attach(s->mpu->mcspi[0], s->ts.txrx, tsc, 0);
695 omap_mcspi_attach(s->mpu->mcspi[0], mipid_txrx, mipid, 1);
7e7c5e4c
AZ		 696}
697
698/* This task is normally performed by the bootloader. If we're loading
699 * a kernel directly, we need to enable the Blizzard ourselves. */
700static void n800_dss_init(struct rfbi_chip_s *chip)
701{
702 uint8_t *fb_blank;
703
704 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
705 chip->write(chip->opaque, 1, 0x64);
706 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
707 chip->write(chip->opaque, 1, 0x1e);
708 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
709 chip->write(chip->opaque, 1, 0xe0);
710 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
711 chip->write(chip->opaque, 1, 0x01);
712 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
713 chip->write(chip->opaque, 1, 0x06);
714 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
715 chip->write(chip->opaque, 1, 1); /* Enable bit */
716
717 chip->write(chip->opaque, 0, 0x6c);
718 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
719 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
720 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
721 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
722 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
723 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
724 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
725 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
726 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
727 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
728 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
729 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
730 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
731 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
732 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
733 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
734 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
735 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
736
7267c094 737 fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
7e7c5e4c
AZ		 738 /* Display Memory Data Port */
739 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
7267c094 740 g_free(fb_blank);
7e7c5e4c
AZ		 741}
742
3023f332 743static void n8x0_dss_setup(struct n800_s *s)
7e7c5e4c 744{
b9d38e95 745 s->blizzard.opaque = s1d13745_init(NULL);
7e7c5e4c
AZ		 746 s->blizzard.block = s1d13745_write_block;
747 s->blizzard.write = s1d13745_write;
748 s->blizzard.read = s1d13745_read;
749
518ec134 750 omap_rfbi_attach(s->mpu->dss, 0, &s->blizzard);
7e7c5e4c
AZ		 751}
752
e927bb00 753static void n8x0_cbus_setup(struct n800_s *s)
7e7c5e4c 754{
518ec134
AF		 755 qemu_irq dat_out = qdev_get_gpio_in(s->mpu->gpio, N8X0_CBUS_DAT_GPIO);
756 qemu_irq retu_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_RETU_GPIO);
757 qemu_irq tahvo_irq = qdev_get_gpio_in(s->mpu->gpio, N8X0_TAHVO_GPIO);
7e7c5e4c 758
bc24a225 759 CBus *cbus = cbus_init(dat_out);
7e7c5e4c 760
518ec134
AF		 761 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
762 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
763 qdev_connect_gpio_out(s->mpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
7e7c5e4c
AZ		 764
765 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
766 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
767}
768
58a26b47
AZ		 769static void n8x0_uart_setup(struct n800_s *s)
770{
771 CharDriverState *radio = uart_hci_init(
518ec134 772 qdev_get_gpio_in(s->mpu->gpio, N8X0_BT_HOST_WKUP_GPIO));
58a26b47 773
518ec134 774 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_RESET_GPIO,
58a26b47 775 csrhci_pins_get(radio)[csrhci_pin_reset]);
518ec134 776 qdev_connect_gpio_out(s->mpu->gpio, N8X0_BT_WKUP_GPIO,
58a26b47
AZ		 777 csrhci_pins_get(radio)[csrhci_pin_wakeup]);
778
518ec134 779 omap_uart_attach(s->mpu->uart[BT_UART], radio);
58a26b47
AZ		 780}
781
e927bb00 782static void n8x0_usb_setup(struct n800_s *s)
942ac052 783{
bdc76462
PM		 784 SysBusDevice *dev;
785 s->usb = qdev_create(NULL, "tusb6010");
1356b98d 786 dev = SYS_BUS_DEVICE(s->usb);
bdc76462
PM		 787 qdev_init_nofail(s->usb);
788 sysbus_connect_irq(dev, 0,
518ec134 789 qdev_get_gpio_in(s->mpu->gpio, N8X0_TUSB_INT_GPIO));
942ac052 790 /* Using the NOR interface */
518ec134 791 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_ASYNC_CS,
bdc76462 792 sysbus_mmio_get_region(dev, 0));
518ec134 793 omap_gpmc_attach(s->mpu->gpmc, N8X0_USB_SYNC_CS,
bdc76462 794 sysbus_mmio_get_region(dev, 1));
518ec134 795 qdev_connect_gpio_out(s->mpu->gpio, N8X0_TUSB_ENABLE_GPIO,
bdc76462 796 qdev_get_gpio_in(s->usb, 0)); /* tusb_pwr */
942ac052
AZ		 797}
798
d238db7f
AZ		 799/* Setup done before the main bootloader starts by some early setup code
800 * - used when we want to run the main bootloader in emulation. This
801 * isn't documented. */
802static uint32_t n800_pinout[104] = {
803 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
804 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
805 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
806 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
807 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
808 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
809 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
810 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
811 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
812 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
813 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
814 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
815 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
816 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
817 0x00000000, 0x00000038, 0x00340000, 0x00000000,
818 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
819 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
820 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
821 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
822 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
823 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
824 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
825 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
826 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
827 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
828 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
829};
830
831static void n800_setup_nolo_tags(void *sram_base)
832{
833 int i;
834 uint32_t *p = sram_base + 0x8000;
835 uint32_t *v = sram_base + 0xa000;
836
837 memset(p, 0, 0x3000);
838
839 strcpy((void *) (p + 0), "QEMU N800");
840
841 strcpy((void *) (p + 8), "F5");
842
843 stl_raw(p + 10, 0x04f70000);
844 strcpy((void *) (p + 9), "RX-34");
845
846 /* RAM size in MB? */
847 stl_raw(p + 12, 0x80);
848
849 /* Pointer to the list of tags */
850 stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000);
851
852 /* The NOLO tags start here */
853 p = sram_base + 0x9000;
854#define ADD_TAG(tag, len) \
855 stw_raw((uint16_t *) p + 0, tag); \
856 stw_raw((uint16_t *) p + 1, len); p ++; \
857 stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
858
859 /* OMAP STI console? Pin out settings? */
860 ADD_TAG(0x6e01, 414);
b1503cda 861 for (i = 0; i < ARRAY_SIZE(n800_pinout); i ++)
d238db7f
AZ		 862 stl_raw(v ++, n800_pinout[i]);
863
864 /* Kernel memsize? */
865 ADD_TAG(0x6e05, 1);
866 stl_raw(v ++, 2);
867
868 /* NOLO serial console */
869 ADD_TAG(0x6e02, 4);
870 stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
871
872#if 0
873 /* CBUS settings (Retu/AVilma) */
874 ADD_TAG(0x6e03, 6);
875 stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
876 stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
877 stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
878 v += 2;
879#endif
880
881 /* Nokia ASIC BB5 (Retu/Tahvo) */
882 ADD_TAG(0x6e0a, 4);
883 stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
884 stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
885 v ++;
886
887 /* LCD console? */
888 ADD_TAG(0x6e04, 4);
889 stw_raw((uint16_t *) v + 0, 30); /* ??? */
890 stw_raw((uint16_t *) v + 1, 24); /* ??? */
891 v ++;
892
893#if 0
894 /* LCD settings */
895 ADD_TAG(0x6e06, 2);
896 stw_raw((uint16_t *) (v ++), 15); /* ??? */
897#endif
898
899 /* I^2C (Menelaus) */
900 ADD_TAG(0x6e07, 4);
901 stl_raw(v ++, 0x00720000); /* ??? */
902
903 /* Unknown */
904 ADD_TAG(0x6e0b, 6);
905 stw_raw((uint16_t *) v + 0, 94); /* ??? */
906 stw_raw((uint16_t *) v + 1, 23); /* ??? */
907 stw_raw((uint16_t *) v + 2, 0); /* ??? */
908 v += 2;
909
910 /* OMAP gpio switch info */
911 ADD_TAG(0x6e0c, 80);
912 strcpy((void *) v, "bat_cover"); v += 3;
913 stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */
914 stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */
915 v += 2;
916 strcpy((void *) v, "cam_act"); v += 3;
917 stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */
918 stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */
919 v += 2;
920 strcpy((void *) v, "cam_turn"); v += 3;
921 stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */
922 stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */
923 v += 2;
924 strcpy((void *) v, "headphone"); v += 3;
925 stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */
926 stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */
927 v += 2;
928
929 /* Bluetooth */
930 ADD_TAG(0x6e0e, 12);
931 stl_raw(v ++, 0x5c623d01); /* ??? */
932 stl_raw(v ++, 0x00000201); /* ??? */
933 stl_raw(v ++, 0x00000000); /* ??? */
934
935 /* CX3110x WLAN settings */
936 ADD_TAG(0x6e0f, 8);
937 stl_raw(v ++, 0x00610025); /* ??? */
938 stl_raw(v ++, 0xffff0057); /* ??? */
939
940 /* MMC host settings */
941 ADD_TAG(0x6e10, 12);
942 stl_raw(v ++, 0xffff000f); /* ??? */
943 stl_raw(v ++, 0xffffffff); /* ??? */
944 stl_raw(v ++, 0x00000060); /* ??? */
945
946 /* OneNAND chip select */
947 ADD_TAG(0x6e11, 10);
948 stl_raw(v ++, 0x00000401); /* ??? */
949 stl_raw(v ++, 0x0002003a); /* ??? */
950 stl_raw(v ++, 0x00000002); /* ??? */
951
952 /* TEA5761 sensor settings */
953 ADD_TAG(0x6e12, 2);
954 stl_raw(v ++, 93); /* GPIO num ??? */
955
956#if 0
957 /* Unknown tag */
958 ADD_TAG(6e09, 0);
959
960 /* Kernel UART / console */
961 ADD_TAG(6e12, 0);
962#endif
963
964 /* End of the list */
965 stl_raw(p ++, 0x00000000);
966 stl_raw(p ++, 0x00000000);
967}
968
7e7c5e4c
AZ		 969/* This task is normally performed by the bootloader. If we're loading
970 * a kernel directly, we need to set up GPMC mappings ourselves. */
971static void n800_gpmc_init(struct n800_s *s)
972{
973 uint32_t config7 =
974 (0xf << 8) | /* MASKADDRESS */
975 (1 << 6) | /* CSVALID */
976 (4 << 0); /* BASEADDRESS */
977
978 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
979 (void *) &config7, sizeof(config7));
980}
981
982/* Setup sequence done by the bootloader */
e927bb00 983static void n8x0_boot_init(void *opaque)
7e7c5e4c
AZ		 984{
985 struct n800_s *s = (struct n800_s *) opaque;
986 uint32_t buf;
987
988 /* PRCM setup */
989#define omap_writel(addr, val) \
990 buf = (val); \
991 cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf))
992
993 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
994 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
995 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
996 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
997 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
998 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
999 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
1000 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
1001 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
1002 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
1003 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
1004 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
1005 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
1006 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
1007 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
1008 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
1009 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
1010 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
1011 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
1012 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
1013 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
1014 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
1015 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
1016 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
1017 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
1018 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
1019 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
1020 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1021 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1022 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1023 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1024 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1025 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1026 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1027 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1028 (0x78 << 12) | (6 << 8));
1029 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1030
1031 /* GPMC setup */
1032 n800_gpmc_init(s);
1033
1034 /* Video setup */
1035 n800_dss_init(&s->blizzard);
1036
1037 /* CPU setup */
518ec134 1038 s->mpu->cpu->env.GE = 0x5;
0941041e
AZ		 1039
1040 /* If the machine has a slided keyboard, open it */
1041 if (s->kbd)
518ec134 1042 qemu_irq_raise(qdev_get_gpio_in(s->mpu->gpio, N810_SLIDE_GPIO));
7e7c5e4c
AZ		 1043}
1044
1045#define OMAP_TAG_NOKIA_BT 0x4e01
1046#define OMAP_TAG_WLAN_CX3110X 0x4e02
1047#define OMAP_TAG_CBUS 0x4e03
1048#define OMAP_TAG_EM_ASIC_BB5 0x4e04
1049
e927bb00
AZ		 1050static struct omap_gpiosw_info_s {
1051 const char *name;
1052 int line;
1053 int type;
1054} n800_gpiosw_info[] = {
1055 {
1056 "bat_cover", N800_BAT_COVER_GPIO,
1057 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1058 }, {
1059 "cam_act", N800_CAM_ACT_GPIO,
1060 OMAP_GPIOSW_TYPE_ACTIVITY,
1061 }, {
1062 "cam_turn", N800_CAM_TURN_GPIO,
1063 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1064 }, {
1065 "headphone", N8X0_HEADPHONE_GPIO,
1066 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1067 },
b9d38e95 1068 { NULL }
e927bb00
AZ		 1069}, n810_gpiosw_info[] = {
1070 {
1071 "gps_reset", N810_GPS_RESET_GPIO,
1072 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1073 }, {
1074 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1075 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1076 }, {
1077 "headphone", N8X0_HEADPHONE_GPIO,
1078 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1079 }, {
1080 "kb_lock", N810_KB_LOCK_GPIO,
1081 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1082 }, {
1083 "sleepx_led", N810_SLEEPX_LED_GPIO,
1084 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1085 }, {
1086 "slide", N810_SLIDE_GPIO,
1087 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1088 },
b9d38e95 1089 { NULL }
e927bb00
AZ		 1090};
1091
1092static struct omap_partition_info_s {
1093 uint32_t offset;
1094 uint32_t size;
1095 int mask;
1096 const char *name;
1097} n800_part_info[] = {
1098 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1099 { 0x00020000, 0x00060000, 0x0, "config" },
1100 { 0x00080000, 0x00200000, 0x0, "kernel" },
1101 { 0x00280000, 0x00200000, 0x3, "initfs" },
1102 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1103
b9d38e95 1104 { 0, 0, 0, NULL }
e927bb00
AZ		 1105}, n810_part_info[] = {
1106 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1107 { 0x00020000, 0x00060000, 0x0, "config" },
1108 { 0x00080000, 0x00220000, 0x0, "kernel" },
1109 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1110 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1111
b9d38e95 1112 { 0, 0, 0, NULL }
e927bb00
AZ		 1113};
1114
c227f099 1115static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
c580d92b 1116
e927bb00 1117static int n8x0_atag_setup(void *p, int model)
7e7c5e4c
AZ		 1118{
1119 uint8_t *b;
1120 uint16_t *w;
1121 uint32_t *l;
e927bb00
AZ		 1122 struct omap_gpiosw_info_s *gpiosw;
1123 struct omap_partition_info_s *partition;
1124 const char *tag;
7e7c5e4c
AZ		 1125
1126 w = p;
1127
1128 stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
1129 stw_raw(w ++, 4); /* u16 len */
1130 stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1131 w ++;
1132
e927bb00
AZ		 1133#if 0
1134 stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
7e7c5e4c 1135 stw_raw(w ++, 4); /* u16 len */
c580d92b 1136 stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */
e927bb00
AZ		 1137 stw_raw(w ++, 115200); /* u32 console_speed */
1138#endif
1139
1140 stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
1141 stw_raw(w ++, 36); /* u16 len */
1142 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1143 w += 8;
1144 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1145 w += 8;
1146 stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1147 stw_raw(w ++, 24); /* u8 data_lines */
7e7c5e4c
AZ		 1148
1149 stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
1150 stw_raw(w ++, 8); /* u16 len */
1151 stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1152 stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1153 stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
1154 w ++;
1155
e927bb00
AZ		 1156 stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1157 stw_raw(w ++, 4); /* u16 len */
1158 stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1159 stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
1160
1161 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1162 for (; gpiosw->name; gpiosw ++) {
1163 stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1164 stw_raw(w ++, 20); /* u16 len */
1165 strcpy((void *) w, gpiosw->name); /* char name[12] */
1166 w += 6;
1167 stw_raw(w ++, gpiosw->line); /* u16 gpio */
1168 stw_raw(w ++, gpiosw->type);
1169 stw_raw(w ++, 0);
1170 stw_raw(w ++, 0);
1171 }
7e7c5e4c
AZ		 1172
1173 stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1174 stw_raw(w ++, 12); /* u16 len */
1175 b = (void *) w;
1176 stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */
e927bb00 1177 stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
7e7c5e4c 1178 stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
e927bb00 1179 stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
c580d92b
AZ		 1180 stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */
1181 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
7e7c5e4c
AZ		 1182 b += 6;
1183 stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */
1184 w = (void *) b;
1185
1186 stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1187 stw_raw(w ++, 8); /* u16 len */
1188 stw_raw(w ++, 0x25); /* u8 chip_type */
e927bb00
AZ		 1189 stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1190 stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
7e7c5e4c
AZ		 1191 stw_raw(w ++, -1); /* s16 spi_cs_gpio */
1192
1193 stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
1194 stw_raw(w ++, 16); /* u16 len */
e927bb00
AZ		 1195 if (model == 810) {
1196 stw_raw(w ++, 0x23f); /* unsigned flags */
1197 stw_raw(w ++, -1); /* s16 power_pin */
1198 stw_raw(w ++, -1); /* s16 switch_pin */
1199 stw_raw(w ++, -1); /* s16 wp_pin */
1200 stw_raw(w ++, 0x240); /* unsigned flags */
1201 stw_raw(w ++, 0xc000); /* s16 power_pin */
1202 stw_raw(w ++, 0x0248); /* s16 switch_pin */
1203 stw_raw(w ++, 0xc000); /* s16 wp_pin */
1204 } else {
1205 stw_raw(w ++, 0xf); /* unsigned flags */
1206 stw_raw(w ++, -1); /* s16 power_pin */
1207 stw_raw(w ++, -1); /* s16 switch_pin */
1208 stw_raw(w ++, -1); /* s16 wp_pin */
1209 stw_raw(w ++, 0); /* unsigned flags */
1210 stw_raw(w ++, 0); /* s16 power_pin */
1211 stw_raw(w ++, 0); /* s16 switch_pin */
1212 stw_raw(w ++, 0); /* s16 wp_pin */
1213 }
7e7c5e4c
AZ		 1214
1215 stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
1216 stw_raw(w ++, 4); /* u16 len */
e927bb00 1217 stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
7e7c5e4c
AZ		 1218 w ++;
1219
e927bb00
AZ		 1220 partition = (model == 810) ? n810_part_info : n800_part_info;
1221 for (; partition->name; partition ++) {
1222 stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
1223 stw_raw(w ++, 28); /* u16 len */
1224 strcpy((void *) w, partition->name); /* char name[16] */
1225 l = (void *) (w + 8);
1226 stl_raw(l ++, partition->size); /* unsigned int size */
1227 stl_raw(l ++, partition->offset); /* unsigned int offset */
1228 stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
1229 w = (void *) l;
1230 }
7e7c5e4c
AZ		 1231
1232 stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1233 stw_raw(w ++, 12); /* u16 len */
1234#if 0
1235 strcpy((void *) w, "por"); /* char reason_str[12] */
1236 strcpy((void *) w, "charger"); /* char reason_str[12] */
1237 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1238 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1239 strcpy((void *) w, "mbus"); /* char reason_str[12] */
1240 strcpy((void *) w, "unknown"); /* char reason_str[12] */
1241 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1242 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1243 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1244 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1245#else
1246 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1247#endif
1248 w += 6;
1249
e927bb00 1250 tag = (model == 810) ? "RX-44" : "RX-34";
7e7c5e4c
AZ		 1251 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1252 stw_raw(w ++, 24); /* u16 len */
1253 strcpy((void *) w, "product"); /* char component[12] */
1254 w += 6;
e927bb00 1255 strcpy((void *) w, tag); /* char version[12] */
7e7c5e4c
AZ		 1256 w += 6;
1257
1258 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1259 stw_raw(w ++, 24); /* u16 len */
1260 strcpy((void *) w, "hw-build"); /* char component[12] */
1261 w += 6;
93bfef4c
CV		 1262 strcpy((void *) w, "QEMU ");
1263 pstrcat((void *) w, 12, qemu_get_version()); /* char version[12] */
7e7c5e4c
AZ		 1264 w += 6;
1265
e927bb00 1266 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
7e7c5e4c
AZ		 1267 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1268 stw_raw(w ++, 24); /* u16 len */
1269 strcpy((void *) w, "nolo"); /* char component[12] */
1270 w += 6;
e927bb00 1271 strcpy((void *) w, tag); /* char version[12] */
7e7c5e4c 1272 w += 6;
7e7c5e4c
AZ		 1273
1274 return (void *) w - p;
1275}
1276
462a8bc6 1277static int n800_atag_setup(const struct arm_boot_info *info, void *p)
e927bb00
AZ		 1278{
1279 return n8x0_atag_setup(p, 800);
1280}
7e7c5e4c 1281
462a8bc6 1282static int n810_atag_setup(const struct arm_boot_info *info, void *p)
e927bb00
AZ		 1283{
1284 return n8x0_atag_setup(p, 810);
1285}
1286
462b69bb
PM		 1287static void n8x0_init(QEMUMachineInitArgs *args,
1288 struct arm_boot_info *binfo, int model)
7e7c5e4c 1289{
aee39503 1290 MemoryRegion *sysmem = get_system_memory();
7267c094 1291 struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
e927bb00 1292 int sdram_size = binfo->ram_size;
7e7c5e4c 1293
462b69bb 1294 s->mpu = omap2420_mpu_init(sysmem, sdram_size, args->cpu_model);
7e7c5e4c 1295
0941041e
AZ		 1296 /* Setup peripherals
1297 *
1298 * Believed external peripherals layout in the N810:
1299 * (spi bus 1)
1300 * tsc2005
1301 * lcd_mipid
1302 * (spi bus 2)
1303 * Conexant cx3110x (WLAN)
1304 * optional: pc2400m (WiMAX)
1305 * (i2c bus 0)
1306 * TLV320AIC33 (audio codec)
1307 * TCM825x (camera by Toshiba)
1308 * lp5521 (clever LEDs)
1309 * tsl2563 (light sensor, hwmon, model 7, rev. 0)
1310 * lm8323 (keypad, manf 00, rev 04)
1311 * (i2c bus 1)
1312 * tmp105 (temperature sensor, hwmon)
1313 * menelaus (pm)
d238db7f
AZ		 1314 * (somewhere on i2c - maybe N800-only)
1315 * tea5761 (FM tuner)
1316 * (serial 0)
1317 * GPS
1318 * (some serial port)
1319 * csr41814 (Bluetooth)
0941041e 1320 */
e927bb00 1321 n8x0_gpio_setup(s);
7e7c5e4c 1322 n8x0_nand_setup(s);
e927bb00
AZ		 1323 n8x0_i2c_setup(s);
1324 if (model == 800)
1325 n800_tsc_kbd_setup(s);
1d4e547b 1326 else if (model == 810) {
e927bb00 1327 n810_tsc_setup(s);
1d4e547b
AZ		 1328 n810_kbd_setup(s);
1329 }
e927bb00 1330 n8x0_spi_setup(s);
3023f332 1331 n8x0_dss_setup(s);
e927bb00 1332 n8x0_cbus_setup(s);
58a26b47 1333 n8x0_uart_setup(s);
094b287f 1334 if (usb_enabled(false)) {
e927bb00 1335 n8x0_usb_setup(s);
094b287f 1336 }
7e7c5e4c 1337
462b69bb 1338 if (args->kernel_filename) {
7e7c5e4c 1339 /* Or at the linux loader. */
462b69bb
PM		 1340 binfo->kernel_filename = args->kernel_filename;
1341 binfo->kernel_cmdline = args->kernel_cmdline;
1342 binfo->initrd_filename = args->initrd_filename;
3aaa8dfa 1343 arm_load_kernel(s->mpu->cpu, binfo);
7e7c5e4c 1344
a08d4367 1345 qemu_register_reset(n8x0_boot_init, s);
7e7c5e4c
AZ		 1346 }
1347
462b69bb
PM		 1348 if (option_rom[0].name &&
1349 (args->boot_device[0] == 'n' || !args->kernel_filename)) {
dcac9679 1350 int rom_size;
5c130f65 1351 uint8_t nolo_tags[0x10000];
d238db7f 1352 /* No, wait, better start at the ROM. */
518ec134 1353 s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
d238db7f
AZ		 1354
1355 /* This is intended for loading the `secondary.bin' program from
1356 * Nokia images (the NOLO bootloader). The entry point seems
1357 * to be at OMAP2_Q2_BASE + 0x400000.
1358 *
1359 * The `2nd.bin' files contain some kind of earlier boot code and
1360 * for them the entry point needs to be set to OMAP2_SRAM_BASE.
1361 *
1362 * The code above is for loading the `zImage' file from Nokia
1363 * images. */
2e55e842 1364 rom_size = load_image_targphys(option_rom[0].name,
dcac9679
PB		 1365 OMAP2_Q2_BASE + 0x400000,
1366 sdram_size - 0x400000);
1367 printf("%i bytes of image loaded\n", rom_size);
d238db7f 1368
5c130f65
PB		 1369 n800_setup_nolo_tags(nolo_tags);
1370 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
d238db7f 1371 }
7e7c5e4c
AZ		 1372}
1373
e927bb00
AZ		 1374static struct arm_boot_info n800_binfo = {
1375 .loader_start = OMAP2_Q2_BASE,
1376 /* Actually two chips of 0x4000000 bytes each */
1377 .ram_size = 0x08000000,
1378 .board_id = 0x4f7,
1379 .atag_board = n800_atag_setup,
1380};
1381
1382static struct arm_boot_info n810_binfo = {
1383 .loader_start = OMAP2_Q2_BASE,
1384 /* Actually two chips of 0x4000000 bytes each */
1385 .ram_size = 0x08000000,
1386 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1387 * used by some older versions of the bootloader and 5555 is used
1388 * instead (including versions that shipped with many devices). */
1389 .board_id = 0x60c,
1390 .atag_board = n810_atag_setup,
1391};
1392
5f072e1f 1393static void n800_init(QEMUMachineInitArgs *args)
e927bb00 1394{
462b69bb 1395 return n8x0_init(args, &n800_binfo, 800);
e927bb00
AZ		 1396}
1397
5f072e1f 1398static void n810_init(QEMUMachineInitArgs *args)
e927bb00 1399{
462b69bb 1400 return n8x0_init(args, &n810_binfo, 810);
e927bb00
AZ		 1401}
1402
f80f9ec9 1403static QEMUMachine n800_machine = {
4b32e168
AL		 1404 .name = "n800",
1405 .desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)",
1406 .init = n800_init,
e4ada29e 1407 DEFAULT_MACHINE_OPTIONS,
7e7c5e4c 1408};
e927bb00 1409
f80f9ec9 1410static QEMUMachine n810_machine = {
4b32e168
AL		 1411 .name = "n810",
1412 .desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)",
1413 .init = n810_init,
e4ada29e 1414 DEFAULT_MACHINE_OPTIONS,
e927bb00 1415};
f80f9ec9
AL		 1416
1417static void nseries_machine_init(void)
1418{
1419 qemu_register_machine(&n800_machine);
1420 qemu_register_machine(&n810_machine);
1421}
1422
1423machine_init(nseries_machine_init);
Empty description
This page took 0.839903 seconds and 4 git commands to generate.