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afb3141c PM |
1 | /* |
2 | * Register Definition API: field macros | |
3 | * | |
4 | * Copyright (c) 2016 Xilinx Inc. | |
5 | * Copyright (c) 2013 Peter Crosthwaite <[email protected]> | |
6 | * | |
7 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
8 | * the COPYING file in the top-level directory. | |
9 | */ | |
10 | ||
11 | #ifndef REGISTERFIELDS_H | |
12 | #define REGISTERFIELDS_H | |
13 | ||
d8e39b70 | 14 | #include "qemu/bitops.h" |
27de8f2d | 15 | |
afb3141c PM |
16 | /* Define constants for a 32 bit register */ |
17 | ||
18 | /* This macro will define A_FOO, for the byte address of a register | |
19 | * as well as R_FOO for the uint32_t[] register number (A_FOO / 4). | |
20 | */ | |
21 | #define REG32(reg, addr) \ | |
22 | enum { A_ ## reg = (addr) }; \ | |
23 | enum { R_ ## reg = (addr) / 4 }; | |
24 | ||
25 | /* Define SHIFT, LENGTH and MASK constants for a field within a register */ | |
26 | ||
9102fe6c | 27 | /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH |
afb3141c PM |
28 | * constants for field BAR in register FOO. |
29 | */ | |
30 | #define FIELD(reg, field, shift, length) \ | |
31 | enum { R_ ## reg ## _ ## field ## _SHIFT = (shift)}; \ | |
32 | enum { R_ ## reg ## _ ## field ## _LENGTH = (length)}; \ | |
33 | enum { R_ ## reg ## _ ## field ## _MASK = \ | |
34 | MAKE_64BIT_MASK(shift, length)}; | |
35 | ||
36 | /* Extract a field from a register */ | |
37 | #define FIELD_EX32(storage, reg, field) \ | |
38 | extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ | |
39 | R_ ## reg ## _ ## field ## _LENGTH) | |
cdb70a5c PMD |
40 | #define FIELD_EX64(storage, reg, field) \ |
41 | extract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ | |
42 | R_ ## reg ## _ ## field ## _LENGTH) | |
afb3141c PM |
43 | |
44 | /* Extract a field from an array of registers */ | |
45 | #define ARRAY_FIELD_EX32(regs, reg, field) \ | |
46 | FIELD_EX32((regs)[R_ ## reg], reg, field) | |
47 | ||
48 | /* Deposit a register field. | |
49 | * Assigning values larger then the target field will result in | |
50 | * compilation warnings. | |
51 | */ | |
52 | #define FIELD_DP32(storage, reg, field, val) ({ \ | |
53 | struct { \ | |
54 | unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ | |
55 | } v = { .v = val }; \ | |
56 | uint32_t d; \ | |
57 | d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ | |
58 | R_ ## reg ## _ ## field ## _LENGTH, v.v); \ | |
59 | d; }) | |
cdb70a5c PMD |
60 | #define FIELD_DP64(storage, reg, field, val) ({ \ |
61 | struct { \ | |
62 | unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ | |
63 | } v = { .v = val }; \ | |
64 | uint64_t d; \ | |
65 | d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ | |
66 | R_ ## reg ## _ ## field ## _LENGTH, v.v); \ | |
67 | d; }) | |
afb3141c PM |
68 | |
69 | /* Deposit a field to array of registers. */ | |
70 | #define ARRAY_FIELD_DP32(regs, reg, field, val) \ | |
71 | (regs)[R_ ## reg] = FIELD_DP32((regs)[R_ ## reg], reg, field, val); | |
72 | ||
73 | #endif |