[qemu.git] / target-arm / machine.c

#include "hw/hw.h"
#include "hw/boards.h"
#include "sysemu/kvm.h"
#include "kvm_arm.h"
#include "internals.h"

static bool vfp_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_VFP);
}

static int get_fpscr(QEMUFile *f, void *opaque, size_t size)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;
    uint32_t val = qemu_get_be32(f);

    vfp_set_fpscr(env, val);
    return 0;
}

static void put_fpscr(QEMUFile *f, void *opaque, size_t size)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    qemu_put_be32(f, vfp_get_fpscr(env));
}

static const VMStateInfo vmstate_fpscr = {
    .name = "fpscr",
    .get = get_fpscr,
    .put = put_fpscr,
};

static const VMStateDescription vmstate_vfp = {
    .name = "cpu/vfp",
    .version_id = 3,
    .minimum_version_id = 3,
    .fields = (VMStateField[]) {
        VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
        /* The xregs array is a little awkward because element 1 (FPSCR)
         * requires a specific accessor, so we have to split it up in
         * the vmstate:
         */
        VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU),
        VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
        {
            .name = "fpscr",
            .version_id = 0,
            .size = sizeof(uint32_t),
            .info = &vmstate_fpscr,
            .flags = VMS_SINGLE,
            .offset = 0,
        },
        VMSTATE_END_OF_LIST()
    }
};

static bool iwmmxt_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_IWMMXT);
}

static const VMStateDescription vmstate_iwmmxt = {
    .name = "cpu/iwmmxt",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
        VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
        VMSTATE_END_OF_LIST()
    }
};

static bool m_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_M);
}

static const VMStateDescription vmstate_m = {
    .name = "cpu/m",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
        VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
        VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
        VMSTATE_UINT32(env.v7m.control, ARMCPU),
        VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
        VMSTATE_INT32(env.v7m.exception, ARMCPU),
        VMSTATE_END_OF_LIST()
    }
};

static bool thumb2ee_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_THUMB2EE);
}

static const VMStateDescription vmstate_thumb2ee = {
    .name = "cpu/thumb2ee",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(env.teecr, ARMCPU),
        VMSTATE_UINT32(env.teehbr, ARMCPU),
        VMSTATE_END_OF_LIST()
    }
};

static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;
    uint32_t val = qemu_get_be32(f);

    env->aarch64 = ((val & PSTATE_nRW) == 0);

    if (is_a64(env)) {
        pstate_write(env, val);
        return 0;
    }

    /* Avoid mode switch when restoring CPSR */
    env->uncached_cpsr = val & CPSR_M;
    cpsr_write(env, val, 0xffffffff);
    return 0;
}

static void put_cpsr(QEMUFile *f, void *opaque, size_t size)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;
    uint32_t val;

    if (is_a64(env)) {
        val = pstate_read(env);
    } else {
        val = cpsr_read(env);
    }

    qemu_put_be32(f, val);
}

static const VMStateInfo vmstate_cpsr = {
    .name = "cpsr",
    .get = get_cpsr,
    .put = put_cpsr,
};

static void cpu_pre_save(void *opaque)
{
    ARMCPU *cpu = opaque;

    if (kvm_enabled()) {
        if (!write_kvmstate_to_list(cpu)) {
            /* This should never fail */
            abort();
        }
    } else {
        if (!write_cpustate_to_list(cpu)) {
            /* This should never fail. */
            abort();
        }
    }

    cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
    memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
           cpu->cpreg_array_len * sizeof(uint64_t));
    memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
           cpu->cpreg_array_len * sizeof(uint64_t));
}

static int cpu_post_load(void *opaque, int version_id)
{
    ARMCPU *cpu = opaque;
    int i, v;

    /* Update the values list from the incoming migration data.
     * Anything in the incoming data which we don't know about is
     * a migration failure; anything we know about but the incoming
     * data doesn't specify retains its current (reset) value.
     * The indexes list remains untouched -- we only inspect the
     * incoming migration index list so we can match the values array
     * entries with the right slots in our own values array.
     */

    for (i = 0, v = 0; i < cpu->cpreg_array_len
             && v < cpu->cpreg_vmstate_array_len; i++) {
        if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) {
            /* register in our list but not incoming : skip it */
            continue;
        }
        if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) {
            /* register in their list but not ours: fail migration */
            return -1;
        }
        /* matching register, copy the value over */
        cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v];
        v++;
    }

    if (kvm_enabled()) {
        if (!write_list_to_kvmstate(cpu)) {
            return -1;
        }
        /* Note that it's OK for the TCG side not to know about
         * every register in the list; KVM is authoritative if
         * we're using it.
         */
        write_list_to_cpustate(cpu);
    } else {
        if (!write_list_to_cpustate(cpu)) {
            return -1;
        }
    }

    hw_breakpoint_update_all(cpu);
    hw_watchpoint_update_all(cpu);

    return 0;
}

const VMStateDescription vmstate_arm_cpu = {
    .name = "cpu",
    .version_id = 22,
    .minimum_version_id = 22,
    .pre_save = cpu_pre_save,
    .post_load = cpu_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
        VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32),
        VMSTATE_UINT64(env.pc, ARMCPU),
        {
            .name = "cpsr",
            .version_id = 0,
            .size = sizeof(uint32_t),
            .info = &vmstate_cpsr,
            .flags = VMS_SINGLE,
            .offset = 0,
        },
        VMSTATE_UINT32(env.spsr, ARMCPU),
        VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
        VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8),
        VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8),
        VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
        VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
        VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
        VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
        /* The length-check must come before the arrays to avoid
         * incoming data possibly overflowing the array.
         */
        VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU),
        VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
                             cpreg_vmstate_array_len,
                             0, vmstate_info_uint64, uint64_t),
        VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
                             cpreg_vmstate_array_len,
                             0, vmstate_info_uint64, uint64_t),
        VMSTATE_UINT64(env.exclusive_addr, ARMCPU),
        VMSTATE_UINT64(env.exclusive_val, ARMCPU),
        VMSTATE_UINT64(env.exclusive_high, ARMCPU),
        VMSTATE_UINT64(env.features, ARMCPU),
        VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
        VMSTATE_UINT32(env.exception.fsr, ARMCPU),
        VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
        VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU),
        VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU),
        VMSTATE_BOOL(powered_off, ARMCPU),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (VMStateSubsection[]) {
        {
            .vmsd = &vmstate_vfp,
            .needed = vfp_needed,
        } , {
            .vmsd = &vmstate_iwmmxt,
            .needed = iwmmxt_needed,
        } , {
            .vmsd = &vmstate_m,
            .needed = m_needed,
        } , {
            .vmsd = &vmstate_thumb2ee,
            .needed = thumb2ee_needed,
        } , {
            /* empty */
        }
    }
};
Commit	Line	Data
8dd3dca3 AJ	1	#include "hw/hw.h"
8dd3dca3 AJ	2	#include "hw/boards.h"
ff047453 PM	3	#include "sysemu/kvm.h"
ff047453 PM	4	#include "kvm_arm.h"
9ee98ce8	5	#include "internals.h"
8dd3dca3	6
3cc1d208	7	static bool vfp_needed(void *opaque)
8dd3dca3	8	{
3cc1d208 JQ	9	ARMCPU *cpu = opaque;
3cc1d208 JQ	10	CPUARMState *env = &cpu->env;
8dd3dca3	11
3cc1d208 JQ	12	return arm_feature(env, ARM_FEATURE_VFP);
3cc1d208 JQ	13	}
8dd3dca3	14
e91f229a PM	15	static int get_fpscr(QEMUFile f, void opaque, size_t size)
	16	{
	17	ARMCPU *cpu = opaque;
	18	CPUARMState *env = &cpu->env;
	19	uint32_t val = qemu_get_be32(f);
	20
	21	vfp_set_fpscr(env, val);
	22	return 0;
	23	}
	24
	25	static void put_fpscr(QEMUFile f, void opaque, size_t size)
	26	{
	27	ARMCPU *cpu = opaque;
	28	CPUARMState *env = &cpu->env;
	29
	30	qemu_put_be32(f, vfp_get_fpscr(env));
	31	}
	32
	33	static const VMStateInfo vmstate_fpscr = {
	34	.name = "fpscr",
	35	.get = get_fpscr,
	36	.put = put_fpscr,
	37	};
	38
3cc1d208 JQ	39	static const VMStateDescription vmstate_vfp = {
3cc1d208 JQ	40	.name = "cpu/vfp",
3926cc84 AG	41	.version_id = 3,
3926cc84 AG	42	.minimum_version_id = 3,
3cc1d208	43	.fields = (VMStateField[]) {
3926cc84	44	VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
e91f229a PM	45	/* The xregs array is a little awkward because element 1 (FPSCR)
	46	* requires a specific accessor, so we have to split it up in
	47	* the vmstate:
	48	*/
	49	VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU),
	50	VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
	51	{
	52	.name = "fpscr",
	53	.version_id = 0,
	54	.size = sizeof(uint32_t),
	55	.info = &vmstate_fpscr,
	56	.flags = VMS_SINGLE,
	57	.offset = 0,
	58	},
3cc1d208	59	VMSTATE_END_OF_LIST()
8dd3dca3	60	}
3cc1d208	61	};
8dd3dca3	62
3cc1d208 JQ	63	static bool iwmmxt_needed(void *opaque)
	64	{
	65	ARMCPU *cpu = opaque;
	66	CPUARMState *env = &cpu->env;
8dd3dca3	67
3cc1d208 JQ	68	return arm_feature(env, ARM_FEATURE_IWMMXT);
3cc1d208 JQ	69	}
ffe47d33	70
3cc1d208 JQ	71	static const VMStateDescription vmstate_iwmmxt = {
	72	.name = "cpu/iwmmxt",
	73	.version_id = 1,
	74	.minimum_version_id = 1,
3cc1d208 JQ	75	.fields = (VMStateField[]) {
	76	VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
	77	VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
	78	VMSTATE_END_OF_LIST()
ffe47d33	79	}
3cc1d208 JQ	80	};
	81
	82	static bool m_needed(void *opaque)
	83	{
	84	ARMCPU *cpu = opaque;
	85	CPUARMState *env = &cpu->env;
	86
	87	return arm_feature(env, ARM_FEATURE_M);
8dd3dca3 AJ	88	}
8dd3dca3 AJ	89
6df05bdd	90	static const VMStateDescription vmstate_m = {
3cc1d208 JQ	91	.name = "cpu/m",
	92	.version_id = 1,
	93	.minimum_version_id = 1,
3cc1d208 JQ	94	.fields = (VMStateField[]) {
	95	VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
	96	VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
	97	VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
	98	VMSTATE_UINT32(env.v7m.control, ARMCPU),
	99	VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
	100	VMSTATE_INT32(env.v7m.exception, ARMCPU),
	101	VMSTATE_END_OF_LIST()
	102	}
	103	};
	104
	105	static bool thumb2ee_needed(void *opaque)
8dd3dca3	106	{
3cc1d208 JQ	107	ARMCPU *cpu = opaque;
3cc1d208 JQ	108	CPUARMState *env = &cpu->env;
8dd3dca3	109
3cc1d208 JQ	110	return arm_feature(env, ARM_FEATURE_THUMB2EE);
3cc1d208 JQ	111	}
8dd3dca3	112
3cc1d208 JQ	113	static const VMStateDescription vmstate_thumb2ee = {
	114	.name = "cpu/thumb2ee",
	115	.version_id = 1,
	116	.minimum_version_id = 1,
3cc1d208 JQ	117	.fields = (VMStateField[]) {
	118	VMSTATE_UINT32(env.teecr, ARMCPU),
	119	VMSTATE_UINT32(env.teehbr, ARMCPU),
	120	VMSTATE_END_OF_LIST()
8dd3dca3	121	}
3cc1d208 JQ	122	};
	123
	124	static int get_cpsr(QEMUFile f, void opaque, size_t size)
	125	{
	126	ARMCPU *cpu = opaque;
	127	CPUARMState *env = &cpu->env;
	128	uint32_t val = qemu_get_be32(f);
	129
a7130a3e PM	130	env->aarch64 = ((val & PSTATE_nRW) == 0);
	131
	132	if (is_a64(env)) {
	133	pstate_write(env, val);
	134	return 0;
	135	}
	136
3cc1d208	137	/* Avoid mode switch when restoring CPSR */
ffe47d33 PB	138	env->uncached_cpsr = val & CPSR_M;
ffe47d33 PB	139	cpsr_write(env, val, 0xffffffff);
3cc1d208 JQ	140	return 0;
3cc1d208 JQ	141	}
8dd3dca3	142
3cc1d208 JQ	143	static void put_cpsr(QEMUFile f, void opaque, size_t size)
	144	{
	145	ARMCPU *cpu = opaque;
	146	CPUARMState *env = &cpu->env;
a7130a3e PM	147	uint32_t val;
	148
	149	if (is_a64(env)) {
	150	val = pstate_read(env);
	151	} else {
	152	val = cpsr_read(env);
	153	}
8dd3dca3	154
a7130a3e	155	qemu_put_be32(f, val);
3cc1d208	156	}
8dd3dca3	157
3cc1d208 JQ	158	static const VMStateInfo vmstate_cpsr = {
	159	.name = "cpsr",
	160	.get = get_cpsr,
	161	.put = put_cpsr,
	162	};
	163
721fae12 PM	164	static void cpu_pre_save(void *opaque)
	165	{
	166	ARMCPU *cpu = opaque;
	167
ff047453 PM	168	if (kvm_enabled()) {
	169	if (!write_kvmstate_to_list(cpu)) {
	170	/* This should never fail */
	171	abort();
	172	}
	173	} else {
	174	if (!write_cpustate_to_list(cpu)) {
	175	/* This should never fail. */
	176	abort();
	177	}
721fae12 PM	178	}
	179
	180	cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
	181	memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
	182	cpu->cpreg_array_len * sizeof(uint64_t));
	183	memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
	184	cpu->cpreg_array_len * sizeof(uint64_t));
	185	}
	186
	187	static int cpu_post_load(void *opaque, int version_id)
	188	{
	189	ARMCPU *cpu = opaque;
	190	int i, v;
	191
	192	/* Update the values list from the incoming migration data.
	193	* Anything in the incoming data which we don't know about is
	194	* a migration failure; anything we know about but the incoming
	195	* data doesn't specify retains its current (reset) value.
	196	* The indexes list remains untouched -- we only inspect the
	197	* incoming migration index list so we can match the values array
	198	* entries with the right slots in our own values array.
	199	*/
	200
	201	for (i = 0, v = 0; i < cpu->cpreg_array_len
	202	&& v < cpu->cpreg_vmstate_array_len; i++) {
	203	if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) {
	204	/* register in our list but not incoming : skip it */
	205	continue;
	206	}
	207	if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) {
	208	/* register in their list but not ours: fail migration */
	209	return -1;
	210	}
	211	/* matching register, copy the value over */
	212	cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v];
	213	v++;
	214	}
	215
ff047453 PM	216	if (kvm_enabled()) {
	217	if (!write_list_to_kvmstate(cpu)) {
	218	return -1;
	219	}
	220	/* Note that it's OK for the TCG side not to know about
	221	* every register in the list; KVM is authoritative if
	222	* we're using it.
	223	*/
	224	write_list_to_cpustate(cpu);
	225	} else {
	226	if (!write_list_to_cpustate(cpu)) {
	227	return -1;
	228	}
721fae12 PM	229	}
721fae12 PM	230
46747d15	231	hw_breakpoint_update_all(cpu);
9ee98ce8 PM	232	hw_watchpoint_update_all(cpu);
9ee98ce8 PM	233
721fae12 PM	234	return 0;
	235	}
	236
3cc1d208 JQ	237	const VMStateDescription vmstate_arm_cpu = {
3cc1d208 JQ	238	.name = "cpu",
a7130a3e PM	239	.version_id = 22,
a7130a3e PM	240	.minimum_version_id = 22,
721fae12 PM	241	.pre_save = cpu_pre_save,
721fae12 PM	242	.post_load = cpu_post_load,
3cc1d208 JQ	243	.fields = (VMStateField[]) {
3cc1d208 JQ	244	VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
a7130a3e PM	245	VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32),
a7130a3e PM	246	VMSTATE_UINT64(env.pc, ARMCPU),
3cc1d208 JQ	247	{
	248	.name = "cpsr",
	249	.version_id = 0,
	250	.size = sizeof(uint32_t),
	251	.info = &vmstate_cpsr,
	252	.flags = VMS_SINGLE,
	253	.offset = 0,
	254	},
	255	VMSTATE_UINT32(env.spsr, ARMCPU),
28c9457d	256	VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
0b7d409d FA	257	VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8),
0b7d409d FA	258	VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8),
3cc1d208 JQ	259	VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
3cc1d208 JQ	260	VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
1b174238	261	VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
73fb3b76	262	VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
721fae12 PM	263	/* The length-check must come before the arrays to avoid
	264	* incoming data possibly overflowing the array.
	265	*/
3476436a	266	VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU),
721fae12 PM	267	VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
	268	cpreg_vmstate_array_len,
	269	0, vmstate_info_uint64, uint64_t),
	270	VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
	271	cpreg_vmstate_array_len,
	272	0, vmstate_info_uint64, uint64_t),
03d05e2d PM	273	VMSTATE_UINT64(env.exclusive_addr, ARMCPU),
	274	VMSTATE_UINT64(env.exclusive_val, ARMCPU),
	275	VMSTATE_UINT64(env.exclusive_high, ARMCPU),
3cc1d208	276	VMSTATE_UINT64(env.features, ARMCPU),
abf1172f PM	277	VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
	278	VMSTATE_UINT32(env.exception.fsr, ARMCPU),
	279	VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
e720677e PB	280	VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU),
e720677e PB	281	VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU),
543486db	282	VMSTATE_BOOL(powered_off, ARMCPU),
3cc1d208 JQ	283	VMSTATE_END_OF_LIST()
	284	},
	285	.subsections = (VMStateSubsection[]) {
	286	{
	287	.vmsd = &vmstate_vfp,
	288	.needed = vfp_needed,
	289	} , {
	290	.vmsd = &vmstate_iwmmxt,
	291	.needed = iwmmxt_needed,
	292	} , {
	293	.vmsd = &vmstate_m,
	294	.needed = m_needed,
	295	} , {
	296	.vmsd = &vmstate_thumb2ee,
	297	.needed = thumb2ee_needed,
	298	} , {
	299	/* empty */
	300	}
ffe47d33	301	}
3cc1d208	302	};