]>
Commit | Line | Data |
---|---|---|
494b00c7 CD |
1 | /* |
2 | * ARM implementation of KVM hooks | |
3 | * | |
4 | * Copyright Christoffer Dall 2009-2010 | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
7 | * See the COPYING file in the top-level directory. | |
8 | * | |
9 | */ | |
10 | ||
11 | #include <stdio.h> | |
12 | #include <sys/types.h> | |
13 | #include <sys/ioctl.h> | |
14 | #include <sys/mman.h> | |
15 | ||
16 | #include <linux/kvm.h> | |
17 | ||
18 | #include "qemu-common.h" | |
19 | #include "qemu/timer.h" | |
20 | #include "sysemu/sysemu.h" | |
21 | #include "sysemu/kvm.h" | |
eb035b48 | 22 | #include "kvm_arm.h" |
494b00c7 | 23 | #include "cpu.h" |
38df27c8 | 24 | #include "internals.h" |
bd2be150 | 25 | #include "hw/arm/arm.h" |
494b00c7 CD |
26 | |
27 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { | |
28 | KVM_CAP_LAST_INFO | |
29 | }; | |
30 | ||
228d5e04 PS |
31 | int kvm_arm_vcpu_init(CPUState *cs) |
32 | { | |
33 | ARMCPU *cpu = ARM_CPU(cs); | |
34 | struct kvm_vcpu_init init; | |
35 | ||
36 | init.target = cpu->kvm_target; | |
37 | memcpy(init.features, cpu->kvm_init_features, sizeof(init.features)); | |
38 | ||
39 | return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init); | |
40 | } | |
41 | ||
a96c0514 PM |
42 | bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, |
43 | int *fdarray, | |
44 | struct kvm_vcpu_init *init) | |
45 | { | |
46 | int ret, kvmfd = -1, vmfd = -1, cpufd = -1; | |
47 | ||
48 | kvmfd = qemu_open("/dev/kvm", O_RDWR); | |
49 | if (kvmfd < 0) { | |
50 | goto err; | |
51 | } | |
52 | vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0); | |
53 | if (vmfd < 0) { | |
54 | goto err; | |
55 | } | |
56 | cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0); | |
57 | if (cpufd < 0) { | |
58 | goto err; | |
59 | } | |
60 | ||
61 | ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, init); | |
62 | if (ret >= 0) { | |
63 | ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init); | |
64 | if (ret < 0) { | |
65 | goto err; | |
66 | } | |
67 | } else { | |
68 | /* Old kernel which doesn't know about the | |
69 | * PREFERRED_TARGET ioctl: we know it will only support | |
70 | * creating one kind of guest CPU which is its preferred | |
71 | * CPU type. | |
72 | */ | |
73 | while (*cpus_to_try != QEMU_KVM_ARM_TARGET_NONE) { | |
74 | init->target = *cpus_to_try++; | |
75 | memset(init->features, 0, sizeof(init->features)); | |
76 | ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init); | |
77 | if (ret >= 0) { | |
78 | break; | |
79 | } | |
80 | } | |
81 | if (ret < 0) { | |
82 | goto err; | |
83 | } | |
84 | } | |
85 | ||
86 | fdarray[0] = kvmfd; | |
87 | fdarray[1] = vmfd; | |
88 | fdarray[2] = cpufd; | |
89 | ||
90 | return true; | |
91 | ||
92 | err: | |
93 | if (cpufd >= 0) { | |
94 | close(cpufd); | |
95 | } | |
96 | if (vmfd >= 0) { | |
97 | close(vmfd); | |
98 | } | |
99 | if (kvmfd >= 0) { | |
100 | close(kvmfd); | |
101 | } | |
102 | ||
103 | return false; | |
104 | } | |
105 | ||
106 | void kvm_arm_destroy_scratch_host_vcpu(int *fdarray) | |
107 | { | |
108 | int i; | |
109 | ||
110 | for (i = 2; i >= 0; i--) { | |
111 | close(fdarray[i]); | |
112 | } | |
113 | } | |
114 | ||
a96c0514 PM |
115 | static void kvm_arm_host_cpu_class_init(ObjectClass *oc, void *data) |
116 | { | |
117 | ARMHostCPUClass *ahcc = ARM_HOST_CPU_CLASS(oc); | |
118 | ||
119 | /* All we really need to set up for the 'host' CPU | |
120 | * is the feature bits -- we rely on the fact that the | |
121 | * various ID register values in ARMCPU are only used for | |
122 | * TCG CPUs. | |
123 | */ | |
124 | if (!kvm_arm_get_host_cpu_features(ahcc)) { | |
125 | fprintf(stderr, "Failed to retrieve host CPU features!\n"); | |
126 | abort(); | |
127 | } | |
128 | } | |
129 | ||
130 | static void kvm_arm_host_cpu_initfn(Object *obj) | |
131 | { | |
132 | ARMHostCPUClass *ahcc = ARM_HOST_CPU_GET_CLASS(obj); | |
133 | ARMCPU *cpu = ARM_CPU(obj); | |
134 | CPUARMState *env = &cpu->env; | |
135 | ||
136 | cpu->kvm_target = ahcc->target; | |
137 | cpu->dtb_compatible = ahcc->dtb_compatible; | |
138 | env->features = ahcc->features; | |
139 | } | |
140 | ||
141 | static const TypeInfo host_arm_cpu_type_info = { | |
142 | .name = TYPE_ARM_HOST_CPU, | |
26861c7c MH |
143 | #ifdef TARGET_AARCH64 |
144 | .parent = TYPE_AARCH64_CPU, | |
145 | #else | |
a96c0514 | 146 | .parent = TYPE_ARM_CPU, |
26861c7c | 147 | #endif |
a96c0514 PM |
148 | .instance_init = kvm_arm_host_cpu_initfn, |
149 | .class_init = kvm_arm_host_cpu_class_init, | |
150 | .class_size = sizeof(ARMHostCPUClass), | |
151 | }; | |
152 | ||
b16565b3 | 153 | int kvm_arch_init(MachineState *ms, KVMState *s) |
494b00c7 CD |
154 | { |
155 | /* For ARM interrupt delivery is always asynchronous, | |
156 | * whether we are using an in-kernel VGIC or not. | |
157 | */ | |
158 | kvm_async_interrupts_allowed = true; | |
a96c0514 PM |
159 | |
160 | type_register_static(&host_arm_cpu_type_info); | |
161 | ||
494b00c7 CD |
162 | return 0; |
163 | } | |
164 | ||
165 | unsigned long kvm_arch_vcpu_id(CPUState *cpu) | |
166 | { | |
167 | return cpu->cpu_index; | |
168 | } | |
169 | ||
eb035b48 PM |
170 | /* We track all the KVM devices which need their memory addresses |
171 | * passing to the kernel in a list of these structures. | |
172 | * When board init is complete we run through the list and | |
173 | * tell the kernel the base addresses of the memory regions. | |
174 | * We use a MemoryListener to track mapping and unmapping of | |
175 | * the regions during board creation, so the board models don't | |
176 | * need to do anything special for the KVM case. | |
177 | */ | |
178 | typedef struct KVMDevice { | |
179 | struct kvm_arm_device_addr kda; | |
1da41cc1 | 180 | struct kvm_device_attr kdattr; |
eb035b48 PM |
181 | MemoryRegion *mr; |
182 | QSLIST_ENTRY(KVMDevice) entries; | |
1da41cc1 | 183 | int dev_fd; |
eb035b48 PM |
184 | } KVMDevice; |
185 | ||
186 | static QSLIST_HEAD(kvm_devices_head, KVMDevice) kvm_devices_head; | |
187 | ||
188 | static void kvm_arm_devlistener_add(MemoryListener *listener, | |
189 | MemoryRegionSection *section) | |
190 | { | |
191 | KVMDevice *kd; | |
192 | ||
193 | QSLIST_FOREACH(kd, &kvm_devices_head, entries) { | |
194 | if (section->mr == kd->mr) { | |
195 | kd->kda.addr = section->offset_within_address_space; | |
196 | } | |
197 | } | |
198 | } | |
199 | ||
200 | static void kvm_arm_devlistener_del(MemoryListener *listener, | |
201 | MemoryRegionSection *section) | |
202 | { | |
203 | KVMDevice *kd; | |
204 | ||
205 | QSLIST_FOREACH(kd, &kvm_devices_head, entries) { | |
206 | if (section->mr == kd->mr) { | |
207 | kd->kda.addr = -1; | |
208 | } | |
209 | } | |
210 | } | |
211 | ||
212 | static MemoryListener devlistener = { | |
213 | .region_add = kvm_arm_devlistener_add, | |
214 | .region_del = kvm_arm_devlistener_del, | |
215 | }; | |
216 | ||
1da41cc1 CD |
217 | static void kvm_arm_set_device_addr(KVMDevice *kd) |
218 | { | |
219 | struct kvm_device_attr *attr = &kd->kdattr; | |
220 | int ret; | |
221 | ||
222 | /* If the device control API is available and we have a device fd on the | |
223 | * KVMDevice struct, let's use the newer API | |
224 | */ | |
225 | if (kd->dev_fd >= 0) { | |
226 | uint64_t addr = kd->kda.addr; | |
227 | attr->addr = (uintptr_t)&addr; | |
228 | ret = kvm_device_ioctl(kd->dev_fd, KVM_SET_DEVICE_ATTR, attr); | |
229 | } else { | |
230 | ret = kvm_vm_ioctl(kvm_state, KVM_ARM_SET_DEVICE_ADDR, &kd->kda); | |
231 | } | |
232 | ||
233 | if (ret < 0) { | |
234 | fprintf(stderr, "Failed to set device address: %s\n", | |
235 | strerror(-ret)); | |
236 | abort(); | |
237 | } | |
238 | } | |
239 | ||
eb035b48 PM |
240 | static void kvm_arm_machine_init_done(Notifier *notifier, void *data) |
241 | { | |
242 | KVMDevice *kd, *tkd; | |
243 | ||
244 | memory_listener_unregister(&devlistener); | |
245 | QSLIST_FOREACH_SAFE(kd, &kvm_devices_head, entries, tkd) { | |
246 | if (kd->kda.addr != -1) { | |
1da41cc1 | 247 | kvm_arm_set_device_addr(kd); |
eb035b48 | 248 | } |
dfde4e6e | 249 | memory_region_unref(kd->mr); |
eb035b48 PM |
250 | g_free(kd); |
251 | } | |
252 | } | |
253 | ||
254 | static Notifier notify = { | |
255 | .notify = kvm_arm_machine_init_done, | |
256 | }; | |
257 | ||
1da41cc1 CD |
258 | void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group, |
259 | uint64_t attr, int dev_fd) | |
eb035b48 PM |
260 | { |
261 | KVMDevice *kd; | |
262 | ||
263 | if (!kvm_irqchip_in_kernel()) { | |
264 | return; | |
265 | } | |
266 | ||
267 | if (QSLIST_EMPTY(&kvm_devices_head)) { | |
268 | memory_listener_register(&devlistener, NULL); | |
269 | qemu_add_machine_init_done_notifier(¬ify); | |
270 | } | |
271 | kd = g_new0(KVMDevice, 1); | |
272 | kd->mr = mr; | |
273 | kd->kda.id = devid; | |
274 | kd->kda.addr = -1; | |
1da41cc1 CD |
275 | kd->kdattr.flags = 0; |
276 | kd->kdattr.group = group; | |
277 | kd->kdattr.attr = attr; | |
278 | kd->dev_fd = dev_fd; | |
eb035b48 | 279 | QSLIST_INSERT_HEAD(&kvm_devices_head, kd, entries); |
dfde4e6e | 280 | memory_region_ref(kd->mr); |
eb035b48 PM |
281 | } |
282 | ||
38df27c8 AB |
283 | static int compare_u64(const void *a, const void *b) |
284 | { | |
285 | if (*(uint64_t *)a > *(uint64_t *)b) { | |
286 | return 1; | |
287 | } | |
288 | if (*(uint64_t *)a < *(uint64_t *)b) { | |
289 | return -1; | |
290 | } | |
291 | return 0; | |
292 | } | |
293 | ||
294 | /* Initialize the CPUState's cpreg list according to the kernel's | |
295 | * definition of what CPU registers it knows about (and throw away | |
296 | * the previous TCG-created cpreg list). | |
297 | */ | |
298 | int kvm_arm_init_cpreg_list(ARMCPU *cpu) | |
299 | { | |
300 | struct kvm_reg_list rl; | |
301 | struct kvm_reg_list *rlp; | |
302 | int i, ret, arraylen; | |
303 | CPUState *cs = CPU(cpu); | |
304 | ||
305 | rl.n = 0; | |
306 | ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl); | |
307 | if (ret != -E2BIG) { | |
308 | return ret; | |
309 | } | |
310 | rlp = g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t)); | |
311 | rlp->n = rl.n; | |
312 | ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, rlp); | |
313 | if (ret) { | |
314 | goto out; | |
315 | } | |
316 | /* Sort the list we get back from the kernel, since cpreg_tuples | |
317 | * must be in strictly ascending order. | |
318 | */ | |
319 | qsort(&rlp->reg, rlp->n, sizeof(rlp->reg[0]), compare_u64); | |
320 | ||
321 | for (i = 0, arraylen = 0; i < rlp->n; i++) { | |
322 | if (!kvm_arm_reg_syncs_via_cpreg_list(rlp->reg[i])) { | |
323 | continue; | |
324 | } | |
325 | switch (rlp->reg[i] & KVM_REG_SIZE_MASK) { | |
326 | case KVM_REG_SIZE_U32: | |
327 | case KVM_REG_SIZE_U64: | |
328 | break; | |
329 | default: | |
330 | fprintf(stderr, "Can't handle size of register in kernel list\n"); | |
331 | ret = -EINVAL; | |
332 | goto out; | |
333 | } | |
334 | ||
335 | arraylen++; | |
336 | } | |
337 | ||
338 | cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen); | |
339 | cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen); | |
340 | cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes, | |
341 | arraylen); | |
342 | cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values, | |
343 | arraylen); | |
344 | cpu->cpreg_array_len = arraylen; | |
345 | cpu->cpreg_vmstate_array_len = arraylen; | |
346 | ||
347 | for (i = 0, arraylen = 0; i < rlp->n; i++) { | |
348 | uint64_t regidx = rlp->reg[i]; | |
349 | if (!kvm_arm_reg_syncs_via_cpreg_list(regidx)) { | |
350 | continue; | |
351 | } | |
352 | cpu->cpreg_indexes[arraylen] = regidx; | |
353 | arraylen++; | |
354 | } | |
355 | assert(cpu->cpreg_array_len == arraylen); | |
356 | ||
357 | if (!write_kvmstate_to_list(cpu)) { | |
358 | /* Shouldn't happen unless kernel is inconsistent about | |
359 | * what registers exist. | |
360 | */ | |
361 | fprintf(stderr, "Initial read of kernel register state failed\n"); | |
362 | ret = -EINVAL; | |
363 | goto out; | |
364 | } | |
365 | ||
366 | out: | |
367 | g_free(rlp); | |
368 | return ret; | |
369 | } | |
370 | ||
ff047453 PM |
371 | bool write_kvmstate_to_list(ARMCPU *cpu) |
372 | { | |
373 | CPUState *cs = CPU(cpu); | |
374 | int i; | |
375 | bool ok = true; | |
376 | ||
377 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
378 | struct kvm_one_reg r; | |
379 | uint64_t regidx = cpu->cpreg_indexes[i]; | |
380 | uint32_t v32; | |
381 | int ret; | |
382 | ||
383 | r.id = regidx; | |
384 | ||
385 | switch (regidx & KVM_REG_SIZE_MASK) { | |
386 | case KVM_REG_SIZE_U32: | |
387 | r.addr = (uintptr_t)&v32; | |
388 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); | |
389 | if (!ret) { | |
390 | cpu->cpreg_values[i] = v32; | |
391 | } | |
392 | break; | |
393 | case KVM_REG_SIZE_U64: | |
394 | r.addr = (uintptr_t)(cpu->cpreg_values + i); | |
395 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); | |
396 | break; | |
397 | default: | |
398 | abort(); | |
399 | } | |
400 | if (ret) { | |
401 | ok = false; | |
402 | } | |
403 | } | |
404 | return ok; | |
405 | } | |
406 | ||
407 | bool write_list_to_kvmstate(ARMCPU *cpu) | |
408 | { | |
409 | CPUState *cs = CPU(cpu); | |
410 | int i; | |
411 | bool ok = true; | |
412 | ||
413 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
414 | struct kvm_one_reg r; | |
415 | uint64_t regidx = cpu->cpreg_indexes[i]; | |
416 | uint32_t v32; | |
417 | int ret; | |
418 | ||
419 | r.id = regidx; | |
420 | switch (regidx & KVM_REG_SIZE_MASK) { | |
421 | case KVM_REG_SIZE_U32: | |
422 | v32 = cpu->cpreg_values[i]; | |
423 | r.addr = (uintptr_t)&v32; | |
424 | break; | |
425 | case KVM_REG_SIZE_U64: | |
426 | r.addr = (uintptr_t)(cpu->cpreg_values + i); | |
427 | break; | |
428 | default: | |
429 | abort(); | |
430 | } | |
431 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); | |
432 | if (ret) { | |
433 | /* We might fail for "unknown register" and also for | |
434 | * "you tried to set a register which is constant with | |
435 | * a different value from what it actually contains". | |
436 | */ | |
437 | ok = false; | |
438 | } | |
439 | } | |
440 | return ok; | |
441 | } | |
442 | ||
38df27c8 AB |
443 | void kvm_arm_reset_vcpu(ARMCPU *cpu) |
444 | { | |
25f2895e CD |
445 | int ret; |
446 | ||
38df27c8 AB |
447 | /* Re-init VCPU so that all registers are set to |
448 | * their respective reset values. | |
449 | */ | |
25f2895e CD |
450 | ret = kvm_arm_vcpu_init(CPU(cpu)); |
451 | if (ret < 0) { | |
452 | fprintf(stderr, "kvm_arm_vcpu_init failed: %s\n", strerror(-ret)); | |
453 | abort(); | |
454 | } | |
455 | if (!write_kvmstate_to_list(cpu)) { | |
456 | fprintf(stderr, "write_kvmstate_to_list failed\n"); | |
457 | abort(); | |
458 | } | |
38df27c8 AB |
459 | } |
460 | ||
494b00c7 CD |
461 | void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) |
462 | { | |
463 | } | |
464 | ||
465 | void kvm_arch_post_run(CPUState *cs, struct kvm_run *run) | |
466 | { | |
467 | } | |
468 | ||
469 | int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) | |
470 | { | |
471 | return 0; | |
472 | } | |
473 | ||
494b00c7 CD |
474 | bool kvm_arch_stop_on_emulation_error(CPUState *cs) |
475 | { | |
476 | return true; | |
477 | } | |
478 | ||
479 | int kvm_arch_process_async_events(CPUState *cs) | |
480 | { | |
481 | return 0; | |
482 | } | |
483 | ||
484 | int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr) | |
485 | { | |
486 | return 1; | |
487 | } | |
488 | ||
489 | int kvm_arch_on_sigbus(int code, void *addr) | |
490 | { | |
491 | return 1; | |
492 | } | |
493 | ||
494 | void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) | |
495 | { | |
496 | qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); | |
497 | } | |
498 | ||
499 | int kvm_arch_insert_sw_breakpoint(CPUState *cs, | |
500 | struct kvm_sw_breakpoint *bp) | |
501 | { | |
502 | qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); | |
503 | return -EINVAL; | |
504 | } | |
505 | ||
506 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
507 | target_ulong len, int type) | |
508 | { | |
509 | qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); | |
510 | return -EINVAL; | |
511 | } | |
512 | ||
513 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
514 | target_ulong len, int type) | |
515 | { | |
516 | qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); | |
517 | return -EINVAL; | |
518 | } | |
519 | ||
520 | int kvm_arch_remove_sw_breakpoint(CPUState *cs, | |
521 | struct kvm_sw_breakpoint *bp) | |
522 | { | |
523 | qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); | |
524 | return -EINVAL; | |
525 | } | |
526 | ||
527 | void kvm_arch_remove_all_hw_breakpoints(void) | |
528 | { | |
529 | qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); | |
530 | } | |
b3a1c626 AK |
531 | |
532 | void kvm_arch_init_irq_routing(KVMState *s) | |
533 | { | |
534 | } | |
1da41cc1 CD |
535 | |
536 | int kvm_arch_irqchip_create(KVMState *s) | |
537 | { | |
538 | int ret; | |
539 | ||
540 | /* If we can create the VGIC using the newer device control API, we | |
541 | * let the device do this when it initializes itself, otherwise we | |
542 | * fall back to the old API */ | |
543 | ||
544 | ret = kvm_create_device(s, KVM_DEV_TYPE_ARM_VGIC_V2, true); | |
545 | if (ret == 0) { | |
546 | return 1; | |
547 | } | |
548 | ||
549 | return 0; | |
550 | } | |
9e03a040 FB |
551 | |
552 | int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, | |
553 | uint64_t address, uint32_t data) | |
554 | { | |
555 | return 0; | |
556 | } |