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Fix OMAP pic handling of simultaneous interrupts.
[qemu.git] / hw / omap.c
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c3d2689d
AZ		 1/*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2006-2007 Andrzej Zaborowski <[email protected]>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21#include "vl.h"
22#include "arm_pic.h"
23
24/* Should signal the TCMI */
25static uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
26{
27 OMAP_16B_REG(addr);
28 return 0;
29}
30
31static void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
32 uint32_t value)
33{
34 OMAP_16B_REG(addr);
35}
36
37static uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
38{
39 OMAP_32B_REG(addr);
40 return 0;
41}
42
43static void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
44 uint32_t value)
45{
46 OMAP_32B_REG(addr);
47}
48
49#define likely
50#define unlikely
51
52/* Interrupt Handlers */
53struct omap_intr_handler_s {
54 qemu_irq *pins;
55 qemu_irq *parent_pic;
56 target_phys_addr_t base;
57
58 /* state */
59 uint32_t irqs;
60 uint32_t mask;
61 uint32_t sens_edge;
62 uint32_t fiq;
63 int priority[32];
64 uint32_t new_irq_agr;
65 uint32_t new_fiq_agr;
66 int sir_irq;
67 int sir_fiq;
68 int stats[32];
69};
70
71static void omap_inth_update(struct omap_intr_handler_s *s)
72{
cfa0b71d
AZ		 73 uint32_t irq = s->irqs & ~s->mask & ~s->fiq;
74 uint32_t fiq = s->irqs & ~s->mask & s->fiq;
c3d2689d 75
cfa0b71d
AZ		 76 if (s->new_irq_agr || !irq) {
77 qemu_set_irq(s->parent_pic[ARM_PIC_CPU_IRQ], irq);
78 if (irq)
79 s->new_irq_agr = 0;
80 }
c3d2689d 81
cfa0b71d
AZ		 82 if (s->new_fiq_agr || !irq) {
83 qemu_set_irq(s->parent_pic[ARM_PIC_CPU_FIQ], fiq);
84 if (fiq)
85 s->new_fiq_agr = 0;
86 }
c3d2689d
AZ		 87}
88
89static void omap_inth_sir_update(struct omap_intr_handler_s *s)
90{
91 int i, intr_irq, intr_fiq, p_irq, p_fiq, p, f;
92 uint32_t level = s->irqs & ~s->mask;
93
94 intr_irq = 0;
95 intr_fiq = 0;
96 p_irq = -1;
97 p_fiq = -1;
98 /* Find the interrupt line with the highest dynamic priority */
99 for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f, level >>= f) {
100 p = s->priority[i];
101 if (s->fiq & (1 << i)) {
102 if (p > p_fiq) {
103 p_fiq = p;
104 intr_fiq = i;
105 }
106 } else {
107 if (p > p_irq) {
108 p_irq = p;
109 intr_irq = i;
110 }
111 }
112
113 f = ffs(level >> 1);
114 }
115
116 s->sir_irq = intr_irq;
117 s->sir_fiq = intr_fiq;
118}
119
120#define INT_FALLING_EDGE 0
121#define INT_LOW_LEVEL 1
122
123static void omap_set_intr(void *opaque, int irq, int req)
124{
125 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
126 uint32_t rise;
127
128 if (req) {
129 rise = ~ih->irqs & (1 << irq);
130 ih->irqs |= rise;
cfa0b71d 131 ih->stats[irq] += !!rise;
c3d2689d
AZ		 132 } else {
133 rise = ih->sens_edge & ih->irqs & (1 << irq);
134 ih->irqs &= ~rise;
135 }
136
137 if (rise & ~ih->mask) {
138 omap_inth_sir_update(ih);
139
140 omap_inth_update(ih);
141 }
142}
143
144static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
145{
146 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
147 int i, offset = addr - s->base;
148
149 switch (offset) {
150 case 0x00: /* ITR */
151 return s->irqs;
152
153 case 0x04: /* MIR */
154 return s->mask;
155
156 case 0x10: /* SIR_IRQ_CODE */
157 i = s->sir_irq;
158 if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) {
159 s->irqs &= ~(1 << i);
160 omap_inth_sir_update(s);
161 omap_inth_update(s);
162 }
163 return i;
164
165 case 0x14: /* SIR_FIQ_CODE */
166 i = s->sir_fiq;
167 if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) {
168 s->irqs &= ~(1 << i);
169 omap_inth_sir_update(s);
170 omap_inth_update(s);
171 }
172 return i;
173
174 case 0x18: /* CONTROL_REG */
175 return 0;
176
177 case 0x1c: /* ILR0 */
178 case 0x20: /* ILR1 */
179 case 0x24: /* ILR2 */
180 case 0x28: /* ILR3 */
181 case 0x2c: /* ILR4 */
182 case 0x30: /* ILR5 */
183 case 0x34: /* ILR6 */
184 case 0x38: /* ILR7 */
185 case 0x3c: /* ILR8 */
186 case 0x40: /* ILR9 */
187 case 0x44: /* ILR10 */
188 case 0x48: /* ILR11 */
189 case 0x4c: /* ILR12 */
190 case 0x50: /* ILR13 */
191 case 0x54: /* ILR14 */
192 case 0x58: /* ILR15 */
193 case 0x5c: /* ILR16 */
194 case 0x60: /* ILR17 */
195 case 0x64: /* ILR18 */
196 case 0x68: /* ILR19 */
197 case 0x6c: /* ILR20 */
198 case 0x70: /* ILR21 */
199 case 0x74: /* ILR22 */
200 case 0x78: /* ILR23 */
201 case 0x7c: /* ILR24 */
202 case 0x80: /* ILR25 */
203 case 0x84: /* ILR26 */
204 case 0x88: /* ILR27 */
205 case 0x8c: /* ILR28 */
206 case 0x90: /* ILR29 */
207 case 0x94: /* ILR30 */
208 case 0x98: /* ILR31 */
209 i = (offset - 0x1c) >> 2;
210 return (s->priority[i] << 2) |
211 (((s->sens_edge >> i) & 1) << 1) |
212 ((s->fiq >> i) & 1);
213
214 case 0x9c: /* ISR */
215 return 0x00000000;
216
217 default:
218 OMAP_BAD_REG(addr);
219 break;
220 }
221 return 0;
222}
223
224static void omap_inth_write(void *opaque, target_phys_addr_t addr,
225 uint32_t value)
226{
227 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
228 int i, offset = addr - s->base;
229
230 switch (offset) {
231 case 0x00: /* ITR */
232 s->irqs &= value;
233 omap_inth_sir_update(s);
234 omap_inth_update(s);
235 return;
236
237 case 0x04: /* MIR */
238 s->mask = value;
239 omap_inth_sir_update(s);
240 omap_inth_update(s);
241 return;
242
243 case 0x10: /* SIR_IRQ_CODE */
244 case 0x14: /* SIR_FIQ_CODE */
245 OMAP_RO_REG(addr);
246 break;
247
248 case 0x18: /* CONTROL_REG */
249 if (value & 2)
250 s->new_fiq_agr = ~0;
251 if (value & 1)
252 s->new_irq_agr = ~0;
253 omap_inth_update(s);
254 return;
255
256 case 0x1c: /* ILR0 */
257 case 0x20: /* ILR1 */
258 case 0x24: /* ILR2 */
259 case 0x28: /* ILR3 */
260 case 0x2c: /* ILR4 */
261 case 0x30: /* ILR5 */
262 case 0x34: /* ILR6 */
263 case 0x38: /* ILR7 */
264 case 0x3c: /* ILR8 */
265 case 0x40: /* ILR9 */
266 case 0x44: /* ILR10 */
267 case 0x48: /* ILR11 */
268 case 0x4c: /* ILR12 */
269 case 0x50: /* ILR13 */
270 case 0x54: /* ILR14 */
271 case 0x58: /* ILR15 */
272 case 0x5c: /* ILR16 */
273 case 0x60: /* ILR17 */
274 case 0x64: /* ILR18 */
275 case 0x68: /* ILR19 */
276 case 0x6c: /* ILR20 */
277 case 0x70: /* ILR21 */
278 case 0x74: /* ILR22 */
279 case 0x78: /* ILR23 */
280 case 0x7c: /* ILR24 */
281 case 0x80: /* ILR25 */
282 case 0x84: /* ILR26 */
283 case 0x88: /* ILR27 */
284 case 0x8c: /* ILR28 */
285 case 0x90: /* ILR29 */
286 case 0x94: /* ILR30 */
287 case 0x98: /* ILR31 */
288 i = (offset - 0x1c) >> 2;
289 s->priority[i] = (value >> 2) & 0x1f;
290 s->sens_edge &= ~(1 << i);
291 s->sens_edge |= ((value >> 1) & 1) << i;
292 s->fiq &= ~(1 << i);
293 s->fiq |= (value & 1) << i;
294 return;
295
296 case 0x9c: /* ISR */
297 for (i = 0; i < 32; i ++)
298 if (value & (1 << i)) {
299 omap_set_intr(s, i, 1);
300 return;
301 }
302 return;
303
304 default:
305 OMAP_BAD_REG(addr);
306 }
307}
308
309static CPUReadMemoryFunc *omap_inth_readfn[] = {
310 omap_badwidth_read32,
311 omap_badwidth_read32,
312 omap_inth_read,
313};
314
315static CPUWriteMemoryFunc *omap_inth_writefn[] = {
316 omap_inth_write,
317 omap_inth_write,
318 omap_inth_write,
319};
320
321static void omap_inth_reset(struct omap_intr_handler_s *s)
322{
323 s->irqs = 0x00000000;
324 s->mask = 0xffffffff;
325 s->sens_edge = 0x00000000;
326 s->fiq = 0x00000000;
327 memset(s->priority, 0, sizeof(s->priority));
328 s->new_irq_agr = ~0;
329 s->new_fiq_agr = ~0;
330 s->sir_irq = 0;
331 s->sir_fiq = 0;
332
333 omap_inth_update(s);
334}
335
336struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
337 unsigned long size, qemu_irq parent[2], omap_clk clk)
338{
339 int iomemtype;
340 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
341 qemu_mallocz(sizeof(struct omap_intr_handler_s));
342
343 s->parent_pic = parent;
344 s->base = base;
345 s->pins = qemu_allocate_irqs(omap_set_intr, s, 32);
346 omap_inth_reset(s);
347
348 iomemtype = cpu_register_io_memory(0, omap_inth_readfn,
349 omap_inth_writefn, s);
350 cpu_register_physical_memory(s->base, size, iomemtype);
351
352 return s;
353}
354
355/* OMAP1 DMA module */
356typedef enum {
357 constant = 0,
358 post_incremented,
359 single_index,
360 double_index,
361} omap_dma_addressing_t;
362
363struct omap_dma_channel_s {
364 int burst[2];
365 int pack[2];
366 enum omap_dma_port port[2];
367 target_phys_addr_t addr[2];
368 omap_dma_addressing_t mode[2];
369 int data_type;
370 int end_prog;
371 int repeat;
372 int auto_init;
373 int priority;
374 int fs;
375 int sync;
376 int running;
377 int interrupts;
378 int status;
379 int signalled;
380 int post_sync;
381 int transfer;
382 uint16_t elements;
383 uint16_t frames;
384 uint16_t frame_index;
385 uint16_t element_index;
386 uint16_t cpc;
387
388 struct omap_dma_reg_set_s {
389 target_phys_addr_t src, dest;
390 int frame;
391 int element;
392 int frame_delta[2];
393 int elem_delta[2];
394 int frames;
395 int elements;
396 } active_set;
397};
398
399struct omap_dma_s {
400 qemu_irq *ih;
401 QEMUTimer *tm;
402 struct omap_mpu_state_s *mpu;
403 target_phys_addr_t base;
404 omap_clk clk;
405 int64_t delay;
406
407 uint16_t gcr;
408 int run_count;
409
410 int chans;
411 struct omap_dma_channel_s ch[16];
412 struct omap_dma_lcd_channel_s lcd_ch;
413};
414
415static void omap_dma_interrupts_update(struct omap_dma_s *s)
416{
417 /* First three interrupts are shared between two channels each. */
418 qemu_set_irq(s->ih[OMAP_INT_DMA_CH0_6],
419 (s->ch[0].status | s->ch[6].status) & 0x3f);
420 qemu_set_irq(s->ih[OMAP_INT_DMA_CH1_7],
421 (s->ch[1].status | s->ch[7].status) & 0x3f);
422 qemu_set_irq(s->ih[OMAP_INT_DMA_CH2_8],
423 (s->ch[2].status | s->ch[8].status) & 0x3f);
424 qemu_set_irq(s->ih[OMAP_INT_DMA_CH3],
425 (s->ch[3].status) & 0x3f);
426 qemu_set_irq(s->ih[OMAP_INT_DMA_CH4],
427 (s->ch[4].status) & 0x3f);
428 qemu_set_irq(s->ih[OMAP_INT_DMA_CH5],
429 (s->ch[5].status) & 0x3f);
430}
431
432static void omap_dma_channel_load(struct omap_dma_s *s, int ch)
433{
434 struct omap_dma_reg_set_s *a = &s->ch[ch].active_set;
435 int i;
436
437 /*
438 * TODO: verify address ranges and alignment
439 * TODO: port endianness
440 */
441
442 a->src = s->ch[ch].addr[0];
443 a->dest = s->ch[ch].addr[1];
444 a->frames = s->ch[ch].frames;
445 a->elements = s->ch[ch].elements;
446 a->frame = 0;
447 a->element = 0;
448
449 if (unlikely(!s->ch[ch].elements || !s->ch[ch].frames)) {
450 printf("%s: bad DMA request\n", __FUNCTION__);
451 return;
452 }
453
454 for (i = 0; i < 2; i ++)
455 switch (s->ch[ch].mode[i]) {
456 case constant:
457 a->elem_delta[i] = 0;
458 a->frame_delta[i] = 0;
459 break;
460 case post_incremented:
461 a->elem_delta[i] = s->ch[ch].data_type;
462 a->frame_delta[i] = 0;
463 break;
464 case single_index:
465 a->elem_delta[i] = s->ch[ch].data_type +
466 s->ch[ch].element_index - 1;
467 if (s->ch[ch].element_index > 0x7fff)
468 a->elem_delta[i] -= 0x10000;
469 a->frame_delta[i] = 0;
470 break;
471 case double_index:
472 a->elem_delta[i] = s->ch[ch].data_type +
473 s->ch[ch].element_index - 1;
474 if (s->ch[ch].element_index > 0x7fff)
475 a->elem_delta[i] -= 0x10000;
476 a->frame_delta[i] = s->ch[ch].frame_index -
477 s->ch[ch].element_index;
478 if (s->ch[ch].frame_index > 0x7fff)
479 a->frame_delta[i] -= 0x10000;
480 break;
481 default:
482 break;
483 }
484}
485
486static inline void omap_dma_request_run(struct omap_dma_s *s,
487 int channel, int request)
488{
489next_channel:
490 if (request > 0)
491 for (; channel < 9; channel ++)
492 if (s->ch[channel].sync == request && s->ch[channel].running)
493 break;
494 if (channel >= 9)
495 return;
496
497 if (s->ch[channel].transfer) {
498 if (request > 0) {
499 s->ch[channel ++].post_sync = request;
500 goto next_channel;
501 }
502 s->ch[channel].status |= 0x02; /* Synchronisation drop */
503 omap_dma_interrupts_update(s);
504 return;
505 }
506
507 if (!s->ch[channel].signalled)
508 s->run_count ++;
509 s->ch[channel].signalled = 1;
510
511 if (request > 0)
512 s->ch[channel].status |= 0x40; /* External request */
513
514 if (s->delay)
515 qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
516
517 if (request > 0) {
518 channel ++;
519 goto next_channel;
520 }
521}
522
523static inline void omap_dma_request_stop(struct omap_dma_s *s, int channel)
524{
525 if (s->ch[channel].signalled)
526 s->run_count --;
527 s->ch[channel].signalled = 0;
528
529 if (!s->run_count)
530 qemu_del_timer(s->tm);
531}
532
533static void omap_dma_channel_run(struct omap_dma_s *s)
534{
535 int ch;
536 uint16_t status;
537 uint8_t value[4];
538 struct omap_dma_port_if_s *src_p, *dest_p;
539 struct omap_dma_reg_set_s *a;
540
541 for (ch = 0; ch < 9; ch ++) {
542 a = &s->ch[ch].active_set;
543
544 src_p = &s->mpu->port[s->ch[ch].port[0]];
545 dest_p = &s->mpu->port[s->ch[ch].port[1]];
546 if (s->ch[ch].signalled && (!src_p->addr_valid(s->mpu, a->src) ||
547 !dest_p->addr_valid(s->mpu, a->dest))) {
548#if 0
549 /* Bus time-out */
550 if (s->ch[ch].interrupts & 0x01)
551 s->ch[ch].status |= 0x01;
552 omap_dma_request_stop(s, ch);
553 continue;
554#endif
555 printf("%s: Bus time-out in DMA%i operation\n", __FUNCTION__, ch);
556 }
557
558 status = s->ch[ch].status;
559 while (status == s->ch[ch].status && s->ch[ch].signalled) {
560 /* Transfer a single element */
561 s->ch[ch].transfer = 1;
562 cpu_physical_memory_read(a->src, value, s->ch[ch].data_type);
563 cpu_physical_memory_write(a->dest, value, s->ch[ch].data_type);
564 s->ch[ch].transfer = 0;
565
566 a->src += a->elem_delta[0];
567 a->dest += a->elem_delta[1];
568 a->element ++;
569
570 /* Check interrupt conditions */
571 if (a->element == a->elements) {
572 a->element = 0;
573 a->src += a->frame_delta[0];
574 a->dest += a->frame_delta[1];
575 a->frame ++;
576
577 if (a->frame == a->frames) {
578 if (!s->ch[ch].repeat || !s->ch[ch].auto_init)
579 s->ch[ch].running = 0;
580
581 if (s->ch[ch].auto_init &&
582 (s->ch[ch].repeat ||
583 s->ch[ch].end_prog))
584 omap_dma_channel_load(s, ch);
585
586 if (s->ch[ch].interrupts & 0x20)
587 s->ch[ch].status |= 0x20;
588
589 if (!s->ch[ch].sync)
590 omap_dma_request_stop(s, ch);
591 }
592
593 if (s->ch[ch].interrupts & 0x08)
594 s->ch[ch].status |= 0x08;
595
596 if (s->ch[ch].sync && s->ch[ch].fs) {
597 s->ch[ch].status &= ~0x40;
598 omap_dma_request_stop(s, ch);
599 }
600 }
601
602 if (a->element == 1 && a->frame == a->frames - 1)
603 if (s->ch[ch].interrupts & 0x10)
604 s->ch[ch].status |= 0x10;
605
606 if (a->element == (a->elements >> 1))
607 if (s->ch[ch].interrupts & 0x04)
608 s->ch[ch].status |= 0x04;
609
610 if (s->ch[ch].sync && !s->ch[ch].fs) {
611 s->ch[ch].status &= ~0x40;
612 omap_dma_request_stop(s, ch);
613 }
614
615 /*
616 * Process requests made while the element was
617 * being transferred.
618 */
619 if (s->ch[ch].post_sync) {
620 omap_dma_request_run(s, 0, s->ch[ch].post_sync);
621 s->ch[ch].post_sync = 0;
622 }
623
624#if 0
625 break;
626#endif
627 }
628
629 s->ch[ch].cpc = a->dest & 0x0000ffff;
630 }
631
632 omap_dma_interrupts_update(s);
633 if (s->run_count && s->delay)
634 qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
635}
636
637static int omap_dma_ch_reg_read(struct omap_dma_s *s,
638 int ch, int reg, uint16_t *value) {
639 switch (reg) {
640 case 0x00: /* SYS_DMA_CSDP_CH0 */
641 *value = (s->ch[ch].burst[1] << 14) |
642 (s->ch[ch].pack[1] << 13) |
643 (s->ch[ch].port[1] << 9) |
644 (s->ch[ch].burst[0] << 7) |
645 (s->ch[ch].pack[0] << 6) |
646 (s->ch[ch].port[0] << 2) |
647 (s->ch[ch].data_type >> 1);
648 break;
649
650 case 0x02: /* SYS_DMA_CCR_CH0 */
651 *value = (s->ch[ch].mode[1] << 14) |
652 (s->ch[ch].mode[0] << 12) |
653 (s->ch[ch].end_prog << 11) |
654 (s->ch[ch].repeat << 9) |
655 (s->ch[ch].auto_init << 8) |
656 (s->ch[ch].running << 7) |
657 (s->ch[ch].priority << 6) |
658 (s->ch[ch].fs << 5) | s->ch[ch].sync;
659 break;
660
661 case 0x04: /* SYS_DMA_CICR_CH0 */
662 *value = s->ch[ch].interrupts;
663 break;
664
665 case 0x06: /* SYS_DMA_CSR_CH0 */
666 /* FIXME: shared CSR for channels sharing the interrupts */
667 *value = s->ch[ch].status;
668 s->ch[ch].status &= 0x40;
669 omap_dma_interrupts_update(s);
670 break;
671
672 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
673 *value = s->ch[ch].addr[0] & 0x0000ffff;
674 break;
675
676 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
677 *value = s->ch[ch].addr[0] >> 16;
678 break;
679
680 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
681 *value = s->ch[ch].addr[1] & 0x0000ffff;
682 break;
683
684 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
685 *value = s->ch[ch].addr[1] >> 16;
686 break;
687
688 case 0x10: /* SYS_DMA_CEN_CH0 */
689 *value = s->ch[ch].elements;
690 break;
691
692 case 0x12: /* SYS_DMA_CFN_CH0 */
693 *value = s->ch[ch].frames;
694 break;
695
696 case 0x14: /* SYS_DMA_CFI_CH0 */
697 *value = s->ch[ch].frame_index;
698 break;
699
700 case 0x16: /* SYS_DMA_CEI_CH0 */
701 *value = s->ch[ch].element_index;
702 break;
703
704 case 0x18: /* SYS_DMA_CPC_CH0 */
705 *value = s->ch[ch].cpc;
706 break;
707
708 default:
709 return 1;
710 }
711 return 0;
712}
713
714static int omap_dma_ch_reg_write(struct omap_dma_s *s,
715 int ch, int reg, uint16_t value) {
716 switch (reg) {
717 case 0x00: /* SYS_DMA_CSDP_CH0 */
718 s->ch[ch].burst[1] = (value & 0xc000) >> 14;
719 s->ch[ch].pack[1] = (value & 0x2000) >> 13;
720 s->ch[ch].port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
721 s->ch[ch].burst[0] = (value & 0x0180) >> 7;
722 s->ch[ch].pack[0] = (value & 0x0040) >> 6;
723 s->ch[ch].port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
724 s->ch[ch].data_type = (1 << (value & 3));
725 if (s->ch[ch].port[0] >= omap_dma_port_last)
726 printf("%s: invalid DMA port %i\n", __FUNCTION__,
727 s->ch[ch].port[0]);
728 if (s->ch[ch].port[1] >= omap_dma_port_last)
729 printf("%s: invalid DMA port %i\n", __FUNCTION__,
730 s->ch[ch].port[1]);
731 if ((value & 3) == 3)
732 printf("%s: bad data_type for DMA channel %i\n", __FUNCTION__, ch);
733 break;
734
735 case 0x02: /* SYS_DMA_CCR_CH0 */
736 s->ch[ch].mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
737 s->ch[ch].mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
738 s->ch[ch].end_prog = (value & 0x0800) >> 11;
739 s->ch[ch].repeat = (value & 0x0200) >> 9;
740 s->ch[ch].auto_init = (value & 0x0100) >> 8;
741 s->ch[ch].priority = (value & 0x0040) >> 6;
742 s->ch[ch].fs = (value & 0x0020) >> 5;
743 s->ch[ch].sync = value & 0x001f;
744 if (value & 0x0080) {
745 if (s->ch[ch].running) {
746 if (!s->ch[ch].signalled &&
747 s->ch[ch].auto_init && s->ch[ch].end_prog)
748 omap_dma_channel_load(s, ch);
749 } else {
750 s->ch[ch].running = 1;
751 omap_dma_channel_load(s, ch);
752 }
753 if (!s->ch[ch].sync)
754 omap_dma_request_run(s, ch, 0);
755 } else {
756 s->ch[ch].running = 0;
757 omap_dma_request_stop(s, ch);
758 }
759 break;
760
761 case 0x04: /* SYS_DMA_CICR_CH0 */
762 s->ch[ch].interrupts = value & 0x003f;
763 break;
764
765 case 0x06: /* SYS_DMA_CSR_CH0 */
766 return 1;
767
768 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
769 s->ch[ch].addr[0] &= 0xffff0000;
770 s->ch[ch].addr[0] |= value;
771 break;
772
773 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
774 s->ch[ch].addr[0] &= 0x0000ffff;
775 s->ch[ch].addr[0] |= value << 16;
776 break;
777
778 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
779 s->ch[ch].addr[1] &= 0xffff0000;
780 s->ch[ch].addr[1] |= value;
781 break;
782
783 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
784 s->ch[ch].addr[1] &= 0x0000ffff;
785 s->ch[ch].addr[1] |= value << 16;
786 break;
787
788 case 0x10: /* SYS_DMA_CEN_CH0 */
789 s->ch[ch].elements = value & 0xffff;
790 break;
791
792 case 0x12: /* SYS_DMA_CFN_CH0 */
793 s->ch[ch].frames = value & 0xffff;
794 break;
795
796 case 0x14: /* SYS_DMA_CFI_CH0 */
797 s->ch[ch].frame_index = value & 0xffff;
798 break;
799
800 case 0x16: /* SYS_DMA_CEI_CH0 */
801 s->ch[ch].element_index = value & 0xffff;
802 break;
803
804 case 0x18: /* SYS_DMA_CPC_CH0 */
805 return 1;
806
807 default:
808 OMAP_BAD_REG((unsigned long) reg);
809 }
810 return 0;
811}
812
813static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
814{
815 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
816 int i, reg, ch, offset = addr - s->base;
817 uint16_t ret;
818
819 switch (offset) {
820 case 0x000 ... 0x2fe:
821 reg = offset & 0x3f;
822 ch = (offset >> 6) & 0x0f;
823 if (omap_dma_ch_reg_read(s, ch, reg, &ret))
824 break;
825 return ret;
826
827 case 0x300: /* SYS_DMA_LCD_CTRL */
828 i = s->lcd_ch.condition;
829 s->lcd_ch.condition = 0;
830 qemu_irq_lower(s->lcd_ch.irq);
831 return ((s->lcd_ch.src == imif) << 6) | (i << 3) |
832 (s->lcd_ch.interrupts << 1) | s->lcd_ch.dual;
833
834 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
835 return s->lcd_ch.src_f1_top & 0xffff;
836
837 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
838 return s->lcd_ch.src_f1_top >> 16;
839
840 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
841 return s->lcd_ch.src_f1_bottom & 0xffff;
842
843 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
844 return s->lcd_ch.src_f1_bottom >> 16;
845
846 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
847 return s->lcd_ch.src_f2_top & 0xffff;
848
849 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
850 return s->lcd_ch.src_f2_top >> 16;
851
852 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
853 return s->lcd_ch.src_f2_bottom & 0xffff;
854
855 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
856 return s->lcd_ch.src_f2_bottom >> 16;
857
858 case 0x400: /* SYS_DMA_GCR */
859 return s->gcr;
860 }
861
862 OMAP_BAD_REG(addr);
863 return 0;
864}
865
866static void omap_dma_write(void *opaque, target_phys_addr_t addr,
867 uint32_t value)
868{
869 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
870 int reg, ch, offset = addr - s->base;
871
872 switch (offset) {
873 case 0x000 ... 0x2fe:
874 reg = offset & 0x3f;
875 ch = (offset >> 6) & 0x0f;
876 if (omap_dma_ch_reg_write(s, ch, reg, value))
877 OMAP_RO_REG(addr);
878 break;
879
880 case 0x300: /* SYS_DMA_LCD_CTRL */
881 s->lcd_ch.src = (value & 0x40) ? imif : emiff;
882 s->lcd_ch.condition = 0;
883 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
884 s->lcd_ch.interrupts = (value >> 1) & 1;
885 s->lcd_ch.dual = value & 1;
886 break;
887
888 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
889 s->lcd_ch.src_f1_top &= 0xffff0000;
890 s->lcd_ch.src_f1_top |= 0x0000ffff & value;
891 break;
892
893 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
894 s->lcd_ch.src_f1_top &= 0x0000ffff;
895 s->lcd_ch.src_f1_top |= value << 16;
896 break;
897
898 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
899 s->lcd_ch.src_f1_bottom &= 0xffff0000;
900 s->lcd_ch.src_f1_bottom |= 0x0000ffff & value;
901 break;
902
903 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
904 s->lcd_ch.src_f1_bottom &= 0x0000ffff;
905 s->lcd_ch.src_f1_bottom |= value << 16;
906 break;
907
908 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
909 s->lcd_ch.src_f2_top &= 0xffff0000;
910 s->lcd_ch.src_f2_top |= 0x0000ffff & value;
911 break;
912
913 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
914 s->lcd_ch.src_f2_top &= 0x0000ffff;
915 s->lcd_ch.src_f2_top |= value << 16;
916 break;
917
918 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
919 s->lcd_ch.src_f2_bottom &= 0xffff0000;
920 s->lcd_ch.src_f2_bottom |= 0x0000ffff & value;
921 break;
922
923 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
924 s->lcd_ch.src_f2_bottom &= 0x0000ffff;
925 s->lcd_ch.src_f2_bottom |= value << 16;
926 break;
927
928 case 0x400: /* SYS_DMA_GCR */
929 s->gcr = value & 0x000c;
930 break;
931
932 default:
933 OMAP_BAD_REG(addr);
934 }
935}
936
937static CPUReadMemoryFunc *omap_dma_readfn[] = {
938 omap_badwidth_read16,
939 omap_dma_read,
940 omap_badwidth_read16,
941};
942
943static CPUWriteMemoryFunc *omap_dma_writefn[] = {
944 omap_badwidth_write16,
945 omap_dma_write,
946 omap_badwidth_write16,
947};
948
949static void omap_dma_request(void *opaque, int drq, int req)
950{
951 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
952 /* All the request pins are edge triggered. */
953 if (req)
954 omap_dma_request_run(s, 0, drq);
955}
956
957static void omap_dma_clk_update(void *opaque, int line, int on)
958{
959 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
960
961 if (on) {
962 s->delay = ticks_per_sec >> 5;
963 if (s->run_count)
964 qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
965 } else {
966 s->delay = 0;
967 qemu_del_timer(s->tm);
968 }
969}
970
971static void omap_dma_reset(struct omap_dma_s *s)
972{
973 int i;
974
975 qemu_del_timer(s->tm);
976 s->gcr = 0x0004;
977 s->run_count = 0;
978 s->lcd_ch.src = emiff;
979 s->lcd_ch.condition = 0;
980 s->lcd_ch.interrupts = 0;
981 s->lcd_ch.dual = 0;
982 memset(s->ch, 0, sizeof(s->ch));
983 for (i = 0; i < s->chans; i ++)
984 s->ch[i].interrupts = 0x0003;
985}
986
987struct omap_dma_s *omap_dma_init(target_phys_addr_t base,
988 qemu_irq pic[], struct omap_mpu_state_s *mpu, omap_clk clk)
989{
990 int iomemtype;
991 struct omap_dma_s *s = (struct omap_dma_s *)
992 qemu_mallocz(sizeof(struct omap_dma_s));
993
994 s->ih = pic;
995 s->base = base;
996 s->chans = 9;
997 s->mpu = mpu;
998 s->clk = clk;
999 s->lcd_ch.irq = pic[OMAP_INT_DMA_LCD];
1000 s->lcd_ch.mpu = mpu;
1001 s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s);
1002 omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
1003 mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
1004 omap_dma_reset(s);
1005
1006 iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
1007 omap_dma_writefn, s);
1008 cpu_register_physical_memory(s->base, 0x800, iomemtype);
1009
1010 return s;
1011}
1012
1013/* DMA ports */
1014int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
1015 target_phys_addr_t addr)
1016{
1017 return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
1018}
1019
1020int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
1021 target_phys_addr_t addr)
1022{
1023 return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
1024}
1025
1026int omap_validate_imif_addr(struct omap_mpu_state_s *s,
1027 target_phys_addr_t addr)
1028{
1029 return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
1030}
1031
1032int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
1033 target_phys_addr_t addr)
1034{
1035 return addr >= 0xfffb0000 && addr < 0xffff0000;
1036}
1037
1038int omap_validate_local_addr(struct omap_mpu_state_s *s,
1039 target_phys_addr_t addr)
1040{
1041 return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000;
1042}
1043
1044int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
1045 target_phys_addr_t addr)
1046{
1047 return addr >= 0xe1010000 && addr < 0xe1020004;
1048}
1049
1050/* MPU OS timers */
1051struct omap_mpu_timer_s {
1052 qemu_irq irq;
1053 omap_clk clk;
1054 target_phys_addr_t base;
1055 uint32_t val;
1056 int64_t time;
1057 QEMUTimer *timer;
1058 int64_t rate;
1059 int it_ena;
1060
1061 int enable;
1062 int ptv;
1063 int ar;
1064 int st;
1065 uint32_t reset_val;
1066};
1067
1068static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
1069{
1070 uint64_t distance = qemu_get_clock(vm_clock) - timer->time;
1071
1072 if (timer->st && timer->enable && timer->rate)
1073 return timer->val - muldiv64(distance >> (timer->ptv + 1),
1074 timer->rate, ticks_per_sec);
1075 else
1076 return timer->val;
1077}
1078
1079static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
1080{
1081 timer->val = omap_timer_read(timer);
1082 timer->time = qemu_get_clock(vm_clock);
1083}
1084
1085static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
1086{
1087 int64_t expires;
1088
1089 if (timer->enable && timer->st && timer->rate) {
1090 timer->val = timer->reset_val; /* Should skip this on clk enable */
1091 expires = timer->time + muldiv64(timer->val << (timer->ptv + 1),
1092 ticks_per_sec, timer->rate);
1093 qemu_mod_timer(timer->timer, expires);
1094 } else
1095 qemu_del_timer(timer->timer);
1096}
1097
1098static void omap_timer_tick(void *opaque)
1099{
1100 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
1101 omap_timer_sync(timer);
1102
1103 if (!timer->ar) {
1104 timer->val = 0;
1105 timer->st = 0;
1106 }
1107
1108 if (timer->it_ena)
1109 qemu_irq_raise(timer->irq);
1110 omap_timer_update(timer);
1111}
1112
1113static void omap_timer_clk_update(void *opaque, int line, int on)
1114{
1115 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
1116
1117 omap_timer_sync(timer);
1118 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
1119 omap_timer_update(timer);
1120}
1121
1122static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
1123{
1124 omap_clk_adduser(timer->clk,
1125 qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]);
1126 timer->rate = omap_clk_getrate(timer->clk);
1127}
1128
1129static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
1130{
1131 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
1132 int offset = addr - s->base;
1133
1134 switch (offset) {
1135 case 0x00: /* CNTL_TIMER */
1136 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
1137
1138 case 0x04: /* LOAD_TIM */
1139 break;
1140
1141 case 0x08: /* READ_TIM */
1142 return omap_timer_read(s);
1143 }
1144
1145 OMAP_BAD_REG(addr);
1146 return 0;
1147}
1148
1149static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
1150 uint32_t value)
1151{
1152 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
1153 int offset = addr - s->base;
1154
1155 switch (offset) {
1156 case 0x00: /* CNTL_TIMER */
1157 omap_timer_sync(s);
1158 s->enable = (value >> 5) & 1;
1159 s->ptv = (value >> 2) & 7;
1160 s->ar = (value >> 1) & 1;
1161 s->st = value & 1;
1162 omap_timer_update(s);
1163 return;
1164
1165 case 0x04: /* LOAD_TIM */
1166 s->reset_val = value;
1167 return;
1168
1169 case 0x08: /* READ_TIM */
1170 OMAP_RO_REG(addr);
1171 break;
1172
1173 default:
1174 OMAP_BAD_REG(addr);
1175 }
1176}
1177
1178static CPUReadMemoryFunc *omap_mpu_timer_readfn[] = {
1179 omap_badwidth_read32,
1180 omap_badwidth_read32,
1181 omap_mpu_timer_read,
1182};
1183
1184static CPUWriteMemoryFunc *omap_mpu_timer_writefn[] = {
1185 omap_badwidth_write32,
1186 omap_badwidth_write32,
1187 omap_mpu_timer_write,
1188};
1189
1190static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
1191{
1192 qemu_del_timer(s->timer);
1193 s->enable = 0;
1194 s->reset_val = 31337;
1195 s->val = 0;
1196 s->ptv = 0;
1197 s->ar = 0;
1198 s->st = 0;
1199 s->it_ena = 1;
1200}
1201
1202struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
1203 qemu_irq irq, omap_clk clk)
1204{
1205 int iomemtype;
1206 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
1207 qemu_mallocz(sizeof(struct omap_mpu_timer_s));
1208
1209 s->irq = irq;
1210 s->clk = clk;
1211 s->base = base;
1212 s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s);
1213 omap_mpu_timer_reset(s);
1214 omap_timer_clk_setup(s);
1215
1216 iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn,
1217 omap_mpu_timer_writefn, s);
1218 cpu_register_physical_memory(s->base, 0x100, iomemtype);
1219
1220 return s;
1221}
1222
1223/* Watchdog timer */
1224struct omap_watchdog_timer_s {
1225 struct omap_mpu_timer_s timer;
1226 uint8_t last_wr;
1227 int mode;
1228 int free;
1229 int reset;
1230};
1231
1232static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
1233{
1234 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
1235 int offset = addr - s->timer.base;
1236
1237 switch (offset) {
1238 case 0x00: /* CNTL_TIMER */
1239 return (s->timer.ptv << 9) | (s->timer.ar << 8) |
1240 (s->timer.st << 7) | (s->free << 1);
1241
1242 case 0x04: /* READ_TIMER */
1243 return omap_timer_read(&s->timer);
1244
1245 case 0x08: /* TIMER_MODE */
1246 return s->mode << 15;
1247 }
1248
1249 OMAP_BAD_REG(addr);
1250 return 0;
1251}
1252
1253static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
1254 uint32_t value)
1255{
1256 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
1257 int offset = addr - s->timer.base;
1258
1259 switch (offset) {
1260 case 0x00: /* CNTL_TIMER */
1261 omap_timer_sync(&s->timer);
1262 s->timer.ptv = (value >> 9) & 7;
1263 s->timer.ar = (value >> 8) & 1;
1264 s->timer.st = (value >> 7) & 1;
1265 s->free = (value >> 1) & 1;
1266 omap_timer_update(&s->timer);
1267 break;
1268
1269 case 0x04: /* LOAD_TIMER */
1270 s->timer.reset_val = value & 0xffff;
1271 break;
1272
1273 case 0x08: /* TIMER_MODE */
1274 if (!s->mode && ((value >> 15) & 1))
1275 omap_clk_get(s->timer.clk);
1276 s->mode |= (value >> 15) & 1;
1277 if (s->last_wr == 0xf5) {
1278 if ((value & 0xff) == 0xa0) {
1279 s->mode = 0;
1280 omap_clk_put(s->timer.clk);
1281 } else {
1282 /* XXX: on T|E hardware somehow this has no effect,
1283 * on Zire 71 it works as specified. */
1284 s->reset = 1;
1285 qemu_system_reset_request();
1286 }
1287 }
1288 s->last_wr = value & 0xff;
1289 break;
1290
1291 default:
1292 OMAP_BAD_REG(addr);
1293 }
1294}
1295
1296static CPUReadMemoryFunc *omap_wd_timer_readfn[] = {
1297 omap_badwidth_read16,
1298 omap_wd_timer_read,
1299 omap_badwidth_read16,
1300};
1301
1302static CPUWriteMemoryFunc *omap_wd_timer_writefn[] = {
1303 omap_badwidth_write16,
1304 omap_wd_timer_write,
1305 omap_badwidth_write16,
1306};
1307
1308static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
1309{
1310 qemu_del_timer(s->timer.timer);
1311 if (!s->mode)
1312 omap_clk_get(s->timer.clk);
1313 s->mode = 1;
1314 s->free = 1;
1315 s->reset = 0;
1316 s->timer.enable = 1;
1317 s->timer.it_ena = 1;
1318 s->timer.reset_val = 0xffff;
1319 s->timer.val = 0;
1320 s->timer.st = 0;
1321 s->timer.ptv = 0;
1322 s->timer.ar = 0;
1323 omap_timer_update(&s->timer);
1324}
1325
1326struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
1327 qemu_irq irq, omap_clk clk)
1328{
1329 int iomemtype;
1330 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
1331 qemu_mallocz(sizeof(struct omap_watchdog_timer_s));
1332
1333 s->timer.irq = irq;
1334 s->timer.clk = clk;
1335 s->timer.base = base;
1336 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
1337 omap_wd_timer_reset(s);
1338 omap_timer_clk_setup(&s->timer);
1339
1340 iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn,
1341 omap_wd_timer_writefn, s);
1342 cpu_register_physical_memory(s->timer.base, 0x100, iomemtype);
1343
1344 return s;
1345}
1346
1347/* 32-kHz timer */
1348struct omap_32khz_timer_s {
1349 struct omap_mpu_timer_s timer;
1350};
1351
1352static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
1353{
1354 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
1355 int offset = addr - s->timer.base;
1356
1357 switch (offset) {
1358 case 0x00: /* TVR */
1359 return s->timer.reset_val;
1360
1361 case 0x04: /* TCR */
1362 return omap_timer_read(&s->timer);
1363
1364 case 0x08: /* CR */
1365 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
1366
1367 default:
1368 break;
1369 }
1370 OMAP_BAD_REG(addr);
1371 return 0;
1372}
1373
1374static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
1375 uint32_t value)
1376{
1377 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
1378 int offset = addr - s->timer.base;
1379
1380 switch (offset) {
1381 case 0x00: /* TVR */
1382 s->timer.reset_val = value & 0x00ffffff;
1383 break;
1384
1385 case 0x04: /* TCR */
1386 OMAP_RO_REG(addr);
1387 break;
1388
1389 case 0x08: /* CR */
1390 s->timer.ar = (value >> 3) & 1;
1391 s->timer.it_ena = (value >> 2) & 1;
1392 if (s->timer.st != (value & 1) || (value & 2)) {
1393 omap_timer_sync(&s->timer);
1394 s->timer.enable = value & 1;
1395 s->timer.st = value & 1;
1396 omap_timer_update(&s->timer);
1397 }
1398 break;
1399
1400 default:
1401 OMAP_BAD_REG(addr);
1402 }
1403}
1404
1405static CPUReadMemoryFunc *omap_os_timer_readfn[] = {
1406 omap_badwidth_read32,
1407 omap_badwidth_read32,
1408 omap_os_timer_read,
1409};
1410
1411static CPUWriteMemoryFunc *omap_os_timer_writefn[] = {
1412 omap_badwidth_write32,
1413 omap_badwidth_write32,
1414 omap_os_timer_write,
1415};
1416
1417static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
1418{
1419 qemu_del_timer(s->timer.timer);
1420 s->timer.enable = 0;
1421 s->timer.it_ena = 0;
1422 s->timer.reset_val = 0x00ffffff;
1423 s->timer.val = 0;
1424 s->timer.st = 0;
1425 s->timer.ptv = 0;
1426 s->timer.ar = 1;
1427}
1428
1429struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
1430 qemu_irq irq, omap_clk clk)
1431{
1432 int iomemtype;
1433 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
1434 qemu_mallocz(sizeof(struct omap_32khz_timer_s));
1435
1436 s->timer.irq = irq;
1437 s->timer.clk = clk;
1438 s->timer.base = base;
1439 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
1440 omap_os_timer_reset(s);
1441 omap_timer_clk_setup(&s->timer);
1442
1443 iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn,
1444 omap_os_timer_writefn, s);
1445 cpu_register_physical_memory(s->timer.base, 0x800, iomemtype);
1446
1447 return s;
1448}
1449
1450/* Ultra Low-Power Device Module */
1451static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr)
1452{
1453 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1454 int offset = addr - s->ulpd_pm_base;
1455 uint16_t ret;
1456
1457 switch (offset) {
1458 case 0x14: /* IT_STATUS */
1459 ret = s->ulpd_pm_regs[offset >> 2];
1460 s->ulpd_pm_regs[offset >> 2] = 0;
1461 qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
1462 return ret;
1463
1464 case 0x18: /* Reserved */
1465 case 0x1c: /* Reserved */
1466 case 0x20: /* Reserved */
1467 case 0x28: /* Reserved */
1468 case 0x2c: /* Reserved */
1469 OMAP_BAD_REG(addr);
1470 case 0x00: /* COUNTER_32_LSB */
1471 case 0x04: /* COUNTER_32_MSB */
1472 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1473 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1474 case 0x10: /* GAUGING_CTRL */
1475 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1476 case 0x30: /* CLOCK_CTRL */
1477 case 0x34: /* SOFT_REQ */
1478 case 0x38: /* COUNTER_32_FIQ */
1479 case 0x3c: /* DPLL_CTRL */
1480 case 0x40: /* STATUS_REQ */
1481 /* XXX: check clk::usecount state for every clock */
1482 case 0x48: /* LOCL_TIME */
1483 case 0x4c: /* APLL_CTRL */
1484 case 0x50: /* POWER_CTRL */
1485 return s->ulpd_pm_regs[offset >> 2];
1486 }
1487
1488 OMAP_BAD_REG(addr);
1489 return 0;
1490}
1491
1492static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
1493 uint16_t diff, uint16_t value)
1494{
1495 if (diff & (1 << 4)) /* USB_MCLK_EN */
1496 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
1497 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
1498 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
1499}
1500
1501static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
1502 uint16_t diff, uint16_t value)
1503{
1504 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
1505 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
1506 if (diff & (1 << 1)) /* SOFT_COM_REQ */
1507 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
1508 if (diff & (1 << 2)) /* SOFT_SDW_REQ */
1509 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
1510 if (diff & (1 << 3)) /* SOFT_USB_REQ */
1511 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
1512}
1513
1514static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
1515 uint32_t value)
1516{
1517 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1518 int offset = addr - s->ulpd_pm_base;
1519 int64_t now, ticks;
1520 int div, mult;
1521 static const int bypass_div[4] = { 1, 2, 4, 4 };
1522 uint16_t diff;
1523
1524 switch (offset) {
1525 case 0x00: /* COUNTER_32_LSB */
1526 case 0x04: /* COUNTER_32_MSB */
1527 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1528 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1529 case 0x14: /* IT_STATUS */
1530 case 0x40: /* STATUS_REQ */
1531 OMAP_RO_REG(addr);
1532 break;
1533
1534 case 0x10: /* GAUGING_CTRL */
1535 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
1536 if ((s->ulpd_pm_regs[offset >> 2] ^ value) & 1) {
1537 now = qemu_get_clock(vm_clock);
1538
1539 if (value & 1)
1540 s->ulpd_gauge_start = now;
1541 else {
1542 now -= s->ulpd_gauge_start;
1543
1544 /* 32-kHz ticks */
1545 ticks = muldiv64(now, 32768, ticks_per_sec);
1546 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
1547 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
1548 if (ticks >> 32) /* OVERFLOW_32K */
1549 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
1550
1551 /* High frequency ticks */
1552 ticks = muldiv64(now, 12000000, ticks_per_sec);
1553 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
1554 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
1555 if (ticks >> 32) /* OVERFLOW_HI_FREQ */
1556 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
1557
1558 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
1559 qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
1560 }
1561 }
1562 s->ulpd_pm_regs[offset >> 2] = value;
1563 break;
1564
1565 case 0x18: /* Reserved */
1566 case 0x1c: /* Reserved */
1567 case 0x20: /* Reserved */
1568 case 0x28: /* Reserved */
1569 case 0x2c: /* Reserved */
1570 OMAP_BAD_REG(addr);
1571 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1572 case 0x38: /* COUNTER_32_FIQ */
1573 case 0x48: /* LOCL_TIME */
1574 case 0x50: /* POWER_CTRL */
1575 s->ulpd_pm_regs[offset >> 2] = value;
1576 break;
1577
1578 case 0x30: /* CLOCK_CTRL */
1579 diff = s->ulpd_pm_regs[offset >> 2] ^ value;
1580 s->ulpd_pm_regs[offset >> 2] = value & 0x3f;
1581 omap_ulpd_clk_update(s, diff, value);
1582 break;
1583
1584 case 0x34: /* SOFT_REQ */
1585 diff = s->ulpd_pm_regs[offset >> 2] ^ value;
1586 s->ulpd_pm_regs[offset >> 2] = value & 0x1f;
1587 omap_ulpd_req_update(s, diff, value);
1588 break;
1589
1590 case 0x3c: /* DPLL_CTRL */
1591 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
1592 * omitted altogether, probably a typo. */
1593 /* This register has identical semantics with DPLL(1:3) control
1594 * registers, see omap_dpll_write() */
1595 diff = s->ulpd_pm_regs[offset >> 2] & value;
1596 s->ulpd_pm_regs[offset >> 2] = value & 0x2fff;
1597 if (diff & (0x3ff << 2)) {
1598 if (value & (1 << 4)) { /* PLL_ENABLE */
1599 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1600 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1601 } else {
1602 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1603 mult = 1;
1604 }
1605 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
1606 }
1607
1608 /* Enter the desired mode. */
1609 s->ulpd_pm_regs[offset >> 2] =
1610 (s->ulpd_pm_regs[offset >> 2] & 0xfffe) |
1611 ((s->ulpd_pm_regs[offset >> 2] >> 4) & 1);
1612
1613 /* Act as if the lock is restored. */
1614 s->ulpd_pm_regs[offset >> 2] |= 2;
1615 break;
1616
1617 case 0x4c: /* APLL_CTRL */
1618 diff = s->ulpd_pm_regs[offset >> 2] & value;
1619 s->ulpd_pm_regs[offset >> 2] = value & 0xf;
1620 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
1621 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
1622 (value & (1 << 0)) ? "apll" : "dpll4"));
1623 break;
1624
1625 default:
1626 OMAP_BAD_REG(addr);
1627 }
1628}
1629
1630static CPUReadMemoryFunc *omap_ulpd_pm_readfn[] = {
1631 omap_badwidth_read16,
1632 omap_ulpd_pm_read,
1633 omap_badwidth_read16,
1634};
1635
1636static CPUWriteMemoryFunc *omap_ulpd_pm_writefn[] = {
1637 omap_badwidth_write16,
1638 omap_ulpd_pm_write,
1639 omap_badwidth_write16,
1640};
1641
1642static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
1643{
1644 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
1645 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
1646 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
1647 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
1648 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
1649 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
1650 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
1651 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
1652 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
1653 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
1654 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
1655 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
1656 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
1657 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
1658 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
1659 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
1660 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
1661 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
1662 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
1663 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
1664 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
1665 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
1666 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
1667}
1668
1669static void omap_ulpd_pm_init(target_phys_addr_t base,
1670 struct omap_mpu_state_s *mpu)
1671{
1672 int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn,
1673 omap_ulpd_pm_writefn, mpu);
1674
1675 mpu->ulpd_pm_base = base;
1676 cpu_register_physical_memory(mpu->ulpd_pm_base, 0x800, iomemtype);
1677 omap_ulpd_pm_reset(mpu);
1678}
1679
1680/* OMAP Pin Configuration */
1681static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr)
1682{
1683 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1684 int offset = addr - s->pin_cfg_base;
1685
1686 switch (offset) {
1687 case 0x00: /* FUNC_MUX_CTRL_0 */
1688 case 0x04: /* FUNC_MUX_CTRL_1 */
1689 case 0x08: /* FUNC_MUX_CTRL_2 */
1690 return s->func_mux_ctrl[offset >> 2];
1691
1692 case 0x0c: /* COMP_MODE_CTRL_0 */
1693 return s->comp_mode_ctrl[0];
1694
1695 case 0x10: /* FUNC_MUX_CTRL_3 */
1696 case 0x14: /* FUNC_MUX_CTRL_4 */
1697 case 0x18: /* FUNC_MUX_CTRL_5 */
1698 case 0x1c: /* FUNC_MUX_CTRL_6 */
1699 case 0x20: /* FUNC_MUX_CTRL_7 */
1700 case 0x24: /* FUNC_MUX_CTRL_8 */
1701 case 0x28: /* FUNC_MUX_CTRL_9 */
1702 case 0x2c: /* FUNC_MUX_CTRL_A */
1703 case 0x30: /* FUNC_MUX_CTRL_B */
1704 case 0x34: /* FUNC_MUX_CTRL_C */
1705 case 0x38: /* FUNC_MUX_CTRL_D */
1706 return s->func_mux_ctrl[(offset >> 2) - 1];
1707
1708 case 0x40: /* PULL_DWN_CTRL_0 */
1709 case 0x44: /* PULL_DWN_CTRL_1 */
1710 case 0x48: /* PULL_DWN_CTRL_2 */
1711 case 0x4c: /* PULL_DWN_CTRL_3 */
1712 return s->pull_dwn_ctrl[(offset & 0xf) >> 2];
1713
1714 case 0x50: /* GATE_INH_CTRL_0 */
1715 return s->gate_inh_ctrl[0];
1716
1717 case 0x60: /* VOLTAGE_CTRL_0 */
1718 return s->voltage_ctrl[0];
1719
1720 case 0x70: /* TEST_DBG_CTRL_0 */
1721 return s->test_dbg_ctrl[0];
1722
1723 case 0x80: /* MOD_CONF_CTRL_0 */
1724 return s->mod_conf_ctrl[0];
1725 }
1726
1727 OMAP_BAD_REG(addr);
1728 return 0;
1729}
1730
1731static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
1732 uint32_t diff, uint32_t value)
1733{
1734 if (s->compat1509) {
1735 if (diff & (1 << 9)) /* BLUETOOTH */
1736 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
1737 (~value >> 9) & 1);
1738 if (diff & (1 << 7)) /* USB.CLKO */
1739 omap_clk_onoff(omap_findclk(s, "usb.clko"),
1740 (value >> 7) & 1);
1741 }
1742}
1743
1744static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
1745 uint32_t diff, uint32_t value)
1746{
1747 if (s->compat1509) {
1748 if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */
1749 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
1750 (value >> 31) & 1);
1751 if (diff & (1 << 1)) /* CLK32K */
1752 omap_clk_onoff(omap_findclk(s, "clk32k_out"),
1753 (~value >> 1) & 1);
1754 }
1755}
1756
1757static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
1758 uint32_t diff, uint32_t value)
1759{
1760 if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */
1761 omap_clk_reparent(omap_findclk(s, "uart3_ck"),
1762 omap_findclk(s, ((value >> 31) & 1) ?
1763 "ck_48m" : "armper_ck"));
1764 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
1765 omap_clk_reparent(omap_findclk(s, "uart2_ck"),
1766 omap_findclk(s, ((value >> 30) & 1) ?
1767 "ck_48m" : "armper_ck"));
1768 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
1769 omap_clk_reparent(omap_findclk(s, "uart1_ck"),
1770 omap_findclk(s, ((value >> 29) & 1) ?
1771 "ck_48m" : "armper_ck"));
1772 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
1773 omap_clk_reparent(omap_findclk(s, "mmc_ck"),
1774 omap_findclk(s, ((value >> 23) & 1) ?
1775 "ck_48m" : "armper_ck"));
1776 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
1777 omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
1778 omap_findclk(s, ((value >> 12) & 1) ?
1779 "ck_48m" : "armper_ck"));
1780 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
1781 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
1782}
1783
1784static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
1785 uint32_t value)
1786{
1787 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1788 int offset = addr - s->pin_cfg_base;
1789 uint32_t diff;
1790
1791 switch (offset) {
1792 case 0x00: /* FUNC_MUX_CTRL_0 */
1793 diff = s->func_mux_ctrl[offset >> 2] ^ value;
1794 s->func_mux_ctrl[offset >> 2] = value;
1795 omap_pin_funcmux0_update(s, diff, value);
1796 return;
1797
1798 case 0x04: /* FUNC_MUX_CTRL_1 */
1799 diff = s->func_mux_ctrl[offset >> 2] ^ value;
1800 s->func_mux_ctrl[offset >> 2] = value;
1801 omap_pin_funcmux1_update(s, diff, value);
1802 return;
1803
1804 case 0x08: /* FUNC_MUX_CTRL_2 */
1805 s->func_mux_ctrl[offset >> 2] = value;
1806 return;
1807
1808 case 0x0c: /* COMP_MODE_CTRL_0 */
1809 s->comp_mode_ctrl[0] = value;
1810 s->compat1509 = (value != 0x0000eaef);
1811 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
1812 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
1813 return;
1814
1815 case 0x10: /* FUNC_MUX_CTRL_3 */
1816 case 0x14: /* FUNC_MUX_CTRL_4 */
1817 case 0x18: /* FUNC_MUX_CTRL_5 */
1818 case 0x1c: /* FUNC_MUX_CTRL_6 */
1819 case 0x20: /* FUNC_MUX_CTRL_7 */
1820 case 0x24: /* FUNC_MUX_CTRL_8 */
1821 case 0x28: /* FUNC_MUX_CTRL_9 */
1822 case 0x2c: /* FUNC_MUX_CTRL_A */
1823 case 0x30: /* FUNC_MUX_CTRL_B */
1824 case 0x34: /* FUNC_MUX_CTRL_C */
1825 case 0x38: /* FUNC_MUX_CTRL_D */
1826 s->func_mux_ctrl[(offset >> 2) - 1] = value;
1827 return;
1828
1829 case 0x40: /* PULL_DWN_CTRL_0 */
1830 case 0x44: /* PULL_DWN_CTRL_1 */
1831 case 0x48: /* PULL_DWN_CTRL_2 */
1832 case 0x4c: /* PULL_DWN_CTRL_3 */
1833 s->pull_dwn_ctrl[(offset & 0xf) >> 2] = value;
1834 return;
1835
1836 case 0x50: /* GATE_INH_CTRL_0 */
1837 s->gate_inh_ctrl[0] = value;
1838 return;
1839
1840 case 0x60: /* VOLTAGE_CTRL_0 */
1841 s->voltage_ctrl[0] = value;
1842 return;
1843
1844 case 0x70: /* TEST_DBG_CTRL_0 */
1845 s->test_dbg_ctrl[0] = value;
1846 return;
1847
1848 case 0x80: /* MOD_CONF_CTRL_0 */
1849 diff = s->mod_conf_ctrl[0] ^ value;
1850 s->mod_conf_ctrl[0] = value;
1851 omap_pin_modconf1_update(s, diff, value);
1852 return;
1853
1854 default:
1855 OMAP_BAD_REG(addr);
1856 }
1857}
1858
1859static CPUReadMemoryFunc *omap_pin_cfg_readfn[] = {
1860 omap_badwidth_read32,
1861 omap_badwidth_read32,
1862 omap_pin_cfg_read,
1863};
1864
1865static CPUWriteMemoryFunc *omap_pin_cfg_writefn[] = {
1866 omap_badwidth_write32,
1867 omap_badwidth_write32,
1868 omap_pin_cfg_write,
1869};
1870
1871static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
1872{
1873 /* Start in Compatibility Mode. */
1874 mpu->compat1509 = 1;
1875 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
1876 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
1877 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
1878 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
1879 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
1880 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
1881 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
1882 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
1883 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
1884 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
1885}
1886
1887static void omap_pin_cfg_init(target_phys_addr_t base,
1888 struct omap_mpu_state_s *mpu)
1889{
1890 int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn,
1891 omap_pin_cfg_writefn, mpu);
1892
1893 mpu->pin_cfg_base = base;
1894 cpu_register_physical_memory(mpu->pin_cfg_base, 0x800, iomemtype);
1895 omap_pin_cfg_reset(mpu);
1896}
1897
1898/* Device Identification, Die Identification */
1899static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
1900{
1901 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1902
1903 switch (addr) {
1904 case 0xfffe1800: /* DIE_ID_LSB */
1905 return 0xc9581f0e;
1906 case 0xfffe1804: /* DIE_ID_MSB */
1907 return 0xa8858bfa;
1908
1909 case 0xfffe2000: /* PRODUCT_ID_LSB */
1910 return 0x00aaaafc;
1911 case 0xfffe2004: /* PRODUCT_ID_MSB */
1912 return 0xcafeb574;
1913
1914 case 0xfffed400: /* JTAG_ID_LSB */
1915 switch (s->mpu_model) {
1916 case omap310:
1917 return 0x03310315;
1918 case omap1510:
1919 return 0x03310115;
1920 }
1921 break;
1922
1923 case 0xfffed404: /* JTAG_ID_MSB */
1924 switch (s->mpu_model) {
1925 case omap310:
1926 return 0xfb57402f;
1927 case omap1510:
1928 return 0xfb47002f;
1929 }
1930 break;
1931 }
1932
1933 OMAP_BAD_REG(addr);
1934 return 0;
1935}
1936
1937static void omap_id_write(void *opaque, target_phys_addr_t addr,
1938 uint32_t value)
1939{
1940 OMAP_BAD_REG(addr);
1941}
1942
1943static CPUReadMemoryFunc *omap_id_readfn[] = {
1944 omap_badwidth_read32,
1945 omap_badwidth_read32,
1946 omap_id_read,
1947};
1948
1949static CPUWriteMemoryFunc *omap_id_writefn[] = {
1950 omap_badwidth_write32,
1951 omap_badwidth_write32,
1952 omap_id_write,
1953};
1954
1955static void omap_id_init(struct omap_mpu_state_s *mpu)
1956{
1957 int iomemtype = cpu_register_io_memory(0, omap_id_readfn,
1958 omap_id_writefn, mpu);
1959 cpu_register_physical_memory(0xfffe1800, 0x800, iomemtype);
1960 cpu_register_physical_memory(0xfffed400, 0x100, iomemtype);
1961 if (!cpu_is_omap15xx(mpu))
1962 cpu_register_physical_memory(0xfffe2000, 0x800, iomemtype);
1963}
1964
1965/* MPUI Control (Dummy) */
1966static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
1967{
1968 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1969 int offset = addr - s->mpui_base;
1970
1971 switch (offset) {
1972 case 0x00: /* CTRL */
1973 return s->mpui_ctrl;
1974 case 0x04: /* DEBUG_ADDR */
1975 return 0x01ffffff;
1976 case 0x08: /* DEBUG_DATA */
1977 return 0xffffffff;
1978 case 0x0c: /* DEBUG_FLAG */
1979 return 0x00000800;
1980 case 0x10: /* STATUS */
1981 return 0x00000000;
1982
1983 /* Not in OMAP310 */
1984 case 0x14: /* DSP_STATUS */
1985 case 0x18: /* DSP_BOOT_CONFIG */
1986 return 0x00000000;
1987 case 0x1c: /* DSP_MPUI_CONFIG */
1988 return 0x0000ffff;
1989 }
1990
1991 OMAP_BAD_REG(addr);
1992 return 0;
1993}
1994
1995static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
1996 uint32_t value)
1997{
1998 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1999 int offset = addr - s->mpui_base;
2000
2001 switch (offset) {
2002 case 0x00: /* CTRL */
2003 s->mpui_ctrl = value & 0x007fffff;
2004 break;
2005
2006 case 0x04: /* DEBUG_ADDR */
2007 case 0x08: /* DEBUG_DATA */
2008 case 0x0c: /* DEBUG_FLAG */
2009 case 0x10: /* STATUS */
2010 /* Not in OMAP310 */
2011 case 0x14: /* DSP_STATUS */
2012 OMAP_RO_REG(addr);
2013 case 0x18: /* DSP_BOOT_CONFIG */
2014 case 0x1c: /* DSP_MPUI_CONFIG */
2015 break;
2016
2017 default:
2018 OMAP_BAD_REG(addr);
2019 }
2020}
2021
2022static CPUReadMemoryFunc *omap_mpui_readfn[] = {
2023 omap_badwidth_read32,
2024 omap_badwidth_read32,
2025 omap_mpui_read,
2026};
2027
2028static CPUWriteMemoryFunc *omap_mpui_writefn[] = {
2029 omap_badwidth_write32,
2030 omap_badwidth_write32,
2031 omap_mpui_write,
2032};
2033
2034static void omap_mpui_reset(struct omap_mpu_state_s *s)
2035{
2036 s->mpui_ctrl = 0x0003ff1b;
2037}
2038
2039static void omap_mpui_init(target_phys_addr_t base,
2040 struct omap_mpu_state_s *mpu)
2041{
2042 int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn,
2043 omap_mpui_writefn, mpu);
2044
2045 mpu->mpui_base = base;
2046 cpu_register_physical_memory(mpu->mpui_base, 0x100, iomemtype);
2047
2048 omap_mpui_reset(mpu);
2049}
2050
2051/* TIPB Bridges */
2052struct omap_tipb_bridge_s {
2053 target_phys_addr_t base;
2054 qemu_irq abort;
2055
2056 int width_intr;
2057 uint16_t control;
2058 uint16_t alloc;
2059 uint16_t buffer;
2060 uint16_t enh_control;
2061};
2062
2063static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
2064{
2065 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
2066 int offset = addr - s->base;
2067
2068 switch (offset) {
2069 case 0x00: /* TIPB_CNTL */
2070 return s->control;
2071 case 0x04: /* TIPB_BUS_ALLOC */
2072 return s->alloc;
2073 case 0x08: /* MPU_TIPB_CNTL */
2074 return s->buffer;
2075 case 0x0c: /* ENHANCED_TIPB_CNTL */
2076 return s->enh_control;
2077 case 0x10: /* ADDRESS_DBG */
2078 case 0x14: /* DATA_DEBUG_LOW */
2079 case 0x18: /* DATA_DEBUG_HIGH */
2080 return 0xffff;
2081 case 0x1c: /* DEBUG_CNTR_SIG */
2082 return 0x00f8;
2083 }
2084
2085 OMAP_BAD_REG(addr);
2086 return 0;
2087}
2088
2089static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
2090 uint32_t value)
2091{
2092 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
2093 int offset = addr - s->base;
2094
2095 switch (offset) {
2096 case 0x00: /* TIPB_CNTL */
2097 s->control = value & 0xffff;
2098 break;
2099
2100 case 0x04: /* TIPB_BUS_ALLOC */
2101 s->alloc = value & 0x003f;
2102 break;
2103
2104 case 0x08: /* MPU_TIPB_CNTL */
2105 s->buffer = value & 0x0003;
2106 break;
2107
2108 case 0x0c: /* ENHANCED_TIPB_CNTL */
2109 s->width_intr = !(value & 2);
2110 s->enh_control = value & 0x000f;
2111 break;
2112
2113 case 0x10: /* ADDRESS_DBG */
2114 case 0x14: /* DATA_DEBUG_LOW */
2115 case 0x18: /* DATA_DEBUG_HIGH */
2116 case 0x1c: /* DEBUG_CNTR_SIG */
2117 OMAP_RO_REG(addr);
2118 break;
2119
2120 default:
2121 OMAP_BAD_REG(addr);
2122 }
2123}
2124
2125static CPUReadMemoryFunc *omap_tipb_bridge_readfn[] = {
2126 omap_badwidth_read16,
2127 omap_tipb_bridge_read,
2128 omap_tipb_bridge_read,
2129};
2130
2131static CPUWriteMemoryFunc *omap_tipb_bridge_writefn[] = {
2132 omap_badwidth_write16,
2133 omap_tipb_bridge_write,
2134 omap_tipb_bridge_write,
2135};
2136
2137static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
2138{
2139 s->control = 0xffff;
2140 s->alloc = 0x0009;
2141 s->buffer = 0x0000;
2142 s->enh_control = 0x000f;
2143}
2144
2145struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
2146 qemu_irq abort_irq, omap_clk clk)
2147{
2148 int iomemtype;
2149 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
2150 qemu_mallocz(sizeof(struct omap_tipb_bridge_s));
2151
2152 s->abort = abort_irq;
2153 s->base = base;
2154 omap_tipb_bridge_reset(s);
2155
2156 iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn,
2157 omap_tipb_bridge_writefn, s);
2158 cpu_register_physical_memory(s->base, 0x100, iomemtype);
2159
2160 return s;
2161}
2162
2163/* Dummy Traffic Controller's Memory Interface */
2164static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
2165{
2166 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2167 int offset = addr - s->tcmi_base;
2168 uint32_t ret;
2169
2170 switch (offset) {
2171 case 0xfffecc00: /* IMIF_PRIO */
2172 case 0xfffecc04: /* EMIFS_PRIO */
2173 case 0xfffecc08: /* EMIFF_PRIO */
2174 case 0xfffecc0c: /* EMIFS_CONFIG */
2175 case 0xfffecc10: /* EMIFS_CS0_CONFIG */
2176 case 0xfffecc14: /* EMIFS_CS1_CONFIG */
2177 case 0xfffecc18: /* EMIFS_CS2_CONFIG */
2178 case 0xfffecc1c: /* EMIFS_CS3_CONFIG */
2179 case 0xfffecc24: /* EMIFF_MRS */
2180 case 0xfffecc28: /* TIMEOUT1 */
2181 case 0xfffecc2c: /* TIMEOUT2 */
2182 case 0xfffecc30: /* TIMEOUT3 */
2183 case 0xfffecc3c: /* EMIFF_SDRAM_CONFIG_2 */
2184 case 0xfffecc40: /* EMIFS_CFG_DYN_WAIT */
2185 return s->tcmi_regs[offset >> 2];
2186
2187 case 0xfffecc20: /* EMIFF_SDRAM_CONFIG */
2188 ret = s->tcmi_regs[offset >> 2];
2189 s->tcmi_regs[offset >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
2190 /* XXX: We can try using the VGA_DIRTY flag for this */
2191 return ret;
2192 }
2193
2194 OMAP_BAD_REG(addr);
2195 return 0;
2196}
2197
2198static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
2199 uint32_t value)
2200{
2201 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2202 int offset = addr - s->tcmi_base;
2203
2204 switch (offset) {
2205 case 0xfffecc00: /* IMIF_PRIO */
2206 case 0xfffecc04: /* EMIFS_PRIO */
2207 case 0xfffecc08: /* EMIFF_PRIO */
2208 case 0xfffecc10: /* EMIFS_CS0_CONFIG */
2209 case 0xfffecc14: /* EMIFS_CS1_CONFIG */
2210 case 0xfffecc18: /* EMIFS_CS2_CONFIG */
2211 case 0xfffecc1c: /* EMIFS_CS3_CONFIG */
2212 case 0xfffecc20: /* EMIFF_SDRAM_CONFIG */
2213 case 0xfffecc24: /* EMIFF_MRS */
2214 case 0xfffecc28: /* TIMEOUT1 */
2215 case 0xfffecc2c: /* TIMEOUT2 */
2216 case 0xfffecc30: /* TIMEOUT3 */
2217 case 0xfffecc3c: /* EMIFF_SDRAM_CONFIG_2 */
2218 case 0xfffecc40: /* EMIFS_CFG_DYN_WAIT */
2219 s->tcmi_regs[offset >> 2] = value;
2220 break;
2221 case 0xfffecc0c: /* EMIFS_CONFIG */
2222 s->tcmi_regs[offset >> 2] = (value & 0xf) | (1 << 4);
2223 break;
2224
2225 default:
2226 OMAP_BAD_REG(addr);
2227 }
2228}
2229
2230static CPUReadMemoryFunc *omap_tcmi_readfn[] = {
2231 omap_badwidth_read32,
2232 omap_badwidth_read32,
2233 omap_tcmi_read,
2234};
2235
2236static CPUWriteMemoryFunc *omap_tcmi_writefn[] = {
2237 omap_badwidth_write32,
2238 omap_badwidth_write32,
2239 omap_tcmi_write,
2240};
2241
2242static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
2243{
2244 mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
2245 mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
2246 mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
2247 mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
2248 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
2249 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
2250 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
2251 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
2252 mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
2253 mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
2254 mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
2255 mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
2256 mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
2257 mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
2258 mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
2259}
2260
2261static void omap_tcmi_init(target_phys_addr_t base,
2262 struct omap_mpu_state_s *mpu)
2263{
2264 int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn,
2265 omap_tcmi_writefn, mpu);
2266
2267 mpu->tcmi_base = base;
2268 cpu_register_physical_memory(mpu->tcmi_base, 0x100, iomemtype);
2269 omap_tcmi_reset(mpu);
2270}
2271
2272/* Digital phase-locked loops control */
2273static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
2274{
2275 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
2276 int offset = addr - s->base;
2277
2278 if (offset == 0x00) /* CTL_REG */
2279 return s->mode;
2280
2281 OMAP_BAD_REG(addr);
2282 return 0;
2283}
2284
2285static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
2286 uint32_t value)
2287{
2288 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
2289 uint16_t diff;
2290 int offset = addr - s->base;
2291 static const int bypass_div[4] = { 1, 2, 4, 4 };
2292 int div, mult;
2293
2294 if (offset == 0x00) { /* CTL_REG */
2295 /* See omap_ulpd_pm_write() too */
2296 diff = s->mode & value;
2297 s->mode = value & 0x2fff;
2298 if (diff & (0x3ff << 2)) {
2299 if (value & (1 << 4)) { /* PLL_ENABLE */
2300 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
2301 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
2302 } else {
2303 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
2304 mult = 1;
2305 }
2306 omap_clk_setrate(s->dpll, div, mult);
2307 }
2308
2309 /* Enter the desired mode. */
2310 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
2311
2312 /* Act as if the lock is restored. */
2313 s->mode |= 2;
2314 } else {
2315 OMAP_BAD_REG(addr);
2316 }
2317}
2318
2319static CPUReadMemoryFunc *omap_dpll_readfn[] = {
2320 omap_badwidth_read16,
2321 omap_dpll_read,
2322 omap_badwidth_read16,
2323};
2324
2325static CPUWriteMemoryFunc *omap_dpll_writefn[] = {
2326 omap_badwidth_write16,
2327 omap_dpll_write,
2328 omap_badwidth_write16,
2329};
2330
2331static void omap_dpll_reset(struct dpll_ctl_s *s)
2332{
2333 s->mode = 0x2002;
2334 omap_clk_setrate(s->dpll, 1, 1);
2335}
2336
2337static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
2338 omap_clk clk)
2339{
2340 int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn,
2341 omap_dpll_writefn, s);
2342
2343 s->base = base;
2344 s->dpll = clk;
2345 omap_dpll_reset(s);
2346
2347 cpu_register_physical_memory(s->base, 0x100, iomemtype);
2348}
2349
2350/* UARTs */
2351struct omap_uart_s {
2352 SerialState *serial; /* TODO */
2353};
2354
2355static void omap_uart_reset(struct omap_uart_s *s)
2356{
2357}
2358
2359struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
2360 qemu_irq irq, omap_clk clk, CharDriverState *chr)
2361{
2362 struct omap_uart_s *s = (struct omap_uart_s *)
2363 qemu_mallocz(sizeof(struct omap_uart_s));
2364 if (chr)
2365 s->serial = serial_mm_init(base, 2, irq, chr, 1);
2366 return s;
2367}
2368
2369/* MPU Clock/Reset/Power Mode Control */
2370static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
2371{
2372 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2373 int offset = addr - s->clkm.mpu_base;
2374
2375 switch (offset) {
2376 case 0x00: /* ARM_CKCTL */
2377 return s->clkm.arm_ckctl;
2378
2379 case 0x04: /* ARM_IDLECT1 */
2380 return s->clkm.arm_idlect1;
2381
2382 case 0x08: /* ARM_IDLECT2 */
2383 return s->clkm.arm_idlect2;
2384
2385 case 0x0c: /* ARM_EWUPCT */
2386 return s->clkm.arm_ewupct;
2387
2388 case 0x10: /* ARM_RSTCT1 */
2389 return s->clkm.arm_rstct1;
2390
2391 case 0x14: /* ARM_RSTCT2 */
2392 return s->clkm.arm_rstct2;
2393
2394 case 0x18: /* ARM_SYSST */
2395 return (s->clkm.clocking_scheme < 11) | s->clkm.cold_start;
2396
2397 case 0x1c: /* ARM_CKOUT1 */
2398 return s->clkm.arm_ckout1;
2399
2400 case 0x20: /* ARM_CKOUT2 */
2401 break;
2402 }
2403
2404 OMAP_BAD_REG(addr);
2405 return 0;
2406}
2407
2408static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
2409 uint16_t diff, uint16_t value)
2410{
2411 omap_clk clk;
2412
2413 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
2414 if (value & (1 << 14))
2415 /* Reserved */;
2416 else {
2417 clk = omap_findclk(s, "arminth_ck");
2418 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
2419 }
2420 }
2421 if (diff & (1 << 12)) { /* ARM_TIMXO */
2422 clk = omap_findclk(s, "armtim_ck");
2423 if (value & (1 << 12))
2424 omap_clk_reparent(clk, omap_findclk(s, "clkin"));
2425 else
2426 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
2427 }
2428 /* XXX: en_dspck */
2429 if (diff & (3 << 10)) { /* DSPMMUDIV */
2430 clk = omap_findclk(s, "dspmmu_ck");
2431 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
2432 }
2433 if (diff & (3 << 8)) { /* TCDIV */
2434 clk = omap_findclk(s, "tc_ck");
2435 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
2436 }
2437 if (diff & (3 << 6)) { /* DSPDIV */
2438 clk = omap_findclk(s, "dsp_ck");
2439 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
2440 }
2441 if (diff & (3 << 4)) { /* ARMDIV */
2442 clk = omap_findclk(s, "arm_ck");
2443 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
2444 }
2445 if (diff & (3 << 2)) { /* LCDDIV */
2446 clk = omap_findclk(s, "lcd_ck");
2447 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
2448 }
2449 if (diff & (3 << 0)) { /* PERDIV */
2450 clk = omap_findclk(s, "armper_ck");
2451 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
2452 }
2453}
2454
2455static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
2456 uint16_t diff, uint16_t value)
2457{
2458 omap_clk clk;
2459
2460 if (value & (1 << 11)) /* SETARM_IDLE */
2461 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
2462 if (!(value & (1 << 10))) /* WKUP_MODE */
2463 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
2464
2465#define SET_CANIDLE(clock, bit) \
2466 if (diff & (1 << bit)) { \
2467 clk = omap_findclk(s, clock); \
2468 omap_clk_canidle(clk, (value >> bit) & 1); \
2469 }
2470 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
2471 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
2472 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
2473 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
2474 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
2475 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
2476 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
2477 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
2478 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
2479 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
2480 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
2481 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
2482 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
2483 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
2484}
2485
2486static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
2487 uint16_t diff, uint16_t value)
2488{
2489 omap_clk clk;
2490
2491#define SET_ONOFF(clock, bit) \
2492 if (diff & (1 << bit)) { \
2493 clk = omap_findclk(s, clock); \
2494 omap_clk_onoff(clk, (value >> bit) & 1); \
2495 }
2496 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
2497 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
2498 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
2499 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
2500 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
2501 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
2502 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
2503 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
2504 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
2505 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
2506 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
2507}
2508
2509static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
2510 uint16_t diff, uint16_t value)
2511{
2512 omap_clk clk;
2513
2514 if (diff & (3 << 4)) { /* TCLKOUT */
2515 clk = omap_findclk(s, "tclk_out");
2516 switch ((value >> 4) & 3) {
2517 case 1:
2518 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
2519 omap_clk_onoff(clk, 1);
2520 break;
2521 case 2:
2522 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
2523 omap_clk_onoff(clk, 1);
2524 break;
2525 default:
2526 omap_clk_onoff(clk, 0);
2527 }
2528 }
2529 if (diff & (3 << 2)) { /* DCLKOUT */
2530 clk = omap_findclk(s, "dclk_out");
2531 switch ((value >> 2) & 3) {
2532 case 0:
2533 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
2534 break;
2535 case 1:
2536 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
2537 break;
2538 case 2:
2539 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
2540 break;
2541 case 3:
2542 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
2543 break;
2544 }
2545 }
2546 if (diff & (3 << 0)) { /* ACLKOUT */
2547 clk = omap_findclk(s, "aclk_out");
2548 switch ((value >> 0) & 3) {
2549 case 1:
2550 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
2551 omap_clk_onoff(clk, 1);
2552 break;
2553 case 2:
2554 omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
2555 omap_clk_onoff(clk, 1);
2556 break;
2557 case 3:
2558 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
2559 omap_clk_onoff(clk, 1);
2560 break;
2561 default:
2562 omap_clk_onoff(clk, 0);
2563 }
2564 }
2565}
2566
2567static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
2568 uint32_t value)
2569{
2570 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2571 int offset = addr - s->clkm.mpu_base;
2572 uint16_t diff;
2573 omap_clk clk;
2574 static const char *clkschemename[8] = {
2575 "fully synchronous", "fully asynchronous", "synchronous scalable",
2576 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
2577 };
2578
2579 switch (offset) {
2580 case 0x00: /* ARM_CKCTL */
2581 diff = s->clkm.arm_ckctl ^ value;
2582 s->clkm.arm_ckctl = value & 0x7fff;
2583 omap_clkm_ckctl_update(s, diff, value);
2584 return;
2585
2586 case 0x04: /* ARM_IDLECT1 */
2587 diff = s->clkm.arm_idlect1 ^ value;
2588 s->clkm.arm_idlect1 = value & 0x0fff;
2589 omap_clkm_idlect1_update(s, diff, value);
2590 return;
2591
2592 case 0x08: /* ARM_IDLECT2 */
2593 diff = s->clkm.arm_idlect2 ^ value;
2594 s->clkm.arm_idlect2 = value & 0x07ff;
2595 omap_clkm_idlect2_update(s, diff, value);
2596 return;
2597
2598 case 0x0c: /* ARM_EWUPCT */
2599 diff = s->clkm.arm_ewupct ^ value;
2600 s->clkm.arm_ewupct = value & 0x003f;
2601 return;
2602
2603 case 0x10: /* ARM_RSTCT1 */
2604 diff = s->clkm.arm_rstct1 ^ value;
2605 s->clkm.arm_rstct1 = value & 0x0007;
2606 if (value & 9) {
2607 qemu_system_reset_request();
2608 s->clkm.cold_start = 0xa;
2609 }
2610 if (diff & ~value & 4) { /* DSP_RST */
2611 omap_mpui_reset(s);
2612 omap_tipb_bridge_reset(s->private_tipb);
2613 omap_tipb_bridge_reset(s->public_tipb);
2614 }
2615 if (diff & 2) { /* DSP_EN */
2616 clk = omap_findclk(s, "dsp_ck");
2617 omap_clk_canidle(clk, (~value >> 1) & 1);
2618 }
2619 return;
2620
2621 case 0x14: /* ARM_RSTCT2 */
2622 s->clkm.arm_rstct2 = value & 0x0001;
2623 return;
2624
2625 case 0x18: /* ARM_SYSST */
2626 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
2627 s->clkm.clocking_scheme = (value >> 11) & 7;
2628 printf("%s: clocking scheme set to %s\n", __FUNCTION__,
2629 clkschemename[s->clkm.clocking_scheme]);
2630 }
2631 s->clkm.cold_start &= value & 0x3f;
2632 return;
2633
2634 case 0x1c: /* ARM_CKOUT1 */
2635 diff = s->clkm.arm_ckout1 ^ value;
2636 s->clkm.arm_ckout1 = value & 0x003f;
2637 omap_clkm_ckout1_update(s, diff, value);
2638 return;
2639
2640 case 0x20: /* ARM_CKOUT2 */
2641 default:
2642 OMAP_BAD_REG(addr);
2643 }
2644}
2645
2646static CPUReadMemoryFunc *omap_clkm_readfn[] = {
2647 omap_badwidth_read16,
2648 omap_clkm_read,
2649 omap_badwidth_read16,
2650};
2651
2652static CPUWriteMemoryFunc *omap_clkm_writefn[] = {
2653 omap_badwidth_write16,
2654 omap_clkm_write,
2655 omap_badwidth_write16,
2656};
2657
2658static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
2659{
2660 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2661 int offset = addr - s->clkm.dsp_base;
2662
2663 switch (offset) {
2664 case 0x04: /* DSP_IDLECT1 */
2665 return s->clkm.dsp_idlect1;
2666
2667 case 0x08: /* DSP_IDLECT2 */
2668 return s->clkm.dsp_idlect2;
2669
2670 case 0x14: /* DSP_RSTCT2 */
2671 return s->clkm.dsp_rstct2;
2672
2673 case 0x18: /* DSP_SYSST */
2674 return (s->clkm.clocking_scheme < 11) | s->clkm.cold_start |
2675 (s->env->halted << 6); /* Quite useless... */
2676 }
2677
2678 OMAP_BAD_REG(addr);
2679 return 0;
2680}
2681
2682static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
2683 uint16_t diff, uint16_t value)
2684{
2685 omap_clk clk;
2686
2687 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
2688}
2689
2690static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
2691 uint16_t diff, uint16_t value)
2692{
2693 omap_clk clk;
2694
2695 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
2696}
2697
2698static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
2699 uint32_t value)
2700{
2701 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2702 int offset = addr - s->clkm.dsp_base;
2703 uint16_t diff;
2704
2705 switch (offset) {
2706 case 0x04: /* DSP_IDLECT1 */
2707 diff = s->clkm.dsp_idlect1 ^ value;
2708 s->clkm.dsp_idlect1 = value & 0x01f7;
2709 omap_clkdsp_idlect1_update(s, diff, value);
2710 break;
2711
2712 case 0x08: /* DSP_IDLECT2 */
2713 s->clkm.dsp_idlect2 = value & 0x0037;
2714 diff = s->clkm.dsp_idlect1 ^ value;
2715 omap_clkdsp_idlect2_update(s, diff, value);
2716 break;
2717
2718 case 0x14: /* DSP_RSTCT2 */
2719 s->clkm.dsp_rstct2 = value & 0x0001;
2720 break;
2721
2722 case 0x18: /* DSP_SYSST */
2723 s->clkm.cold_start &= value & 0x3f;
2724 break;
2725
2726 default:
2727 OMAP_BAD_REG(addr);
2728 }
2729}
2730
2731static CPUReadMemoryFunc *omap_clkdsp_readfn[] = {
2732 omap_badwidth_read16,
2733 omap_clkdsp_read,
2734 omap_badwidth_read16,
2735};
2736
2737static CPUWriteMemoryFunc *omap_clkdsp_writefn[] = {
2738 omap_badwidth_write16,
2739 omap_clkdsp_write,
2740 omap_badwidth_write16,
2741};
2742
2743static void omap_clkm_reset(struct omap_mpu_state_s *s)
2744{
2745 if (s->wdt && s->wdt->reset)
2746 s->clkm.cold_start = 0x6;
2747 s->clkm.clocking_scheme = 0;
2748 omap_clkm_ckctl_update(s, ~0, 0x3000);
2749 s->clkm.arm_ckctl = 0x3000;
2750 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 & 0x0400, 0x0400);
2751 s->clkm.arm_idlect1 = 0x0400;
2752 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 & 0x0100, 0x0100);
2753 s->clkm.arm_idlect2 = 0x0100;
2754 s->clkm.arm_ewupct = 0x003f;
2755 s->clkm.arm_rstct1 = 0x0000;
2756 s->clkm.arm_rstct2 = 0x0000;
2757 s->clkm.arm_ckout1 = 0x0015;
2758 s->clkm.dpll1_mode = 0x2002;
2759 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
2760 s->clkm.dsp_idlect1 = 0x0040;
2761 omap_clkdsp_idlect2_update(s, ~0, 0x0000);
2762 s->clkm.dsp_idlect2 = 0x0000;
2763 s->clkm.dsp_rstct2 = 0x0000;
2764}
2765
2766static void omap_clkm_init(target_phys_addr_t mpu_base,
2767 target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
2768{
2769 int iomemtype[2] = {
2770 cpu_register_io_memory(0, omap_clkm_readfn, omap_clkm_writefn, s),
2771 cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s),
2772 };
2773
2774 s->clkm.mpu_base = mpu_base;
2775 s->clkm.dsp_base = dsp_base;
2776 s->clkm.cold_start = 0x3a;
2777 omap_clkm_reset(s);
2778
2779 cpu_register_physical_memory(s->clkm.mpu_base, 0x100, iomemtype[0]);
2780 cpu_register_physical_memory(s->clkm.dsp_base, 0x1000, iomemtype[1]);
2781}
2782
2783/* General chip reset */
2784static void omap_mpu_reset(void *opaque)
2785{
2786 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
2787
2788 omap_clkm_reset(mpu);
2789 omap_inth_reset(mpu->ih[0]);
2790 omap_inth_reset(mpu->ih[1]);
2791 omap_dma_reset(mpu->dma);
2792 omap_mpu_timer_reset(mpu->timer[0]);
2793 omap_mpu_timer_reset(mpu->timer[1]);
2794 omap_mpu_timer_reset(mpu->timer[2]);
2795 omap_wd_timer_reset(mpu->wdt);
2796 omap_os_timer_reset(mpu->os_timer);
2797 omap_lcdc_reset(mpu->lcd);
2798 omap_ulpd_pm_reset(mpu);
2799 omap_pin_cfg_reset(mpu);
2800 omap_mpui_reset(mpu);
2801 omap_tipb_bridge_reset(mpu->private_tipb);
2802 omap_tipb_bridge_reset(mpu->public_tipb);
2803 omap_dpll_reset(&mpu->dpll[0]);
2804 omap_dpll_reset(&mpu->dpll[1]);
2805 omap_dpll_reset(&mpu->dpll[2]);
2806 omap_uart_reset(mpu->uart1);
2807 omap_uart_reset(mpu->uart2);
2808 omap_uart_reset(mpu->uart3);
2809 cpu_reset(mpu->env);
2810}
2811
2812static void omap_mpu_wakeup(void *opaque, int irq, int req)
2813{
2814 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
2815
2816 cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB);
2817}
2818
2819struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
2820 DisplayState *ds, const char *core)
2821{
2822 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
2823 qemu_mallocz(sizeof(struct omap_mpu_state_s));
2824 ram_addr_t imif_base, emiff_base;
2825
2826 /* Core */
2827 s->mpu_model = omap310;
2828 s->env = cpu_init();
2829 s->sdram_size = sdram_size;
2830 s->sram_size = OMAP15XX_SRAM_SIZE;
2831
2832 cpu_arm_set_model(s->env, core ?: "ti925t");
2833
2834 /* Clocks */
2835 omap_clk_init(s);
2836
2837 /* Memory-mapped stuff */
2838 cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size,
2839 (emiff_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
2840 cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size,
2841 (imif_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
2842
2843 omap_clkm_init(0xfffece00, 0xe1008000, s);
2844
2845 s->ih[0] = omap_inth_init(0xfffecb00, 0x100,
2846 arm_pic_init_cpu(s->env),
2847 omap_findclk(s, "arminth_ck"));
2848 s->ih[1] = omap_inth_init(0xfffe0000, 0x800,
2849 &s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ],
2850 omap_findclk(s, "arminth_ck"));
2851 s->irq[0] = s->ih[0]->pins;
2852 s->irq[1] = s->ih[1]->pins;
2853
2854 s->dma = omap_dma_init(0xfffed800, s->irq[0], s,
2855 omap_findclk(s, "dma_ck"));
2856 s->port[emiff ].addr_valid = omap_validate_emiff_addr;
2857 s->port[emifs ].addr_valid = omap_validate_emifs_addr;
2858 s->port[imif ].addr_valid = omap_validate_imif_addr;
2859 s->port[tipb ].addr_valid = omap_validate_tipb_addr;
2860 s->port[local ].addr_valid = omap_validate_local_addr;
2861 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
2862
2863 s->timer[0] = omap_mpu_timer_init(0xfffec500,
2864 s->irq[0][OMAP_INT_TIMER1],
2865 omap_findclk(s, "mputim_ck"));
2866 s->timer[1] = omap_mpu_timer_init(0xfffec600,
2867 s->irq[0][OMAP_INT_TIMER2],
2868 omap_findclk(s, "mputim_ck"));
2869 s->timer[2] = omap_mpu_timer_init(0xfffec700,
2870 s->irq[0][OMAP_INT_TIMER3],
2871 omap_findclk(s, "mputim_ck"));
2872
2873 s->wdt = omap_wd_timer_init(0xfffec800,
2874 s->irq[0][OMAP_INT_WD_TIMER],
2875 omap_findclk(s, "armwdt_ck"));
2876
2877 s->os_timer = omap_os_timer_init(0xfffb9000,
2878 s->irq[1][OMAP_INT_OS_TIMER],
2879 omap_findclk(s, "clk32-kHz"));
2880
2881 s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
2882 &s->dma->lcd_ch, ds, imif_base, emiff_base,
2883 omap_findclk(s, "lcd_ck"));
2884
2885 omap_ulpd_pm_init(0xfffe0800, s);
2886 omap_pin_cfg_init(0xfffe1000, s);
2887 omap_id_init(s);
2888
2889 omap_mpui_init(0xfffec900, s);
2890
2891 s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
2892 s->irq[0][OMAP_INT_BRIDGE_PRIV],
2893 omap_findclk(s, "tipb_ck"));
2894 s->public_tipb = omap_tipb_bridge_init(0xfffed300,
2895 s->irq[0][OMAP_INT_BRIDGE_PUB],
2896 omap_findclk(s, "tipb_ck"));
2897
2898 omap_tcmi_init(0xfffecc00, s);
2899
2900 s->uart1 = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1],
2901 omap_findclk(s, "uart1_ck"),
2902 serial_hds[0]);
2903 s->uart2 = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2],
2904 omap_findclk(s, "uart2_ck"),
2905 serial_hds[0] ? serial_hds[1] : 0);
2906 s->uart3 = omap_uart_init(0xe1019800, s->irq[0][OMAP_INT_UART3],
2907 omap_findclk(s, "uart3_ck"),
2908 serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0);
2909
2910 omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
2911 omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
2912 omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
2913
2914 qemu_register_reset(omap_mpu_reset, s);
2915 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
2916
2917 return s;
2918}
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