[qemu.git] / target-arm / machine.c

#include "hw/hw.h"
#include "hw/boards.h"
#include "sysemu/kvm.h"
#include "kvm_arm.h"
#include "internals.h"

static bool vfp_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_VFP);
}

static int get_fpscr(QEMUFile *f, void *opaque, size_t size)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;
    uint32_t val = qemu_get_be32(f);

    vfp_set_fpscr(env, val);
    return 0;
}

static void put_fpscr(QEMUFile *f, void *opaque, size_t size)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    qemu_put_be32(f, vfp_get_fpscr(env));
}

static const VMStateInfo vmstate_fpscr = {
    .name = "fpscr",
    .get = get_fpscr,
    .put = put_fpscr,
};

static const VMStateDescription vmstate_vfp = {
    .name = "cpu/vfp",
    .version_id = 3,
    .minimum_version_id = 3,
    .needed = vfp_needed,
    .fields = (VMStateField[]) {
        VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
        /* The xregs array is a little awkward because element 1 (FPSCR)
         * requires a specific accessor, so we have to split it up in
         * the vmstate:
         */
        VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU),
        VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
        {
            .name = "fpscr",
            .version_id = 0,
            .size = sizeof(uint32_t),
            .info = &vmstate_fpscr,
            .flags = VMS_SINGLE,
            .offset = 0,
        },
        VMSTATE_END_OF_LIST()
    }
};

static bool iwmmxt_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_IWMMXT);
}

static const VMStateDescription vmstate_iwmmxt = {
    .name = "cpu/iwmmxt",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = iwmmxt_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
        VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
        VMSTATE_END_OF_LIST()
    }
};

static bool m_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_M);
}

static const VMStateDescription vmstate_m = {
    .name = "cpu/m",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = m_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
        VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
        VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
        VMSTATE_UINT32(env.v7m.control, ARMCPU),
        VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
        VMSTATE_INT32(env.v7m.exception, ARMCPU),
        VMSTATE_END_OF_LIST()
    }
};

static bool thumb2ee_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_THUMB2EE);
}

static const VMStateDescription vmstate_thumb2ee = {
    .name = "cpu/thumb2ee",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = thumb2ee_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(env.teecr, ARMCPU),
        VMSTATE_UINT32(env.teehbr, ARMCPU),
        VMSTATE_END_OF_LIST()
    }
};

static bool pmsav7_needed(void *opaque)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;

    return arm_feature(env, ARM_FEATURE_MPU) &&
           arm_feature(env, ARM_FEATURE_V7);
}

static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id)
{
    ARMCPU *cpu = opaque;

    return cpu->env.cp15.c6_rgnr < cpu->pmsav7_dregion;
}

static const VMStateDescription vmstate_pmsav7 = {
    .name = "cpu/pmsav7",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pmsav7_needed,
    .fields = (VMStateField[]) {
        VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0,
                              vmstate_info_uint32, uint32_t),
        VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0,
                              vmstate_info_uint32, uint32_t),
        VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0,
                              vmstate_info_uint32, uint32_t),
        VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate),
        VMSTATE_END_OF_LIST()
    }
};

static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;
    uint32_t val = qemu_get_be32(f);

    env->aarch64 = ((val & PSTATE_nRW) == 0);

    if (is_a64(env)) {
        pstate_write(env, val);
        return 0;
    }

    /* Avoid mode switch when restoring CPSR */
    env->uncached_cpsr = val & CPSR_M;
    cpsr_write(env, val, 0xffffffff);
    return 0;
}

static void put_cpsr(QEMUFile *f, void *opaque, size_t size)
{
    ARMCPU *cpu = opaque;
    CPUARMState *env = &cpu->env;
    uint32_t val;

    if (is_a64(env)) {
        val = pstate_read(env);
    } else {
        val = cpsr_read(env);
    }

    qemu_put_be32(f, val);
}

static const VMStateInfo vmstate_cpsr = {
    .name = "cpsr",
    .get = get_cpsr,
    .put = put_cpsr,
};

static void cpu_pre_save(void *opaque)
{
    ARMCPU *cpu = opaque;

    if (kvm_enabled()) {
        if (!write_kvmstate_to_list(cpu)) {
            /* This should never fail */
            abort();
        }
    } else {
        if (!write_cpustate_to_list(cpu)) {
            /* This should never fail. */
            abort();
        }
    }

    cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
    memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
           cpu->cpreg_array_len * sizeof(uint64_t));
    memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
           cpu->cpreg_array_len * sizeof(uint64_t));
}

static int cpu_post_load(void *opaque, int version_id)
{
    ARMCPU *cpu = opaque;
    int i, v;

    /* Update the values list from the incoming migration data.
     * Anything in the incoming data which we don't know about is
     * a migration failure; anything we know about but the incoming
     * data doesn't specify retains its current (reset) value.
     * The indexes list remains untouched -- we only inspect the
     * incoming migration index list so we can match the values array
     * entries with the right slots in our own values array.
     */

    for (i = 0, v = 0; i < cpu->cpreg_array_len
             && v < cpu->cpreg_vmstate_array_len; i++) {
        if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) {
            /* register in our list but not incoming : skip it */
            continue;
        }
        if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) {
            /* register in their list but not ours: fail migration */
            return -1;
        }
        /* matching register, copy the value over */
        cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v];
        v++;
    }

    if (kvm_enabled()) {
        if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) {
            return -1;
        }
        /* Note that it's OK for the TCG side not to know about
         * every register in the list; KVM is authoritative if
         * we're using it.
         */
        write_list_to_cpustate(cpu);
    } else {
        if (!write_list_to_cpustate(cpu)) {
            return -1;
        }
    }

    hw_breakpoint_update_all(cpu);
    hw_watchpoint_update_all(cpu);

    return 0;
}

const VMStateDescription vmstate_arm_cpu = {
    .name = "cpu",
    .version_id = 22,
    .minimum_version_id = 22,
    .pre_save = cpu_pre_save,
    .post_load = cpu_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
        VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32),
        VMSTATE_UINT64(env.pc, ARMCPU),
        {
            .name = "cpsr",
            .version_id = 0,
            .size = sizeof(uint32_t),
            .info = &vmstate_cpsr,
            .flags = VMS_SINGLE,
            .offset = 0,
        },
        VMSTATE_UINT32(env.spsr, ARMCPU),
        VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
        VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8),
        VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8),
        VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
        VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
        VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
        VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
        /* The length-check must come before the arrays to avoid
         * incoming data possibly overflowing the array.
         */
        VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU),
        VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
                             cpreg_vmstate_array_len,
                             0, vmstate_info_uint64, uint64_t),
        VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
                             cpreg_vmstate_array_len,
                             0, vmstate_info_uint64, uint64_t),
        VMSTATE_UINT64(env.exclusive_addr, ARMCPU),
        VMSTATE_UINT64(env.exclusive_val, ARMCPU),
        VMSTATE_UINT64(env.exclusive_high, ARMCPU),
        VMSTATE_UINT64(env.features, ARMCPU),
        VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
        VMSTATE_UINT32(env.exception.fsr, ARMCPU),
        VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
        VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU),
        VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU),
        VMSTATE_BOOL(powered_off, ARMCPU),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_vfp,
        &vmstate_iwmmxt,
        &vmstate_m,
        &vmstate_thumb2ee,
        &vmstate_pmsav7,
        NULL
    }
};
Commit	Line	Data
8dd3dca3 AJ	1	#include "hw/hw.h"
8dd3dca3 AJ	2	#include "hw/boards.h"
ff047453 PM	3	#include "sysemu/kvm.h"
ff047453 PM	4	#include "kvm_arm.h"
9ee98ce8	5	#include "internals.h"
8dd3dca3	6
3cc1d208	7	static bool vfp_needed(void *opaque)
8dd3dca3	8	{
3cc1d208 JQ	9	ARMCPU *cpu = opaque;
3cc1d208 JQ	10	CPUARMState *env = &cpu->env;
8dd3dca3	11
3cc1d208 JQ	12	return arm_feature(env, ARM_FEATURE_VFP);
3cc1d208 JQ	13	}
8dd3dca3	14
e91f229a PM	15	static int get_fpscr(QEMUFile f, void opaque, size_t size)
	16	{
	17	ARMCPU *cpu = opaque;
	18	CPUARMState *env = &cpu->env;
	19	uint32_t val = qemu_get_be32(f);
	20
	21	vfp_set_fpscr(env, val);
	22	return 0;
	23	}
	24
	25	static void put_fpscr(QEMUFile f, void opaque, size_t size)
	26	{
	27	ARMCPU *cpu = opaque;
	28	CPUARMState *env = &cpu->env;
	29
	30	qemu_put_be32(f, vfp_get_fpscr(env));
	31	}
	32
	33	static const VMStateInfo vmstate_fpscr = {
	34	.name = "fpscr",
	35	.get = get_fpscr,
	36	.put = put_fpscr,
	37	};
	38
3cc1d208 JQ	39	static const VMStateDescription vmstate_vfp = {
3cc1d208 JQ	40	.name = "cpu/vfp",
3926cc84 AG	41	.version_id = 3,
3926cc84 AG	42	.minimum_version_id = 3,
5cd8cada	43	.needed = vfp_needed,
3cc1d208	44	.fields = (VMStateField[]) {
3926cc84	45	VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
e91f229a PM	46	/* The xregs array is a little awkward because element 1 (FPSCR)
	47	* requires a specific accessor, so we have to split it up in
	48	* the vmstate:
	49	*/
	50	VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU),
	51	VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
	52	{
	53	.name = "fpscr",
	54	.version_id = 0,
	55	.size = sizeof(uint32_t),
	56	.info = &vmstate_fpscr,
	57	.flags = VMS_SINGLE,
	58	.offset = 0,
	59	},
3cc1d208	60	VMSTATE_END_OF_LIST()
8dd3dca3	61	}
3cc1d208	62	};
8dd3dca3	63
3cc1d208 JQ	64	static bool iwmmxt_needed(void *opaque)
	65	{
	66	ARMCPU *cpu = opaque;
	67	CPUARMState *env = &cpu->env;
8dd3dca3	68
3cc1d208 JQ	69	return arm_feature(env, ARM_FEATURE_IWMMXT);
3cc1d208 JQ	70	}
ffe47d33	71
3cc1d208 JQ	72	static const VMStateDescription vmstate_iwmmxt = {
	73	.name = "cpu/iwmmxt",
	74	.version_id = 1,
	75	.minimum_version_id = 1,
5cd8cada	76	.needed = iwmmxt_needed,
3cc1d208 JQ	77	.fields = (VMStateField[]) {
	78	VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
	79	VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
	80	VMSTATE_END_OF_LIST()
ffe47d33	81	}
3cc1d208 JQ	82	};
	83
	84	static bool m_needed(void *opaque)
	85	{
	86	ARMCPU *cpu = opaque;
	87	CPUARMState *env = &cpu->env;
	88
	89	return arm_feature(env, ARM_FEATURE_M);
8dd3dca3 AJ	90	}
8dd3dca3 AJ	91
6df05bdd	92	static const VMStateDescription vmstate_m = {
3cc1d208 JQ	93	.name = "cpu/m",
	94	.version_id = 1,
	95	.minimum_version_id = 1,
5cd8cada	96	.needed = m_needed,
3cc1d208 JQ	97	.fields = (VMStateField[]) {
	98	VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
	99	VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
	100	VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
	101	VMSTATE_UINT32(env.v7m.control, ARMCPU),
	102	VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
	103	VMSTATE_INT32(env.v7m.exception, ARMCPU),
	104	VMSTATE_END_OF_LIST()
	105	}
	106	};
	107
	108	static bool thumb2ee_needed(void *opaque)
8dd3dca3	109	{
3cc1d208 JQ	110	ARMCPU *cpu = opaque;
3cc1d208 JQ	111	CPUARMState *env = &cpu->env;
8dd3dca3	112
3cc1d208 JQ	113	return arm_feature(env, ARM_FEATURE_THUMB2EE);
3cc1d208 JQ	114	}
8dd3dca3	115
3cc1d208 JQ	116	static const VMStateDescription vmstate_thumb2ee = {
	117	.name = "cpu/thumb2ee",
	118	.version_id = 1,
	119	.minimum_version_id = 1,
5cd8cada	120	.needed = thumb2ee_needed,
3cc1d208 JQ	121	.fields = (VMStateField[]) {
	122	VMSTATE_UINT32(env.teecr, ARMCPU),
	123	VMSTATE_UINT32(env.teehbr, ARMCPU),
	124	VMSTATE_END_OF_LIST()
8dd3dca3	125	}
3cc1d208 JQ	126	};
3cc1d208 JQ	127
6cb0b013 PC	128	static bool pmsav7_needed(void *opaque)
	129	{
	130	ARMCPU *cpu = opaque;
	131	CPUARMState *env = &cpu->env;
	132
	133	return arm_feature(env, ARM_FEATURE_MPU) &&
	134	arm_feature(env, ARM_FEATURE_V7);
	135	}
	136
	137	static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id)
	138	{
	139	ARMCPU *cpu = opaque;
	140
	141	return cpu->env.cp15.c6_rgnr < cpu->pmsav7_dregion;
	142	}
	143
	144	static const VMStateDescription vmstate_pmsav7 = {
	145	.name = "cpu/pmsav7",
	146	.version_id = 1,
	147	.minimum_version_id = 1,
	148	.needed = pmsav7_needed,
	149	.fields = (VMStateField[]) {
	150	VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0,
	151	vmstate_info_uint32, uint32_t),
	152	VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0,
	153	vmstate_info_uint32, uint32_t),
	154	VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0,
	155	vmstate_info_uint32, uint32_t),
	156	VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate),
	157	VMSTATE_END_OF_LIST()
	158	}
	159	};
	160
3cc1d208 JQ	161	static int get_cpsr(QEMUFile f, void opaque, size_t size)
	162	{
	163	ARMCPU *cpu = opaque;
	164	CPUARMState *env = &cpu->env;
	165	uint32_t val = qemu_get_be32(f);
	166
a7130a3e PM	167	env->aarch64 = ((val & PSTATE_nRW) == 0);
	168
	169	if (is_a64(env)) {
	170	pstate_write(env, val);
	171	return 0;
	172	}
	173
3cc1d208	174	/* Avoid mode switch when restoring CPSR */
ffe47d33 PB	175	env->uncached_cpsr = val & CPSR_M;
ffe47d33 PB	176	cpsr_write(env, val, 0xffffffff);
3cc1d208 JQ	177	return 0;
3cc1d208 JQ	178	}
8dd3dca3	179
3cc1d208 JQ	180	static void put_cpsr(QEMUFile f, void opaque, size_t size)
	181	{
	182	ARMCPU *cpu = opaque;
	183	CPUARMState *env = &cpu->env;
a7130a3e PM	184	uint32_t val;
	185
	186	if (is_a64(env)) {
	187	val = pstate_read(env);
	188	} else {
	189	val = cpsr_read(env);
	190	}
8dd3dca3	191
a7130a3e	192	qemu_put_be32(f, val);
3cc1d208	193	}
8dd3dca3	194
3cc1d208 JQ	195	static const VMStateInfo vmstate_cpsr = {
	196	.name = "cpsr",
	197	.get = get_cpsr,
	198	.put = put_cpsr,
	199	};
	200
721fae12 PM	201	static void cpu_pre_save(void *opaque)
	202	{
	203	ARMCPU *cpu = opaque;
	204
ff047453 PM	205	if (kvm_enabled()) {
	206	if (!write_kvmstate_to_list(cpu)) {
	207	/* This should never fail */
	208	abort();
	209	}
	210	} else {
	211	if (!write_cpustate_to_list(cpu)) {
	212	/* This should never fail. */
	213	abort();
	214	}
721fae12 PM	215	}
	216
	217	cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
	218	memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
	219	cpu->cpreg_array_len * sizeof(uint64_t));
	220	memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
	221	cpu->cpreg_array_len * sizeof(uint64_t));
	222	}
	223
	224	static int cpu_post_load(void *opaque, int version_id)
	225	{
	226	ARMCPU *cpu = opaque;
	227	int i, v;
	228
	229	/* Update the values list from the incoming migration data.
	230	* Anything in the incoming data which we don't know about is
	231	* a migration failure; anything we know about but the incoming
	232	* data doesn't specify retains its current (reset) value.
	233	* The indexes list remains untouched -- we only inspect the
	234	* incoming migration index list so we can match the values array
	235	* entries with the right slots in our own values array.
	236	*/
	237
	238	for (i = 0, v = 0; i < cpu->cpreg_array_len
	239	&& v < cpu->cpreg_vmstate_array_len; i++) {
	240	if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) {
	241	/* register in our list but not incoming : skip it */
	242	continue;
	243	}
	244	if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) {
	245	/* register in their list but not ours: fail migration */
	246	return -1;
	247	}
	248	/* matching register, copy the value over */
	249	cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v];
	250	v++;
	251	}
	252
ff047453	253	if (kvm_enabled()) {
4b7a6bf4	254	if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) {
ff047453 PM	255	return -1;
	256	}
	257	/* Note that it's OK for the TCG side not to know about
	258	* every register in the list; KVM is authoritative if
	259	* we're using it.
	260	*/
	261	write_list_to_cpustate(cpu);
	262	} else {
	263	if (!write_list_to_cpustate(cpu)) {
	264	return -1;
	265	}
721fae12 PM	266	}
721fae12 PM	267
46747d15	268	hw_breakpoint_update_all(cpu);
9ee98ce8 PM	269	hw_watchpoint_update_all(cpu);
9ee98ce8 PM	270
721fae12 PM	271	return 0;
	272	}
	273
3cc1d208 JQ	274	const VMStateDescription vmstate_arm_cpu = {
3cc1d208 JQ	275	.name = "cpu",
a7130a3e PM	276	.version_id = 22,
a7130a3e PM	277	.minimum_version_id = 22,
721fae12 PM	278	.pre_save = cpu_pre_save,
721fae12 PM	279	.post_load = cpu_post_load,
3cc1d208 JQ	280	.fields = (VMStateField[]) {
3cc1d208 JQ	281	VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
a7130a3e PM	282	VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32),
a7130a3e PM	283	VMSTATE_UINT64(env.pc, ARMCPU),
3cc1d208 JQ	284	{
	285	.name = "cpsr",
	286	.version_id = 0,
	287	.size = sizeof(uint32_t),
	288	.info = &vmstate_cpsr,
	289	.flags = VMS_SINGLE,
	290	.offset = 0,
	291	},
	292	VMSTATE_UINT32(env.spsr, ARMCPU),
28c9457d	293	VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
0b7d409d FA	294	VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8),
0b7d409d FA	295	VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8),
3cc1d208 JQ	296	VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
3cc1d208 JQ	297	VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
1b174238	298	VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
73fb3b76	299	VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
721fae12 PM	300	/* The length-check must come before the arrays to avoid
	301	* incoming data possibly overflowing the array.
	302	*/
3476436a	303	VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU),
721fae12 PM	304	VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
	305	cpreg_vmstate_array_len,
	306	0, vmstate_info_uint64, uint64_t),
	307	VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
	308	cpreg_vmstate_array_len,
	309	0, vmstate_info_uint64, uint64_t),
03d05e2d PM	310	VMSTATE_UINT64(env.exclusive_addr, ARMCPU),
	311	VMSTATE_UINT64(env.exclusive_val, ARMCPU),
	312	VMSTATE_UINT64(env.exclusive_high, ARMCPU),
3cc1d208	313	VMSTATE_UINT64(env.features, ARMCPU),
abf1172f PM	314	VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
	315	VMSTATE_UINT32(env.exception.fsr, ARMCPU),
	316	VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
e720677e PB	317	VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU),
e720677e PB	318	VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU),
543486db	319	VMSTATE_BOOL(powered_off, ARMCPU),
3cc1d208 JQ	320	VMSTATE_END_OF_LIST()
3cc1d208 JQ	321	},
5cd8cada JQ	322	.subsections = (const VMStateDescription*[]) {
	323	&vmstate_vfp,
	324	&vmstate_iwmmxt,
	325	&vmstate_m,
	326	&vmstate_thumb2ee,
6cb0b013	327	&vmstate_pmsav7,
5cd8cada	328	NULL
ffe47d33	329	}
3cc1d208	330	};