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56b7c66f PM |
1 | /* |
2 | * ARMv7M CPU object | |
3 | * | |
4 | * Copyright (c) 2017 Linaro Ltd | |
5 | * Written by Peter Maydell <[email protected]> | |
6 | * | |
7 | * This code is licensed under the GPL version 2 or later. | |
8 | */ | |
9 | ||
10 | #ifndef HW_ARM_ARMV7M_H | |
11 | #define HW_ARM_ARMV7M_H | |
12 | ||
13 | #include "hw/sysbus.h" | |
d2db1de6 | 14 | #include "hw/intc/armv7m_nvic.h" |
c60c1b0d | 15 | #include "target/arm/idau.h" |
56b7c66f PM |
16 | |
17 | #define TYPE_BITBAND "ARM,bitband-memory" | |
18 | #define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND) | |
19 | ||
20 | typedef struct { | |
21 | /*< private >*/ | |
22 | SysBusDevice parent_obj; | |
23 | /*< public >*/ | |
24 | ||
b516572f | 25 | AddressSpace source_as; |
56b7c66f PM |
26 | MemoryRegion iomem; |
27 | uint32_t base; | |
f68d881c | 28 | MemoryRegion *source_memory; |
56b7c66f PM |
29 | } BitBandState; |
30 | ||
31 | #define TYPE_ARMV7M "armv7m" | |
32 | #define ARMV7M(obj) OBJECT_CHECK(ARMv7MState, (obj), TYPE_ARMV7M) | |
33 | ||
34 | #define ARMV7M_NUM_BITBANDS 2 | |
35 | ||
36 | /* ARMv7M container object. | |
37 | * + Unnamed GPIO input lines: external IRQ lines for the NVIC | |
38 | * + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ | |
ba1ba5cc | 39 | * + Property "cpu-type": CPU type to instantiate |
56b7c66f | 40 | * + Property "num-irq": number of external IRQ lines |
618119c2 PM |
41 | * + Property "memory": MemoryRegion defining the physical address space |
42 | * that CPU accesses see. (The NVIC, bitbanding and other CPU-internal | |
43 | * devices will be automatically layered on top of this view.) | |
c60c1b0d | 44 | * + Property "idau": IDAU interface (forwarded to CPU object) |
60d75d81 | 45 | * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object) |
a1c5a062 | 46 | * + Property "enable-bitband": expose bitbanded IO |
56b7c66f PM |
47 | */ |
48 | typedef struct ARMv7MState { | |
49 | /*< private >*/ | |
50 | SysBusDevice parent_obj; | |
51 | /*< public >*/ | |
52 | NVICState nvic; | |
53 | BitBandState bitband[ARMV7M_NUM_BITBANDS]; | |
54 | ARMCPU *cpu; | |
55 | ||
618119c2 PM |
56 | /* MemoryRegion we pass to the CPU, with our devices layered on |
57 | * top of the ones the board provides in board_memory. | |
58 | */ | |
59 | MemoryRegion container; | |
60 | ||
56b7c66f | 61 | /* Properties */ |
ba1ba5cc | 62 | char *cpu_type; |
618119c2 PM |
63 | /* MemoryRegion the board provides to us (with its devices, RAM, etc) */ |
64 | MemoryRegion *board_memory; | |
c60c1b0d | 65 | Object *idau; |
60d75d81 | 66 | uint32_t init_svtor; |
a1c5a062 | 67 | bool enable_bitband; |
66647809 | 68 | bool start_powered_off; |
56b7c66f PM |
69 | } ARMv7MState; |
70 | ||
71 | #endif |