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Commit | Line | Data |
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29e4bcb2 AF |
1 | /* |
2 | * QEMU S/390 CPU | |
3 | * | |
1ac1a749 AF |
4 | * Copyright (c) 2009 Ulrich Hecht |
5 | * Copyright (c) 2011 Alexander Graf | |
29e4bcb2 | 6 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
70bada03 | 7 | * Copyright (c) 2012 IBM Corp. |
29e4bcb2 AF |
8 | * |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2.1 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
20 | * License along with this library; if not, see | |
21 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
70bada03 JF |
22 | * Contributions after 2012-12-11 are licensed under the terms of the |
23 | * GNU GPL, version 2 or (at your option) any later version. | |
29e4bcb2 AF |
24 | */ |
25 | ||
9615495a | 26 | #include "qemu/osdep.h" |
da34e65c | 27 | #include "qapi/error.h" |
564b863d | 28 | #include "cpu.h" |
29e4bcb2 | 29 | #include "qemu-common.h" |
f348b6d1 | 30 | #include "qemu/cutils.h" |
1de7afc9 | 31 | #include "qemu/timer.h" |
eb24f7c6 | 32 | #include "qemu/error-report.h" |
eb24f7c6 | 33 | #include "trace.h" |
96b1a8bb | 34 | #include "qapi/visitor.h" |
741da0d3 | 35 | #include "migration/vmstate.h" |
63c91552 | 36 | #include "exec/exec-all.h" |
c7396bbb | 37 | #ifndef CONFIG_USER_ONLY |
741da0d3 | 38 | #include "hw/hw.h" |
904e5fd5 | 39 | #include "sysemu/arch_init.h" |
96b1a8bb | 40 | #include "sysemu/sysemu.h" |
a006b67f | 41 | #include "hw/s390x/sclp.h" |
904e5fd5 VM |
42 | #endif |
43 | ||
70bada03 JF |
44 | #define CR0_RESET 0xE0UL |
45 | #define CR14_RESET 0xC2000000UL; | |
46 | ||
f45748f1 AF |
47 | static void s390_cpu_set_pc(CPUState *cs, vaddr value) |
48 | { | |
49 | S390CPU *cpu = S390_CPU(cs); | |
50 | ||
51 | cpu->env.psw.addr = value; | |
52 | } | |
53 | ||
8c2e1b00 AF |
54 | static bool s390_cpu_has_work(CPUState *cs) |
55 | { | |
56 | S390CPU *cpu = S390_CPU(cs); | |
57 | CPUS390XState *env = &cpu->env; | |
58 | ||
59 | return (cs->interrupt_request & CPU_INTERRUPT_HARD) && | |
60 | (env->psw.mask & PSW_MASK_EXT); | |
61 | } | |
62 | ||
29c6157c CB |
63 | #if !defined(CONFIG_USER_ONLY) |
64 | /* S390CPUClass::load_normal() */ | |
65 | static void s390_cpu_load_normal(CPUState *s) | |
66 | { | |
67 | S390CPU *cpu = S390_CPU(s); | |
fdfba1a2 | 68 | cpu->env.psw.addr = ldl_phys(s->as, 4) & PSW_MASK_ESA_ADDR; |
29c6157c | 69 | cpu->env.psw.mask = PSW_MASK_32 | PSW_MASK_64; |
eb24f7c6 | 70 | s390_cpu_set_state(CPU_STATE_OPERATING, cpu); |
29c6157c CB |
71 | } |
72 | #endif | |
73 | ||
f5ae2a4f | 74 | /* S390CPUClass::cpu_reset() */ |
29e4bcb2 AF |
75 | static void s390_cpu_reset(CPUState *s) |
76 | { | |
77 | S390CPU *cpu = S390_CPU(s); | |
78 | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | |
79 | CPUS390XState *env = &cpu->env; | |
80 | ||
819bd309 | 81 | env->pfault_token = -1UL; |
f5ae2a4f | 82 | scc->parent_reset(s); |
18ff9494 | 83 | cpu->env.sigp_order = 0; |
eb24f7c6 | 84 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
00c8cb0a | 85 | tlb_flush(s, 1); |
f5ae2a4f CB |
86 | } |
87 | ||
88 | /* S390CPUClass::initial_reset() */ | |
89 | static void s390_cpu_initial_reset(CPUState *s) | |
90 | { | |
91 | S390CPU *cpu = S390_CPU(s); | |
92 | CPUS390XState *env = &cpu->env; | |
cc0d079d | 93 | int i; |
f5ae2a4f CB |
94 | |
95 | s390_cpu_reset(s); | |
96 | /* initial reset does not touch regs,fregs and aregs */ | |
f0c3c505 | 97 | memset(&env->fpc, 0, offsetof(CPUS390XState, cpu_num) - |
f5ae2a4f CB |
98 | offsetof(CPUS390XState, fpc)); |
99 | ||
100 | /* architectured initial values for CR 0 and 14 */ | |
101 | env->cregs[0] = CR0_RESET; | |
102 | env->cregs[14] = CR14_RESET; | |
819bd309 | 103 | |
3da0ab35 AJ |
104 | /* architectured initial value for Breaking-Event-Address register */ |
105 | env->gbea = 1; | |
106 | ||
819bd309 | 107 | env->pfault_token = -1UL; |
7107e5a7 | 108 | env->ext_index = -1; |
cc0d079d AJ |
109 | for (i = 0; i < ARRAY_SIZE(env->io_index); i++) { |
110 | env->io_index[i] = -1; | |
111 | } | |
49f5c9e9 | 112 | |
4a33565f AJ |
113 | /* tininess for underflow is detected before rounding */ |
114 | set_float_detect_tininess(float_tininess_before_rounding, | |
115 | &env->fpu_status); | |
116 | ||
49f5c9e9 TH |
117 | /* Reset state inside the kernel that we cannot access yet from QEMU. */ |
118 | if (kvm_enabled()) { | |
99607144 | 119 | kvm_s390_reset_vcpu(cpu); |
49f5c9e9 | 120 | } |
cbed0ba7 | 121 | tlb_flush(s, 1); |
f5ae2a4f CB |
122 | } |
123 | ||
124 | /* CPUClass:reset() */ | |
125 | static void s390_cpu_full_reset(CPUState *s) | |
126 | { | |
127 | S390CPU *cpu = S390_CPU(s); | |
128 | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | |
129 | CPUS390XState *env = &cpu->env; | |
cc0d079d | 130 | int i; |
f5ae2a4f | 131 | |
29e4bcb2 | 132 | scc->parent_reset(s); |
18ff9494 | 133 | cpu->env.sigp_order = 0; |
eb24f7c6 | 134 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
29e4bcb2 | 135 | |
f0c3c505 | 136 | memset(env, 0, offsetof(CPUS390XState, cpu_num)); |
70bada03 JF |
137 | |
138 | /* architectured initial values for CR 0 and 14 */ | |
139 | env->cregs[0] = CR0_RESET; | |
140 | env->cregs[14] = CR14_RESET; | |
819bd309 | 141 | |
3da0ab35 AJ |
142 | /* architectured initial value for Breaking-Event-Address register */ |
143 | env->gbea = 1; | |
144 | ||
819bd309 | 145 | env->pfault_token = -1UL; |
7107e5a7 | 146 | env->ext_index = -1; |
cc0d079d AJ |
147 | for (i = 0; i < ARRAY_SIZE(env->io_index); i++) { |
148 | env->io_index[i] = -1; | |
149 | } | |
819bd309 | 150 | |
4a33565f AJ |
151 | /* tininess for underflow is detected before rounding */ |
152 | set_float_detect_tininess(float_tininess_before_rounding, | |
153 | &env->fpu_status); | |
154 | ||
99607144 | 155 | /* Reset state inside the kernel that we cannot access yet from QEMU. */ |
50a2c6e5 PB |
156 | if (kvm_enabled()) { |
157 | kvm_s390_reset_vcpu(cpu); | |
158 | } | |
00c8cb0a | 159 | tlb_flush(s, 1); |
29e4bcb2 AF |
160 | } |
161 | ||
70bada03 JF |
162 | #if !defined(CONFIG_USER_ONLY) |
163 | static void s390_cpu_machine_reset_cb(void *opaque) | |
164 | { | |
165 | S390CPU *cpu = opaque; | |
166 | ||
e0eeb4a2 | 167 | run_on_cpu(CPU(cpu), s390_do_cpu_full_reset, NULL); |
70bada03 JF |
168 | } |
169 | #endif | |
170 | ||
dbad6b74 PC |
171 | static void s390_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) |
172 | { | |
173 | info->mach = bfd_mach_s390_64; | |
174 | info->print_insn = print_insn_s390; | |
175 | } | |
176 | ||
1f136632 AF |
177 | static void s390_cpu_realizefn(DeviceState *dev, Error **errp) |
178 | { | |
14a10fc3 | 179 | CPUState *cs = CPU(dev); |
1f136632 | 180 | S390CPUClass *scc = S390_CPU_GET_CLASS(dev); |
c6644fc8 MR |
181 | S390CPU *cpu = S390_CPU(dev); |
182 | CPUS390XState *env = &cpu->env; | |
183 | Error *err = NULL; | |
184 | ||
41868f84 DH |
185 | /* the model has to be realized before qemu_init_vcpu() due to kvm */ |
186 | s390_realize_cpu_model(cs, &err); | |
187 | if (err) { | |
188 | goto out; | |
189 | } | |
190 | ||
96b1a8bb MR |
191 | #if !defined(CONFIG_USER_ONLY) |
192 | if (cpu->id >= max_cpus) { | |
193 | error_setg(&err, "Unable to add CPU: %" PRIi64 | |
194 | ", max allowed: %d", cpu->id, max_cpus - 1); | |
195 | goto out; | |
196 | } | |
197 | #endif | |
198 | if (cpu_exists(cpu->id)) { | |
199 | error_setg(&err, "Unable to add CPU: %" PRIi64 | |
200 | ", it already exists", cpu->id); | |
201 | goto out; | |
202 | } | |
203 | if (cpu->id != scc->next_cpu_id) { | |
204 | error_setg(&err, "Unable to add CPU: %" PRIi64 | |
205 | ", The next available id is %" PRIi64, cpu->id, | |
206 | scc->next_cpu_id); | |
207 | goto out; | |
208 | } | |
209 | ||
ce5b1bbf | 210 | cpu_exec_realizefn(cs, &err); |
c6644fc8 | 211 | if (err != NULL) { |
96b1a8bb | 212 | goto out; |
c6644fc8 | 213 | } |
96b1a8bb | 214 | scc->next_cpu_id++; |
1f136632 | 215 | |
c6644fc8 MR |
216 | #if !defined(CONFIG_USER_ONLY) |
217 | qemu_register_reset(s390_cpu_machine_reset_cb, cpu); | |
218 | #endif | |
96b1a8bb | 219 | env->cpu_num = cpu->id; |
73d510c9 | 220 | s390_cpu_gdb_init(cs); |
14a10fc3 | 221 | qemu_init_vcpu(cs); |
159855f0 | 222 | #if !defined(CONFIG_USER_ONLY) |
e0eeb4a2 | 223 | run_on_cpu(cs, s390_do_cpu_full_reset, NULL); |
159855f0 | 224 | #else |
14a10fc3 | 225 | cpu_reset(cs); |
159855f0 | 226 | #endif |
1f136632 | 227 | |
96b1a8bb MR |
228 | scc->parent_realize(dev, &err); |
229 | ||
a006b67f MR |
230 | #if !defined(CONFIG_USER_ONLY) |
231 | if (dev->hotplugged) { | |
232 | raise_irq_cpu_hotplug(); | |
233 | } | |
234 | #endif | |
235 | ||
96b1a8bb MR |
236 | out: |
237 | error_propagate(errp, err); | |
238 | } | |
239 | ||
240 | static void s390x_cpu_get_id(Object *obj, Visitor *v, const char *name, | |
241 | void *opaque, Error **errp) | |
242 | { | |
243 | S390CPU *cpu = S390_CPU(obj); | |
244 | int64_t value = cpu->id; | |
245 | ||
246 | visit_type_int(v, name, &value, errp); | |
247 | } | |
248 | ||
249 | static void s390x_cpu_set_id(Object *obj, Visitor *v, const char *name, | |
250 | void *opaque, Error **errp) | |
251 | { | |
252 | S390CPU *cpu = S390_CPU(obj); | |
253 | DeviceState *dev = DEVICE(obj); | |
254 | const int64_t min = 0; | |
255 | const int64_t max = UINT32_MAX; | |
256 | Error *err = NULL; | |
257 | int64_t value; | |
258 | ||
259 | if (dev->realized) { | |
260 | error_setg(errp, "Attempt to set property '%s' on '%s' after " | |
261 | "it was realized", name, object_get_typename(obj)); | |
262 | return; | |
263 | } | |
264 | ||
265 | visit_type_int(v, name, &value, &err); | |
266 | if (err) { | |
267 | error_propagate(errp, err); | |
268 | return; | |
269 | } | |
270 | if (value < min || value > max) { | |
271 | error_setg(errp, "Property %s.%s doesn't take value %" PRId64 | |
272 | " (minimum: %" PRId64 ", maximum: %" PRId64 ")" , | |
273 | object_get_typename(obj), name, value, min, max); | |
274 | return; | |
275 | } | |
276 | cpu->id = value; | |
1f136632 AF |
277 | } |
278 | ||
8f22e0df AF |
279 | static void s390_cpu_initfn(Object *obj) |
280 | { | |
c05efcb1 | 281 | CPUState *cs = CPU(obj); |
8f22e0df AF |
282 | S390CPU *cpu = S390_CPU(obj); |
283 | CPUS390XState *env = &cpu->env; | |
2b7ac767 | 284 | static bool inited; |
8f22e0df AF |
285 | #if !defined(CONFIG_USER_ONLY) |
286 | struct tm tm; | |
287 | #endif | |
288 | ||
c05efcb1 | 289 | cs->env_ptr = env; |
ef3027af MR |
290 | cs->halted = 1; |
291 | cs->exception_index = EXCP_HLT; | |
96b1a8bb MR |
292 | object_property_add(OBJECT(cpu), "id", "int64_t", s390x_cpu_get_id, |
293 | s390x_cpu_set_id, NULL, NULL, NULL); | |
0754f604 | 294 | s390_cpu_model_register_props(obj); |
8f22e0df AF |
295 | #if !defined(CONFIG_USER_ONLY) |
296 | qemu_get_timedate(&tm, 0); | |
297 | env->tod_offset = TOD_UNIX_EPOCH + | |
298 | (time2tod(mktimegm(&tm)) * 1000000000ULL); | |
299 | env->tod_basetime = 0; | |
bc72ad67 AB |
300 | env->tod_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu); |
301 | env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu); | |
eb24f7c6 | 302 | s390_cpu_set_state(CPU_STATE_STOPPED, cpu); |
8f22e0df | 303 | #endif |
2b7ac767 AF |
304 | |
305 | if (tcg_enabled() && !inited) { | |
306 | inited = true; | |
307 | s390x_translate_init(); | |
308 | } | |
8f22e0df AF |
309 | } |
310 | ||
d5627ce8 AF |
311 | static void s390_cpu_finalize(Object *obj) |
312 | { | |
313 | #if !defined(CONFIG_USER_ONLY) | |
314 | S390CPU *cpu = S390_CPU(obj); | |
315 | ||
316 | qemu_unregister_reset(s390_cpu_machine_reset_cb, cpu); | |
3cda44f7 | 317 | g_free(cpu->irqstate); |
d5627ce8 AF |
318 | #endif |
319 | } | |
320 | ||
75973bfe | 321 | #if !defined(CONFIG_USER_ONLY) |
eb24f7c6 DH |
322 | static bool disabled_wait(CPUState *cpu) |
323 | { | |
324 | return cpu->halted && !(S390_CPU(cpu)->env.psw.mask & | |
325 | (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK)); | |
326 | } | |
327 | ||
75973bfe DH |
328 | static unsigned s390_count_running_cpus(void) |
329 | { | |
330 | CPUState *cpu; | |
331 | int nr_running = 0; | |
332 | ||
333 | CPU_FOREACH(cpu) { | |
334 | uint8_t state = S390_CPU(cpu)->env.cpu_state; | |
335 | if (state == CPU_STATE_OPERATING || | |
336 | state == CPU_STATE_LOAD) { | |
eb24f7c6 DH |
337 | if (!disabled_wait(cpu)) { |
338 | nr_running++; | |
339 | } | |
75973bfe DH |
340 | } |
341 | } | |
342 | ||
343 | return nr_running; | |
344 | } | |
345 | ||
eb24f7c6 | 346 | unsigned int s390_cpu_halt(S390CPU *cpu) |
75973bfe DH |
347 | { |
348 | CPUState *cs = CPU(cpu); | |
eb24f7c6 | 349 | trace_cpu_halt(cs->cpu_index); |
75973bfe | 350 | |
eb24f7c6 DH |
351 | if (!cs->halted) { |
352 | cs->halted = 1; | |
353 | cs->exception_index = EXCP_HLT; | |
75973bfe | 354 | } |
eb24f7c6 DH |
355 | |
356 | return s390_count_running_cpus(); | |
75973bfe DH |
357 | } |
358 | ||
eb24f7c6 | 359 | void s390_cpu_unhalt(S390CPU *cpu) |
75973bfe DH |
360 | { |
361 | CPUState *cs = CPU(cpu); | |
eb24f7c6 | 362 | trace_cpu_unhalt(cs->cpu_index); |
75973bfe | 363 | |
eb24f7c6 DH |
364 | if (cs->halted) { |
365 | cs->halted = 0; | |
366 | cs->exception_index = -1; | |
367 | } | |
368 | } | |
369 | ||
370 | unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) | |
371 | { | |
372 | trace_cpu_set_state(CPU(cpu)->cpu_index, cpu_state); | |
373 | ||
374 | switch (cpu_state) { | |
375 | case CPU_STATE_STOPPED: | |
376 | case CPU_STATE_CHECK_STOP: | |
377 | /* halt the cpu for common infrastructure */ | |
378 | s390_cpu_halt(cpu); | |
379 | break; | |
380 | case CPU_STATE_OPERATING: | |
381 | case CPU_STATE_LOAD: | |
382 | /* unhalt the cpu for common infrastructure */ | |
383 | s390_cpu_unhalt(cpu); | |
384 | break; | |
385 | default: | |
386 | error_report("Requested CPU state is not a valid S390 CPU state: %u", | |
387 | cpu_state); | |
388 | exit(1); | |
75973bfe | 389 | } |
c9e659c9 DH |
390 | if (kvm_enabled() && cpu->env.cpu_state != cpu_state) { |
391 | kvm_s390_set_cpu_state(cpu, cpu_state); | |
392 | } | |
eb24f7c6 | 393 | cpu->env.cpu_state = cpu_state; |
75973bfe DH |
394 | |
395 | return s390_count_running_cpus(); | |
396 | } | |
397 | #endif | |
398 | ||
b3820e6c DH |
399 | static gchar *s390_gdb_arch_name(CPUState *cs) |
400 | { | |
401 | return g_strdup("s390:64-bit"); | |
402 | } | |
403 | ||
29e4bcb2 AF |
404 | static void s390_cpu_class_init(ObjectClass *oc, void *data) |
405 | { | |
406 | S390CPUClass *scc = S390_CPU_CLASS(oc); | |
407 | CPUClass *cc = CPU_CLASS(scc); | |
c7396bbb | 408 | DeviceClass *dc = DEVICE_CLASS(oc); |
29e4bcb2 | 409 | |
c6644fc8 | 410 | scc->next_cpu_id = 0; |
1f136632 AF |
411 | scc->parent_realize = dc->realize; |
412 | dc->realize = s390_cpu_realizefn; | |
413 | ||
29e4bcb2 | 414 | scc->parent_reset = cc->reset; |
29c6157c CB |
415 | #if !defined(CONFIG_USER_ONLY) |
416 | scc->load_normal = s390_cpu_load_normal; | |
417 | #endif | |
f5ae2a4f CB |
418 | scc->cpu_reset = s390_cpu_reset; |
419 | scc->initial_cpu_reset = s390_cpu_initial_reset; | |
420 | cc->reset = s390_cpu_full_reset; | |
41868f84 | 421 | cc->class_by_name = s390_cpu_class_by_name, |
8c2e1b00 | 422 | cc->has_work = s390_cpu_has_work; |
97a8ea5a | 423 | cc->do_interrupt = s390_cpu_do_interrupt; |
878096ee | 424 | cc->dump_state = s390_cpu_dump_state; |
f45748f1 | 425 | cc->set_pc = s390_cpu_set_pc; |
5b50e790 AF |
426 | cc->gdb_read_register = s390_cpu_gdb_read_register; |
427 | cc->gdb_write_register = s390_cpu_gdb_write_register; | |
7510454e AF |
428 | #ifdef CONFIG_USER_ONLY |
429 | cc->handle_mmu_fault = s390_cpu_handle_mmu_fault; | |
430 | #else | |
00b941e5 | 431 | cc->get_phys_page_debug = s390_cpu_get_phys_page_debug; |
ef1df130 | 432 | cc->vmsd = &vmstate_s390_cpu; |
9b4f38e1 | 433 | cc->write_elf64_note = s390_cpu_write_elf64_note; |
02bb9bbf | 434 | cc->cpu_exec_interrupt = s390_cpu_exec_interrupt; |
311918b9 | 435 | cc->debug_excp_handler = s390x_cpu_debug_excp_handler; |
00b941e5 | 436 | #endif |
dbad6b74 PC |
437 | cc->disas_set_info = s390_cpu_disas_set_info; |
438 | ||
73d510c9 DH |
439 | cc->gdb_num_core_regs = S390_NUM_CORE_REGS; |
440 | cc->gdb_core_xml_file = "s390x-core64.xml"; | |
b3820e6c | 441 | cc->gdb_arch_name = s390_gdb_arch_name; |
4c315c27 | 442 | |
6efadc90 | 443 | s390_cpu_model_class_register_props(oc); |
29e4bcb2 AF |
444 | } |
445 | ||
446 | static const TypeInfo s390_cpu_type_info = { | |
447 | .name = TYPE_S390_CPU, | |
448 | .parent = TYPE_CPU, | |
449 | .instance_size = sizeof(S390CPU), | |
8f22e0df | 450 | .instance_init = s390_cpu_initfn, |
d5627ce8 | 451 | .instance_finalize = s390_cpu_finalize, |
41868f84 | 452 | .abstract = true, |
29e4bcb2 AF |
453 | .class_size = sizeof(S390CPUClass), |
454 | .class_init = s390_cpu_class_init, | |
455 | }; | |
456 | ||
457 | static void s390_cpu_register_types(void) | |
458 | { | |
459 | type_register_static(&s390_cpu_type_info); | |
460 | } | |
461 | ||
462 | type_init(s390_cpu_register_types) |