]>
Commit | Line | Data |
---|---|---|
e67db06e JL |
1 | /* |
2 | * OpenRISC translation | |
3 | * | |
4 | * Copyright (c) 2011-2012 Jia Liu <[email protected]> | |
5 | * Feng Gao <[email protected]> | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include "cpu.h" | |
022c62cb | 22 | #include "exec/exec-all.h" |
76cad711 | 23 | #include "disas/disas.h" |
e67db06e JL |
24 | #include "tcg-op.h" |
25 | #include "qemu-common.h" | |
1de7afc9 | 26 | #include "qemu/log.h" |
e67db06e | 27 | #include "config.h" |
1de7afc9 | 28 | #include "qemu/bitops.h" |
f08b6170 | 29 | #include "exec/cpu_ldst.h" |
bbe418f2 | 30 | |
2ef6175a RH |
31 | #include "exec/helper-proto.h" |
32 | #include "exec/helper-gen.h" | |
e67db06e | 33 | |
a7e30d84 LV |
34 | #include "trace-tcg.h" |
35 | ||
36 | ||
e67db06e JL |
37 | #define OPENRISC_DISAS |
38 | ||
39 | #ifdef OPENRISC_DISAS | |
40 | # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) | |
41 | #else | |
42 | # define LOG_DIS(...) do { } while (0) | |
43 | #endif | |
44 | ||
bbe418f2 JL |
45 | typedef struct DisasContext { |
46 | TranslationBlock *tb; | |
47 | target_ulong pc, ppc, npc; | |
48 | uint32_t tb_flags, synced_flags, flags; | |
49 | uint32_t is_jmp; | |
50 | uint32_t mem_idx; | |
51 | int singlestep_enabled; | |
52 | uint32_t delayed_branch; | |
53 | } DisasContext; | |
54 | ||
55 | static TCGv_ptr cpu_env; | |
56 | static TCGv cpu_sr; | |
57 | static TCGv cpu_R[32]; | |
58 | static TCGv cpu_pc; | |
59 | static TCGv jmp_pc; /* l.jr/l.jalr temp pc */ | |
60 | static TCGv cpu_npc; | |
61 | static TCGv cpu_ppc; | |
62 | static TCGv_i32 env_btaken; /* bf/bnf , F flag taken */ | |
63 | static TCGv_i32 fpcsr; | |
64 | static TCGv machi, maclo; | |
65 | static TCGv fpmaddhi, fpmaddlo; | |
66 | static TCGv_i32 env_flags; | |
022c62cb | 67 | #include "exec/gen-icount.h" |
bbe418f2 | 68 | |
e67db06e JL |
69 | void openrisc_translate_init(void) |
70 | { | |
bbe418f2 JL |
71 | static const char * const regnames[] = { |
72 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
73 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
74 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
75 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
76 | }; | |
77 | int i; | |
78 | ||
79 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | |
80 | cpu_sr = tcg_global_mem_new(TCG_AREG0, | |
81 | offsetof(CPUOpenRISCState, sr), "sr"); | |
82 | env_flags = tcg_global_mem_new_i32(TCG_AREG0, | |
83 | offsetof(CPUOpenRISCState, flags), | |
84 | "flags"); | |
85 | cpu_pc = tcg_global_mem_new(TCG_AREG0, | |
86 | offsetof(CPUOpenRISCState, pc), "pc"); | |
87 | cpu_npc = tcg_global_mem_new(TCG_AREG0, | |
88 | offsetof(CPUOpenRISCState, npc), "npc"); | |
89 | cpu_ppc = tcg_global_mem_new(TCG_AREG0, | |
90 | offsetof(CPUOpenRISCState, ppc), "ppc"); | |
91 | jmp_pc = tcg_global_mem_new(TCG_AREG0, | |
92 | offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc"); | |
93 | env_btaken = tcg_global_mem_new_i32(TCG_AREG0, | |
94 | offsetof(CPUOpenRISCState, btaken), | |
95 | "btaken"); | |
96 | fpcsr = tcg_global_mem_new_i32(TCG_AREG0, | |
97 | offsetof(CPUOpenRISCState, fpcsr), | |
98 | "fpcsr"); | |
99 | machi = tcg_global_mem_new(TCG_AREG0, | |
100 | offsetof(CPUOpenRISCState, machi), | |
101 | "machi"); | |
102 | maclo = tcg_global_mem_new(TCG_AREG0, | |
103 | offsetof(CPUOpenRISCState, maclo), | |
104 | "maclo"); | |
105 | fpmaddhi = tcg_global_mem_new(TCG_AREG0, | |
106 | offsetof(CPUOpenRISCState, fpmaddhi), | |
107 | "fpmaddhi"); | |
108 | fpmaddlo = tcg_global_mem_new(TCG_AREG0, | |
109 | offsetof(CPUOpenRISCState, fpmaddlo), | |
110 | "fpmaddlo"); | |
111 | for (i = 0; i < 32; i++) { | |
112 | cpu_R[i] = tcg_global_mem_new(TCG_AREG0, | |
113 | offsetof(CPUOpenRISCState, gpr[i]), | |
114 | regnames[i]); | |
115 | } | |
bbe418f2 JL |
116 | } |
117 | ||
2e0fc3a4 | 118 | /* Writeback SR_F translation space to execution space. */ |
bbe418f2 JL |
119 | static inline void wb_SR_F(void) |
120 | { | |
121 | int label; | |
122 | ||
123 | label = gen_new_label(); | |
124 | tcg_gen_andi_tl(cpu_sr, cpu_sr, ~SR_F); | |
125 | tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, label); | |
126 | tcg_gen_ori_tl(cpu_sr, cpu_sr, SR_F); | |
127 | gen_set_label(label); | |
128 | } | |
129 | ||
130 | static inline int zero_extend(unsigned int val, int width) | |
131 | { | |
132 | return val & ((1 << width) - 1); | |
133 | } | |
134 | ||
135 | static inline int sign_extend(unsigned int val, int width) | |
136 | { | |
137 | int sval; | |
138 | ||
139 | /* LSL */ | |
140 | val <<= TARGET_LONG_BITS - width; | |
141 | sval = val; | |
142 | /* ASR. */ | |
143 | sval >>= TARGET_LONG_BITS - width; | |
144 | return sval; | |
145 | } | |
146 | ||
147 | static inline void gen_sync_flags(DisasContext *dc) | |
148 | { | |
149 | /* Sync the tb dependent flag between translate and runtime. */ | |
150 | if (dc->tb_flags != dc->synced_flags) { | |
151 | tcg_gen_movi_tl(env_flags, dc->tb_flags); | |
152 | dc->synced_flags = dc->tb_flags; | |
153 | } | |
154 | } | |
155 | ||
156 | static void gen_exception(DisasContext *dc, unsigned int excp) | |
157 | { | |
158 | TCGv_i32 tmp = tcg_const_i32(excp); | |
159 | gen_helper_exception(cpu_env, tmp); | |
160 | tcg_temp_free_i32(tmp); | |
161 | } | |
162 | ||
163 | static void gen_illegal_exception(DisasContext *dc) | |
164 | { | |
165 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
166 | gen_exception(dc, EXCP_ILLEGAL); | |
167 | dc->is_jmp = DISAS_UPDATE; | |
168 | } | |
169 | ||
170 | /* not used yet, open it when we need or64. */ | |
171 | /*#ifdef TARGET_OPENRISC64 | |
172 | static void check_ob64s(DisasContext *dc) | |
173 | { | |
174 | if (!(dc->flags & CPUCFGR_OB64S)) { | |
175 | gen_illegal_exception(dc); | |
176 | } | |
177 | } | |
178 | ||
179 | static void check_of64s(DisasContext *dc) | |
180 | { | |
181 | if (!(dc->flags & CPUCFGR_OF64S)) { | |
182 | gen_illegal_exception(dc); | |
183 | } | |
184 | } | |
185 | ||
186 | static void check_ov64s(DisasContext *dc) | |
187 | { | |
188 | if (!(dc->flags & CPUCFGR_OV64S)) { | |
189 | gen_illegal_exception(dc); | |
190 | } | |
191 | } | |
192 | #endif*/ | |
193 | ||
194 | static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) | |
195 | { | |
196 | TranslationBlock *tb; | |
197 | tb = dc->tb; | |
198 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && | |
199 | likely(!dc->singlestep_enabled)) { | |
200 | tcg_gen_movi_tl(cpu_pc, dest); | |
201 | tcg_gen_goto_tb(n); | |
8cfd0495 | 202 | tcg_gen_exit_tb((uintptr_t)tb + n); |
bbe418f2 JL |
203 | } else { |
204 | tcg_gen_movi_tl(cpu_pc, dest); | |
205 | if (dc->singlestep_enabled) { | |
206 | gen_exception(dc, EXCP_DEBUG); | |
207 | } | |
208 | tcg_gen_exit_tb(0); | |
209 | } | |
210 | } | |
211 | ||
212 | static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_t op0) | |
213 | { | |
214 | target_ulong tmp_pc; | |
bbe418f2 JL |
215 | /* N26, 26bits imm */ |
216 | tmp_pc = sign_extend((imm<<2), 26) + dc->pc; | |
bbe418f2 | 217 | |
da1d7759 SM |
218 | switch (op0) { |
219 | case 0x00: /* l.j */ | |
bbe418f2 | 220 | tcg_gen_movi_tl(jmp_pc, tmp_pc); |
da1d7759 SM |
221 | break; |
222 | case 0x01: /* l.jal */ | |
bbe418f2 JL |
223 | tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8)); |
224 | tcg_gen_movi_tl(jmp_pc, tmp_pc); | |
da1d7759 SM |
225 | break; |
226 | case 0x03: /* l.bnf */ | |
227 | case 0x04: /* l.bf */ | |
228 | { | |
229 | int lab = gen_new_label(); | |
230 | TCGv sr_f = tcg_temp_new(); | |
231 | tcg_gen_movi_tl(jmp_pc, dc->pc+8); | |
232 | tcg_gen_andi_tl(sr_f, cpu_sr, SR_F); | |
233 | tcg_gen_brcondi_i32(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE, | |
234 | sr_f, SR_F, lab); | |
235 | tcg_gen_movi_tl(jmp_pc, tmp_pc); | |
236 | gen_set_label(lab); | |
237 | tcg_temp_free(sr_f); | |
238 | } | |
239 | break; | |
240 | case 0x11: /* l.jr */ | |
bbe418f2 | 241 | tcg_gen_mov_tl(jmp_pc, cpu_R[reg]); |
da1d7759 SM |
242 | break; |
243 | case 0x12: /* l.jalr */ | |
bbe418f2 JL |
244 | tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8)); |
245 | tcg_gen_mov_tl(jmp_pc, cpu_R[reg]); | |
da1d7759 SM |
246 | break; |
247 | default: | |
bbe418f2 | 248 | gen_illegal_exception(dc); |
da1d7759 | 249 | break; |
bbe418f2 JL |
250 | } |
251 | ||
bbe418f2 JL |
252 | dc->delayed_branch = 2; |
253 | dc->tb_flags |= D_FLAG; | |
254 | gen_sync_flags(dc); | |
255 | } | |
256 | ||
da1d7759 | 257 | |
bbe418f2 JL |
258 | static void dec_calc(DisasContext *dc, uint32_t insn) |
259 | { | |
260 | uint32_t op0, op1, op2; | |
261 | uint32_t ra, rb, rd; | |
262 | op0 = extract32(insn, 0, 4); | |
263 | op1 = extract32(insn, 8, 2); | |
264 | op2 = extract32(insn, 6, 2); | |
265 | ra = extract32(insn, 16, 5); | |
266 | rb = extract32(insn, 11, 5); | |
267 | rd = extract32(insn, 21, 5); | |
268 | ||
269 | switch (op0) { | |
270 | case 0x0000: | |
271 | switch (op1) { | |
272 | case 0x00: /* l.add */ | |
273 | LOG_DIS("l.add r%d, r%d, r%d\n", rd, ra, rb); | |
274 | { | |
275 | int lab = gen_new_label(); | |
276 | TCGv_i64 ta = tcg_temp_new_i64(); | |
277 | TCGv_i64 tb = tcg_temp_new_i64(); | |
278 | TCGv_i64 td = tcg_temp_local_new_i64(); | |
279 | TCGv_i32 res = tcg_temp_local_new_i32(); | |
280 | TCGv_i32 sr_ove = tcg_temp_local_new_i32(); | |
281 | tcg_gen_extu_i32_i64(ta, cpu_R[ra]); | |
282 | tcg_gen_extu_i32_i64(tb, cpu_R[rb]); | |
283 | tcg_gen_add_i64(td, ta, tb); | |
284 | tcg_gen_trunc_i64_i32(res, td); | |
285 | tcg_gen_shri_i64(td, td, 31); | |
286 | tcg_gen_andi_i64(td, td, 0x3); | |
287 | /* Jump to lab when no overflow. */ | |
288 | tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab); | |
289 | tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab); | |
290 | tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY)); | |
291 | tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE); | |
292 | tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab); | |
293 | gen_exception(dc, EXCP_RANGE); | |
294 | gen_set_label(lab); | |
295 | tcg_gen_mov_i32(cpu_R[rd], res); | |
296 | tcg_temp_free_i64(ta); | |
297 | tcg_temp_free_i64(tb); | |
298 | tcg_temp_free_i64(td); | |
299 | tcg_temp_free_i32(res); | |
300 | tcg_temp_free_i32(sr_ove); | |
301 | } | |
302 | break; | |
303 | default: | |
304 | gen_illegal_exception(dc); | |
305 | break; | |
306 | } | |
307 | break; | |
308 | ||
309 | case 0x0001: /* l.addc */ | |
310 | switch (op1) { | |
311 | case 0x00: | |
312 | LOG_DIS("l.addc r%d, r%d, r%d\n", rd, ra, rb); | |
313 | { | |
314 | int lab = gen_new_label(); | |
315 | TCGv_i64 ta = tcg_temp_new_i64(); | |
316 | TCGv_i64 tb = tcg_temp_new_i64(); | |
317 | TCGv_i64 tcy = tcg_temp_local_new_i64(); | |
318 | TCGv_i64 td = tcg_temp_local_new_i64(); | |
319 | TCGv_i32 res = tcg_temp_local_new_i32(); | |
320 | TCGv_i32 sr_cy = tcg_temp_local_new_i32(); | |
321 | TCGv_i32 sr_ove = tcg_temp_local_new_i32(); | |
322 | tcg_gen_extu_i32_i64(ta, cpu_R[ra]); | |
323 | tcg_gen_extu_i32_i64(tb, cpu_R[rb]); | |
324 | tcg_gen_andi_i32(sr_cy, cpu_sr, SR_CY); | |
325 | tcg_gen_extu_i32_i64(tcy, sr_cy); | |
326 | tcg_gen_shri_i64(tcy, tcy, 10); | |
327 | tcg_gen_add_i64(td, ta, tb); | |
328 | tcg_gen_add_i64(td, td, tcy); | |
329 | tcg_gen_trunc_i64_i32(res, td); | |
330 | tcg_gen_shri_i64(td, td, 32); | |
331 | tcg_gen_andi_i64(td, td, 0x3); | |
332 | /* Jump to lab when no overflow. */ | |
333 | tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab); | |
334 | tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab); | |
335 | tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY)); | |
336 | tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE); | |
337 | tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab); | |
338 | gen_exception(dc, EXCP_RANGE); | |
339 | gen_set_label(lab); | |
340 | tcg_gen_mov_i32(cpu_R[rd], res); | |
341 | tcg_temp_free_i64(ta); | |
342 | tcg_temp_free_i64(tb); | |
343 | tcg_temp_free_i64(tcy); | |
344 | tcg_temp_free_i64(td); | |
345 | tcg_temp_free_i32(res); | |
346 | tcg_temp_free_i32(sr_cy); | |
347 | tcg_temp_free_i32(sr_ove); | |
348 | } | |
349 | break; | |
350 | default: | |
351 | gen_illegal_exception(dc); | |
352 | break; | |
353 | } | |
354 | break; | |
355 | ||
356 | case 0x0002: /* l.sub */ | |
357 | switch (op1) { | |
358 | case 0x00: | |
359 | LOG_DIS("l.sub r%d, r%d, r%d\n", rd, ra, rb); | |
360 | { | |
361 | int lab = gen_new_label(); | |
362 | TCGv_i64 ta = tcg_temp_new_i64(); | |
363 | TCGv_i64 tb = tcg_temp_new_i64(); | |
364 | TCGv_i64 td = tcg_temp_local_new_i64(); | |
365 | TCGv_i32 res = tcg_temp_local_new_i32(); | |
366 | TCGv_i32 sr_ove = tcg_temp_local_new_i32(); | |
367 | ||
368 | tcg_gen_extu_i32_i64(ta, cpu_R[ra]); | |
369 | tcg_gen_extu_i32_i64(tb, cpu_R[rb]); | |
370 | tcg_gen_sub_i64(td, ta, tb); | |
371 | tcg_gen_trunc_i64_i32(res, td); | |
372 | tcg_gen_shri_i64(td, td, 31); | |
373 | tcg_gen_andi_i64(td, td, 0x3); | |
374 | /* Jump to lab when no overflow. */ | |
375 | tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab); | |
376 | tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab); | |
377 | tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY)); | |
378 | tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE); | |
379 | tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab); | |
380 | gen_exception(dc, EXCP_RANGE); | |
381 | gen_set_label(lab); | |
382 | tcg_gen_mov_i32(cpu_R[rd], res); | |
383 | tcg_temp_free_i64(ta); | |
384 | tcg_temp_free_i64(tb); | |
385 | tcg_temp_free_i64(td); | |
386 | tcg_temp_free_i32(res); | |
387 | tcg_temp_free_i32(sr_ove); | |
388 | } | |
389 | break; | |
390 | default: | |
391 | gen_illegal_exception(dc); | |
392 | break; | |
393 | } | |
394 | break; | |
395 | ||
396 | case 0x0003: /* l.and */ | |
397 | switch (op1) { | |
398 | case 0x00: | |
399 | LOG_DIS("l.and r%d, r%d, r%d\n", rd, ra, rb); | |
400 | tcg_gen_and_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
401 | break; | |
402 | default: | |
403 | gen_illegal_exception(dc); | |
404 | break; | |
405 | } | |
406 | break; | |
407 | ||
408 | case 0x0004: /* l.or */ | |
409 | switch (op1) { | |
410 | case 0x00: | |
411 | LOG_DIS("l.or r%d, r%d, r%d\n", rd, ra, rb); | |
412 | tcg_gen_or_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
413 | break; | |
414 | default: | |
415 | gen_illegal_exception(dc); | |
416 | break; | |
417 | } | |
418 | break; | |
419 | ||
420 | case 0x0005: | |
421 | switch (op1) { | |
422 | case 0x00: /* l.xor */ | |
423 | LOG_DIS("l.xor r%d, r%d, r%d\n", rd, ra, rb); | |
424 | tcg_gen_xor_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
425 | break; | |
426 | default: | |
427 | gen_illegal_exception(dc); | |
428 | break; | |
429 | } | |
430 | break; | |
431 | ||
432 | case 0x0006: | |
433 | switch (op1) { | |
434 | case 0x03: /* l.mul */ | |
435 | LOG_DIS("l.mul r%d, r%d, r%d\n", rd, ra, rb); | |
436 | if (ra != 0 && rb != 0) { | |
437 | gen_helper_mul32(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
438 | } else { | |
439 | tcg_gen_movi_tl(cpu_R[rd], 0x0); | |
440 | } | |
441 | break; | |
442 | default: | |
443 | gen_illegal_exception(dc); | |
444 | break; | |
445 | } | |
446 | break; | |
447 | ||
448 | case 0x0009: | |
449 | switch (op1) { | |
450 | case 0x03: /* l.div */ | |
451 | LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb); | |
452 | { | |
453 | int lab0 = gen_new_label(); | |
454 | int lab1 = gen_new_label(); | |
455 | int lab2 = gen_new_label(); | |
456 | int lab3 = gen_new_label(); | |
457 | TCGv_i32 sr_ove = tcg_temp_local_new_i32(); | |
458 | if (rb == 0) { | |
459 | tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY)); | |
460 | tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE); | |
461 | tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0); | |
462 | gen_exception(dc, EXCP_RANGE); | |
463 | gen_set_label(lab0); | |
464 | } else { | |
465 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[rb], | |
466 | 0x00000000, lab1); | |
467 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[ra], | |
468 | 0x80000000, lab2); | |
469 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[rb], | |
470 | 0xffffffff, lab2); | |
471 | gen_set_label(lab1); | |
472 | tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY)); | |
473 | tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE); | |
474 | tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab3); | |
475 | gen_exception(dc, EXCP_RANGE); | |
476 | gen_set_label(lab2); | |
477 | tcg_gen_div_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
478 | gen_set_label(lab3); | |
479 | } | |
480 | tcg_temp_free_i32(sr_ove); | |
481 | } | |
482 | break; | |
483 | ||
484 | default: | |
485 | gen_illegal_exception(dc); | |
486 | break; | |
487 | } | |
488 | break; | |
489 | ||
490 | case 0x000a: | |
491 | switch (op1) { | |
492 | case 0x03: /* l.divu */ | |
493 | LOG_DIS("l.divu r%d, r%d, r%d\n", rd, ra, rb); | |
494 | { | |
495 | int lab0 = gen_new_label(); | |
496 | int lab1 = gen_new_label(); | |
497 | int lab2 = gen_new_label(); | |
498 | TCGv_i32 sr_ove = tcg_temp_local_new_i32(); | |
499 | if (rb == 0) { | |
500 | tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY)); | |
501 | tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE); | |
502 | tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0); | |
503 | gen_exception(dc, EXCP_RANGE); | |
504 | gen_set_label(lab0); | |
505 | } else { | |
506 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[rb], | |
507 | 0x00000000, lab1); | |
508 | tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY)); | |
509 | tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE); | |
510 | tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab2); | |
511 | gen_exception(dc, EXCP_RANGE); | |
512 | gen_set_label(lab1); | |
513 | tcg_gen_divu_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
514 | gen_set_label(lab2); | |
515 | } | |
516 | tcg_temp_free_i32(sr_ove); | |
517 | } | |
518 | break; | |
519 | ||
520 | default: | |
521 | gen_illegal_exception(dc); | |
522 | break; | |
523 | } | |
524 | break; | |
525 | ||
526 | case 0x000b: | |
527 | switch (op1) { | |
528 | case 0x03: /* l.mulu */ | |
529 | LOG_DIS("l.mulu r%d, r%d, r%d\n", rd, ra, rb); | |
530 | if (rb != 0 && ra != 0) { | |
531 | TCGv_i64 result = tcg_temp_local_new_i64(); | |
532 | TCGv_i64 tra = tcg_temp_local_new_i64(); | |
533 | TCGv_i64 trb = tcg_temp_local_new_i64(); | |
534 | TCGv_i64 high = tcg_temp_new_i64(); | |
535 | TCGv_i32 sr_ove = tcg_temp_local_new_i32(); | |
536 | int lab = gen_new_label(); | |
29923e94 | 537 | /* Calculate each result. */ |
bbe418f2 JL |
538 | tcg_gen_extu_i32_i64(tra, cpu_R[ra]); |
539 | tcg_gen_extu_i32_i64(trb, cpu_R[rb]); | |
540 | tcg_gen_mul_i64(result, tra, trb); | |
541 | tcg_temp_free_i64(tra); | |
542 | tcg_temp_free_i64(trb); | |
543 | tcg_gen_shri_i64(high, result, TARGET_LONG_BITS); | |
29923e94 | 544 | /* Overflow or not. */ |
bbe418f2 JL |
545 | tcg_gen_brcondi_i64(TCG_COND_EQ, high, 0x00000000, lab); |
546 | tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY)); | |
547 | tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE); | |
548 | tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab); | |
549 | gen_exception(dc, EXCP_RANGE); | |
550 | gen_set_label(lab); | |
551 | tcg_temp_free_i64(high); | |
552 | tcg_gen_trunc_i64_tl(cpu_R[rd], result); | |
553 | tcg_temp_free_i64(result); | |
554 | tcg_temp_free_i32(sr_ove); | |
555 | } else { | |
556 | tcg_gen_movi_tl(cpu_R[rd], 0); | |
557 | } | |
558 | break; | |
559 | ||
560 | default: | |
561 | gen_illegal_exception(dc); | |
562 | break; | |
563 | } | |
564 | break; | |
565 | ||
566 | case 0x000e: | |
567 | switch (op1) { | |
568 | case 0x00: /* l.cmov */ | |
569 | LOG_DIS("l.cmov r%d, r%d, r%d\n", rd, ra, rb); | |
570 | { | |
571 | int lab = gen_new_label(); | |
572 | TCGv res = tcg_temp_local_new(); | |
573 | TCGv sr_f = tcg_temp_new(); | |
574 | tcg_gen_andi_tl(sr_f, cpu_sr, SR_F); | |
575 | tcg_gen_mov_tl(res, cpu_R[rb]); | |
576 | tcg_gen_brcondi_tl(TCG_COND_NE, sr_f, SR_F, lab); | |
577 | tcg_gen_mov_tl(res, cpu_R[ra]); | |
578 | gen_set_label(lab); | |
579 | tcg_gen_mov_tl(cpu_R[rd], res); | |
580 | tcg_temp_free(sr_f); | |
581 | tcg_temp_free(res); | |
582 | } | |
583 | break; | |
584 | ||
585 | default: | |
586 | gen_illegal_exception(dc); | |
587 | break; | |
588 | } | |
589 | break; | |
590 | ||
591 | case 0x000f: | |
592 | switch (op1) { | |
593 | case 0x00: /* l.ff1 */ | |
594 | LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd, ra, rb); | |
595 | gen_helper_ff1(cpu_R[rd], cpu_R[ra]); | |
596 | break; | |
597 | case 0x01: /* l.fl1 */ | |
598 | LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd, ra, rb); | |
599 | gen_helper_fl1(cpu_R[rd], cpu_R[ra]); | |
600 | break; | |
601 | ||
602 | default: | |
603 | gen_illegal_exception(dc); | |
604 | break; | |
605 | } | |
606 | break; | |
607 | ||
608 | case 0x0008: | |
609 | switch (op1) { | |
610 | case 0x00: | |
611 | switch (op2) { | |
612 | case 0x00: /* l.sll */ | |
613 | LOG_DIS("l.sll r%d, r%d, r%d\n", rd, ra, rb); | |
614 | tcg_gen_shl_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
615 | break; | |
616 | case 0x01: /* l.srl */ | |
617 | LOG_DIS("l.srl r%d, r%d, r%d\n", rd, ra, rb); | |
618 | tcg_gen_shr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
619 | break; | |
620 | case 0x02: /* l.sra */ | |
621 | LOG_DIS("l.sra r%d, r%d, r%d\n", rd, ra, rb); | |
622 | tcg_gen_sar_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
623 | break; | |
624 | case 0x03: /* l.ror */ | |
625 | LOG_DIS("l.ror r%d, r%d, r%d\n", rd, ra, rb); | |
626 | tcg_gen_rotr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
627 | break; | |
628 | ||
629 | default: | |
630 | gen_illegal_exception(dc); | |
631 | break; | |
632 | } | |
633 | break; | |
634 | ||
635 | default: | |
636 | gen_illegal_exception(dc); | |
637 | break; | |
638 | } | |
639 | break; | |
640 | ||
641 | case 0x000c: | |
642 | switch (op1) { | |
643 | case 0x00: | |
644 | switch (op2) { | |
645 | case 0x00: /* l.exths */ | |
646 | LOG_DIS("l.exths r%d, r%d\n", rd, ra); | |
647 | tcg_gen_ext16s_tl(cpu_R[rd], cpu_R[ra]); | |
648 | break; | |
649 | case 0x01: /* l.extbs */ | |
650 | LOG_DIS("l.extbs r%d, r%d\n", rd, ra); | |
651 | tcg_gen_ext8s_tl(cpu_R[rd], cpu_R[ra]); | |
652 | break; | |
653 | case 0x02: /* l.exthz */ | |
654 | LOG_DIS("l.exthz r%d, r%d\n", rd, ra); | |
655 | tcg_gen_ext16u_tl(cpu_R[rd], cpu_R[ra]); | |
656 | break; | |
657 | case 0x03: /* l.extbz */ | |
658 | LOG_DIS("l.extbz r%d, r%d\n", rd, ra); | |
659 | tcg_gen_ext8u_tl(cpu_R[rd], cpu_R[ra]); | |
660 | break; | |
661 | ||
662 | default: | |
663 | gen_illegal_exception(dc); | |
664 | break; | |
665 | } | |
666 | break; | |
667 | ||
668 | default: | |
669 | gen_illegal_exception(dc); | |
670 | break; | |
671 | } | |
672 | break; | |
673 | ||
674 | case 0x000d: | |
675 | switch (op1) { | |
676 | case 0x00: | |
677 | switch (op2) { | |
678 | case 0x00: /* l.extws */ | |
679 | LOG_DIS("l.extws r%d, r%d\n", rd, ra); | |
680 | tcg_gen_ext32s_tl(cpu_R[rd], cpu_R[ra]); | |
681 | break; | |
682 | case 0x01: /* l.extwz */ | |
683 | LOG_DIS("l.extwz r%d, r%d\n", rd, ra); | |
684 | tcg_gen_ext32u_tl(cpu_R[rd], cpu_R[ra]); | |
685 | break; | |
686 | ||
687 | default: | |
688 | gen_illegal_exception(dc); | |
689 | break; | |
690 | } | |
691 | break; | |
692 | ||
693 | default: | |
694 | gen_illegal_exception(dc); | |
695 | break; | |
696 | } | |
697 | break; | |
698 | ||
699 | default: | |
700 | gen_illegal_exception(dc); | |
701 | break; | |
702 | } | |
703 | } | |
704 | ||
705 | static void dec_misc(DisasContext *dc, uint32_t insn) | |
706 | { | |
707 | uint32_t op0, op1; | |
708 | uint32_t ra, rb, rd; | |
709 | #ifdef OPENRISC_DISAS | |
710 | uint32_t L6, K5; | |
711 | #endif | |
712 | uint32_t I16, I5, I11, N26, tmp; | |
5631e69c RH |
713 | TCGMemOp mop; |
714 | ||
bbe418f2 JL |
715 | op0 = extract32(insn, 26, 6); |
716 | op1 = extract32(insn, 24, 2); | |
717 | ra = extract32(insn, 16, 5); | |
718 | rb = extract32(insn, 11, 5); | |
719 | rd = extract32(insn, 21, 5); | |
720 | #ifdef OPENRISC_DISAS | |
721 | L6 = extract32(insn, 5, 6); | |
722 | K5 = extract32(insn, 0, 5); | |
723 | #endif | |
724 | I16 = extract32(insn, 0, 16); | |
725 | I5 = extract32(insn, 21, 5); | |
726 | I11 = extract32(insn, 0, 11); | |
727 | N26 = extract32(insn, 0, 26); | |
728 | tmp = (I5<<11) + I11; | |
729 | ||
730 | switch (op0) { | |
731 | case 0x00: /* l.j */ | |
732 | LOG_DIS("l.j %d\n", N26); | |
733 | gen_jump(dc, N26, 0, op0); | |
734 | break; | |
735 | ||
736 | case 0x01: /* l.jal */ | |
737 | LOG_DIS("l.jal %d\n", N26); | |
738 | gen_jump(dc, N26, 0, op0); | |
739 | break; | |
740 | ||
741 | case 0x03: /* l.bnf */ | |
742 | LOG_DIS("l.bnf %d\n", N26); | |
743 | gen_jump(dc, N26, 0, op0); | |
744 | break; | |
745 | ||
746 | case 0x04: /* l.bf */ | |
747 | LOG_DIS("l.bf %d\n", N26); | |
748 | gen_jump(dc, N26, 0, op0); | |
749 | break; | |
750 | ||
751 | case 0x05: | |
752 | switch (op1) { | |
753 | case 0x01: /* l.nop */ | |
754 | LOG_DIS("l.nop %d\n", I16); | |
755 | break; | |
756 | ||
757 | default: | |
758 | gen_illegal_exception(dc); | |
759 | break; | |
760 | } | |
761 | break; | |
762 | ||
763 | case 0x11: /* l.jr */ | |
764 | LOG_DIS("l.jr r%d\n", rb); | |
765 | gen_jump(dc, 0, rb, op0); | |
766 | break; | |
767 | ||
768 | case 0x12: /* l.jalr */ | |
769 | LOG_DIS("l.jalr r%d\n", rb); | |
770 | gen_jump(dc, 0, rb, op0); | |
771 | break; | |
772 | ||
773 | case 0x13: /* l.maci */ | |
774 | LOG_DIS("l.maci %d, r%d, %d\n", I5, ra, I11); | |
775 | { | |
776 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
777 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
778 | TCGv_i32 dst = tcg_temp_new_i32(); | |
779 | TCGv ttmp = tcg_const_tl(tmp); | |
780 | tcg_gen_mul_tl(dst, cpu_R[ra], ttmp); | |
781 | tcg_gen_ext_i32_i64(t1, dst); | |
782 | tcg_gen_concat_i32_i64(t2, maclo, machi); | |
783 | tcg_gen_add_i64(t2, t2, t1); | |
784 | tcg_gen_trunc_i64_i32(maclo, t2); | |
785 | tcg_gen_shri_i64(t2, t2, 32); | |
786 | tcg_gen_trunc_i64_i32(machi, t2); | |
787 | tcg_temp_free_i32(dst); | |
788 | tcg_temp_free(ttmp); | |
789 | tcg_temp_free_i64(t1); | |
790 | tcg_temp_free_i64(t2); | |
791 | } | |
792 | break; | |
793 | ||
794 | case 0x09: /* l.rfe */ | |
795 | LOG_DIS("l.rfe\n"); | |
796 | { | |
797 | #if defined(CONFIG_USER_ONLY) | |
798 | return; | |
799 | #else | |
800 | if (dc->mem_idx == MMU_USER_IDX) { | |
801 | gen_illegal_exception(dc); | |
802 | return; | |
803 | } | |
804 | gen_helper_rfe(cpu_env); | |
805 | dc->is_jmp = DISAS_UPDATE; | |
806 | #endif | |
807 | } | |
808 | break; | |
809 | ||
810 | case 0x1c: /* l.cust1 */ | |
811 | LOG_DIS("l.cust1\n"); | |
812 | break; | |
813 | ||
814 | case 0x1d: /* l.cust2 */ | |
815 | LOG_DIS("l.cust2\n"); | |
816 | break; | |
817 | ||
818 | case 0x1e: /* l.cust3 */ | |
819 | LOG_DIS("l.cust3\n"); | |
820 | break; | |
821 | ||
822 | case 0x1f: /* l.cust4 */ | |
823 | LOG_DIS("l.cust4\n"); | |
824 | break; | |
825 | ||
826 | case 0x3c: /* l.cust5 */ | |
827 | LOG_DIS("l.cust5 r%d, r%d, r%d, %d, %d\n", rd, ra, rb, L6, K5); | |
828 | break; | |
829 | ||
830 | case 0x3d: /* l.cust6 */ | |
831 | LOG_DIS("l.cust6\n"); | |
832 | break; | |
833 | ||
834 | case 0x3e: /* l.cust7 */ | |
835 | LOG_DIS("l.cust7\n"); | |
836 | break; | |
837 | ||
838 | case 0x3f: /* l.cust8 */ | |
839 | LOG_DIS("l.cust8\n"); | |
840 | break; | |
841 | ||
842 | /* not used yet, open it when we need or64. */ | |
843 | /*#ifdef TARGET_OPENRISC64 | |
844 | case 0x20: l.ld | |
845 | LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
846 | check_ob64s(dc); |
847 | mop = MO_TEQ; | |
848 | goto do_load; | |
bbe418f2 JL |
849 | #endif*/ |
850 | ||
851 | case 0x21: /* l.lwz */ | |
852 | LOG_DIS("l.lwz r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
853 | mop = MO_TEUL; |
854 | goto do_load; | |
bbe418f2 JL |
855 | |
856 | case 0x22: /* l.lws */ | |
857 | LOG_DIS("l.lws r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
858 | mop = MO_TESL; |
859 | goto do_load; | |
bbe418f2 JL |
860 | |
861 | case 0x23: /* l.lbz */ | |
862 | LOG_DIS("l.lbz r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
863 | mop = MO_UB; |
864 | goto do_load; | |
bbe418f2 JL |
865 | |
866 | case 0x24: /* l.lbs */ | |
867 | LOG_DIS("l.lbs r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
868 | mop = MO_SB; |
869 | goto do_load; | |
bbe418f2 JL |
870 | |
871 | case 0x25: /* l.lhz */ | |
872 | LOG_DIS("l.lhz r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
873 | mop = MO_TEUW; |
874 | goto do_load; | |
bbe418f2 JL |
875 | |
876 | case 0x26: /* l.lhs */ | |
877 | LOG_DIS("l.lhs r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
878 | mop = MO_TESW; |
879 | goto do_load; | |
880 | ||
881 | do_load: | |
bbe418f2 JL |
882 | { |
883 | TCGv t0 = tcg_temp_new(); | |
884 | tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16)); | |
5631e69c | 885 | tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc->mem_idx, mop); |
bbe418f2 JL |
886 | tcg_temp_free(t0); |
887 | } | |
888 | break; | |
889 | ||
890 | case 0x27: /* l.addi */ | |
891 | LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16); | |
892 | { | |
352367e8 SM |
893 | if (I16 == 0) { |
894 | tcg_gen_mov_tl(cpu_R[rd], cpu_R[ra]); | |
895 | } else { | |
896 | int lab = gen_new_label(); | |
897 | TCGv_i64 ta = tcg_temp_new_i64(); | |
898 | TCGv_i64 td = tcg_temp_local_new_i64(); | |
899 | TCGv_i32 res = tcg_temp_local_new_i32(); | |
900 | TCGv_i32 sr_ove = tcg_temp_local_new_i32(); | |
901 | tcg_gen_extu_i32_i64(ta, cpu_R[ra]); | |
902 | tcg_gen_addi_i64(td, ta, sign_extend(I16, 16)); | |
903 | tcg_gen_trunc_i64_i32(res, td); | |
904 | tcg_gen_shri_i64(td, td, 32); | |
905 | tcg_gen_andi_i64(td, td, 0x3); | |
906 | /* Jump to lab when no overflow. */ | |
907 | tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab); | |
908 | tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab); | |
909 | tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY)); | |
910 | tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE); | |
911 | tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab); | |
912 | gen_exception(dc, EXCP_RANGE); | |
913 | gen_set_label(lab); | |
914 | tcg_gen_mov_i32(cpu_R[rd], res); | |
915 | tcg_temp_free_i64(ta); | |
916 | tcg_temp_free_i64(td); | |
917 | tcg_temp_free_i32(res); | |
918 | tcg_temp_free_i32(sr_ove); | |
919 | } | |
bbe418f2 JL |
920 | } |
921 | break; | |
922 | ||
923 | case 0x28: /* l.addic */ | |
924 | LOG_DIS("l.addic r%d, r%d, %d\n", rd, ra, I16); | |
925 | { | |
926 | int lab = gen_new_label(); | |
927 | TCGv_i64 ta = tcg_temp_new_i64(); | |
928 | TCGv_i64 td = tcg_temp_local_new_i64(); | |
929 | TCGv_i64 tcy = tcg_temp_local_new_i64(); | |
930 | TCGv_i32 res = tcg_temp_local_new_i32(); | |
931 | TCGv_i32 sr_cy = tcg_temp_local_new_i32(); | |
932 | TCGv_i32 sr_ove = tcg_temp_local_new_i32(); | |
933 | tcg_gen_extu_i32_i64(ta, cpu_R[ra]); | |
934 | tcg_gen_andi_i32(sr_cy, cpu_sr, SR_CY); | |
935 | tcg_gen_shri_i32(sr_cy, sr_cy, 10); | |
936 | tcg_gen_extu_i32_i64(tcy, sr_cy); | |
937 | tcg_gen_addi_i64(td, ta, sign_extend(I16, 16)); | |
938 | tcg_gen_add_i64(td, td, tcy); | |
939 | tcg_gen_trunc_i64_i32(res, td); | |
940 | tcg_gen_shri_i64(td, td, 32); | |
941 | tcg_gen_andi_i64(td, td, 0x3); | |
942 | /* Jump to lab when no overflow. */ | |
943 | tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab); | |
944 | tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab); | |
945 | tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY)); | |
946 | tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE); | |
947 | tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab); | |
948 | gen_exception(dc, EXCP_RANGE); | |
949 | gen_set_label(lab); | |
950 | tcg_gen_mov_i32(cpu_R[rd], res); | |
951 | tcg_temp_free_i64(ta); | |
952 | tcg_temp_free_i64(td); | |
953 | tcg_temp_free_i64(tcy); | |
954 | tcg_temp_free_i32(res); | |
955 | tcg_temp_free_i32(sr_cy); | |
956 | tcg_temp_free_i32(sr_ove); | |
957 | } | |
958 | break; | |
959 | ||
960 | case 0x29: /* l.andi */ | |
961 | LOG_DIS("l.andi r%d, r%d, %d\n", rd, ra, I16); | |
962 | tcg_gen_andi_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16)); | |
963 | break; | |
964 | ||
965 | case 0x2a: /* l.ori */ | |
966 | LOG_DIS("l.ori r%d, r%d, %d\n", rd, ra, I16); | |
967 | tcg_gen_ori_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16)); | |
968 | break; | |
969 | ||
970 | case 0x2b: /* l.xori */ | |
971 | LOG_DIS("l.xori r%d, r%d, %d\n", rd, ra, I16); | |
972 | tcg_gen_xori_tl(cpu_R[rd], cpu_R[ra], sign_extend(I16, 16)); | |
973 | break; | |
974 | ||
975 | case 0x2c: /* l.muli */ | |
976 | LOG_DIS("l.muli r%d, r%d, %d\n", rd, ra, I16); | |
977 | if (ra != 0 && I16 != 0) { | |
978 | TCGv_i32 im = tcg_const_i32(I16); | |
979 | gen_helper_mul32(cpu_R[rd], cpu_env, cpu_R[ra], im); | |
980 | tcg_temp_free_i32(im); | |
981 | } else { | |
982 | tcg_gen_movi_tl(cpu_R[rd], 0x0); | |
983 | } | |
984 | break; | |
985 | ||
986 | case 0x2d: /* l.mfspr */ | |
987 | LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, I16); | |
4dd044c6 JL |
988 | { |
989 | #if defined(CONFIG_USER_ONLY) | |
990 | return; | |
991 | #else | |
992 | TCGv_i32 ti = tcg_const_i32(I16); | |
993 | if (dc->mem_idx == MMU_USER_IDX) { | |
994 | gen_illegal_exception(dc); | |
995 | return; | |
996 | } | |
997 | gen_helper_mfspr(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], ti); | |
998 | tcg_temp_free_i32(ti); | |
999 | #endif | |
1000 | } | |
bbe418f2 JL |
1001 | break; |
1002 | ||
1003 | case 0x30: /* l.mtspr */ | |
1004 | LOG_DIS("l.mtspr %d, r%d, r%d, %d\n", I5, ra, rb, I11); | |
4dd044c6 JL |
1005 | { |
1006 | #if defined(CONFIG_USER_ONLY) | |
1007 | return; | |
1008 | #else | |
1009 | TCGv_i32 im = tcg_const_i32(tmp); | |
1010 | if (dc->mem_idx == MMU_USER_IDX) { | |
1011 | gen_illegal_exception(dc); | |
1012 | return; | |
1013 | } | |
1014 | gen_helper_mtspr(cpu_env, cpu_R[ra], cpu_R[rb], im); | |
1015 | tcg_temp_free_i32(im); | |
1016 | #endif | |
1017 | } | |
bbe418f2 JL |
1018 | break; |
1019 | ||
1020 | /* not used yet, open it when we need or64. */ | |
1021 | /*#ifdef TARGET_OPENRISC64 | |
1022 | case 0x34: l.sd | |
1023 | LOG_DIS("l.sd %d, r%d, r%d, %d\n", I5, ra, rb, I11); | |
5631e69c RH |
1024 | check_ob64s(dc); |
1025 | mop = MO_TEQ; | |
1026 | goto do_store; | |
bbe418f2 JL |
1027 | #endif*/ |
1028 | ||
1029 | case 0x35: /* l.sw */ | |
1030 | LOG_DIS("l.sw %d, r%d, r%d, %d\n", I5, ra, rb, I11); | |
5631e69c RH |
1031 | mop = MO_TEUL; |
1032 | goto do_store; | |
bbe418f2 JL |
1033 | |
1034 | case 0x36: /* l.sb */ | |
1035 | LOG_DIS("l.sb %d, r%d, r%d, %d\n", I5, ra, rb, I11); | |
5631e69c RH |
1036 | mop = MO_UB; |
1037 | goto do_store; | |
bbe418f2 JL |
1038 | |
1039 | case 0x37: /* l.sh */ | |
1040 | LOG_DIS("l.sh %d, r%d, r%d, %d\n", I5, ra, rb, I11); | |
5631e69c RH |
1041 | mop = MO_TEUW; |
1042 | goto do_store; | |
1043 | ||
1044 | do_store: | |
bbe418f2 JL |
1045 | { |
1046 | TCGv t0 = tcg_temp_new(); | |
1047 | tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16)); | |
5631e69c | 1048 | tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc->mem_idx, mop); |
bbe418f2 JL |
1049 | tcg_temp_free(t0); |
1050 | } | |
1051 | break; | |
1052 | ||
1053 | default: | |
1054 | gen_illegal_exception(dc); | |
1055 | break; | |
1056 | } | |
1057 | } | |
1058 | ||
1059 | static void dec_mac(DisasContext *dc, uint32_t insn) | |
1060 | { | |
1061 | uint32_t op0; | |
1062 | uint32_t ra, rb; | |
1063 | op0 = extract32(insn, 0, 4); | |
1064 | ra = extract32(insn, 16, 5); | |
1065 | rb = extract32(insn, 11, 5); | |
1066 | ||
1067 | switch (op0) { | |
1068 | case 0x0001: /* l.mac */ | |
1069 | LOG_DIS("l.mac r%d, r%d\n", ra, rb); | |
1070 | { | |
1071 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1072 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1073 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1074 | tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]); | |
1075 | tcg_gen_ext_i32_i64(t1, t0); | |
1076 | tcg_gen_concat_i32_i64(t2, maclo, machi); | |
1077 | tcg_gen_add_i64(t2, t2, t1); | |
1078 | tcg_gen_trunc_i64_i32(maclo, t2); | |
1079 | tcg_gen_shri_i64(t2, t2, 32); | |
1080 | tcg_gen_trunc_i64_i32(machi, t2); | |
1081 | tcg_temp_free_i32(t0); | |
1082 | tcg_temp_free_i64(t1); | |
1083 | tcg_temp_free_i64(t2); | |
1084 | } | |
1085 | break; | |
1086 | ||
1087 | case 0x0002: /* l.msb */ | |
1088 | LOG_DIS("l.msb r%d, r%d\n", ra, rb); | |
1089 | { | |
1090 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1091 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1092 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1093 | tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]); | |
1094 | tcg_gen_ext_i32_i64(t1, t0); | |
1095 | tcg_gen_concat_i32_i64(t2, maclo, machi); | |
1096 | tcg_gen_sub_i64(t2, t2, t1); | |
1097 | tcg_gen_trunc_i64_i32(maclo, t2); | |
1098 | tcg_gen_shri_i64(t2, t2, 32); | |
1099 | tcg_gen_trunc_i64_i32(machi, t2); | |
1100 | tcg_temp_free_i32(t0); | |
1101 | tcg_temp_free_i64(t1); | |
1102 | tcg_temp_free_i64(t2); | |
1103 | } | |
1104 | break; | |
1105 | ||
1106 | default: | |
1107 | gen_illegal_exception(dc); | |
1108 | break; | |
1109 | } | |
1110 | } | |
1111 | ||
1112 | static void dec_logic(DisasContext *dc, uint32_t insn) | |
1113 | { | |
1114 | uint32_t op0; | |
1115 | uint32_t rd, ra, L6; | |
1116 | op0 = extract32(insn, 6, 2); | |
1117 | rd = extract32(insn, 21, 5); | |
1118 | ra = extract32(insn, 16, 5); | |
1119 | L6 = extract32(insn, 0, 6); | |
1120 | ||
1121 | switch (op0) { | |
1122 | case 0x00: /* l.slli */ | |
1123 | LOG_DIS("l.slli r%d, r%d, %d\n", rd, ra, L6); | |
1124 | tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f)); | |
1125 | break; | |
1126 | ||
1127 | case 0x01: /* l.srli */ | |
1128 | LOG_DIS("l.srli r%d, r%d, %d\n", rd, ra, L6); | |
1129 | tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f)); | |
1130 | break; | |
1131 | ||
1132 | case 0x02: /* l.srai */ | |
1133 | LOG_DIS("l.srai r%d, r%d, %d\n", rd, ra, L6); | |
1134 | tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f)); break; | |
1135 | ||
1136 | case 0x03: /* l.rori */ | |
1137 | LOG_DIS("l.rori r%d, r%d, %d\n", rd, ra, L6); | |
1138 | tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f)); | |
1139 | break; | |
1140 | ||
1141 | default: | |
1142 | gen_illegal_exception(dc); | |
1143 | break; | |
1144 | } | |
1145 | } | |
1146 | ||
1147 | static void dec_M(DisasContext *dc, uint32_t insn) | |
1148 | { | |
1149 | uint32_t op0; | |
1150 | uint32_t rd; | |
1151 | uint32_t K16; | |
1152 | op0 = extract32(insn, 16, 1); | |
1153 | rd = extract32(insn, 21, 5); | |
1154 | K16 = extract32(insn, 0, 16); | |
1155 | ||
1156 | switch (op0) { | |
1157 | case 0x0: /* l.movhi */ | |
1158 | LOG_DIS("l.movhi r%d, %d\n", rd, K16); | |
1159 | tcg_gen_movi_tl(cpu_R[rd], (K16 << 16)); | |
1160 | break; | |
1161 | ||
1162 | case 0x1: /* l.macrc */ | |
1163 | LOG_DIS("l.macrc r%d\n", rd); | |
1164 | tcg_gen_mov_tl(cpu_R[rd], maclo); | |
1165 | tcg_gen_movi_tl(maclo, 0x0); | |
1166 | tcg_gen_movi_tl(machi, 0x0); | |
1167 | break; | |
1168 | ||
1169 | default: | |
1170 | gen_illegal_exception(dc); | |
1171 | break; | |
1172 | } | |
1173 | } | |
1174 | ||
1175 | static void dec_comp(DisasContext *dc, uint32_t insn) | |
1176 | { | |
1177 | uint32_t op0; | |
1178 | uint32_t ra, rb; | |
1179 | ||
1180 | op0 = extract32(insn, 21, 5); | |
1181 | ra = extract32(insn, 16, 5); | |
1182 | rb = extract32(insn, 11, 5); | |
1183 | ||
1184 | tcg_gen_movi_i32(env_btaken, 0x0); | |
1185 | /* unsigned integers */ | |
1186 | tcg_gen_ext32u_tl(cpu_R[ra], cpu_R[ra]); | |
1187 | tcg_gen_ext32u_tl(cpu_R[rb], cpu_R[rb]); | |
1188 | ||
1189 | switch (op0) { | |
1190 | case 0x0: /* l.sfeq */ | |
1191 | LOG_DIS("l.sfeq r%d, r%d\n", ra, rb); | |
1192 | tcg_gen_setcond_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], cpu_R[rb]); | |
1193 | break; | |
1194 | ||
1195 | case 0x1: /* l.sfne */ | |
1196 | LOG_DIS("l.sfne r%d, r%d\n", ra, rb); | |
1197 | tcg_gen_setcond_tl(TCG_COND_NE, env_btaken, cpu_R[ra], cpu_R[rb]); | |
1198 | break; | |
1199 | ||
1200 | case 0x2: /* l.sfgtu */ | |
1201 | LOG_DIS("l.sfgtu r%d, r%d\n", ra, rb); | |
1202 | tcg_gen_setcond_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], cpu_R[rb]); | |
1203 | break; | |
1204 | ||
1205 | case 0x3: /* l.sfgeu */ | |
1206 | LOG_DIS("l.sfgeu r%d, r%d\n", ra, rb); | |
1207 | tcg_gen_setcond_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], cpu_R[rb]); | |
1208 | break; | |
1209 | ||
1210 | case 0x4: /* l.sfltu */ | |
1211 | LOG_DIS("l.sfltu r%d, r%d\n", ra, rb); | |
1212 | tcg_gen_setcond_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], cpu_R[rb]); | |
1213 | break; | |
1214 | ||
1215 | case 0x5: /* l.sfleu */ | |
1216 | LOG_DIS("l.sfleu r%d, r%d\n", ra, rb); | |
1217 | tcg_gen_setcond_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], cpu_R[rb]); | |
1218 | break; | |
1219 | ||
1220 | case 0xa: /* l.sfgts */ | |
1221 | LOG_DIS("l.sfgts r%d, r%d\n", ra, rb); | |
1222 | tcg_gen_setcond_tl(TCG_COND_GT, env_btaken, cpu_R[ra], cpu_R[rb]); | |
1223 | break; | |
1224 | ||
1225 | case 0xb: /* l.sfges */ | |
1226 | LOG_DIS("l.sfges r%d, r%d\n", ra, rb); | |
1227 | tcg_gen_setcond_tl(TCG_COND_GE, env_btaken, cpu_R[ra], cpu_R[rb]); | |
1228 | break; | |
1229 | ||
1230 | case 0xc: /* l.sflts */ | |
1231 | LOG_DIS("l.sflts r%d, r%d\n", ra, rb); | |
1232 | tcg_gen_setcond_tl(TCG_COND_LT, env_btaken, cpu_R[ra], cpu_R[rb]); | |
1233 | break; | |
1234 | ||
1235 | case 0xd: /* l.sfles */ | |
1236 | LOG_DIS("l.sfles r%d, r%d\n", ra, rb); | |
1237 | tcg_gen_setcond_tl(TCG_COND_LE, env_btaken, cpu_R[ra], cpu_R[rb]); | |
1238 | break; | |
1239 | ||
1240 | default: | |
1241 | gen_illegal_exception(dc); | |
1242 | break; | |
1243 | } | |
1244 | wb_SR_F(); | |
1245 | } | |
1246 | ||
1247 | static void dec_compi(DisasContext *dc, uint32_t insn) | |
1248 | { | |
1249 | uint32_t op0; | |
1250 | uint32_t ra, I16; | |
1251 | ||
1252 | op0 = extract32(insn, 21, 5); | |
1253 | ra = extract32(insn, 16, 5); | |
1254 | I16 = extract32(insn, 0, 16); | |
1255 | ||
1256 | tcg_gen_movi_i32(env_btaken, 0x0); | |
1257 | I16 = sign_extend(I16, 16); | |
1258 | ||
1259 | switch (op0) { | |
1260 | case 0x0: /* l.sfeqi */ | |
1261 | LOG_DIS("l.sfeqi r%d, %d\n", ra, I16); | |
1262 | tcg_gen_setcondi_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], I16); | |
1263 | break; | |
1264 | ||
1265 | case 0x1: /* l.sfnei */ | |
1266 | LOG_DIS("l.sfnei r%d, %d\n", ra, I16); | |
1267 | tcg_gen_setcondi_tl(TCG_COND_NE, env_btaken, cpu_R[ra], I16); | |
1268 | break; | |
1269 | ||
1270 | case 0x2: /* l.sfgtui */ | |
1271 | LOG_DIS("l.sfgtui r%d, %d\n", ra, I16); | |
1272 | tcg_gen_setcondi_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], I16); | |
1273 | break; | |
1274 | ||
1275 | case 0x3: /* l.sfgeui */ | |
1276 | LOG_DIS("l.sfgeui r%d, %d\n", ra, I16); | |
1277 | tcg_gen_setcondi_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], I16); | |
1278 | break; | |
1279 | ||
1280 | case 0x4: /* l.sfltui */ | |
1281 | LOG_DIS("l.sfltui r%d, %d\n", ra, I16); | |
1282 | tcg_gen_setcondi_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], I16); | |
1283 | break; | |
1284 | ||
1285 | case 0x5: /* l.sfleui */ | |
1286 | LOG_DIS("l.sfleui r%d, %d\n", ra, I16); | |
1287 | tcg_gen_setcondi_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], I16); | |
1288 | break; | |
1289 | ||
1290 | case 0xa: /* l.sfgtsi */ | |
1291 | LOG_DIS("l.sfgtsi r%d, %d\n", ra, I16); | |
1292 | tcg_gen_setcondi_tl(TCG_COND_GT, env_btaken, cpu_R[ra], I16); | |
1293 | break; | |
1294 | ||
1295 | case 0xb: /* l.sfgesi */ | |
1296 | LOG_DIS("l.sfgesi r%d, %d\n", ra, I16); | |
1297 | tcg_gen_setcondi_tl(TCG_COND_GE, env_btaken, cpu_R[ra], I16); | |
1298 | break; | |
1299 | ||
1300 | case 0xc: /* l.sfltsi */ | |
1301 | LOG_DIS("l.sfltsi r%d, %d\n", ra, I16); | |
1302 | tcg_gen_setcondi_tl(TCG_COND_LT, env_btaken, cpu_R[ra], I16); | |
1303 | break; | |
1304 | ||
1305 | case 0xd: /* l.sflesi */ | |
1306 | LOG_DIS("l.sflesi r%d, %d\n", ra, I16); | |
1307 | tcg_gen_setcondi_tl(TCG_COND_LE, env_btaken, cpu_R[ra], I16); | |
1308 | break; | |
1309 | ||
1310 | default: | |
1311 | gen_illegal_exception(dc); | |
1312 | break; | |
1313 | } | |
1314 | wb_SR_F(); | |
1315 | } | |
1316 | ||
1317 | static void dec_sys(DisasContext *dc, uint32_t insn) | |
1318 | { | |
1319 | uint32_t op0; | |
1320 | #ifdef OPENRISC_DISAS | |
1321 | uint32_t K16; | |
1322 | #endif | |
1323 | op0 = extract32(insn, 16, 8); | |
1324 | #ifdef OPENRISC_DISAS | |
1325 | K16 = extract32(insn, 0, 16); | |
1326 | #endif | |
1327 | ||
1328 | switch (op0) { | |
1329 | case 0x000: /* l.sys */ | |
1330 | LOG_DIS("l.sys %d\n", K16); | |
1331 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
1332 | gen_exception(dc, EXCP_SYSCALL); | |
1333 | dc->is_jmp = DISAS_UPDATE; | |
1334 | break; | |
1335 | ||
1336 | case 0x100: /* l.trap */ | |
1337 | LOG_DIS("l.trap %d\n", K16); | |
1338 | #if defined(CONFIG_USER_ONLY) | |
1339 | return; | |
1340 | #else | |
1341 | if (dc->mem_idx == MMU_USER_IDX) { | |
1342 | gen_illegal_exception(dc); | |
1343 | return; | |
1344 | } | |
1345 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
1346 | gen_exception(dc, EXCP_TRAP); | |
1347 | #endif | |
1348 | break; | |
1349 | ||
1350 | case 0x300: /* l.csync */ | |
1351 | LOG_DIS("l.csync\n"); | |
1352 | #if defined(CONFIG_USER_ONLY) | |
1353 | return; | |
1354 | #else | |
1355 | if (dc->mem_idx == MMU_USER_IDX) { | |
1356 | gen_illegal_exception(dc); | |
1357 | return; | |
1358 | } | |
1359 | #endif | |
1360 | break; | |
1361 | ||
1362 | case 0x200: /* l.msync */ | |
1363 | LOG_DIS("l.msync\n"); | |
1364 | #if defined(CONFIG_USER_ONLY) | |
1365 | return; | |
1366 | #else | |
1367 | if (dc->mem_idx == MMU_USER_IDX) { | |
1368 | gen_illegal_exception(dc); | |
1369 | return; | |
1370 | } | |
1371 | #endif | |
1372 | break; | |
1373 | ||
1374 | case 0x270: /* l.psync */ | |
1375 | LOG_DIS("l.psync\n"); | |
1376 | #if defined(CONFIG_USER_ONLY) | |
1377 | return; | |
1378 | #else | |
1379 | if (dc->mem_idx == MMU_USER_IDX) { | |
1380 | gen_illegal_exception(dc); | |
1381 | return; | |
1382 | } | |
1383 | #endif | |
1384 | break; | |
1385 | ||
1386 | default: | |
1387 | gen_illegal_exception(dc); | |
1388 | break; | |
1389 | } | |
1390 | } | |
1391 | ||
1392 | static void dec_float(DisasContext *dc, uint32_t insn) | |
1393 | { | |
1394 | uint32_t op0; | |
1395 | uint32_t ra, rb, rd; | |
1396 | op0 = extract32(insn, 0, 8); | |
1397 | ra = extract32(insn, 16, 5); | |
1398 | rb = extract32(insn, 11, 5); | |
1399 | rd = extract32(insn, 21, 5); | |
1400 | ||
1401 | switch (op0) { | |
1402 | case 0x00: /* lf.add.s */ | |
1403 | LOG_DIS("lf.add.s r%d, r%d, r%d\n", rd, ra, rb); | |
1404 | gen_helper_float_add_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1405 | break; | |
1406 | ||
1407 | case 0x01: /* lf.sub.s */ | |
1408 | LOG_DIS("lf.sub.s r%d, r%d, r%d\n", rd, ra, rb); | |
1409 | gen_helper_float_sub_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1410 | break; | |
1411 | ||
1412 | ||
1413 | case 0x02: /* lf.mul.s */ | |
1414 | LOG_DIS("lf.mul.s r%d, r%d, r%d\n", rd, ra, rb); | |
1415 | if (ra != 0 && rb != 0) { | |
1416 | gen_helper_float_mul_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1417 | } else { | |
1418 | tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF); | |
1419 | tcg_gen_movi_i32(cpu_R[rd], 0x0); | |
1420 | } | |
1421 | break; | |
1422 | ||
1423 | case 0x03: /* lf.div.s */ | |
1424 | LOG_DIS("lf.div.s r%d, r%d, r%d\n", rd, ra, rb); | |
1425 | gen_helper_float_div_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1426 | break; | |
1427 | ||
1428 | case 0x04: /* lf.itof.s */ | |
1429 | LOG_DIS("lf.itof r%d, r%d\n", rd, ra); | |
1430 | gen_helper_itofs(cpu_R[rd], cpu_env, cpu_R[ra]); | |
1431 | break; | |
1432 | ||
1433 | case 0x05: /* lf.ftoi.s */ | |
1434 | LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra); | |
1435 | gen_helper_ftois(cpu_R[rd], cpu_env, cpu_R[ra]); | |
1436 | break; | |
1437 | ||
1438 | case 0x06: /* lf.rem.s */ | |
1439 | LOG_DIS("lf.rem.s r%d, r%d, r%d\n", rd, ra, rb); | |
1440 | gen_helper_float_rem_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1441 | break; | |
1442 | ||
1443 | case 0x07: /* lf.madd.s */ | |
1444 | LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd, ra, rb); | |
1445 | gen_helper_float_muladd_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1446 | break; | |
1447 | ||
1448 | case 0x08: /* lf.sfeq.s */ | |
1449 | LOG_DIS("lf.sfeq.s r%d, r%d\n", ra, rb); | |
1450 | gen_helper_float_eq_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); | |
1451 | break; | |
1452 | ||
1453 | case 0x09: /* lf.sfne.s */ | |
1454 | LOG_DIS("lf.sfne.s r%d, r%d\n", ra, rb); | |
1455 | gen_helper_float_ne_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); | |
1456 | break; | |
1457 | ||
1458 | case 0x0a: /* lf.sfgt.s */ | |
1459 | LOG_DIS("lf.sfgt.s r%d, r%d\n", ra, rb); | |
1460 | gen_helper_float_gt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); | |
1461 | break; | |
1462 | ||
1463 | case 0x0b: /* lf.sfge.s */ | |
1464 | LOG_DIS("lf.sfge.s r%d, r%d\n", ra, rb); | |
1465 | gen_helper_float_ge_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); | |
1466 | break; | |
1467 | ||
1468 | case 0x0c: /* lf.sflt.s */ | |
1469 | LOG_DIS("lf.sflt.s r%d, r%d\n", ra, rb); | |
1470 | gen_helper_float_lt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); | |
1471 | break; | |
1472 | ||
1473 | case 0x0d: /* lf.sfle.s */ | |
1474 | LOG_DIS("lf.sfle.s r%d, r%d\n", ra, rb); | |
1475 | gen_helper_float_le_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); | |
1476 | break; | |
1477 | ||
1478 | /* not used yet, open it when we need or64. */ | |
1479 | /*#ifdef TARGET_OPENRISC64 | |
1480 | case 0x10: lf.add.d | |
1481 | LOG_DIS("lf.add.d r%d, r%d, r%d\n", rd, ra, rb); | |
1482 | check_of64s(dc); | |
1483 | gen_helper_float_add_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1484 | break; | |
1485 | ||
1486 | case 0x11: lf.sub.d | |
1487 | LOG_DIS("lf.sub.d r%d, r%d, r%d\n", rd, ra, rb); | |
1488 | check_of64s(dc); | |
1489 | gen_helper_float_sub_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1490 | break; | |
1491 | ||
1492 | case 0x12: lf.mul.d | |
1493 | LOG_DIS("lf.mul.d r%d, r%d, r%d\n", rd, ra, rb); | |
1494 | check_of64s(dc); | |
1495 | if (ra != 0 && rb != 0) { | |
1496 | gen_helper_float_mul_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1497 | } else { | |
1498 | tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF); | |
1499 | tcg_gen_movi_i64(cpu_R[rd], 0x0); | |
1500 | } | |
1501 | break; | |
1502 | ||
1503 | case 0x13: lf.div.d | |
1504 | LOG_DIS("lf.div.d r%d, r%d, r%d\n", rd, ra, rb); | |
1505 | check_of64s(dc); | |
1506 | gen_helper_float_div_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1507 | break; | |
1508 | ||
1509 | case 0x14: lf.itof.d | |
1510 | LOG_DIS("lf.itof r%d, r%d\n", rd, ra); | |
1511 | check_of64s(dc); | |
1512 | gen_helper_itofd(cpu_R[rd], cpu_env, cpu_R[ra]); | |
1513 | break; | |
1514 | ||
1515 | case 0x15: lf.ftoi.d | |
1516 | LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra); | |
1517 | check_of64s(dc); | |
1518 | gen_helper_ftoid(cpu_R[rd], cpu_env, cpu_R[ra]); | |
1519 | break; | |
1520 | ||
1521 | case 0x16: lf.rem.d | |
1522 | LOG_DIS("lf.rem.d r%d, r%d, r%d\n", rd, ra, rb); | |
1523 | check_of64s(dc); | |
1524 | gen_helper_float_rem_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1525 | break; | |
1526 | ||
1527 | case 0x17: lf.madd.d | |
1528 | LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb); | |
1529 | check_of64s(dc); | |
1530 | gen_helper_float_muladd_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1531 | break; | |
1532 | ||
1533 | case 0x18: lf.sfeq.d | |
1534 | LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb); | |
1535 | check_of64s(dc); | |
1536 | gen_helper_float_eq_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); | |
1537 | break; | |
1538 | ||
1539 | case 0x1a: lf.sfgt.d | |
1540 | LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb); | |
1541 | check_of64s(dc); | |
1542 | gen_helper_float_gt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); | |
1543 | break; | |
1544 | ||
1545 | case 0x1b: lf.sfge.d | |
1546 | LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb); | |
1547 | check_of64s(dc); | |
1548 | gen_helper_float_ge_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); | |
1549 | break; | |
1550 | ||
1551 | case 0x19: lf.sfne.d | |
1552 | LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb); | |
1553 | check_of64s(dc); | |
1554 | gen_helper_float_ne_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); | |
1555 | break; | |
1556 | ||
1557 | case 0x1c: lf.sflt.d | |
1558 | LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb); | |
1559 | check_of64s(dc); | |
1560 | gen_helper_float_lt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); | |
1561 | break; | |
1562 | ||
1563 | case 0x1d: lf.sfle.d | |
1564 | LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb); | |
1565 | check_of64s(dc); | |
1566 | gen_helper_float_le_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]); | |
1567 | break; | |
1568 | #endif*/ | |
1569 | ||
1570 | default: | |
1571 | gen_illegal_exception(dc); | |
1572 | break; | |
1573 | } | |
1574 | wb_SR_F(); | |
1575 | } | |
1576 | ||
1577 | static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) | |
1578 | { | |
1579 | uint32_t op0; | |
1580 | uint32_t insn; | |
1581 | insn = cpu_ldl_code(&cpu->env, dc->pc); | |
1582 | op0 = extract32(insn, 26, 6); | |
1583 | ||
1584 | switch (op0) { | |
1585 | case 0x06: | |
1586 | dec_M(dc, insn); | |
1587 | break; | |
1588 | ||
1589 | case 0x08: | |
1590 | dec_sys(dc, insn); | |
1591 | break; | |
1592 | ||
1593 | case 0x2e: | |
1594 | dec_logic(dc, insn); | |
1595 | break; | |
1596 | ||
1597 | case 0x2f: | |
1598 | dec_compi(dc, insn); | |
1599 | break; | |
1600 | ||
1601 | case 0x31: | |
1602 | dec_mac(dc, insn); | |
1603 | break; | |
1604 | ||
1605 | case 0x32: | |
1606 | dec_float(dc, insn); | |
1607 | break; | |
1608 | ||
1609 | case 0x38: | |
1610 | dec_calc(dc, insn); | |
1611 | break; | |
1612 | ||
1613 | case 0x39: | |
1614 | dec_comp(dc, insn); | |
1615 | break; | |
1616 | ||
1617 | default: | |
1618 | dec_misc(dc, insn); | |
1619 | break; | |
1620 | } | |
1621 | } | |
1622 | ||
1623 | static void check_breakpoint(OpenRISCCPU *cpu, DisasContext *dc) | |
1624 | { | |
f0c3c505 | 1625 | CPUState *cs = CPU(cpu); |
bbe418f2 JL |
1626 | CPUBreakpoint *bp; |
1627 | ||
f0c3c505 AF |
1628 | if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { |
1629 | QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { | |
bbe418f2 JL |
1630 | if (bp->pc == dc->pc) { |
1631 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
1632 | gen_exception(dc, EXCP_DEBUG); | |
1633 | dc->is_jmp = DISAS_UPDATE; | |
1634 | } | |
1635 | } | |
1636 | } | |
e67db06e JL |
1637 | } |
1638 | ||
1639 | static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu, | |
1640 | TranslationBlock *tb, | |
1641 | int search_pc) | |
1642 | { | |
ed2803da | 1643 | CPUState *cs = CPU(cpu); |
bbe418f2 JL |
1644 | struct DisasContext ctx, *dc = &ctx; |
1645 | uint16_t *gen_opc_end; | |
1646 | uint32_t pc_start; | |
1647 | int j, k; | |
1648 | uint32_t next_page_start; | |
1649 | int num_insns; | |
1650 | int max_insns; | |
1651 | ||
bbe418f2 JL |
1652 | pc_start = tb->pc; |
1653 | dc->tb = tb; | |
1654 | ||
92414b31 | 1655 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
bbe418f2 JL |
1656 | dc->is_jmp = DISAS_NEXT; |
1657 | dc->ppc = pc_start; | |
1658 | dc->pc = pc_start; | |
1659 | dc->flags = cpu->env.cpucfgr; | |
1660 | dc->mem_idx = cpu_mmu_index(&cpu->env); | |
1661 | dc->synced_flags = dc->tb_flags = tb->flags; | |
1662 | dc->delayed_branch = !!(dc->tb_flags & D_FLAG); | |
ed2803da | 1663 | dc->singlestep_enabled = cs->singlestep_enabled; |
bbe418f2 JL |
1664 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
1665 | qemu_log("-----------------------------------------\n"); | |
a0762859 | 1666 | log_cpu_state(CPU(cpu), 0); |
bbe418f2 JL |
1667 | } |
1668 | ||
1669 | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; | |
1670 | k = -1; | |
1671 | num_insns = 0; | |
1672 | max_insns = tb->cflags & CF_COUNT_MASK; | |
1673 | ||
1674 | if (max_insns == 0) { | |
1675 | max_insns = CF_COUNT_MASK; | |
1676 | } | |
1677 | ||
cd42d5b2 | 1678 | gen_tb_start(tb); |
bbe418f2 JL |
1679 | |
1680 | do { | |
1681 | check_breakpoint(cpu, dc); | |
1682 | if (search_pc) { | |
92414b31 | 1683 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
bbe418f2 JL |
1684 | if (k < j) { |
1685 | k++; | |
1686 | while (k < j) { | |
ab1103de | 1687 | tcg_ctx.gen_opc_instr_start[k++] = 0; |
bbe418f2 JL |
1688 | } |
1689 | } | |
25983cad | 1690 | tcg_ctx.gen_opc_pc[k] = dc->pc; |
ab1103de | 1691 | tcg_ctx.gen_opc_instr_start[k] = 1; |
c9c99c22 | 1692 | tcg_ctx.gen_opc_icount[k] = num_insns; |
bbe418f2 JL |
1693 | } |
1694 | ||
fdefe51c | 1695 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
bbe418f2 JL |
1696 | tcg_gen_debug_insn_start(dc->pc); |
1697 | } | |
1698 | ||
1699 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { | |
1700 | gen_io_start(); | |
1701 | } | |
1702 | dc->ppc = dc->pc - 4; | |
1703 | dc->npc = dc->pc + 4; | |
1704 | tcg_gen_movi_tl(cpu_ppc, dc->ppc); | |
1705 | tcg_gen_movi_tl(cpu_npc, dc->npc); | |
1706 | disas_openrisc_insn(dc, cpu); | |
1707 | dc->pc = dc->npc; | |
1708 | num_insns++; | |
1709 | /* delay slot */ | |
1710 | if (dc->delayed_branch) { | |
1711 | dc->delayed_branch--; | |
1712 | if (!dc->delayed_branch) { | |
1713 | dc->tb_flags &= ~D_FLAG; | |
1714 | gen_sync_flags(dc); | |
1715 | tcg_gen_mov_tl(cpu_pc, jmp_pc); | |
1716 | tcg_gen_mov_tl(cpu_npc, jmp_pc); | |
1717 | tcg_gen_movi_tl(jmp_pc, 0); | |
1718 | tcg_gen_exit_tb(0); | |
1719 | dc->is_jmp = DISAS_JUMP; | |
1720 | break; | |
1721 | } | |
1722 | } | |
1723 | } while (!dc->is_jmp | |
efd7f486 | 1724 | && tcg_ctx.gen_opc_ptr < gen_opc_end |
ed2803da | 1725 | && !cs->singlestep_enabled |
bbe418f2 JL |
1726 | && !singlestep |
1727 | && (dc->pc < next_page_start) | |
1728 | && num_insns < max_insns); | |
1729 | ||
1730 | if (tb->cflags & CF_LAST_IO) { | |
1731 | gen_io_end(); | |
1732 | } | |
1733 | if (dc->is_jmp == DISAS_NEXT) { | |
1734 | dc->is_jmp = DISAS_UPDATE; | |
1735 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
1736 | } | |
ed2803da | 1737 | if (unlikely(cs->singlestep_enabled)) { |
bbe418f2 JL |
1738 | if (dc->is_jmp == DISAS_NEXT) { |
1739 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
1740 | } | |
1741 | gen_exception(dc, EXCP_DEBUG); | |
1742 | } else { | |
1743 | switch (dc->is_jmp) { | |
1744 | case DISAS_NEXT: | |
1745 | gen_goto_tb(dc, 0, dc->pc); | |
1746 | break; | |
1747 | default: | |
1748 | case DISAS_JUMP: | |
1749 | break; | |
1750 | case DISAS_UPDATE: | |
1751 | /* indicate that the hash table must be used | |
1752 | to find the next TB */ | |
1753 | tcg_gen_exit_tb(0); | |
1754 | break; | |
1755 | case DISAS_TB_JUMP: | |
1756 | /* nothing more to generate */ | |
1757 | break; | |
1758 | } | |
1759 | } | |
1760 | ||
806f352d | 1761 | gen_tb_end(tb, num_insns); |
efd7f486 | 1762 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
bbe418f2 | 1763 | if (search_pc) { |
92414b31 | 1764 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
bbe418f2 JL |
1765 | k++; |
1766 | while (k <= j) { | |
ab1103de | 1767 | tcg_ctx.gen_opc_instr_start[k++] = 0; |
bbe418f2 JL |
1768 | } |
1769 | } else { | |
1770 | tb->size = dc->pc - pc_start; | |
1771 | tb->icount = num_insns; | |
1772 | } | |
1773 | ||
1774 | #ifdef DEBUG_DISAS | |
1775 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { | |
1776 | qemu_log("\n"); | |
f4359b9f | 1777 | log_target_disas(&cpu->env, pc_start, dc->pc - pc_start, 0); |
bbe418f2 | 1778 | qemu_log("\nisize=%d osize=%td\n", |
92414b31 EV |
1779 | dc->pc - pc_start, tcg_ctx.gen_opc_ptr - |
1780 | tcg_ctx.gen_opc_buf); | |
bbe418f2 JL |
1781 | } |
1782 | #endif | |
e67db06e JL |
1783 | } |
1784 | ||
1785 | void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb) | |
1786 | { | |
1787 | gen_intermediate_code_internal(openrisc_env_get_cpu(env), tb, 0); | |
1788 | } | |
1789 | ||
1790 | void gen_intermediate_code_pc(CPUOpenRISCState *env, | |
1791 | struct TranslationBlock *tb) | |
1792 | { | |
1793 | gen_intermediate_code_internal(openrisc_env_get_cpu(env), tb, 1); | |
1794 | } | |
1795 | ||
878096ee AF |
1796 | void openrisc_cpu_dump_state(CPUState *cs, FILE *f, |
1797 | fprintf_function cpu_fprintf, | |
1798 | int flags) | |
e67db06e | 1799 | { |
878096ee AF |
1800 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); |
1801 | CPUOpenRISCState *env = &cpu->env; | |
e67db06e | 1802 | int i; |
878096ee | 1803 | |
e67db06e JL |
1804 | cpu_fprintf(f, "PC=%08x\n", env->pc); |
1805 | for (i = 0; i < 32; ++i) { | |
878096ee | 1806 | cpu_fprintf(f, "R%02d=%08x%c", i, env->gpr[i], |
e67db06e JL |
1807 | (i % 4) == 3 ? '\n' : ' '); |
1808 | } | |
1809 | } | |
1810 | ||
1811 | void restore_state_to_opc(CPUOpenRISCState *env, TranslationBlock *tb, | |
1812 | int pc_pos) | |
1813 | { | |
25983cad | 1814 | env->pc = tcg_ctx.gen_opc_pc[pc_pos]; |
e67db06e | 1815 | } |