[qemu.git] / hw / pci-host / ppce500.c

/*
 * QEMU PowerPC E500 embedded processors pci controller emulation
 *
 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
 *
 * Author: Yu Liu,     <[email protected]>
 *
 * This file is derived from hw/ppc4xx_pci.c,
 * the copyright for that material belongs to the original owners.
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of  the GNU General  Public License as published by
 * the Free Software Foundation;  either version 2 of the  License, or
 * (at your option) any later version.
 */

#include "hw/hw.h"
#include "hw/ppc/e500-ccsr.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "qemu/bswap.h"
#include "hw/pci-host/ppce500.h"

#ifdef DEBUG_PCI
#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
#else
#define pci_debug(fmt, ...)
#endif

#define PCIE500_CFGADDR       0x0
#define PCIE500_CFGDATA       0x4
#define PCIE500_REG_BASE      0xC00
#define PCIE500_ALL_SIZE      0x1000
#define PCIE500_REG_SIZE      (PCIE500_ALL_SIZE - PCIE500_REG_BASE)

#define PCIE500_PCI_IOLEN     0x10000ULL

#define PPCE500_PCI_CONFIG_ADDR         0x0
#define PPCE500_PCI_CONFIG_DATA         0x4
#define PPCE500_PCI_INTACK              0x8

#define PPCE500_PCI_OW1                 (0xC20 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW2                 (0xC40 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW3                 (0xC60 - PCIE500_REG_BASE)
#define PPCE500_PCI_OW4                 (0xC80 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW3                 (0xDA0 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW2                 (0xDC0 - PCIE500_REG_BASE)
#define PPCE500_PCI_IW1                 (0xDE0 - PCIE500_REG_BASE)

#define PPCE500_PCI_GASKET_TIMR         (0xE20 - PCIE500_REG_BASE)

#define PCI_POTAR               0x0
#define PCI_POTEAR              0x4
#define PCI_POWBAR              0x8
#define PCI_POWAR               0x10

#define PCI_PITAR               0x0
#define PCI_PIWBAR              0x8
#define PCI_PIWBEAR             0xC
#define PCI_PIWAR               0x10

#define PPCE500_PCI_NR_POBS     5
#define PPCE500_PCI_NR_PIBS     3

struct  pci_outbound {
    uint32_t potar;
    uint32_t potear;
    uint32_t powbar;
    uint32_t powar;
};

struct pci_inbound {
    uint32_t pitar;
    uint32_t piwbar;
    uint32_t piwbear;
    uint32_t piwar;
};

#define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"

#define PPC_E500_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE)

struct PPCE500PCIState {
    PCIHostState parent_obj;

    struct pci_outbound pob[PPCE500_PCI_NR_POBS];
    struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
    uint32_t gasket_time;
    qemu_irq irq[PCI_NUM_PINS];
    uint32_t irq_num[PCI_NUM_PINS];
    uint32_t first_slot;
    uint32_t first_pin_irq;
    /* mmio maps */
    MemoryRegion container;
    MemoryRegion iomem;
    MemoryRegion pio;
};

#define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge"
#define PPC_E500_PCI_BRIDGE(obj) \
    OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE)

struct PPCE500PCIBridgeState {
    /*< private >*/
    PCIDevice parent;
    /*< public >*/

    MemoryRegion bar0;
};

typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState;
typedef struct PPCE500PCIState PPCE500PCIState;

static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
                              unsigned size)
{
    PPCE500PCIState *pci = opaque;
    unsigned long win;
    uint32_t value = 0;
    int idx;

    win = addr & 0xfe0;

    switch (win) {
    case PPCE500_PCI_OW1:
    case PPCE500_PCI_OW2:
    case PPCE500_PCI_OW3:
    case PPCE500_PCI_OW4:
        idx = (addr >> 5) & 0x7;
        switch (addr & 0xC) {
        case PCI_POTAR:
            value = pci->pob[idx].potar;
            break;
        case PCI_POTEAR:
            value = pci->pob[idx].potear;
            break;
        case PCI_POWBAR:
            value = pci->pob[idx].powbar;
            break;
        case PCI_POWAR:
            value = pci->pob[idx].powar;
            break;
        default:
            break;
        }
        break;

    case PPCE500_PCI_IW3:
    case PPCE500_PCI_IW2:
    case PPCE500_PCI_IW1:
        idx = ((addr >> 5) & 0x3) - 1;
        switch (addr & 0xC) {
        case PCI_PITAR:
            value = pci->pib[idx].pitar;
            break;
        case PCI_PIWBAR:
            value = pci->pib[idx].piwbar;
            break;
        case PCI_PIWBEAR:
            value = pci->pib[idx].piwbear;
            break;
        case PCI_PIWAR:
            value = pci->pib[idx].piwar;
            break;
        default:
            break;
        };
        break;

    case PPCE500_PCI_GASKET_TIMR:
        value = pci->gasket_time;
        break;

    default:
        break;
    }

    pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
              win, addr, value);
    return value;
}

static void pci_reg_write4(void *opaque, hwaddr addr,
                           uint64_t value, unsigned size)
{
    PPCE500PCIState *pci = opaque;
    unsigned long win;
    int idx;

    win = addr & 0xfe0;

    pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
              __func__, (unsigned)value, win, addr);

    switch (win) {
    case PPCE500_PCI_OW1:
    case PPCE500_PCI_OW2:
    case PPCE500_PCI_OW3:
    case PPCE500_PCI_OW4:
        idx = (addr >> 5) & 0x7;
        switch (addr & 0xC) {
        case PCI_POTAR:
            pci->pob[idx].potar = value;
            break;
        case PCI_POTEAR:
            pci->pob[idx].potear = value;
            break;
        case PCI_POWBAR:
            pci->pob[idx].powbar = value;
            break;
        case PCI_POWAR:
            pci->pob[idx].powar = value;
            break;
        default:
            break;
        };
        break;

    case PPCE500_PCI_IW3:
    case PPCE500_PCI_IW2:
    case PPCE500_PCI_IW1:
        idx = ((addr >> 5) & 0x3) - 1;
        switch (addr & 0xC) {
        case PCI_PITAR:
            pci->pib[idx].pitar = value;
            break;
        case PCI_PIWBAR:
            pci->pib[idx].piwbar = value;
            break;
        case PCI_PIWBEAR:
            pci->pib[idx].piwbear = value;
            break;
        case PCI_PIWAR:
            pci->pib[idx].piwar = value;
            break;
        default:
            break;
        };
        break;

    case PPCE500_PCI_GASKET_TIMR:
        pci->gasket_time = value;
        break;

    default:
        break;
    };
}

static const MemoryRegionOps e500_pci_reg_ops = {
    .read = pci_reg_read4,
    .write = pci_reg_write4,
    .endianness = DEVICE_BIG_ENDIAN,
};

static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin)
{
    int devno = pci_dev->devfn >> 3;
    int ret;

    ret = ppce500_pci_map_irq_slot(devno, pin);

    pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
           pci_dev->devfn, pin, ret, devno);

    return ret;
}

static void mpc85xx_pci_set_irq(void *opaque, int pin, int level)
{
    PPCE500PCIState *s = opaque;
    qemu_irq *pic = s->irq;

    pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level);

    qemu_set_irq(pic[pin], level);
}

static PCIINTxRoute e500_route_intx_pin_to_irq(void *opaque, int pin)
{
    PCIINTxRoute route;
    PPCE500PCIState *s = opaque;

    route.mode = PCI_INTX_ENABLED;
    route.irq = s->irq_num[pin];

    pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq);
    return route;
}

static const VMStateDescription vmstate_pci_outbound = {
    .name = "pci_outbound",
    .version_id = 0,
    .minimum_version_id = 0,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(potar, struct pci_outbound),
        VMSTATE_UINT32(potear, struct pci_outbound),
        VMSTATE_UINT32(powbar, struct pci_outbound),
        VMSTATE_UINT32(powar, struct pci_outbound),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pci_inbound = {
    .name = "pci_inbound",
    .version_id = 0,
    .minimum_version_id = 0,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(pitar, struct pci_inbound),
        VMSTATE_UINT32(piwbar, struct pci_inbound),
        VMSTATE_UINT32(piwbear, struct pci_inbound),
        VMSTATE_UINT32(piwar, struct pci_inbound),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_ppce500_pci = {
    .name = "ppce500_pci",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
                             vmstate_pci_outbound, struct pci_outbound),
        VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
                             vmstate_pci_inbound, struct pci_inbound),
        VMSTATE_UINT32(gasket_time, PPCE500PCIState),
        VMSTATE_END_OF_LIST()
    }
};

#include "exec/address-spaces.h"

static int e500_pcihost_bridge_initfn(PCIDevice *d)
{
    PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d);
    PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(),
                                  "/e500-ccsr"));

    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
    d->config[PCI_HEADER_TYPE] =
        (d->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
        PCI_HEADER_TYPE_BRIDGE;

    memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space,
                             0, int128_get64(ccsr->ccsr_space.size));
    pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);

    return 0;
}

static int e500_pcihost_initfn(SysBusDevice *dev)
{
    PCIHostState *h;
    PPCE500PCIState *s;
    PCIBus *b;
    int i;
    MemoryRegion *address_space_mem = get_system_memory();

    h = PCI_HOST_BRIDGE(dev);
    s = PPC_E500_PCI_HOST_BRIDGE(dev);

    for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
        sysbus_init_irq(dev, &s->irq[i]);
    }

    for (i = 0; i < PCI_NUM_PINS; i++) {
        s->irq_num[i] = s->first_pin_irq + i;
    }

    memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN);

    b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
                         mpc85xx_pci_map_irq, s, address_space_mem,
                         &s->pio, PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS);
    h->bus = b;

    pci_create_simple(b, 0, "e500-host-bridge");

    memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE);
    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h,
                          "pci-conf-idx", 4);
    memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, h,
                          "pci-conf-data", 4);
    memory_region_init_io(&s->iomem, OBJECT(s), &e500_pci_reg_ops, s,
                          "pci.reg", PCIE500_REG_SIZE);
    memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
    memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
    memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
    sysbus_init_mmio(dev, &s->container);
    sysbus_init_mmio(dev, &s->pio);
    pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq);

    return 0;
}

static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = e500_pcihost_bridge_initfn;
    k->vendor_id = PCI_VENDOR_ID_FREESCALE;
    k->device_id = PCI_DEVICE_ID_MPC8533E;
    k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
    dc->desc = "Host bridge";
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo e500_host_bridge_info = {
    .name          = "e500-host-bridge",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PPCE500PCIBridgeState),
    .class_init    = e500_host_bridge_class_init,
};

static Property pcihost_properties[] = {
    DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11),
    DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1),
    DEFINE_PROP_END_OF_LIST(),
};

static void e500_pcihost_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = e500_pcihost_initfn;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
    dc->props = pcihost_properties;
    dc->vmsd = &vmstate_ppce500_pci;
}

static const TypeInfo e500_pcihost_info = {
    .name          = TYPE_PPC_E500_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(PPCE500PCIState),
    .class_init    = e500_pcihost_class_init,
};

static void e500_pci_register_types(void)
{
    type_register_static(&e500_pcihost_info);
    type_register_static(&e500_host_bridge_info);
}

type_init(e500_pci_register_types)
Commit	Line	Data
74c62ba8 AJ	1	/*
	2	* QEMU PowerPC E500 embedded processors pci controller emulation
	3	*
	4	* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
	5	*
	6	* Author: Yu Liu, <[email protected]>
	7	*
	8	* This file is derived from hw/ppc4xx_pci.c,
	9	* the copyright for that material belongs to the original owners.
	10	*
	11	* This is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*/
	16
83c9f4ca	17	#include "hw/hw.h"
3eddc1be	18	#include "hw/ppc/e500-ccsr.h"
83c9f4ca PB	19	#include "hw/pci/pci.h"
83c9f4ca PB	20	#include "hw/pci/pci_host.h"
1de7afc9	21	#include "qemu/bswap.h"
0d09e41a	22	#include "hw/pci-host/ppce500.h"
74c62ba8 AJ	23
74c62ba8 AJ	24	#ifdef DEBUG_PCI
001faf32	25	#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
74c62ba8	26	#else
001faf32	27	#define pci_debug(fmt, ...)
74c62ba8 AJ	28	#endif
	29
	30	#define PCIE500_CFGADDR 0x0
	31	#define PCIE500_CFGDATA 0x4
	32	#define PCIE500_REG_BASE 0xC00
be13cc7a AG	33	#define PCIE500_ALL_SIZE 0x1000
be13cc7a AG	34	#define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
74c62ba8	35
a1bc20df AG	36	#define PCIE500_PCI_IOLEN 0x10000ULL
a1bc20df AG	37
74c62ba8 AJ	38	#define PPCE500_PCI_CONFIG_ADDR 0x0
	39	#define PPCE500_PCI_CONFIG_DATA 0x4
	40	#define PPCE500_PCI_INTACK 0x8
	41
	42	#define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE)
	43	#define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE)
	44	#define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE)
	45	#define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE)
	46	#define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE)
	47	#define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE)
	48	#define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE)
	49
	50	#define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE)
	51
	52	#define PCI_POTAR 0x0
	53	#define PCI_POTEAR 0x4
	54	#define PCI_POWBAR 0x8
	55	#define PCI_POWAR 0x10
	56
	57	#define PCI_PITAR 0x0
	58	#define PCI_PIWBAR 0x8
	59	#define PCI_PIWBEAR 0xC
	60	#define PCI_PIWAR 0x10
	61
	62	#define PPCE500_PCI_NR_POBS 5
	63	#define PPCE500_PCI_NR_PIBS 3
	64
	65	struct pci_outbound {
	66	uint32_t potar;
	67	uint32_t potear;
	68	uint32_t powbar;
	69	uint32_t powar;
	70	};
	71
	72	struct pci_inbound {
	73	uint32_t pitar;
	74	uint32_t piwbar;
	75	uint32_t piwbear;
	76	uint32_t piwar;
	77	};
	78
9c1a61f0 AF	79	#define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"
	80
	81	#define PPC_E500_PCI_HOST_BRIDGE(obj) \
	82	OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE)
	83
74c62ba8	84	struct PPCE500PCIState {
67c332fd	85	PCIHostState parent_obj;
9c1a61f0	86
74c62ba8 AJ	87	struct pci_outbound pob[PPCE500_PCI_NR_POBS];
	88	struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
	89	uint32_t gasket_time;
d575a6ce	90	qemu_irq irq[PCI_NUM_PINS];
3016dca0	91	uint32_t irq_num[PCI_NUM_PINS];
eafb325f	92	uint32_t first_slot;
3016dca0	93	uint32_t first_pin_irq;
be13cc7a	94	/* mmio maps */
cb4e15c7	95	MemoryRegion container;
cd5cba79	96	MemoryRegion iomem;
a1bc20df	97	MemoryRegion pio;
74c62ba8 AJ	98	};
74c62ba8 AJ	99
3eddc1be BB	100	#define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge"
	101	#define PPC_E500_PCI_BRIDGE(obj) \
	102	OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE)
	103
	104	struct PPCE500PCIBridgeState {
	105	/< private >/
	106	PCIDevice parent;
	107	/< public >/
	108
	109	MemoryRegion bar0;
	110	};
	111
	112	typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState;
74c62ba8 AJ	113	typedef struct PPCE500PCIState PPCE500PCIState;
74c62ba8 AJ	114
a8170e5e	115	static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
cd5cba79	116	unsigned size)
74c62ba8 AJ	117	{
	118	PPCE500PCIState *pci = opaque;
	119	unsigned long win;
	120	uint32_t value = 0;
eeae2e7b	121	int idx;
74c62ba8 AJ	122
	123	win = addr & 0xfe0;
	124
	125	switch (win) {
	126	case PPCE500_PCI_OW1:
	127	case PPCE500_PCI_OW2:
	128	case PPCE500_PCI_OW3:
	129	case PPCE500_PCI_OW4:
eeae2e7b	130	idx = (addr >> 5) & 0x7;
74c62ba8	131	switch (addr & 0xC) {
6875dc8e	132	case PCI_POTAR:
eeae2e7b	133	value = pci->pob[idx].potar;
6875dc8e LY	134	break;
6875dc8e LY	135	case PCI_POTEAR:
eeae2e7b	136	value = pci->pob[idx].potear;
6875dc8e LY	137	break;
6875dc8e LY	138	case PCI_POWBAR:
eeae2e7b	139	value = pci->pob[idx].powbar;
6875dc8e LY	140	break;
6875dc8e LY	141	case PCI_POWAR:
eeae2e7b	142	value = pci->pob[idx].powar;
6875dc8e LY	143	break;
	144	default:
	145	break;
74c62ba8 AJ	146	}
	147	break;
	148
	149	case PPCE500_PCI_IW3:
	150	case PPCE500_PCI_IW2:
	151	case PPCE500_PCI_IW1:
eeae2e7b	152	idx = ((addr >> 5) & 0x3) - 1;
74c62ba8	153	switch (addr & 0xC) {
6875dc8e	154	case PCI_PITAR:
eeae2e7b	155	value = pci->pib[idx].pitar;
6875dc8e LY	156	break;
6875dc8e LY	157	case PCI_PIWBAR:
eeae2e7b	158	value = pci->pib[idx].piwbar;
6875dc8e LY	159	break;
6875dc8e LY	160	case PCI_PIWBEAR:
eeae2e7b	161	value = pci->pib[idx].piwbear;
6875dc8e LY	162	break;
6875dc8e LY	163	case PCI_PIWAR:
eeae2e7b	164	value = pci->pib[idx].piwar;
6875dc8e LY	165	break;
	166	default:
	167	break;
74c62ba8 AJ	168	};
	169	break;
	170
	171	case PPCE500_PCI_GASKET_TIMR:
	172	value = pci->gasket_time;
	173	break;
	174
	175	default:
	176	break;
	177	}
	178
c0a2a096 BS	179	pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
c0a2a096 BS	180	win, addr, value);
74c62ba8 AJ	181	return value;
	182	}
	183
a8170e5e	184	static void pci_reg_write4(void *opaque, hwaddr addr,
cd5cba79	185	uint64_t value, unsigned size)
74c62ba8 AJ	186	{
	187	PPCE500PCIState *pci = opaque;
	188	unsigned long win;
eeae2e7b	189	int idx;
74c62ba8 AJ	190
	191	win = addr & 0xfe0;
	192
c0a2a096	193	pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
cd5cba79	194	__func__, (unsigned)value, win, addr);
74c62ba8 AJ	195
	196	switch (win) {
	197	case PPCE500_PCI_OW1:
	198	case PPCE500_PCI_OW2:
	199	case PPCE500_PCI_OW3:
	200	case PPCE500_PCI_OW4:
eeae2e7b	201	idx = (addr >> 5) & 0x7;
74c62ba8	202	switch (addr & 0xC) {
6875dc8e	203	case PCI_POTAR:
eeae2e7b	204	pci->pob[idx].potar = value;
6875dc8e LY	205	break;
6875dc8e LY	206	case PCI_POTEAR:
eeae2e7b	207	pci->pob[idx].potear = value;
6875dc8e LY	208	break;
6875dc8e LY	209	case PCI_POWBAR:
eeae2e7b	210	pci->pob[idx].powbar = value;
6875dc8e LY	211	break;
6875dc8e LY	212	case PCI_POWAR:
eeae2e7b	213	pci->pob[idx].powar = value;
6875dc8e LY	214	break;
	215	default:
	216	break;
74c62ba8 AJ	217	};
	218	break;
	219
	220	case PPCE500_PCI_IW3:
	221	case PPCE500_PCI_IW2:
	222	case PPCE500_PCI_IW1:
eeae2e7b	223	idx = ((addr >> 5) & 0x3) - 1;
74c62ba8	224	switch (addr & 0xC) {
6875dc8e	225	case PCI_PITAR:
eeae2e7b	226	pci->pib[idx].pitar = value;
6875dc8e LY	227	break;
6875dc8e LY	228	case PCI_PIWBAR:
eeae2e7b	229	pci->pib[idx].piwbar = value;
6875dc8e LY	230	break;
6875dc8e LY	231	case PCI_PIWBEAR:
eeae2e7b	232	pci->pib[idx].piwbear = value;
6875dc8e LY	233	break;
6875dc8e LY	234	case PCI_PIWAR:
eeae2e7b	235	pci->pib[idx].piwar = value;
6875dc8e LY	236	break;
	237	default:
	238	break;
74c62ba8 AJ	239	};
	240	break;
	241
	242	case PPCE500_PCI_GASKET_TIMR:
	243	pci->gasket_time = value;
	244	break;
	245
	246	default:
	247	break;
	248	};
	249	}
	250
cd5cba79 AK	251	static const MemoryRegionOps e500_pci_reg_ops = {
	252	.read = pci_reg_read4,
	253	.write = pci_reg_write4,
	254	.endianness = DEVICE_BIG_ENDIAN,
74c62ba8 AJ	255	};
74c62ba8 AJ	256
d575a6ce	257	static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin)
74c62ba8	258	{
05f57d9d AG	259	int devno = pci_dev->devfn >> 3;
05f57d9d AG	260	int ret;
74c62ba8	261
d575a6ce	262	ret = ppce500_pci_map_irq_slot(devno, pin);
74c62ba8 AJ	263
74c62ba8 AJ	264	pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
d575a6ce	265	pci_dev->devfn, pin, ret, devno);
74c62ba8 AJ	266
	267	return ret;
	268	}
	269
d575a6ce	270	static void mpc85xx_pci_set_irq(void *opaque, int pin, int level)
74c62ba8	271	{
3016dca0 BB	272	PPCE500PCIState *s = opaque;
3016dca0 BB	273	qemu_irq *pic = s->irq;
5d4e84c8	274
d575a6ce	275	pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level);
74c62ba8	276
d575a6ce	277	qemu_set_irq(pic[pin], level);
74c62ba8 AJ	278	}
74c62ba8 AJ	279
3016dca0 BB	280	static PCIINTxRoute e500_route_intx_pin_to_irq(void *opaque, int pin)
	281	{
	282	PCIINTxRoute route;
	283	PPCE500PCIState *s = opaque;
	284
	285	route.mode = PCI_INTX_ENABLED;
	286	route.irq = s->irq_num[pin];
	287
	288	pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq);
	289	return route;
	290	}
	291
e0433ecc JQ	292	static const VMStateDescription vmstate_pci_outbound = {
	293	.name = "pci_outbound",
	294	.version_id = 0,
	295	.minimum_version_id = 0,
3aff6c2f	296	.fields = (VMStateField[]) {
e0433ecc JQ	297	VMSTATE_UINT32(potar, struct pci_outbound),
	298	VMSTATE_UINT32(potear, struct pci_outbound),
	299	VMSTATE_UINT32(powbar, struct pci_outbound),
	300	VMSTATE_UINT32(powar, struct pci_outbound),
	301	VMSTATE_END_OF_LIST()
74c62ba8	302	}
e0433ecc	303	};
74c62ba8	304
e0433ecc JQ	305	static const VMStateDescription vmstate_pci_inbound = {
	306	.name = "pci_inbound",
	307	.version_id = 0,
	308	.minimum_version_id = 0,
3aff6c2f	309	.fields = (VMStateField[]) {
e0433ecc JQ	310	VMSTATE_UINT32(pitar, struct pci_inbound),
	311	VMSTATE_UINT32(piwbar, struct pci_inbound),
	312	VMSTATE_UINT32(piwbear, struct pci_inbound),
	313	VMSTATE_UINT32(piwar, struct pci_inbound),
	314	VMSTATE_END_OF_LIST()
74c62ba8	315	}
e0433ecc	316	};
74c62ba8	317
e0433ecc JQ	318	static const VMStateDescription vmstate_ppce500_pci = {
	319	.name = "ppce500_pci",
	320	.version_id = 1,
	321	.minimum_version_id = 1,
3aff6c2f	322	.fields = (VMStateField[]) {
e0433ecc JQ	323	VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
	324	vmstate_pci_outbound, struct pci_outbound),
	325	VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
f2e2bc9c	326	vmstate_pci_inbound, struct pci_inbound),
e0433ecc JQ	327	VMSTATE_UINT32(gasket_time, PPCE500PCIState),
e0433ecc JQ	328	VMSTATE_END_OF_LIST()
74c62ba8	329	}
e0433ecc	330	};
74c62ba8	331
022c62cb	332	#include "exec/address-spaces.h"
1e39101c	333
3eddc1be BB	334	static int e500_pcihost_bridge_initfn(PCIDevice *d)
	335	{
	336	PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d);
	337	PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(),
	338	"/e500-ccsr"));
	339
99750506 AG	340	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
	341	d->config[PCI_HEADER_TYPE] =
	342	(d->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) \|
	343	PCI_HEADER_TYPE_BRIDGE;
	344
40c5dce9	345	memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space,
3eddc1be BB	346	0, int128_get64(ccsr->ccsr_space.size));
3eddc1be BB	347	pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
99750506	348
3eddc1be BB	349	return 0;
	350	}
	351
be13cc7a AG	352	static int e500_pcihost_initfn(SysBusDevice *dev)
	353	{
	354	PCIHostState *h;
	355	PPCE500PCIState *s;
	356	PCIBus *b;
	357	int i;
aee97b84	358	MemoryRegion *address_space_mem = get_system_memory();
be13cc7a	359
8558d942	360	h = PCI_HOST_BRIDGE(dev);
9c1a61f0	361	s = PPC_E500_PCI_HOST_BRIDGE(dev);
be13cc7a AG	362
	363	for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
	364	sysbus_init_irq(dev, &s->irq[i]);
	365	}
	366
3016dca0 BB	367	for (i = 0; i < PCI_NUM_PINS; i++) {
	368	s->irq_num[i] = s->first_pin_irq + i;
	369	}
	370
40c5dce9	371	memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN);
a1bc20df	372
9c1a61f0	373	b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
3016dca0	374	mpc85xx_pci_map_irq, s, address_space_mem,
60a0e443	375	&s->pio, PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS);
9c1a61f0	376	h->bus = b;
be13cc7a AG	377
	378	pci_create_simple(b, 0, "e500-host-bridge");
	379
40c5dce9 PB	380	memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE);
40c5dce9 PB	381	memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h,
d0ed8076	382	"pci-conf-idx", 4);
40c5dce9	383	memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, h,
d0ed8076	384	"pci-conf-data", 4);
40c5dce9	385	memory_region_init_io(&s->iomem, OBJECT(s), &e500_pci_reg_ops, s,
cd5cba79	386	"pci.reg", PCIE500_REG_SIZE);
cb4e15c7 BC	387	memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
	388	memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
	389	memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
	390	sysbus_init_mmio(dev, &s->container);
a1bc20df	391	sysbus_init_mmio(dev, &s->pio);
3016dca0	392	pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq);
be13cc7a AG	393
	394	return 0;
	395	}
	396
40021f08 AL	397	static void e500_host_bridge_class_init(ObjectClass klass, void data)
40021f08 AL	398	{
39bffca2	399	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	400	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
40021f08 AL	401
3eddc1be	402	k->init = e500_pcihost_bridge_initfn;
40021f08 AL	403	k->vendor_id = PCI_VENDOR_ID_FREESCALE;
	404	k->device_id = PCI_DEVICE_ID_MPC8533E;
	405	k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
39bffca2	406	dc->desc = "Host bridge";
08c58f92 MA	407	/*
	408	* PCI-facing part of the host bridge, not usable without the
	409	* host-facing part, which can't be device_add'ed, yet.
	410	*/
	411	dc->cannot_instantiate_with_device_add_yet = true;
40021f08 AL	412	}
40021f08 AL	413
4240abff	414	static const TypeInfo e500_host_bridge_info = {
39bffca2 AL	415	.name = "e500-host-bridge",
39bffca2 AL	416	.parent = TYPE_PCI_DEVICE,
3eddc1be	417	.instance_size = sizeof(PPCE500PCIBridgeState),
39bffca2	418	.class_init = e500_host_bridge_class_init,
be13cc7a AG	419	};
be13cc7a AG	420
eafb325f AG	421	static Property pcihost_properties[] = {
eafb325f AG	422	DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11),
3016dca0	423	DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1),
eafb325f AG	424	DEFINE_PROP_END_OF_LIST(),
	425	};
	426
999e12bb AL	427	static void e500_pcihost_class_init(ObjectClass klass, void data)
999e12bb AL	428	{
39bffca2	429	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	430	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	431
	432	k->init = e500_pcihost_initfn;
125ee0ed	433	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
eafb325f	434	dc->props = pcihost_properties;
39bffca2	435	dc->vmsd = &vmstate_ppce500_pci;
999e12bb AL	436	}
999e12bb AL	437
4240abff	438	static const TypeInfo e500_pcihost_info = {
9c1a61f0	439	.name = TYPE_PPC_E500_PCI_HOST_BRIDGE,
8558d942	440	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	441	.instance_size = sizeof(PPCE500PCIState),
39bffca2 AL	442	.class_init = e500_pcihost_class_init,
be13cc7a AG	443	};
be13cc7a AG	444
83f7d43a	445	static void e500_pci_register_types(void)
74c62ba8	446	{
39bffca2 AL	447	type_register_static(&e500_pcihost_info);
39bffca2 AL	448	type_register_static(&e500_host_bridge_info);
74c62ba8	449	}
83f7d43a AF	450
83f7d43a AF	451	type_init(e500_pci_register_types)