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[qemu.git] / hw / i386 / xen / xen_platform.c
CommitLineData
01195b73
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1/*
2 * XEN platform pci device, formerly known as the event channel device
3 *
4 * Copyright (c) 2003-2004 Intel Corp.
5 * Copyright (c) 2006 XenSource
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26#include <assert.h>
27
83c9f4ca 28#include "hw/hw.h"
0d09e41a 29#include "hw/i386/pc.h"
15e8159e 30#include "hw/ide.h"
83c9f4ca
PB
31#include "hw/pci/pci.h"
32#include "hw/irq.h"
0d09e41a
PB
33#include "hw/xen/xen_common.h"
34#include "hw/xen/xen_backend.h"
01195b73 35#include "trace.h"
022c62cb 36#include "exec/address-spaces.h"
01195b73
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37
38#include <xenguest.h>
39
40//#define DEBUG_PLATFORM
41
42#ifdef DEBUG_PLATFORM
43#define DPRINTF(fmt, ...) do { \
44 fprintf(stderr, "xen_platform: " fmt, ## __VA_ARGS__); \
45} while (0)
46#else
47#define DPRINTF(fmt, ...) do { } while (0)
48#endif
49
50#define PFFLAG_ROM_LOCK 1 /* Sets whether ROM memory area is RW or RO */
51
52typedef struct PCIXenPlatformState {
dc4aa51b
AF
53 /*< private >*/
54 PCIDevice parent_obj;
55 /*< public >*/
56
de00982e
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57 MemoryRegion fixed_io;
58 MemoryRegion bar;
59 MemoryRegion mmio_bar;
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60 uint8_t flags; /* used only for version_id == 2 */
61 int drivers_blacklisted;
62 uint16_t driver_product_version;
63
64 /* Log from guest drivers */
65 char log_buffer[4096];
66 int log_buffer_off;
67} PCIXenPlatformState;
68
51a3fe99
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69#define TYPE_XEN_PLATFORM "xen-platform"
70#define XEN_PLATFORM(obj) \
71 OBJECT_CHECK(PCIXenPlatformState, (obj), TYPE_XEN_PLATFORM)
72
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73#define XEN_PLATFORM_IOPORT 0x10
74
75/* Send bytes to syslog */
76static void log_writeb(PCIXenPlatformState *s, char val)
77{
78 if (val == '\n' || s->log_buffer_off == sizeof(s->log_buffer) - 1) {
79 /* Flush buffer */
80 s->log_buffer[s->log_buffer_off] = 0;
81 trace_xen_platform_log(s->log_buffer);
82 s->log_buffer_off = 0;
83 } else {
84 s->log_buffer[s->log_buffer_off++] = val;
85 }
86}
87
88/* Xen Platform, Fixed IOPort */
679f4f8b
SS
89#define UNPLUG_ALL_IDE_DISKS 1
90#define UNPLUG_ALL_NICS 2
91#define UNPLUG_AUX_IDE_DISKS 4
92
7aa8cbb9 93static void unplug_nic(PCIBus *b, PCIDevice *d, void *o)
679f4f8b 94{
bd4982a6 95 /* We have to ignore passthrough devices */
679f4f8b 96 if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
bd4982a6
AP
97 PCI_CLASS_NETWORK_ETHERNET
98 && strcmp(d->name, "xen-pci-passthrough") != 0) {
02a5c4c9 99 object_unparent(OBJECT(d));
679f4f8b
SS
100 }
101}
102
103static void pci_unplug_nics(PCIBus *bus)
104{
7aa8cbb9 105 pci_for_each_device(bus, 0, unplug_nic, NULL);
679f4f8b
SS
106}
107
7aa8cbb9 108static void unplug_disks(PCIBus *b, PCIDevice *d, void *o)
679f4f8b 109{
bd4982a6 110 /* We have to ignore passthrough devices */
679f4f8b 111 if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
bd4982a6
AP
112 PCI_CLASS_STORAGE_IDE
113 && strcmp(d->name, "xen-pci-passthrough") != 0) {
15e8159e 114 pci_piix3_xen_ide_unplug(DEVICE(d));
679f4f8b
SS
115 }
116}
117
118static void pci_unplug_disks(PCIBus *bus)
119{
7aa8cbb9 120 pci_for_each_device(bus, 0, unplug_disks, NULL);
679f4f8b 121}
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122
123static void platform_fixed_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
124{
125 PCIXenPlatformState *s = opaque;
126
e7b48c97 127 switch (addr) {
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128 case 0: {
129 PCIDevice *pci_dev = PCI_DEVICE(s);
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130 /* Unplug devices. Value is a bitmask of which devices to
131 unplug, with bit 0 the IDE devices, bit 1 the network
132 devices, and bit 2 the non-primary-master IDE devices. */
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133 if (val & UNPLUG_ALL_IDE_DISKS) {
134 DPRINTF("unplug disks\n");
922453bc 135 bdrv_drain_all();
679f4f8b 136 bdrv_flush_all();
dc4aa51b 137 pci_unplug_disks(pci_dev->bus);
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SS
138 }
139 if (val & UNPLUG_ALL_NICS) {
140 DPRINTF("unplug nics\n");
dc4aa51b 141 pci_unplug_nics(pci_dev->bus);
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142 }
143 if (val & UNPLUG_AUX_IDE_DISKS) {
144 DPRINTF("unplug auxiliary disks not supported\n");
145 }
01195b73 146 break;
dc4aa51b 147 }
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148 case 2:
149 switch (val) {
150 case 1:
151 DPRINTF("Citrix Windows PV drivers loaded in guest\n");
152 break;
153 case 0:
154 DPRINTF("Guest claimed to be running PV product 0?\n");
155 break;
156 default:
157 DPRINTF("Unknown PV product %d loaded in guest\n", val);
158 break;
159 }
160 s->driver_product_version = val;
161 break;
162 }
163}
164
165static void platform_fixed_ioport_writel(void *opaque, uint32_t addr,
166 uint32_t val)
167{
e7b48c97 168 switch (addr) {
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169 case 0:
170 /* PV driver version */
171 break;
172 }
173}
174
175static void platform_fixed_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
176{
177 PCIXenPlatformState *s = opaque;
178
e7b48c97 179 switch (addr) {
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180 case 0: /* Platform flags */ {
181 hvmmem_type_t mem_type = (val & PFFLAG_ROM_LOCK) ?
182 HVMMEM_ram_ro : HVMMEM_ram_rw;
183 if (xc_hvm_set_mem_type(xen_xc, xen_domid, mem_type, 0xc0, 0x40)) {
184 DPRINTF("unable to change ro/rw state of ROM memory area!\n");
185 } else {
186 s->flags = val & PFFLAG_ROM_LOCK;
187 DPRINTF("changed ro/rw state of ROM memory area. now is %s state.\n",
188 (mem_type == HVMMEM_ram_ro ? "ro":"rw"));
189 }
190 break;
191 }
192 case 2:
193 log_writeb(s, val);
194 break;
195 }
196}
197
198static uint32_t platform_fixed_ioport_readw(void *opaque, uint32_t addr)
199{
200 PCIXenPlatformState *s = opaque;
201
e7b48c97 202 switch (addr) {
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203 case 0:
204 if (s->drivers_blacklisted) {
205 /* The drivers will recognise this magic number and refuse
206 * to do anything. */
207 return 0xd249;
208 } else {
209 /* Magic value so that you can identify the interface. */
210 return 0x49d2;
211 }
212 default:
213 return 0xffff;
214 }
215}
216
217static uint32_t platform_fixed_ioport_readb(void *opaque, uint32_t addr)
218{
219 PCIXenPlatformState *s = opaque;
220
e7b48c97 221 switch (addr) {
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222 case 0:
223 /* Platform flags */
224 return s->flags;
225 case 2:
226 /* Version number */
227 return 1;
228 default:
229 return 0xff;
230 }
231}
232
233static void platform_fixed_ioport_reset(void *opaque)
234{
235 PCIXenPlatformState *s = opaque;
236
e7b48c97 237 platform_fixed_ioport_writeb(s, 0, 0);
01195b73
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238}
239
626c7a17
AG
240static uint64_t platform_fixed_ioport_read(void *opaque,
241 hwaddr addr,
242 unsigned size)
243{
244 switch (size) {
245 case 1:
246 return platform_fixed_ioport_readb(opaque, addr);
247 case 2:
248 return platform_fixed_ioport_readw(opaque, addr);
249 default:
250 return -1;
251 }
252}
253
254static void platform_fixed_ioport_write(void *opaque, hwaddr addr,
255
256 uint64_t val, unsigned size)
257{
258 switch (size) {
259 case 1:
260 platform_fixed_ioport_writeb(opaque, addr, val);
261 break;
262 case 2:
263 platform_fixed_ioport_writew(opaque, addr, val);
264 break;
265 case 4:
266 platform_fixed_ioport_writel(opaque, addr, val);
267 break;
268 }
269}
270
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271
272static const MemoryRegionOps platform_fixed_io_ops = {
626c7a17
AG
273 .read = platform_fixed_ioport_read,
274 .write = platform_fixed_ioport_write,
962b03fc
JK
275 .valid = {
276 .unaligned = true,
277 },
626c7a17
AG
278 .impl = {
279 .min_access_size = 1,
280 .max_access_size = 4,
962b03fc 281 .unaligned = true,
626c7a17
AG
282 },
283 .endianness = DEVICE_LITTLE_ENDIAN,
de00982e
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284};
285
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286static void platform_fixed_ioport_init(PCIXenPlatformState* s)
287{
22fc860b 288 memory_region_init_io(&s->fixed_io, OBJECT(s), &platform_fixed_io_ops, s,
de00982e
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289 "xen-fixed", 16);
290 memory_region_add_subregion(get_system_io(), XEN_PLATFORM_IOPORT,
291 &s->fixed_io);
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292}
293
294/* Xen Platform PCI Device */
295
7a652efa
HP
296static uint64_t xen_platform_ioport_readb(void *opaque, hwaddr addr,
297 unsigned int size)
01195b73 298{
01195b73 299 if (addr == 0) {
e7b48c97 300 return platform_fixed_ioport_readb(opaque, 0);
01195b73
SS
301 } else {
302 return ~0u;
303 }
304}
305
7a652efa
HP
306static void xen_platform_ioport_writeb(void *opaque, hwaddr addr,
307 uint64_t val, unsigned int size)
01195b73
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308{
309 PCIXenPlatformState *s = opaque;
310
01195b73
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311 switch (addr) {
312 case 0: /* Platform flags */
7a652efa 313 platform_fixed_ioport_writeb(opaque, 0, (uint32_t)val);
01195b73
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314 break;
315 case 8:
7a652efa 316 log_writeb(s, (uint32_t)val);
01195b73
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317 break;
318 default:
319 break;
320 }
321}
322
de00982e 323static const MemoryRegionOps xen_pci_io_ops = {
7a652efa
HP
324 .read = xen_platform_ioport_readb,
325 .write = xen_platform_ioport_writeb,
326 .impl.min_access_size = 1,
327 .impl.max_access_size = 1,
de00982e 328};
01195b73 329
de00982e
AK
330static void platform_ioport_bar_setup(PCIXenPlatformState *d)
331{
22fc860b
PB
332 memory_region_init_io(&d->bar, OBJECT(d), &xen_pci_io_ops, d,
333 "xen-pci", 0x100);
01195b73
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334}
335
a8170e5e 336static uint64_t platform_mmio_read(void *opaque, hwaddr addr,
de00982e 337 unsigned size)
01195b73
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338{
339 DPRINTF("Warning: attempted read from physical address "
340 "0x" TARGET_FMT_plx " in xen platform mmio space\n", addr);
341
342 return 0;
343}
344
a8170e5e 345static void platform_mmio_write(void *opaque, hwaddr addr,
de00982e 346 uint64_t val, unsigned size)
01195b73 347{
de00982e 348 DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical "
01195b73
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349 "address 0x" TARGET_FMT_plx " in xen platform mmio space\n",
350 val, addr);
351}
352
de00982e 353static const MemoryRegionOps platform_mmio_handler = {
01195b73
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354 .read = &platform_mmio_read,
355 .write = &platform_mmio_write,
de00982e 356 .endianness = DEVICE_NATIVE_ENDIAN,
01195b73
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357};
358
de00982e 359static void platform_mmio_setup(PCIXenPlatformState *d)
01195b73 360{
22fc860b 361 memory_region_init_io(&d->mmio_bar, OBJECT(d), &platform_mmio_handler, d,
de00982e 362 "xen-mmio", 0x1000000);
01195b73
SS
363}
364
365static int xen_platform_post_load(void *opaque, int version_id)
366{
367 PCIXenPlatformState *s = opaque;
368
e7b48c97 369 platform_fixed_ioport_writeb(s, 0, s->flags);
01195b73
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370
371 return 0;
372}
373
374static const VMStateDescription vmstate_xen_platform = {
375 .name = "platform",
376 .version_id = 4,
377 .minimum_version_id = 4,
01195b73 378 .post_load = xen_platform_post_load,
d49805ae 379 .fields = (VMStateField[]) {
dc4aa51b 380 VMSTATE_PCI_DEVICE(parent_obj, PCIXenPlatformState),
01195b73
SS
381 VMSTATE_UINT8(flags, PCIXenPlatformState),
382 VMSTATE_END_OF_LIST()
383 }
384};
385
386static int xen_platform_initfn(PCIDevice *dev)
387{
51a3fe99 388 PCIXenPlatformState *d = XEN_PLATFORM(dev);
01195b73
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389 uint8_t *pci_conf;
390
dc4aa51b 391 pci_conf = dev->config;
01195b73 392
01195b73
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393 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
394
01195b73
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395 pci_config_set_prog_interface(pci_conf, 0);
396
01195b73
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397 pci_conf[PCI_INTERRUPT_PIN] = 1;
398
de00982e 399 platform_ioport_bar_setup(d);
dc4aa51b 400 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->bar);
01195b73
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401
402 /* reserve 16MB mmio address for share memory*/
de00982e 403 platform_mmio_setup(d);
dc4aa51b 404 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
e824b2cc 405 &d->mmio_bar);
01195b73
SS
406
407 platform_fixed_ioport_init(d);
408
409 return 0;
410}
411
412static void platform_reset(DeviceState *dev)
413{
51a3fe99 414 PCIXenPlatformState *s = XEN_PLATFORM(dev);
01195b73
SS
415
416 platform_fixed_ioport_reset(s);
417}
418
40021f08
AL
419static void xen_platform_class_init(ObjectClass *klass, void *data)
420{
39bffca2 421 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL
422 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
423
424 k->init = xen_platform_initfn;
425 k->vendor_id = PCI_VENDOR_ID_XEN;
426 k->device_id = PCI_DEVICE_ID_XEN_PLATFORM;
427 k->class_id = PCI_CLASS_OTHERS << 8 | 0x80;
428 k->subsystem_vendor_id = PCI_VENDOR_ID_XEN;
429 k->subsystem_id = PCI_DEVICE_ID_XEN_PLATFORM;
430 k->revision = 1;
125ee0ed 431 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
39bffca2
AL
432 dc->desc = "XEN platform pci device";
433 dc->reset = platform_reset;
434 dc->vmsd = &vmstate_xen_platform;
40021f08
AL
435}
436
8c43a6f0 437static const TypeInfo xen_platform_info = {
51a3fe99 438 .name = TYPE_XEN_PLATFORM,
39bffca2
AL
439 .parent = TYPE_PCI_DEVICE,
440 .instance_size = sizeof(PCIXenPlatformState),
441 .class_init = xen_platform_class_init,
01195b73
SS
442};
443
83f7d43a 444static void xen_platform_register_types(void)
01195b73 445{
39bffca2 446 type_register_static(&xen_platform_info);
01195b73
SS
447}
448
83f7d43a 449type_init(xen_platform_register_types)
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