[qemu.git] / hw / timer / pxa2xx_timer.c

/*
 * Intel XScale PXA255/270 OS Timers.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Copyright (c) 2006 Thorsten Zitterell
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "qemu/timer.h"
#include "sysemu/sysemu.h"
#include "hw/arm/pxa.h"
#include "hw/sysbus.h"
#include "qemu/log.h"

#define OSMR0	0x00
#define OSMR1	0x04
#define OSMR2	0x08
#define OSMR3	0x0c
#define OSMR4	0x80
#define OSMR5	0x84
#define OSMR6	0x88
#define OSMR7	0x8c
#define OSMR8	0x90
#define OSMR9	0x94
#define OSMR10	0x98
#define OSMR11	0x9c
#define OSCR	0x10	/* OS Timer Count */
#define OSCR4	0x40
#define OSCR5	0x44
#define OSCR6	0x48
#define OSCR7	0x4c
#define OSCR8	0x50
#define OSCR9	0x54
#define OSCR10	0x58
#define OSCR11	0x5c
#define OSSR	0x14	/* Timer status register */
#define OWER	0x18
#define OIER	0x1c	/* Interrupt enable register  3-0 to E3-E0 */
#define OMCR4	0xc0	/* OS Match Control registers */
#define OMCR5	0xc4
#define OMCR6	0xc8
#define OMCR7	0xcc
#define OMCR8	0xd0
#define OMCR9	0xd4
#define OMCR10	0xd8
#define OMCR11	0xdc
#define OSNR	0x20

#define PXA25X_FREQ	3686400	/* 3.6864 MHz */
#define PXA27X_FREQ	3250000	/* 3.25 MHz */

static int pxa2xx_timer4_freq[8] = {
    [0] = 0,
    [1] = 32768,
    [2] = 1000,
    [3] = 1,
    [4] = 1000000,
    /* [5] is the "Externally supplied clock".  Assign if necessary.  */
    [5 ... 7] = 0,
};

#define TYPE_PXA2XX_TIMER "pxa2xx-timer"
#define PXA2XX_TIMER(obj) \
    OBJECT_CHECK(PXA2xxTimerInfo, (obj), TYPE_PXA2XX_TIMER)

typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;

typedef struct {
    uint32_t value;
    qemu_irq irq;
    QEMUTimer *qtimer;
    int num;
    PXA2xxTimerInfo *info;
} PXA2xxTimer0;

typedef struct {
    PXA2xxTimer0 tm;
    int32_t oldclock;
    int32_t clock;
    uint64_t lastload;
    uint32_t freq;
    uint32_t control;
} PXA2xxTimer4;

struct PXA2xxTimerInfo {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint32_t flags;

    int32_t clock;
    int32_t oldclock;
    uint64_t lastload;
    uint32_t freq;
    PXA2xxTimer0 timer[4];
    uint32_t events;
    uint32_t irq_enabled;
    uint32_t reset3;
    uint32_t snapshot;

    qemu_irq irq4;
    PXA2xxTimer4 tm4[8];
};

#define PXA2XX_TIMER_HAVE_TM4	0

static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
{
    return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
}

static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int i;
    uint32_t now_vm;
    uint64_t new_qemu;

    now_vm = s->clock +
            muldiv64(now_qemu - s->lastload, s->freq, NANOSECONDS_PER_SECOND);

    for (i = 0; i < 4; i ++) {
        new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
                        NANOSECONDS_PER_SECOND, s->freq);
        timer_mod(s->timer[i].qtimer, new_qemu);
    }
}

static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    uint32_t now_vm;
    uint64_t new_qemu;
    static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
    int counter;

    if (s->tm4[n].control & (1 << 7))
        counter = n;
    else
        counter = counters[n];

    if (!s->tm4[counter].freq) {
        timer_del(s->tm4[n].tm.qtimer);
        return;
    }

    now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
                    s->tm4[counter].lastload,
                    s->tm4[counter].freq, NANOSECONDS_PER_SECOND);

    new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
                    NANOSECONDS_PER_SECOND, s->tm4[counter].freq);
    timer_mod(s->tm4[n].tm.qtimer, new_qemu);
}

static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
                                  unsigned size)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int tm = 0;

    switch (offset) {
    case OSMR3:  tm ++;
        /* fall through */
    case OSMR2:  tm ++;
        /* fall through */
    case OSMR1:  tm ++;
        /* fall through */
    case OSMR0:
        return s->timer[tm].value;
    case OSMR11: tm ++;
        /* fall through */
    case OSMR10: tm ++;
        /* fall through */
    case OSMR9:  tm ++;
        /* fall through */
    case OSMR8:  tm ++;
        /* fall through */
    case OSMR7:  tm ++;
        /* fall through */
    case OSMR6:  tm ++;
        /* fall through */
    case OSMR5:  tm ++;
        /* fall through */
    case OSMR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        return s->tm4[tm].tm.value;
    case OSCR:
        return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
                        s->lastload, s->freq, NANOSECONDS_PER_SECOND);
    case OSCR11: tm ++;
        /* fall through */
    case OSCR10: tm ++;
        /* fall through */
    case OSCR9:  tm ++;
        /* fall through */
    case OSCR8:  tm ++;
        /* fall through */
    case OSCR7:  tm ++;
        /* fall through */
    case OSCR6:  tm ++;
        /* fall through */
    case OSCR5:  tm ++;
        /* fall through */
    case OSCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;

        if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
            if (s->tm4[tm - 1].freq)
                s->snapshot = s->tm4[tm - 1].clock + muldiv64(
                                qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
                                s->tm4[tm - 1].lastload,
                                s->tm4[tm - 1].freq, NANOSECONDS_PER_SECOND);
            else
                s->snapshot = s->tm4[tm - 1].clock;
        }

        if (!s->tm4[tm].freq)
            return s->tm4[tm].clock;
        return s->tm4[tm].clock +
            muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
                     s->tm4[tm].lastload, s->tm4[tm].freq,
                     NANOSECONDS_PER_SECOND);
    case OIER:
        return s->irq_enabled;
    case OSSR:	/* Status register */
        return s->events;
    case OWER:
        return s->reset3;
    case OMCR11: tm ++;
        /* fall through */
    case OMCR10: tm ++;
        /* fall through */
    case OMCR9:  tm ++;
        /* fall through */
    case OMCR8:  tm ++;
        /* fall through */
    case OMCR7:  tm ++;
        /* fall through */
    case OMCR6:  tm ++;
        /* fall through */
    case OMCR5:  tm ++;
        /* fall through */
    case OMCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        return s->tm4[tm].control;
    case OSNR:
        return s->snapshot;
    default:
        qemu_log_mask(LOG_UNIMP,
                      "%s: unknown register 0x%02" HWADDR_PRIx "\n",
                      __func__, offset);
        break;
    badreg:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: incorrect register 0x%02" HWADDR_PRIx "\n",
                      __func__, offset);
    }

    return 0;
}

static void pxa2xx_timer_write(void *opaque, hwaddr offset,
                               uint64_t value, unsigned size)
{
    int i, tm = 0;
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;

    switch (offset) {
    case OSMR3:  tm ++;
        /* fall through */
    case OSMR2:  tm ++;
        /* fall through */
    case OSMR1:  tm ++;
        /* fall through */
    case OSMR0:
        s->timer[tm].value = value;
        pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
        break;
    case OSMR11: tm ++;
        /* fall through */
    case OSMR10: tm ++;
        /* fall through */
    case OSMR9:  tm ++;
        /* fall through */
    case OSMR8:  tm ++;
        /* fall through */
    case OSMR7:  tm ++;
        /* fall through */
    case OSMR6:  tm ++;
        /* fall through */
    case OSMR5:  tm ++;
        /* fall through */
    case OSMR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].tm.value = value;
        pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
        break;
    case OSCR:
        s->oldclock = s->clock;
        s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
        s->clock = value;
        pxa2xx_timer_update(s, s->lastload);
        break;
    case OSCR11: tm ++;
        /* fall through */
    case OSCR10: tm ++;
        /* fall through */
    case OSCR9:  tm ++;
        /* fall through */
    case OSCR8:  tm ++;
        /* fall through */
    case OSCR7:  tm ++;
        /* fall through */
    case OSCR6:  tm ++;
        /* fall through */
    case OSCR5:  tm ++;
        /* fall through */
    case OSCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].oldclock = s->tm4[tm].clock;
        s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
        s->tm4[tm].clock = value;
        pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
        break;
    case OIER:
        s->irq_enabled = value & 0xfff;
        break;
    case OSSR:	/* Status register */
        value &= s->events;
        s->events &= ~value;
        for (i = 0; i < 4; i ++, value >>= 1)
            if (value & 1)
                qemu_irq_lower(s->timer[i].irq);
        if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
            qemu_irq_lower(s->irq4);
        break;
    case OWER:	/* XXX: Reset on OSMR3 match? */
        s->reset3 = value;
        break;
    case OMCR7:  tm ++;
        /* fall through */
    case OMCR6:  tm ++;
        /* fall through */
    case OMCR5:  tm ++;
        /* fall through */
    case OMCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].control = value & 0x0ff;
        /* XXX Stop if running (shouldn't happen) */
        if ((value & (1 << 7)) || tm == 0)
            s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
        else {
            s->tm4[tm].freq = 0;
            pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
        }
        break;
    case OMCR11: tm ++;
        /* fall through */
    case OMCR10: tm ++;
        /* fall through */
    case OMCR9:  tm ++;
        /* fall through */
    case OMCR8:  tm += 4;
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].control = value & 0x3ff;
        /* XXX Stop if running (shouldn't happen) */
        if ((value & (1 << 7)) || !(tm & 1))
            s->tm4[tm].freq =
                    pxa2xx_timer4_freq[(value & (1 << 8)) ?  0 : (value & 7)];
        else {
            s->tm4[tm].freq = 0;
            pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
        }
        break;
    default:
        qemu_log_mask(LOG_UNIMP,
                      "%s: unknown register 0x%02" HWADDR_PRIx " "
                      "(value 0x%08" PRIx64 ")\n",  __func__, offset, value);
        break;
    badreg:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: incorrect register 0x%02" HWADDR_PRIx " "
                      "(value 0x%08" PRIx64 ")\n", __func__, offset, value);
    }
}

static const MemoryRegionOps pxa2xx_timer_ops = {
    .read = pxa2xx_timer_read,
    .write = pxa2xx_timer_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pxa2xx_timer_tick(void *opaque)
{
    PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
    PXA2xxTimerInfo *i = t->info;

    if (i->irq_enabled & (1 << t->num)) {
        i->events |= 1 << t->num;
        qemu_irq_raise(t->irq);
    }

    if (t->num == 3)
        if (i->reset3 & 1) {
            i->reset3 = 0;
            qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
        }
}

static void pxa2xx_timer_tick4(void *opaque)
{
    PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
    PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info;

    pxa2xx_timer_tick(&t->tm);
    if (t->control & (1 << 3))
        t->clock = 0;
    if (t->control & (1 << 6))
        pxa2xx_timer_update4(i, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), t->tm.num - 4);
    if (i->events & 0xff0)
        qemu_irq_raise(i->irq4);
}

static int pxa25x_timer_post_load(void *opaque, int version_id)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int64_t now;
    int i;

    now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
    pxa2xx_timer_update(s, now);

    if (pxa2xx_timer_has_tm4(s))
        for (i = 0; i < 8; i ++)
            pxa2xx_timer_update4(s, now, i);

    return 0;
}

static void pxa2xx_timer_init(Object *obj)
{
    PXA2xxTimerInfo *s = PXA2XX_TIMER(obj);
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);

    s->irq_enabled = 0;
    s->oldclock = 0;
    s->clock = 0;
    s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
    s->reset3 = 0;

    memory_region_init_io(&s->iomem, obj, &pxa2xx_timer_ops, s,
                          "pxa2xx-timer", 0x00001000);
    sysbus_init_mmio(dev, &s->iomem);
}

static void pxa2xx_timer_realize(DeviceState *dev, Error **errp)
{
    PXA2xxTimerInfo *s = PXA2XX_TIMER(dev);
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
    int i;

    for (i = 0; i < 4; i ++) {
        s->timer[i].value = 0;
        sysbus_init_irq(sbd, &s->timer[i].irq);
        s->timer[i].info = s;
        s->timer[i].num = i;
        s->timer[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                                          pxa2xx_timer_tick, &s->timer[i]);
    }

    if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
        sysbus_init_irq(sbd, &s->irq4);

        for (i = 0; i < 8; i ++) {
            s->tm4[i].tm.value = 0;
            s->tm4[i].tm.info = s;
            s->tm4[i].tm.num = i + 4;
            s->tm4[i].freq = 0;
            s->tm4[i].control = 0x0;
            s->tm4[i].tm.qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                                               pxa2xx_timer_tick4, &s->tm4[i]);
        }
    }
}

static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
    .name = "pxa2xx_timer0",
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(value, PXA2xxTimer0),
        VMSTATE_END_OF_LIST(),
    },
};

static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
    .name = "pxa2xx_timer4",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
                        vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
        VMSTATE_INT32(oldclock, PXA2xxTimer4),
        VMSTATE_INT32(clock, PXA2xxTimer4),
        VMSTATE_UINT64(lastload, PXA2xxTimer4),
        VMSTATE_UINT32(freq, PXA2xxTimer4),
        VMSTATE_UINT32(control, PXA2xxTimer4),
        VMSTATE_END_OF_LIST(),
    },
};

static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
{
    return pxa2xx_timer_has_tm4(opaque);
}

static const VMStateDescription vmstate_pxa2xx_timer_regs = {
    .name = "pxa2xx_timer",
    .version_id = 1,
    .minimum_version_id = 1,
    .post_load = pxa25x_timer_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(clock, PXA2xxTimerInfo),
        VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
        VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
        VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
                        vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
        VMSTATE_UINT32(events, PXA2xxTimerInfo),
        VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
        VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
        VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
        VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
                        pxa2xx_timer_has_tm4_test, 0,
                        vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
        VMSTATE_END_OF_LIST(),
    }
};

static Property pxa25x_timer_dev_properties[] = {
    DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
    DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
                    PXA2XX_TIMER_HAVE_TM4, false),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa25x_timer_dev_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc = "PXA25x timer";
    dc->props = pxa25x_timer_dev_properties;
}

static const TypeInfo pxa25x_timer_dev_info = {
    .name          = "pxa25x-timer",
    .parent        = TYPE_PXA2XX_TIMER,
    .instance_size = sizeof(PXA2xxTimerInfo),
    .class_init    = pxa25x_timer_dev_class_init,
};

static Property pxa27x_timer_dev_properties[] = {
    DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
    DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
                    PXA2XX_TIMER_HAVE_TM4, true),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa27x_timer_dev_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc = "PXA27x timer";
    dc->props = pxa27x_timer_dev_properties;
}

static const TypeInfo pxa27x_timer_dev_info = {
    .name          = "pxa27x-timer",
    .parent        = TYPE_PXA2XX_TIMER,
    .instance_size = sizeof(PXA2xxTimerInfo),
    .class_init    = pxa27x_timer_dev_class_init,
};

static void pxa2xx_timer_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize  = pxa2xx_timer_realize;
    dc->vmsd = &vmstate_pxa2xx_timer_regs;
}

static const TypeInfo pxa2xx_timer_type_info = {
    .name          = TYPE_PXA2XX_TIMER,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxTimerInfo),
    .instance_init = pxa2xx_timer_init,
    .abstract      = true,
    .class_init    = pxa2xx_timer_class_init,
};

static void pxa2xx_timer_register_types(void)
{
    type_register_static(&pxa2xx_timer_type_info);
    type_register_static(&pxa25x_timer_dev_info);
    type_register_static(&pxa27x_timer_dev_info);
}

type_init(pxa2xx_timer_register_types)
Commit	Line	Data
a171fe39 AZ	1	/*
	2	* Intel XScale PXA255/270 OS Timers.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Copyright (c) 2006 Thorsten Zitterell
	6	*
8e31bf38	7	* This code is licensed under the GPL.
a171fe39 AZ	8	*/
a171fe39 AZ	9
8ef94f0b	10	#include "qemu/osdep.h"
83c9f4ca	11	#include "hw/hw.h"
1de7afc9	12	#include "qemu/timer.h"
9c17d615	13	#include "sysemu/sysemu.h"
0d09e41a	14	#include "hw/arm/pxa.h"
83c9f4ca	15	#include "hw/sysbus.h"
2ba63e4a	16	#include "qemu/log.h"
a171fe39 AZ	17
	18	#define OSMR0 0x00
	19	#define OSMR1 0x04
	20	#define OSMR2 0x08
	21	#define OSMR3 0x0c
	22	#define OSMR4 0x80
	23	#define OSMR5 0x84
	24	#define OSMR6 0x88
	25	#define OSMR7 0x8c
	26	#define OSMR8 0x90
	27	#define OSMR9 0x94
	28	#define OSMR10 0x98
	29	#define OSMR11 0x9c
	30	#define OSCR 0x10 /* OS Timer Count */
	31	#define OSCR4 0x40
	32	#define OSCR5 0x44
	33	#define OSCR6 0x48
	34	#define OSCR7 0x4c
	35	#define OSCR8 0x50
	36	#define OSCR9 0x54
	37	#define OSCR10 0x58
	38	#define OSCR11 0x5c
	39	#define OSSR 0x14 /* Timer status register */
	40	#define OWER 0x18
	41	#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
	42	#define OMCR4 0xc0 /* OS Match Control registers */
	43	#define OMCR5 0xc4
	44	#define OMCR6 0xc8
	45	#define OMCR7 0xcc
	46	#define OMCR8 0xd0
	47	#define OMCR9 0xd4
	48	#define OMCR10 0xd8
	49	#define OMCR11 0xdc
	50	#define OSNR 0x20
	51
	52	#define PXA25X_FREQ 3686400 /* 3.6864 MHz */
	53	#define PXA27X_FREQ 3250000 /* 3.25 MHz */
	54
	55	static int pxa2xx_timer4_freq[8] = {
	56	[0] = 0,
	57	[1] = 32768,
	58	[2] = 1000,
	59	[3] = 1,
	60	[4] = 1000000,
	61	/* [5] is the "Externally supplied clock". Assign if necessary. */
	62	[5 ... 7] = 0,
	63	};
	64
feea4361 AF	65	#define TYPE_PXA2XX_TIMER "pxa2xx-timer"
	66	#define PXA2XX_TIMER(obj) \
	67	OBJECT_CHECK(PXA2xxTimerInfo, (obj), TYPE_PXA2XX_TIMER)
	68
797e9542 DES	69	typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;
797e9542 DES	70
bc24a225	71	typedef struct {
a171fe39	72	uint32_t value;
5251d196	73	qemu_irq irq;
a171fe39 AZ	74	QEMUTimer *qtimer;
a171fe39 AZ	75	int num;
797e9542	76	PXA2xxTimerInfo *info;
bc24a225	77	} PXA2xxTimer0;
a171fe39	78
bc24a225 PB	79	typedef struct {
bc24a225 PB	80	PXA2xxTimer0 tm;
a171fe39 AZ	81	int32_t oldclock;
	82	int32_t clock;
	83	uint64_t lastload;
	84	uint32_t freq;
	85	uint32_t control;
bc24a225	86	} PXA2xxTimer4;
a171fe39	87
797e9542	88	struct PXA2xxTimerInfo {
feea4361 AF	89	SysBusDevice parent_obj;
feea4361 AF	90
b755bde3	91	MemoryRegion iomem;
797e9542 DES	92	uint32_t flags;
797e9542 DES	93
a171fe39 AZ	94	int32_t clock;
	95	int32_t oldclock;
	96	uint64_t lastload;
	97	uint32_t freq;
bc24a225	98	PXA2xxTimer0 timer[4];
a171fe39 AZ	99	uint32_t events;
	100	uint32_t irq_enabled;
	101	uint32_t reset3;
a171fe39	102	uint32_t snapshot;
797e9542	103
4ff927cc	104	qemu_irq irq4;
797e9542	105	PXA2xxTimer4 tm4[8];
797e9542 DES	106	};
	107
	108	#define PXA2XX_TIMER_HAVE_TM4 0
	109
	110	static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
	111	{
	112	return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
	113	}
a171fe39 AZ	114
	115	static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
	116	{
d353eb43	117	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	118	int i;
	119	uint32_t now_vm;
	120	uint64_t new_qemu;
	121
	122	now_vm = s->clock +
73bcb24d	123	muldiv64(now_qemu - s->lastload, s->freq, NANOSECONDS_PER_SECOND);
a171fe39 AZ	124
	125	for (i = 0; i < 4; i ++) {
	126	new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
73bcb24d	127	NANOSECONDS_PER_SECOND, s->freq);
bc72ad67	128	timer_mod(s->timer[i].qtimer, new_qemu);
a171fe39 AZ	129	}
	130	}
	131
	132	static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
	133	{
d353eb43	134	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	135	uint32_t now_vm;
	136	uint64_t new_qemu;
	137	static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
	138	int counter;
	139
	140	if (s->tm4[n].control & (1 << 7))
	141	counter = n;
	142	else
	143	counter = counters[n];
	144
	145	if (!s->tm4[counter].freq) {
bc72ad67	146	timer_del(s->tm4[n].tm.qtimer);
a171fe39 AZ	147	return;
	148	}
	149
	150	now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
	151	s->tm4[counter].lastload,
73bcb24d	152	s->tm4[counter].freq, NANOSECONDS_PER_SECOND);
a171fe39	153
3bdd58a4	154	new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
73bcb24d	155	NANOSECONDS_PER_SECOND, s->tm4[counter].freq);
bc72ad67	156	timer_mod(s->tm4[n].tm.qtimer, new_qemu);
a171fe39 AZ	157	}
a171fe39 AZ	158
a8170e5e	159	static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
b755bde3	160	unsigned size)
a171fe39	161	{
d353eb43	162	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	163	int tm = 0;
a171fe39 AZ	164
a171fe39 AZ	165	switch (offset) {
a171fe39 AZ	166	case OSMR3: tm ++;
de16017d	167	/* fall through */
a171fe39	168	case OSMR2: tm ++;
de16017d	169	/* fall through */
a171fe39	170	case OSMR1: tm ++;
de16017d	171	/* fall through */
a171fe39 AZ	172	case OSMR0:
	173	return s->timer[tm].value;
	174	case OSMR11: tm ++;
de16017d	175	/* fall through */
a171fe39	176	case OSMR10: tm ++;
de16017d	177	/* fall through */
a171fe39	178	case OSMR9: tm ++;
de16017d	179	/* fall through */
a171fe39	180	case OSMR8: tm ++;
de16017d	181	/* fall through */
a171fe39	182	case OSMR7: tm ++;
de16017d	183	/* fall through */
a171fe39	184	case OSMR6: tm ++;
de16017d	185	/* fall through */
a171fe39	186	case OSMR5: tm ++;
de16017d	187	/* fall through */
a171fe39	188	case OSMR4:
797e9542	189	if (!pxa2xx_timer_has_tm4(s))
a171fe39	190	goto badreg;
3bdd58a4	191	return s->tm4[tm].tm.value;
a171fe39	192	case OSCR:
bc72ad67	193	return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
73bcb24d	194	s->lastload, s->freq, NANOSECONDS_PER_SECOND);
a171fe39	195	case OSCR11: tm ++;
de16017d	196	/* fall through */
a171fe39	197	case OSCR10: tm ++;
de16017d	198	/* fall through */
a171fe39	199	case OSCR9: tm ++;
de16017d	200	/* fall through */
a171fe39	201	case OSCR8: tm ++;
de16017d	202	/* fall through */
a171fe39	203	case OSCR7: tm ++;
de16017d	204	/* fall through */
a171fe39	205	case OSCR6: tm ++;
de16017d	206	/* fall through */
a171fe39	207	case OSCR5: tm ++;
de16017d	208	/* fall through */
a171fe39	209	case OSCR4:
797e9542	210	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	211	goto badreg;
	212
	213	if ((tm == 9 - 4 \|\| tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
	214	if (s->tm4[tm - 1].freq)
	215	s->snapshot = s->tm4[tm - 1].clock + muldiv64(
bc72ad67	216	qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
a171fe39	217	s->tm4[tm - 1].lastload,
73bcb24d	218	s->tm4[tm - 1].freq, NANOSECONDS_PER_SECOND);
a171fe39 AZ	219	else
	220	s->snapshot = s->tm4[tm - 1].clock;
	221	}
	222
	223	if (!s->tm4[tm].freq)
	224	return s->tm4[tm].clock;
73bcb24d RS	225	return s->tm4[tm].clock +
	226	muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
	227	s->tm4[tm].lastload, s->tm4[tm].freq,
	228	NANOSECONDS_PER_SECOND);
a171fe39 AZ	229	case OIER:
	230	return s->irq_enabled;
	231	case OSSR: /* Status register */
	232	return s->events;
	233	case OWER:
	234	return s->reset3;
	235	case OMCR11: tm ++;
de16017d	236	/* fall through */
a171fe39	237	case OMCR10: tm ++;
de16017d	238	/* fall through */
a171fe39	239	case OMCR9: tm ++;
de16017d	240	/* fall through */
a171fe39	241	case OMCR8: tm ++;
de16017d	242	/* fall through */
a171fe39	243	case OMCR7: tm ++;
de16017d	244	/* fall through */
a171fe39	245	case OMCR6: tm ++;
de16017d	246	/* fall through */
a171fe39	247	case OMCR5: tm ++;
de16017d	248	/* fall through */
a171fe39	249	case OMCR4:
797e9542	250	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	251	goto badreg;
	252	return s->tm4[tm].control;
	253	case OSNR:
	254	return s->snapshot;
	255	default:
2ba63e4a PMD	256	qemu_log_mask(LOG_UNIMP,
	257	"%s: unknown register 0x%02" HWADDR_PRIx "\n",
	258	__func__, offset);
	259	break;
a171fe39	260	badreg:
2ba63e4a PMD	261	qemu_log_mask(LOG_GUEST_ERROR,
	262	"%s: incorrect register 0x%02" HWADDR_PRIx "\n",
	263	__func__, offset);
a171fe39 AZ	264	}
	265
	266	return 0;
	267	}
	268
a8170e5e	269	static void pxa2xx_timer_write(void *opaque, hwaddr offset,
b755bde3	270	uint64_t value, unsigned size)
a171fe39 AZ	271	{
a171fe39 AZ	272	int i, tm = 0;
d353eb43	273	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39	274
a171fe39 AZ	275	switch (offset) {
a171fe39 AZ	276	case OSMR3: tm ++;
de16017d	277	/* fall through */
a171fe39	278	case OSMR2: tm ++;
de16017d	279	/* fall through */
a171fe39	280	case OSMR1: tm ++;
de16017d	281	/* fall through */
a171fe39 AZ	282	case OSMR0:
a171fe39 AZ	283	s->timer[tm].value = value;
bc72ad67	284	pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
a171fe39 AZ	285	break;
a171fe39 AZ	286	case OSMR11: tm ++;
de16017d	287	/* fall through */
a171fe39	288	case OSMR10: tm ++;
de16017d	289	/* fall through */
a171fe39	290	case OSMR9: tm ++;
de16017d	291	/* fall through */
a171fe39	292	case OSMR8: tm ++;
de16017d	293	/* fall through */
a171fe39	294	case OSMR7: tm ++;
de16017d	295	/* fall through */
a171fe39	296	case OSMR6: tm ++;
de16017d	297	/* fall through */
a171fe39	298	case OSMR5: tm ++;
de16017d	299	/* fall through */
a171fe39	300	case OSMR4:
797e9542	301	if (!pxa2xx_timer_has_tm4(s))
a171fe39	302	goto badreg;
3bdd58a4	303	s->tm4[tm].tm.value = value;
bc72ad67	304	pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
a171fe39 AZ	305	break;
	306	case OSCR:
	307	s->oldclock = s->clock;
bc72ad67	308	s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
a171fe39 AZ	309	s->clock = value;
	310	pxa2xx_timer_update(s, s->lastload);
	311	break;
	312	case OSCR11: tm ++;
de16017d	313	/* fall through */
a171fe39	314	case OSCR10: tm ++;
de16017d	315	/* fall through */
a171fe39	316	case OSCR9: tm ++;
de16017d	317	/* fall through */
a171fe39	318	case OSCR8: tm ++;
de16017d	319	/* fall through */
a171fe39	320	case OSCR7: tm ++;
de16017d	321	/* fall through */
a171fe39	322	case OSCR6: tm ++;
de16017d	323	/* fall through */
a171fe39	324	case OSCR5: tm ++;
de16017d	325	/* fall through */
a171fe39	326	case OSCR4:
797e9542	327	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	328	goto badreg;
a171fe39 AZ	329	s->tm4[tm].oldclock = s->tm4[tm].clock;
bc72ad67	330	s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
a171fe39 AZ	331	s->tm4[tm].clock = value;
	332	pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
	333	break;
	334	case OIER:
	335	s->irq_enabled = value & 0xfff;
	336	break;
	337	case OSSR: /* Status register */
8034ce7d	338	value &= s->events;
a171fe39	339	s->events &= ~value;
8034ce7d AZ	340	for (i = 0; i < 4; i ++, value >>= 1)
8034ce7d AZ	341	if (value & 1)
5251d196	342	qemu_irq_lower(s->timer[i].irq);
8034ce7d AZ	343	if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
8034ce7d AZ	344	qemu_irq_lower(s->irq4);
a171fe39 AZ	345	break;
	346	case OWER: /* XXX: Reset on OSMR3 match? */
	347	s->reset3 = value;
	348	break;
	349	case OMCR7: tm ++;
de16017d	350	/* fall through */
a171fe39	351	case OMCR6: tm ++;
de16017d	352	/* fall through */
a171fe39	353	case OMCR5: tm ++;
de16017d	354	/* fall through */
a171fe39	355	case OMCR4:
797e9542	356	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	357	goto badreg;
	358	s->tm4[tm].control = value & 0x0ff;
	359	/* XXX Stop if running (shouldn't happen) */
	360	if ((value & (1 << 7)) \|\| tm == 0)
	361	s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
	362	else {
	363	s->tm4[tm].freq = 0;
bc72ad67	364	pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
a171fe39 AZ	365	}
	366	break;
	367	case OMCR11: tm ++;
de16017d	368	/* fall through */
a171fe39	369	case OMCR10: tm ++;
de16017d	370	/* fall through */
a171fe39	371	case OMCR9: tm ++;
de16017d	372	/* fall through */
a171fe39	373	case OMCR8: tm += 4;
797e9542	374	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	375	goto badreg;
	376	s->tm4[tm].control = value & 0x3ff;
	377	/* XXX Stop if running (shouldn't happen) */
	378	if ((value & (1 << 7)) \|\| !(tm & 1))
	379	s->tm4[tm].freq =
	380	pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
	381	else {
	382	s->tm4[tm].freq = 0;
bc72ad67	383	pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
a171fe39 AZ	384	}
	385	break;
	386	default:
2ba63e4a PMD	387	qemu_log_mask(LOG_UNIMP,
	388	"%s: unknown register 0x%02" HWADDR_PRIx " "
	389	"(value 0x%08" PRIx64 ")\n", __func__, offset, value);
	390	break;
a171fe39	391	badreg:
2ba63e4a PMD	392	qemu_log_mask(LOG_GUEST_ERROR,
	393	"%s: incorrect register 0x%02" HWADDR_PRIx " "
	394	"(value 0x%08" PRIx64 ")\n", __func__, offset, value);
a171fe39 AZ	395	}
	396	}
	397
b755bde3 BC	398	static const MemoryRegionOps pxa2xx_timer_ops = {
	399	.read = pxa2xx_timer_read,
	400	.write = pxa2xx_timer_write,
	401	.endianness = DEVICE_NATIVE_ENDIAN,
a171fe39 AZ	402	};
	403
	404	static void pxa2xx_timer_tick(void *opaque)
	405	{
bc24a225	406	PXA2xxTimer0 t = (PXA2xxTimer0 ) opaque;
797e9542	407	PXA2xxTimerInfo *i = t->info;
a171fe39 AZ	408
a171fe39 AZ	409	if (i->irq_enabled & (1 << t->num)) {
a171fe39	410	i->events \|= 1 << t->num;
5251d196	411	qemu_irq_raise(t->irq);
a171fe39 AZ	412	}
	413
	414	if (t->num == 3)
	415	if (i->reset3 & 1) {
	416	i->reset3 = 0;
cf83f140	417	qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
a171fe39 AZ	418	}
	419	}
	420
	421	static void pxa2xx_timer_tick4(void *opaque)
	422	{
bc24a225	423	PXA2xxTimer4 t = (PXA2xxTimer4 ) opaque;
d353eb43	424	PXA2xxTimerInfo i = (PXA2xxTimerInfo ) t->tm.info;
a171fe39	425
3bdd58a4	426	pxa2xx_timer_tick(&t->tm);
a171fe39 AZ	427	if (t->control & (1 << 3))
	428	t->clock = 0;
	429	if (t->control & (1 << 6))
bc72ad67	430	pxa2xx_timer_update4(i, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), t->tm.num - 4);
4ff927cc DES	431	if (i->events & 0xff0)
4ff927cc DES	432	qemu_irq_raise(i->irq4);
a171fe39 AZ	433	}
a171fe39 AZ	434
797e9542	435	static int pxa25x_timer_post_load(void *opaque, int version_id)
aa941b94	436	{
d353eb43	437	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
aa941b94 AZ	438	int64_t now;
	439	int i;
	440
bc72ad67	441	now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
aa941b94 AZ	442	pxa2xx_timer_update(s, now);
aa941b94 AZ	443
797e9542 DES	444	if (pxa2xx_timer_has_tm4(s))
797e9542 DES	445	for (i = 0; i < 8; i ++)
aa941b94	446	pxa2xx_timer_update4(s, now, i);
aa941b94 AZ	447
	448	return 0;
	449	}
	450
5d83e348	451	static void pxa2xx_timer_init(Object *obj)
a171fe39	452	{
5d83e348 XZ	453	PXA2xxTimerInfo *s = PXA2XX_TIMER(obj);
5d83e348 XZ	454	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
a171fe39	455
a171fe39 AZ	456	s->irq_enabled = 0;
	457	s->oldclock = 0;
	458	s->clock = 0;
bc72ad67	459	s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
a171fe39	460	s->reset3 = 0;
a171fe39	461
5d83e348 XZ	462	memory_region_init_io(&s->iomem, obj, &pxa2xx_timer_ops, s,
	463	"pxa2xx-timer", 0x00001000);
	464	sysbus_init_mmio(dev, &s->iomem);
	465	}
	466
	467	static void pxa2xx_timer_realize(DeviceState dev, Error *errp)
	468	{
	469	PXA2xxTimerInfo *s = PXA2XX_TIMER(dev);
	470	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
	471	int i;
	472
a171fe39 AZ	473	for (i = 0; i < 4; i ++) {
a171fe39 AZ	474	s->timer[i].value = 0;
5d83e348	475	sysbus_init_irq(sbd, &s->timer[i].irq);
a171fe39 AZ	476	s->timer[i].info = s;
a171fe39 AZ	477	s->timer[i].num = i;
bc72ad67	478	s->timer[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
5d83e348	479	pxa2xx_timer_tick, &s->timer[i]);
a171fe39	480	}
5d83e348	481
797e9542	482	if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
5d83e348	483	sysbus_init_irq(sbd, &s->irq4);
797e9542 DES	484
	485	for (i = 0; i < 8; i ++) {
	486	s->tm4[i].tm.value = 0;
	487	s->tm4[i].tm.info = s;
	488	s->tm4[i].tm.num = i + 4;
797e9542 DES	489	s->tm4[i].freq = 0;
797e9542 DES	490	s->tm4[i].control = 0x0;
bc72ad67	491	s->tm4[i].tm.qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
5d83e348	492	pxa2xx_timer_tick4, &s->tm4[i]);
797e9542 DES	493	}
797e9542 DES	494	}
a171fe39 AZ	495	}
a171fe39 AZ	496
797e9542 DES	497	static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
797e9542 DES	498	.name = "pxa2xx_timer0",
8034ce7d AZ	499	.version_id = 2,
8034ce7d AZ	500	.minimum_version_id = 2,
797e9542 DES	501	.fields = (VMStateField[]) {
797e9542 DES	502	VMSTATE_UINT32(value, PXA2xxTimer0),
797e9542 DES	503	VMSTATE_END_OF_LIST(),
	504	},
	505	};
	506
	507	static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
	508	.name = "pxa2xx_timer4",
	509	.version_id = 1,
	510	.minimum_version_id = 1,
797e9542 DES	511	.fields = (VMStateField[]) {
	512	VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
	513	vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
	514	VMSTATE_INT32(oldclock, PXA2xxTimer4),
	515	VMSTATE_INT32(clock, PXA2xxTimer4),
	516	VMSTATE_UINT64(lastload, PXA2xxTimer4),
	517	VMSTATE_UINT32(freq, PXA2xxTimer4),
	518	VMSTATE_UINT32(control, PXA2xxTimer4),
	519	VMSTATE_END_OF_LIST(),
	520	},
	521	};
	522
	523	static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
a171fe39	524	{
797e9542	525	return pxa2xx_timer_has_tm4(opaque);
a171fe39 AZ	526	}
a171fe39 AZ	527
797e9542 DES	528	static const VMStateDescription vmstate_pxa2xx_timer_regs = {
	529	.name = "pxa2xx_timer",
	530	.version_id = 1,
	531	.minimum_version_id = 1,
797e9542 DES	532	.post_load = pxa25x_timer_post_load,
	533	.fields = (VMStateField[]) {
	534	VMSTATE_INT32(clock, PXA2xxTimerInfo),
	535	VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
	536	VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
	537	VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
	538	vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
	539	VMSTATE_UINT32(events, PXA2xxTimerInfo),
	540	VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
	541	VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
	542	VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
	543	VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
	544	pxa2xx_timer_has_tm4_test, 0,
	545	vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
	546	VMSTATE_END_OF_LIST(),
a171fe39	547	}
797e9542 DES	548	};
797e9542 DES	549
999e12bb AL	550	static Property pxa25x_timer_dev_properties[] = {
	551	DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
	552	DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
feea4361	553	PXA2XX_TIMER_HAVE_TM4, false),
999e12bb	554	DEFINE_PROP_END_OF_LIST(),
797e9542 DES	555	};
797e9542 DES	556
999e12bb AL	557	static void pxa25x_timer_dev_class_init(ObjectClass klass, void data)
999e12bb AL	558	{
39bffca2	559	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	560
39bffca2	561	dc->desc = "PXA25x timer";
39bffca2	562	dc->props = pxa25x_timer_dev_properties;
999e12bb AL	563	}
999e12bb AL	564
8c43a6f0	565	static const TypeInfo pxa25x_timer_dev_info = {
39bffca2	566	.name = "pxa25x-timer",
feea4361	567	.parent = TYPE_PXA2XX_TIMER,
39bffca2 AL	568	.instance_size = sizeof(PXA2xxTimerInfo),
39bffca2 AL	569	.class_init = pxa25x_timer_dev_class_init,
999e12bb AL	570	};
	571
	572	static Property pxa27x_timer_dev_properties[] = {
	573	DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
	574	DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
feea4361	575	PXA2XX_TIMER_HAVE_TM4, true),
999e12bb AL	576	DEFINE_PROP_END_OF_LIST(),
	577	};
	578
	579	static void pxa27x_timer_dev_class_init(ObjectClass klass, void data)
	580	{
39bffca2	581	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	582
39bffca2	583	dc->desc = "PXA27x timer";
39bffca2	584	dc->props = pxa27x_timer_dev_properties;
999e12bb AL	585	}
999e12bb AL	586
8c43a6f0	587	static const TypeInfo pxa27x_timer_dev_info = {
39bffca2	588	.name = "pxa27x-timer",
feea4361	589	.parent = TYPE_PXA2XX_TIMER,
39bffca2 AL	590	.instance_size = sizeof(PXA2xxTimerInfo),
39bffca2 AL	591	.class_init = pxa27x_timer_dev_class_init,
797e9542 DES	592	};
797e9542 DES	593
feea4361 AF	594	static void pxa2xx_timer_class_init(ObjectClass oc, void data)
	595	{
	596	DeviceClass *dc = DEVICE_CLASS(oc);
feea4361	597
5d83e348	598	dc->realize = pxa2xx_timer_realize;
feea4361 AF	599	dc->vmsd = &vmstate_pxa2xx_timer_regs;
	600	}
	601
	602	static const TypeInfo pxa2xx_timer_type_info = {
	603	.name = TYPE_PXA2XX_TIMER,
	604	.parent = TYPE_SYS_BUS_DEVICE,
	605	.instance_size = sizeof(PXA2xxTimerInfo),
5d83e348	606	.instance_init = pxa2xx_timer_init,
feea4361 AF	607	.abstract = true,
	608	.class_init = pxa2xx_timer_class_init,
	609	};
	610
83f7d43a	611	static void pxa2xx_timer_register_types(void)
797e9542	612	{
feea4361	613	type_register_static(&pxa2xx_timer_type_info);
39bffca2 AL	614	type_register_static(&pxa25x_timer_dev_info);
39bffca2 AL	615	type_register_static(&pxa27x_timer_dev_info);
83f7d43a AF	616	}
	617
	618	type_init(pxa2xx_timer_register_types)