[qemu.git] / hw / xilinx_timer.c

/*
 * QEMU model of the Xilinx timer block.
 *
 * Copyright (c) 2009 Edgar E. Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sysbus.h"
#include "qemu-timer.h"

#define D(x)

#define R_TCSR     0
#define R_TLR      1
#define R_TCR      2
#define R_MAX      4

#define TCSR_MDT        (1<<0)
#define TCSR_UDT        (1<<1)
#define TCSR_GENT       (1<<2)
#define TCSR_CAPT       (1<<3)
#define TCSR_ARHT       (1<<4)
#define TCSR_LOAD       (1<<5)
#define TCSR_ENIT       (1<<6)
#define TCSR_ENT        (1<<7)
#define TCSR_TINT       (1<<8)
#define TCSR_PWMA       (1<<9)
#define TCSR_ENALL      (1<<10)

struct xlx_timer
{
    QEMUBH *bh;
    ptimer_state *ptimer;
    void *parent;
    int nr; /* for debug.  */

    unsigned long timer_div;

    uint32_t regs[R_MAX];
};

struct timerblock
{
    SysBusDevice busdev;
    MemoryRegion mmio;
    qemu_irq irq;
    uint32_t nr_timers;
    uint32_t freq_hz;
    struct xlx_timer *timers;
};

static inline unsigned int timer_from_addr(target_phys_addr_t addr)
{
    /* Timers get a 4x32bit control reg area each.  */
    return addr >> 2;
}

static void timer_update_irq(struct timerblock *t)
{
    unsigned int i, irq = 0;
    uint32_t csr;

    for (i = 0; i < t->nr_timers; i++) {
        csr = t->timers[i].regs[R_TCSR];
        irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
    }

    /* All timers within the same slave share a single IRQ line.  */
    qemu_set_irq(t->irq, !!irq);
}

static uint64_t
timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
{
    struct timerblock *t = opaque;
    struct xlx_timer *xt;
    uint32_t r = 0;
    unsigned int timer;

    addr >>= 2;
    timer = timer_from_addr(addr);
    xt = &t->timers[timer];
    /* Further decoding to address a specific timers reg.  */
    addr &= 0x3;
    switch (addr)
    {
        case R_TCR:
                r = ptimer_get_count(xt->ptimer);
                if (!(xt->regs[R_TCSR] & TCSR_UDT))
                    r = ~r;
                D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
                         timer, r, xt->regs[R_TCSR] & TCSR_UDT));
            break;
        default:
            if (addr < ARRAY_SIZE(xt->regs))
                r = xt->regs[addr];
            break;

    }
    D(printf("%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
    return r;
}

static void timer_enable(struct xlx_timer *xt)
{
    uint64_t count;

    D(printf("%s timer=%d down=%d\n", __func__,
              xt->nr, xt->regs[R_TCSR] & TCSR_UDT));

    ptimer_stop(xt->ptimer);

    if (xt->regs[R_TCSR] & TCSR_UDT)
        count = xt->regs[R_TLR];
    else
        count = ~0 - xt->regs[R_TLR];
    ptimer_set_count(xt->ptimer, count);
    ptimer_run(xt->ptimer, 1);
}

static void
timer_write(void *opaque, target_phys_addr_t addr,
            uint64_t val64, unsigned int size)
{
    struct timerblock *t = opaque;
    struct xlx_timer *xt;
    unsigned int timer;
    uint32_t value = val64;

    addr >>= 2;
    timer = timer_from_addr(addr);
    xt = &t->timers[timer];
    D(printf("%s addr=%x val=%x (timer=%d off=%d)\n",
             __func__, addr * 4, value, timer, addr & 3));
    /* Further decoding to address a specific timers reg.  */
    addr &= 3;
    switch (addr) 
    {
        case R_TCSR:
            if (value & TCSR_TINT)
                value &= ~TCSR_TINT;

            xt->regs[addr] = value;
            if (value & TCSR_ENT)
                timer_enable(xt);
            break;
 
        default:
            if (addr < ARRAY_SIZE(xt->regs))
                xt->regs[addr] = value;
            break;
    }
    timer_update_irq(t);
}

static const MemoryRegionOps timer_ops = {
    .read = timer_read,
    .write = timer_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4
    }
};

static void timer_hit(void *opaque)
{
    struct xlx_timer *xt = opaque;
    struct timerblock *t = xt->parent;
    D(printf("%s %d\n", __func__, timer));
    xt->regs[R_TCSR] |= TCSR_TINT;

    if (xt->regs[R_TCSR] & TCSR_ARHT)
        timer_enable(xt);
    timer_update_irq(t);
}

static int xilinx_timer_init(SysBusDevice *dev)
{
    struct timerblock *t = FROM_SYSBUS(typeof (*t), dev);
    unsigned int i;

    /* All timers share a single irq line.  */
    sysbus_init_irq(dev, &t->irq);

    /* Init all the ptimers.  */
    t->timers = g_malloc0(sizeof t->timers[0] * t->nr_timers);
    for (i = 0; i < t->nr_timers; i++) {
        struct xlx_timer *xt = &t->timers[i];

        xt->parent = t;
        xt->nr = i;
        xt->bh = qemu_bh_new(timer_hit, xt);
        xt->ptimer = ptimer_init(xt->bh);
        ptimer_set_freq(xt->ptimer, t->freq_hz);
    }

    memory_region_init_io(&t->mmio, &timer_ops, t, "xilinx-timer",
                          R_MAX * 4 * t->nr_timers);
    sysbus_init_mmio_region(dev, &t->mmio);
    return 0;
}

static SysBusDeviceInfo xilinx_timer_info = {
    .init = xilinx_timer_init,
    .qdev.name  = "xilinx,timer",
    .qdev.size  = sizeof(struct timerblock),
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("frequency", struct timerblock, freq_hz,   0),
        DEFINE_PROP_UINT32("nr-timers", struct timerblock, nr_timers, 0),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void xilinx_timer_register(void)
{
    sysbus_register_withprop(&xilinx_timer_info);
}

device_init(xilinx_timer_register)
Commit	Line	Data
388f60b1 EI	1	/*
	2	* QEMU model of the Xilinx timer block.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include "sysbus.h"
388f60b1 EI	26	#include "qemu-timer.h"
	27
	28	#define D(x)
	29
	30	#define R_TCSR 0
	31	#define R_TLR 1
	32	#define R_TCR 2
	33	#define R_MAX 4
	34
	35	#define TCSR_MDT (1<<0)
	36	#define TCSR_UDT (1<<1)
	37	#define TCSR_GENT (1<<2)
	38	#define TCSR_CAPT (1<<3)
	39	#define TCSR_ARHT (1<<4)
	40	#define TCSR_LOAD (1<<5)
	41	#define TCSR_ENIT (1<<6)
	42	#define TCSR_ENT (1<<7)
	43	#define TCSR_TINT (1<<8)
	44	#define TCSR_PWMA (1<<9)
	45	#define TCSR_ENALL (1<<10)
	46
	47	struct xlx_timer
	48	{
	49	QEMUBH *bh;
	50	ptimer_state *ptimer;
	51	void *parent;
	52	int nr; /* for debug. */
	53
	54	unsigned long timer_div;
	55
	56	uint32_t regs[R_MAX];
	57	};
	58
	59	struct timerblock
	60	{
	61	SysBusDevice busdev;
010f3f5f	62	MemoryRegion mmio;
388f60b1	63	qemu_irq irq;
ee6847d1 GH	64	uint32_t nr_timers;
ee6847d1 GH	65	uint32_t freq_hz;
388f60b1 EI	66	struct xlx_timer *timers;
	67	};
	68
c227f099	69	static inline unsigned int timer_from_addr(target_phys_addr_t addr)
388f60b1 EI	70	{
	71	/* Timers get a 4x32bit control reg area each. */
	72	return addr >> 2;
	73	}
	74
	75	static void timer_update_irq(struct timerblock *t)
	76	{
	77	unsigned int i, irq = 0;
	78	uint32_t csr;
	79
	80	for (i = 0; i < t->nr_timers; i++) {
	81	csr = t->timers[i].regs[R_TCSR];
	82	irq \|= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
	83	}
	84
	85	/* All timers within the same slave share a single IRQ line. */
	86	qemu_set_irq(t->irq, !!irq);
	87	}
	88
010f3f5f EI	89	static uint64_t
010f3f5f EI	90	timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
388f60b1 EI	91	{
	92	struct timerblock *t = opaque;
	93	struct xlx_timer *xt;
	94	uint32_t r = 0;
	95	unsigned int timer;
	96
	97	addr >>= 2;
	98	timer = timer_from_addr(addr);
	99	xt = &t->timers[timer];
	100	/* Further decoding to address a specific timers reg. */
	101	addr &= 0x3;
	102	switch (addr)
	103	{
	104	case R_TCR:
	105	r = ptimer_get_count(xt->ptimer);
	106	if (!(xt->regs[R_TCSR] & TCSR_UDT))
	107	r = ~r;
	108	D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
	109	timer, r, xt->regs[R_TCSR] & TCSR_UDT));
	110	break;
	111	default:
	112	if (addr < ARRAY_SIZE(xt->regs))
	113	r = xt->regs[addr];
	114	break;
	115
	116	}
	117	D(printf("%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
	118	return r;
	119	}
	120
	121	static void timer_enable(struct xlx_timer *xt)
	122	{
	123	uint64_t count;
	124
	125	D(printf("%s timer=%d down=%d\n", __func__,
	126	xt->nr, xt->regs[R_TCSR] & TCSR_UDT));
	127
	128	ptimer_stop(xt->ptimer);
	129
	130	if (xt->regs[R_TCSR] & TCSR_UDT)
	131	count = xt->regs[R_TLR];
	132	else
	133	count = ~0 - xt->regs[R_TLR];
	134	ptimer_set_count(xt->ptimer, count);
	135	ptimer_run(xt->ptimer, 1);
	136	}
	137
	138	static void
010f3f5f EI	139	timer_write(void *opaque, target_phys_addr_t addr,
010f3f5f EI	140	uint64_t val64, unsigned int size)
388f60b1 EI	141	{
	142	struct timerblock *t = opaque;
	143	struct xlx_timer *xt;
	144	unsigned int timer;
010f3f5f	145	uint32_t value = val64;
388f60b1 EI	146
	147	addr >>= 2;
	148	timer = timer_from_addr(addr);
	149	xt = &t->timers[timer];
	150	D(printf("%s addr=%x val=%x (timer=%d off=%d)\n",
	151	__func__, addr * 4, value, timer, addr & 3));
	152	/* Further decoding to address a specific timers reg. */
	153	addr &= 3;
	154	switch (addr)
	155	{
	156	case R_TCSR:
	157	if (value & TCSR_TINT)
	158	value &= ~TCSR_TINT;
	159
	160	xt->regs[addr] = value;
	161	if (value & TCSR_ENT)
	162	timer_enable(xt);
	163	break;
	164
	165	default:
	166	if (addr < ARRAY_SIZE(xt->regs))
	167	xt->regs[addr] = value;
	168	break;
	169	}
	170	timer_update_irq(t);
	171	}
	172
010f3f5f EI	173	static const MemoryRegionOps timer_ops = {
	174	.read = timer_read,
	175	.write = timer_write,
	176	.endianness = DEVICE_NATIVE_ENDIAN,
	177	.valid = {
	178	.min_access_size = 4,
	179	.max_access_size = 4
	180	}
388f60b1 EI	181	};
	182
	183	static void timer_hit(void *opaque)
	184	{
	185	struct xlx_timer *xt = opaque;
	186	struct timerblock *t = xt->parent;
	187	D(printf("%s %d\n", __func__, timer));
	188	xt->regs[R_TCSR] \|= TCSR_TINT;
	189
	190	if (xt->regs[R_TCSR] & TCSR_ARHT)
	191	timer_enable(xt);
	192	timer_update_irq(t);
	193	}
	194
81a322d4	195	static int xilinx_timer_init(SysBusDevice *dev)
388f60b1 EI	196	{
	197	struct timerblock t = FROM_SYSBUS(typeof (t), dev);
	198	unsigned int i;
388f60b1 EI	199
	200	/* All timers share a single irq line. */
	201	sysbus_init_irq(dev, &t->irq);
	202
	203	/* Init all the ptimers. */
7267c094	204	t->timers = g_malloc0(sizeof t->timers[0] * t->nr_timers);
388f60b1 EI	205	for (i = 0; i < t->nr_timers; i++) {
	206	struct xlx_timer *xt = &t->timers[i];
	207
	208	xt->parent = t;
	209	xt->nr = i;
	210	xt->bh = qemu_bh_new(timer_hit, xt);
	211	xt->ptimer = ptimer_init(xt->bh);
ee6847d1	212	ptimer_set_freq(xt->ptimer, t->freq_hz);
388f60b1 EI	213	}
388f60b1 EI	214
010f3f5f EI	215	memory_region_init_io(&t->mmio, &timer_ops, t, "xilinx-timer",
	216	R_MAX * 4 * t->nr_timers);
	217	sysbus_init_mmio_region(dev, &t->mmio);
81a322d4	218	return 0;
388f60b1 EI	219	}
388f60b1 EI	220
ee6847d1 GH	221	static SysBusDeviceInfo xilinx_timer_info = {
	222	.init = xilinx_timer_init,
	223	.qdev.name = "xilinx,timer",
	224	.qdev.size = sizeof(struct timerblock),
	225	.qdev.props = (Property[]) {
ea2b7271 GH	226	DEFINE_PROP_UINT32("frequency", struct timerblock, freq_hz, 0),
	227	DEFINE_PROP_UINT32("nr-timers", struct timerblock, nr_timers, 0),
	228	DEFINE_PROP_END_OF_LIST(),
ee6847d1 GH	229	}
	230	};
	231
388f60b1 EI	232	static void xilinx_timer_register(void)
388f60b1 EI	233	{
ee6847d1	234	sysbus_register_withprop(&xilinx_timer_info);
388f60b1 EI	235	}
	236
	237	device_init(xilinx_timer_register)