projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 5bc95aa2 DES |
1 | #ifndef _STRONGARM_H |
| 2 | #define _STRONGARM_H | |
| 3 | ||
| 4 | #define SA_CS0 0x00000000 | |
| 5 | #define SA_CS1 0x08000000 | |
| 6 | #define SA_CS2 0x10000000 | |
| 7 | #define SA_CS3 0x18000000 | |
| 8 | #define SA_PCMCIA_CS0 0x20000000 | |
| 9 | #define SA_PCMCIA_CS1 0x30000000 | |
| 10 | #define SA_CS4 0x40000000 | |
| 11 | #define SA_CS5 0x48000000 | |
| 12 | /* system registers here */ | |
| 13 | #define SA_SDCS0 0xc0000000 | |
| 14 | #define SA_SDCS1 0xc8000000 | |
| 15 | #define SA_SDCS2 0xd0000000 | |
| 16 | #define SA_SDCS3 0xd8000000 | |
| 17 | ||
| 18 | enum { | |
| 19 | SA_PIC_GPIO0_EDGE = 0, | |
| 20 | SA_PIC_GPIO1_EDGE, | |
| 21 | SA_PIC_GPIO2_EDGE, | |
| 22 | SA_PIC_GPIO3_EDGE, | |
| 23 | SA_PIC_GPIO4_EDGE, | |
| 24 | SA_PIC_GPIO5_EDGE, | |
| 25 | SA_PIC_GPIO6_EDGE, | |
| 26 | SA_PIC_GPIO7_EDGE, | |
| 27 | SA_PIC_GPIO8_EDGE, | |
| 28 | SA_PIC_GPIO9_EDGE, | |
| 29 | SA_PIC_GPIO10_EDGE, | |
| 30 | SA_PIC_GPIOX_EDGE, | |
| 31 | SA_PIC_LCD, | |
| 32 | SA_PIC_UDC, | |
| 33 | SA_PIC_RSVD1, | |
| 34 | SA_PIC_UART1, | |
| 35 | SA_PIC_UART2, | |
| 36 | SA_PIC_UART3, | |
| 37 | SA_PIC_MCP, | |
| 38 | SA_PIC_SSP, | |
| 39 | SA_PIC_DMA_CH0, | |
| 40 | SA_PIC_DMA_CH1, | |
| 41 | SA_PIC_DMA_CH2, | |
| 42 | SA_PIC_DMA_CH3, | |
| 43 | SA_PIC_DMA_CH4, | |
| 44 | SA_PIC_DMA_CH5, | |
| 45 | SA_PIC_OSTC0, | |
| 46 | SA_PIC_OSTC1, | |
| 47 | SA_PIC_OSTC2, | |
| 48 | SA_PIC_OSTC3, | |
| 49 | SA_PIC_RTC_HZ, | |
| 50 | SA_PIC_RTC_ALARM, | |
| 51 | }; | |
| 52 | ||
| 53 | typedef struct { | |
| 54 | CPUState *env; | |
| 55 | DeviceState *pic; | |
| 56 | DeviceState *gpio; | |
| 57 | DeviceState *ppc; | |
| 58 | DeviceState *ssp; | |
| 59 | SSIBus *ssp_bus; | |
| 60 | } StrongARMState; | |
| 61 | ||
| 62 | StrongARMState *sa1110_init(unsigned int sdram_size, const char *rev); | |
| 63 | ||
| 64 | #endif |