[qemu.git] / hw / sh_intc.h

#ifndef __SH_INTC_H__
#define __SH_INTC_H__

#include "qemu-common.h"
#include "irq.h"

typedef unsigned char intc_enum;

struct intc_vect {
    intc_enum enum_id;
    unsigned short vect;
};

#define INTC_VECT(enum_id, vect) { enum_id, vect }

struct intc_group {
    intc_enum enum_id;
    intc_enum enum_ids[32];
};

#define INTC_GROUP(enum_id, ...) { enum_id, {  __VA_ARGS__ } }

struct intc_mask_reg {
    unsigned long set_reg, clr_reg, reg_width;
    intc_enum enum_ids[32];
    unsigned long value;
};

struct intc_prio_reg {
    unsigned long set_reg, clr_reg, reg_width, field_width;
    intc_enum enum_ids[16];
    unsigned long value;
};

#define _INTC_ARRAY(a) a, ARRAY_SIZE(a)

struct intc_source {
    unsigned short vect;
    intc_enum next_enum_id;

    int asserted; /* emulates the interrupt signal line from device to intc */
    int enable_count;
    int enable_max;
    int pending; /* emulates the result of signal and masking */
    struct intc_desc *parent;
};

struct intc_desc {
    qemu_irq *irqs;
    struct intc_source *sources;
    int nr_sources;
    struct intc_mask_reg *mask_regs;
    int nr_mask_regs;
    struct intc_prio_reg *prio_regs;
    int nr_prio_regs;
    int iomemtype;
    int pending; /* number of interrupt sources that has pending set */
};

int sh_intc_get_pending_vector(struct intc_desc *desc, int imask);
struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id);
void sh_intc_toggle_source(struct intc_source *source,
			   int enable_adj, int assert_adj);

void sh_intc_register_sources(struct intc_desc *desc,
			      struct intc_vect *vectors,
			      int nr_vectors,
			      struct intc_group *groups,
			      int nr_groups);

int sh_intc_init(struct intc_desc *desc,
		 int nr_sources,
		 struct intc_mask_reg *mask_regs,
		 int nr_mask_regs,
		 struct intc_prio_reg *prio_regs,
		 int nr_prio_regs);

void sh_intc_set_irl(void *opaque, int n, int level);

#endif /* __SH_INTC_H__ */
Commit	Line	Data
80f515e6 AZ	1	#ifndef __SH_INTC_H__
	2	#define __SH_INTC_H__
	3
96e2fc41 AJ	4	#include "qemu-common.h"
	5	#include "irq.h"
	6
80f515e6 AZ	7	typedef unsigned char intc_enum;
	8
	9	struct intc_vect {
	10	intc_enum enum_id;
	11	unsigned short vect;
	12	};
	13
	14	#define INTC_VECT(enum_id, vect) { enum_id, vect }
	15
	16	struct intc_group {
	17	intc_enum enum_id;
	18	intc_enum enum_ids[32];
	19	};
	20
001faf32	21	#define INTC_GROUP(enum_id, ...) { enum_id, { __VA_ARGS__ } }
80f515e6 AZ	22
	23	struct intc_mask_reg {
	24	unsigned long set_reg, clr_reg, reg_width;
	25	intc_enum enum_ids[32];
	26	unsigned long value;
	27	};
	28
	29	struct intc_prio_reg {
	30	unsigned long set_reg, clr_reg, reg_width, field_width;
	31	intc_enum enum_ids[16];
	32	unsigned long value;
	33	};
	34
b1503cda	35	#define _INTC_ARRAY(a) a, ARRAY_SIZE(a)
80f515e6 AZ	36
	37	struct intc_source {
	38	unsigned short vect;
	39	intc_enum next_enum_id;
	40
e96e2044	41	int asserted; /* emulates the interrupt signal line from device to intc */
80f515e6 AZ	42	int enable_count;
80f515e6 AZ	43	int enable_max;
e96e2044 TS	44	int pending; /* emulates the result of signal and masking */
e96e2044 TS	45	struct intc_desc *parent;
80f515e6 AZ	46	};
	47
	48	struct intc_desc {
96e2fc41	49	qemu_irq *irqs;
80f515e6 AZ	50	struct intc_source *sources;
	51	int nr_sources;
	52	struct intc_mask_reg *mask_regs;
	53	int nr_mask_regs;
	54	struct intc_prio_reg *prio_regs;
	55	int nr_prio_regs;
80f515e6	56	int iomemtype;
e96e2044	57	int pending; /* number of interrupt sources that has pending set */
80f515e6 AZ	58	};
80f515e6 AZ	59
e96e2044	60	int sh_intc_get_pending_vector(struct intc_desc *desc, int imask);
80f515e6	61	struct intc_source sh_intc_source(struct intc_desc desc, intc_enum id);
e96e2044 TS	62	void sh_intc_toggle_source(struct intc_source *source,
e96e2044 TS	63	int enable_adj, int assert_adj);
80f515e6 AZ	64
	65	void sh_intc_register_sources(struct intc_desc *desc,
	66	struct intc_vect *vectors,
	67	int nr_vectors,
	68	struct intc_group *groups,
	69	int nr_groups);
	70
	71	int sh_intc_init(struct intc_desc *desc,
	72	int nr_sources,
	73	struct intc_mask_reg *mask_regs,
	74	int nr_mask_regs,
	75	struct intc_prio_reg *prio_regs,
	76	int nr_prio_regs);
	77
c6d86a33 AZ	78	void sh_intc_set_irl(void *opaque, int n, int level);
c6d86a33 AZ	79
80f515e6	80	#endif /* __SH_INTC_H__ */