[qemu.git] / target-microblaze / helper.c

/*
 *  MicroBlaze helper routines.
 *
 *  Copyright (c) 2009 Edgar E. Iglesias <[email protected]>
 *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "qemu/host-utils.h"

#define D(x)

#if defined(CONFIG_USER_ONLY)

void mb_cpu_do_interrupt(CPUState *cs)
{
    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
    CPUMBState *env = &cpu->env;

    cs->exception_index = -1;
    env->res_addr = RES_ADDR_NONE;
    env->regs[14] = env->sregs[SR_PC];
}

int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
                            int mmu_idx)
{
    cs->exception_index = 0xaa;
    cpu_dump_state(cs, stderr, fprintf, 0);
    return 1;
}

#else /* !CONFIG_USER_ONLY */

int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
                            int mmu_idx)
{
    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
    CPUMBState *env = &cpu->env;
    unsigned int hit;
    unsigned int mmu_available;
    int r = 1;
    int prot;

    mmu_available = 0;
    if (env->pvr.regs[0] & PVR0_USE_MMU) {
        mmu_available = 1;
        if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
            && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
            mmu_available = 0;
        }
    }

    /* Translate if the MMU is available and enabled.  */
    if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
        target_ulong vaddr, paddr;
        struct microblaze_mmu_lookup lu;

        hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
        if (hit) {
            vaddr = address & TARGET_PAGE_MASK;
            paddr = lu.paddr + vaddr - lu.vaddr;

            qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n",
                    mmu_idx, vaddr, paddr, lu.prot);
            tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
            r = 0;
        } else {
            env->sregs[SR_EAR] = address;
            qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n",
                                        mmu_idx, address);

            switch (lu.err) {
                case ERR_PROT:
                    env->sregs[SR_ESR] = rw == 2 ? 17 : 16;
                    env->sregs[SR_ESR] |= (rw == 1) << 10;
                    break;
                case ERR_MISS:
                    env->sregs[SR_ESR] = rw == 2 ? 19 : 18;
                    env->sregs[SR_ESR] |= (rw == 1) << 10;
                    break;
                default:
                    abort();
                    break;
            }

            if (cs->exception_index == EXCP_MMU) {
                cpu_abort(cs, "recursive faults\n");
            }

            /* TLB miss.  */
            cs->exception_index = EXCP_MMU;
        }
    } else {
        /* MMU disabled or not available.  */
        address &= TARGET_PAGE_MASK;
        prot = PAGE_BITS;
        tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
        r = 0;
    }
    return r;
}

void mb_cpu_do_interrupt(CPUState *cs)
{
    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
    CPUMBState *env = &cpu->env;
    uint32_t t;

    /* IMM flag cannot propagate across a branch and into the dslot.  */
    assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
    assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
/*    assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions.  */
    env->res_addr = RES_ADDR_NONE;
    switch (cs->exception_index) {
        case EXCP_HW_EXCP:
            if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
                qemu_log("Exception raised on system without exceptions!\n");
                return;
            }

            env->regs[17] = env->sregs[SR_PC] + 4;
            env->sregs[SR_ESR] &= ~(1 << 12);

            /* Exception breaks branch + dslot sequence?  */
            if (env->iflags & D_FLAG) {
                env->sregs[SR_ESR] |= 1 << 12 ;
                env->sregs[SR_BTR] = env->btarget;
            }

            /* Disable the MMU.  */
            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
            env->sregs[SR_MSR] |= t;
            /* Exception in progress.  */
            env->sregs[SR_MSR] |= MSR_EIP;

            qemu_log_mask(CPU_LOG_INT,
                          "hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
                          env->sregs[SR_PC], env->sregs[SR_EAR],
                          env->sregs[SR_ESR], env->iflags);
            log_cpu_state_mask(CPU_LOG_INT, cs, 0);
            env->iflags &= ~(IMM_FLAG | D_FLAG);
            env->sregs[SR_PC] = cpu->base_vectors + 0x20;
            break;

        case EXCP_MMU:
            env->regs[17] = env->sregs[SR_PC];

            env->sregs[SR_ESR] &= ~(1 << 12);
            /* Exception breaks branch + dslot sequence?  */
            if (env->iflags & D_FLAG) {
                D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
                env->sregs[SR_ESR] |= 1 << 12 ;
                env->sregs[SR_BTR] = env->btarget;

                /* Reexecute the branch.  */
                env->regs[17] -= 4;
                /* was the branch immprefixed?.  */
                if (env->bimm) {
                    qemu_log_mask(CPU_LOG_INT,
                                  "bimm exception at pc=%x iflags=%x\n",
                                  env->sregs[SR_PC], env->iflags);
                    env->regs[17] -= 4;
                    log_cpu_state_mask(CPU_LOG_INT, cs, 0);
                }
            } else if (env->iflags & IMM_FLAG) {
                D(qemu_log("IMM_FLAG set at exception\n"));
                env->regs[17] -= 4;
            }

            /* Disable the MMU.  */
            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
            env->sregs[SR_MSR] |= t;
            /* Exception in progress.  */
            env->sregs[SR_MSR] |= MSR_EIP;

            qemu_log_mask(CPU_LOG_INT,
                          "exception at pc=%x ear=%x iflags=%x\n",
                          env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
            log_cpu_state_mask(CPU_LOG_INT, cs, 0);
            env->iflags &= ~(IMM_FLAG | D_FLAG);
            env->sregs[SR_PC] = cpu->base_vectors + 0x20;
            break;

        case EXCP_IRQ:
            assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)));
            assert(env->sregs[SR_MSR] & MSR_IE);
            assert(!(env->iflags & D_FLAG));

            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;

#if 0
#include "disas/disas.h"

/* Useful instrumentation when debugging interrupt issues in either
   the models or in sw.  */
            {
                const char *sym;

                sym = lookup_symbol(env->sregs[SR_PC]);
                if (sym
                    && (!strcmp("netif_rx", sym)
                        || !strcmp("process_backlog", sym))) {

                    qemu_log(
                         "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
                         sym);

                    log_cpu_state(cs, 0);
                }
            }
#endif
            qemu_log_mask(CPU_LOG_INT,
                         "interrupt at pc=%x msr=%x %x iflags=%x\n",
                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);

            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
                                    | MSR_UM | MSR_IE);
            env->sregs[SR_MSR] |= t;

            env->regs[14] = env->sregs[SR_PC];
            env->sregs[SR_PC] = cpu->base_vectors + 0x10;
            //log_cpu_state_mask(CPU_LOG_INT, cs, 0);
            break;

        case EXCP_BREAK:
        case EXCP_HW_BREAK:
            assert(!(env->iflags & IMM_FLAG));
            assert(!(env->iflags & D_FLAG));
            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
            qemu_log_mask(CPU_LOG_INT,
                        "break at pc=%x msr=%x %x iflags=%x\n",
                        env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
            log_cpu_state_mask(CPU_LOG_INT, cs, 0);
            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
            env->sregs[SR_MSR] |= t;
            env->sregs[SR_MSR] |= MSR_BIP;
            if (cs->exception_index == EXCP_HW_BREAK) {
                env->regs[16] = env->sregs[SR_PC];
                env->sregs[SR_MSR] |= MSR_BIP;
                env->sregs[SR_PC] = cpu->base_vectors + 0x18;
            } else
                env->sregs[SR_PC] = env->btarget;
            break;
        default:
            cpu_abort(cs, "unhandled exception type=%d\n",
                      cs->exception_index);
            break;
    }
}

hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
    CPUMBState *env = &cpu->env;
    target_ulong vaddr, paddr = 0;
    struct microblaze_mmu_lookup lu;
    unsigned int hit;

    if (env->sregs[SR_MSR] & MSR_VM) {
        hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
        if (hit) {
            vaddr = addr & TARGET_PAGE_MASK;
            paddr = lu.paddr + vaddr - lu.vaddr;
        } else
            paddr = 0; /* ???.  */
    } else
        paddr = addr & TARGET_PAGE_MASK;

    return paddr;
}
#endif

bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
    CPUMBState *env = &cpu->env;

    if ((interrupt_request & CPU_INTERRUPT_HARD)
        && (env->sregs[SR_MSR] & MSR_IE)
        && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
        && !(env->iflags & (D_FLAG | IMM_FLAG))) {
        cs->exception_index = EXCP_IRQ;
        mb_cpu_do_interrupt(cs);
        return true;
    }
    return false;
}
Commit	Line	Data
4acb54ba EI	1	/*
	2	* MicroBlaze helper routines.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias <[email protected]>
dadc1064	5	* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
4acb54ba EI	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba EI	19	*/
4acb54ba EI	20
4acb54ba	21	#include "cpu.h"
1de7afc9	22	#include "qemu/host-utils.h"
4acb54ba EI	23
4acb54ba EI	24	#define D(x)
4acb54ba EI	25
	26	#if defined(CONFIG_USER_ONLY)
	27
97a8ea5a	28	void mb_cpu_do_interrupt(CPUState *cs)
4acb54ba	29	{
97a8ea5a AF	30	MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
	31	CPUMBState *env = &cpu->env;
	32
27103424	33	cs->exception_index = -1;
8cc9b43f	34	env->res_addr = RES_ADDR_NONE;
4acb54ba EI	35	env->regs[14] = env->sregs[SR_PC];
	36	}
	37
7510454e	38	int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
97b348e7	39	int mmu_idx)
4acb54ba	40	{
27103424	41	cs->exception_index = 0xaa;
7510454e	42	cpu_dump_state(cs, stderr, fprintf, 0);
4acb54ba EI	43	return 1;
	44	}
	45
4acb54ba EI	46	#else /* !CONFIG_USER_ONLY */
4acb54ba EI	47
7510454e AF	48	int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
7510454e AF	49	int mmu_idx)
4acb54ba	50	{
7510454e AF	51	MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
7510454e AF	52	CPUMBState *env = &cpu->env;
4acb54ba EI	53	unsigned int hit;
	54	unsigned int mmu_available;
	55	int r = 1;
	56	int prot;
	57
	58	mmu_available = 0;
	59	if (env->pvr.regs[0] & PVR0_USE_MMU) {
	60	mmu_available = 1;
	61	if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
	62	&& (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
	63	mmu_available = 0;
	64	}
	65	}
	66
	67	/* Translate if the MMU is available and enabled. */
	68	if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
	69	target_ulong vaddr, paddr;
	70	struct microblaze_mmu_lookup lu;
	71
	72	hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
	73	if (hit) {
	74	vaddr = address & TARGET_PAGE_MASK;
	75	paddr = lu.paddr + vaddr - lu.vaddr;
	76
339aaf5b AP	77	qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n",
339aaf5b AP	78	mmu_idx, vaddr, paddr, lu.prot);
0c591eb0	79	tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
d4c430a8	80	r = 0;
4acb54ba EI	81	} else {
4acb54ba EI	82	env->sregs[SR_EAR] = address;
339aaf5b AP	83	qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n",
339aaf5b AP	84	mmu_idx, address);
4acb54ba EI	85
	86	switch (lu.err) {
	87	case ERR_PROT:
	88	env->sregs[SR_ESR] = rw == 2 ? 17 : 16;
	89	env->sregs[SR_ESR] \|= (rw == 1) << 10;
	90	break;
	91	case ERR_MISS:
	92	env->sregs[SR_ESR] = rw == 2 ? 19 : 18;
	93	env->sregs[SR_ESR] \|= (rw == 1) << 10;
	94	break;
	95	default:
	96	abort();
	97	break;
	98	}
	99
27103424	100	if (cs->exception_index == EXCP_MMU) {
a47dddd7	101	cpu_abort(cs, "recursive faults\n");
4acb54ba EI	102	}
	103
	104	/* TLB miss. */
27103424	105	cs->exception_index = EXCP_MMU;
4acb54ba EI	106	}
	107	} else {
	108	/* MMU disabled or not available. */
	109	address &= TARGET_PAGE_MASK;
	110	prot = PAGE_BITS;
0c591eb0	111	tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
d4c430a8	112	r = 0;
4acb54ba EI	113	}
	114	return r;
	115	}
	116
97a8ea5a	117	void mb_cpu_do_interrupt(CPUState *cs)
4acb54ba	118	{
97a8ea5a AF	119	MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
97a8ea5a AF	120	CPUMBState *env = &cpu->env;
4acb54ba EI	121	uint32_t t;
4acb54ba EI	122
5225d669	123	/* IMM flag cannot propagate across a branch and into the dslot. */
4acb54ba EI	124	assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
	125	assert(!(env->iflags & (DRTI_FLAG \| DRTE_FLAG \| DRTB_FLAG)));
	126	/* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */
8cc9b43f	127	env->res_addr = RES_ADDR_NONE;
27103424	128	switch (cs->exception_index) {
cedb936b EI	129	case EXCP_HW_EXCP:
	130	if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
	131	qemu_log("Exception raised on system without exceptions!\n");
	132	return;
	133	}
	134
	135	env->regs[17] = env->sregs[SR_PC] + 4;
	136	env->sregs[SR_ESR] &= ~(1 << 12);
	137
	138	/* Exception breaks branch + dslot sequence? */
	139	if (env->iflags & D_FLAG) {
	140	env->sregs[SR_ESR] \|= 1 << 12 ;
	141	env->sregs[SR_BTR] = env->btarget;
	142	}
	143
	144	/* Disable the MMU. */
	145	t = (env->sregs[SR_MSR] & (MSR_VM \| MSR_UM)) << 1;
	146	env->sregs[SR_MSR] &= ~(MSR_VMS \| MSR_UMS \| MSR_VM \| MSR_UM);
	147	env->sregs[SR_MSR] \|= t;
	148	/* Exception in progress. */
	149	env->sregs[SR_MSR] \|= MSR_EIP;
	150
	151	qemu_log_mask(CPU_LOG_INT,
	152	"hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
	153	env->sregs[SR_PC], env->sregs[SR_EAR],
	154	env->sregs[SR_ESR], env->iflags);
a0762859	155	log_cpu_state_mask(CPU_LOG_INT, cs, 0);
cedb936b	156	env->iflags &= ~(IMM_FLAG \| D_FLAG);
a1bff71c	157	env->sregs[SR_PC] = cpu->base_vectors + 0x20;
cedb936b EI	158	break;
cedb936b EI	159
4acb54ba EI	160	case EXCP_MMU:
	161	env->regs[17] = env->sregs[SR_PC];
	162
a75cf0c5	163	env->sregs[SR_ESR] &= ~(1 << 12);
4acb54ba EI	164	/* Exception breaks branch + dslot sequence? */
	165	if (env->iflags & D_FLAG) {
	166	D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
	167	env->sregs[SR_ESR] \|= 1 << 12 ;
	168	env->sregs[SR_BTR] = env->btarget;
	169
	170	/* Reexecute the branch. */
	171	env->regs[17] -= 4;
	172	/* was the branch immprefixed?. */
	173	if (env->bimm) {
	174	qemu_log_mask(CPU_LOG_INT,
	175	"bimm exception at pc=%x iflags=%x\n",
	176	env->sregs[SR_PC], env->iflags);
	177	env->regs[17] -= 4;
a0762859	178	log_cpu_state_mask(CPU_LOG_INT, cs, 0);
4acb54ba EI	179	}
	180	} else if (env->iflags & IMM_FLAG) {
	181	D(qemu_log("IMM_FLAG set at exception\n"));
	182	env->regs[17] -= 4;
	183	}
	184
	185	/* Disable the MMU. */
	186	t = (env->sregs[SR_MSR] & (MSR_VM \| MSR_UM)) << 1;
	187	env->sregs[SR_MSR] &= ~(MSR_VMS \| MSR_UMS \| MSR_VM \| MSR_UM);
	188	env->sregs[SR_MSR] \|= t;
	189	/* Exception in progress. */
	190	env->sregs[SR_MSR] \|= MSR_EIP;
	191
	192	qemu_log_mask(CPU_LOG_INT,
	193	"exception at pc=%x ear=%x iflags=%x\n",
	194	env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
a0762859	195	log_cpu_state_mask(CPU_LOG_INT, cs, 0);
4acb54ba	196	env->iflags &= ~(IMM_FLAG \| D_FLAG);
a1bff71c	197	env->sregs[SR_PC] = cpu->base_vectors + 0x20;
4acb54ba EI	198	break;
	199
	200	case EXCP_IRQ:
	201	assert(!(env->sregs[SR_MSR] & (MSR_EIP \| MSR_BIP)));
	202	assert(env->sregs[SR_MSR] & MSR_IE);
	203	assert(!(env->iflags & D_FLAG));
	204
	205	t = (env->sregs[SR_MSR] & (MSR_VM \| MSR_UM)) << 1;
	206
	207	#if 0
76cad711	208	#include "disas/disas.h"
4acb54ba EI	209
	210	/* Useful instrumentation when debugging interrupt issues in either
	211	the models or in sw. */
	212	{
	213	const char *sym;
	214
	215	sym = lookup_symbol(env->sregs[SR_PC]);
	216	if (sym
	217	&& (!strcmp("netif_rx", sym)
	218	\|\| !strcmp("process_backlog", sym))) {
	219
	220	qemu_log(
	221	"interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
	222	env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
	223	sym);
	224
a0762859	225	log_cpu_state(cs, 0);
4acb54ba EI	226	}
	227	}
	228	#endif
	229	qemu_log_mask(CPU_LOG_INT,
	230	"interrupt at pc=%x msr=%x %x iflags=%x\n",
	231	env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
	232
	233	env->sregs[SR_MSR] &= ~(MSR_VMS \| MSR_UMS \| MSR_VM \
	234	\| MSR_UM \| MSR_IE);
	235	env->sregs[SR_MSR] \|= t;
	236
	237	env->regs[14] = env->sregs[SR_PC];
a1bff71c	238	env->sregs[SR_PC] = cpu->base_vectors + 0x10;
a0762859	239	//log_cpu_state_mask(CPU_LOG_INT, cs, 0);
4acb54ba EI	240	break;
	241
	242	case EXCP_BREAK:
	243	case EXCP_HW_BREAK:
	244	assert(!(env->iflags & IMM_FLAG));
	245	assert(!(env->iflags & D_FLAG));
	246	t = (env->sregs[SR_MSR] & (MSR_VM \| MSR_UM)) << 1;
	247	qemu_log_mask(CPU_LOG_INT,
	248	"break at pc=%x msr=%x %x iflags=%x\n",
	249	env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
a0762859	250	log_cpu_state_mask(CPU_LOG_INT, cs, 0);
4acb54ba EI	251	env->sregs[SR_MSR] &= ~(MSR_VMS \| MSR_UMS \| MSR_VM \| MSR_UM);
	252	env->sregs[SR_MSR] \|= t;
	253	env->sregs[SR_MSR] \|= MSR_BIP;
27103424	254	if (cs->exception_index == EXCP_HW_BREAK) {
4acb54ba EI	255	env->regs[16] = env->sregs[SR_PC];
4acb54ba EI	256	env->sregs[SR_MSR] \|= MSR_BIP;
a1bff71c	257	env->sregs[SR_PC] = cpu->base_vectors + 0x18;
4acb54ba EI	258	} else
	259	env->sregs[SR_PC] = env->btarget;
	260	break;
	261	default:
a47dddd7	262	cpu_abort(cs, "unhandled exception type=%d\n",
27103424	263	cs->exception_index);
4acb54ba EI	264	break;
	265	}
	266	}
	267
00b941e5	268	hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
4acb54ba	269	{
00b941e5 AF	270	MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
00b941e5 AF	271	CPUMBState *env = &cpu->env;
4acb54ba EI	272	target_ulong vaddr, paddr = 0;
	273	struct microblaze_mmu_lookup lu;
	274	unsigned int hit;
	275
	276	if (env->sregs[SR_MSR] & MSR_VM) {
	277	hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
	278	if (hit) {
	279	vaddr = addr & TARGET_PAGE_MASK;
	280	paddr = lu.paddr + vaddr - lu.vaddr;
	281	} else
	282	paddr = 0; /* ???. */
	283	} else
	284	paddr = addr & TARGET_PAGE_MASK;
	285
	286	return paddr;
	287	}
	288	#endif
29cd33d3 RH	289
	290	bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
	291	{
	292	MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
	293	CPUMBState *env = &cpu->env;
	294
	295	if ((interrupt_request & CPU_INTERRUPT_HARD)
	296	&& (env->sregs[SR_MSR] & MSR_IE)
	297	&& !(env->sregs[SR_MSR] & (MSR_EIP \| MSR_BIP))
	298	&& !(env->iflags & (D_FLAG \| IMM_FLAG))) {
	299	cs->exception_index = EXCP_IRQ;
	300	mb_cpu_do_interrupt(cs);
	301	return true;
	302	}
	303	return false;
	304	}