projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 72b0cd35 PM |
1 | /* |
| 2 | * KVM ARM ABI constant definitions | |
| 3 | * | |
| 4 | * Copyright (c) 2013 Linaro Limited | |
| 5 | * | |
| 6 | * Provide versions of KVM constant defines that can be used even | |
| 7 | * when CONFIG_KVM is not set and we don't have access to the | |
| 8 | * KVM headers. If CONFIG_KVM is set, we do a compile-time check | |
| 9 | * that we haven't got out of sync somehow. | |
| 10 | * | |
| 11 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
| 12 | * See the COPYING file in the top-level directory. | |
| 13 | */ | |
| 14 | #ifndef ARM_KVM_CONSTS_H | |
| 15 | #define ARM_KVM_CONSTS_H | |
| 16 | ||
| 17 | #ifdef CONFIG_KVM | |
| 18 | #include "qemu/compiler.h" | |
| 19 | #include <linux/kvm.h> | |
| 863714ba | 20 | #include <linux/psci.h> |
| 72b0cd35 PM |
21 | |
| 22 | #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(X != Y) | |
| 23 | ||
| 24 | #else | |
| 25 | #define MISMATCH_CHECK(X, Y) | |
| 26 | #endif | |
| 27 | ||
| 28 | #define CP_REG_SIZE_SHIFT 52 | |
| 29 | #define CP_REG_SIZE_MASK 0x00f0000000000000ULL | |
| 30 | #define CP_REG_SIZE_U32 0x0020000000000000ULL | |
| 31 | #define CP_REG_SIZE_U64 0x0030000000000000ULL | |
| 32 | #define CP_REG_ARM 0x4000000000000000ULL | |
| f5a0a5a5 | 33 | #define CP_REG_ARCH_MASK 0xff00000000000000ULL |
| 72b0cd35 PM |
34 | |
| 35 | MISMATCH_CHECK(CP_REG_SIZE_SHIFT, KVM_REG_SIZE_SHIFT) | |
| 36 | MISMATCH_CHECK(CP_REG_SIZE_MASK, KVM_REG_SIZE_MASK) | |
| 37 | MISMATCH_CHECK(CP_REG_SIZE_U32, KVM_REG_SIZE_U32) | |
| 38 | MISMATCH_CHECK(CP_REG_SIZE_U64, KVM_REG_SIZE_U64) | |
| 39 | MISMATCH_CHECK(CP_REG_ARM, KVM_REG_ARM) | |
| f5a0a5a5 | 40 | MISMATCH_CHECK(CP_REG_ARCH_MASK, KVM_REG_ARCH_MASK) |
| 72b0cd35 | 41 | |
| a65c9c17 CD |
42 | #define QEMU_PSCI_0_1_FN_BASE 0x95c1ba5e |
| 43 | #define QEMU_PSCI_0_1_FN(n) (QEMU_PSCI_0_1_FN_BASE + (n)) | |
| 44 | #define QEMU_PSCI_0_1_FN_CPU_SUSPEND QEMU_PSCI_0_1_FN(0) | |
| 45 | #define QEMU_PSCI_0_1_FN_CPU_OFF QEMU_PSCI_0_1_FN(1) | |
| 46 | #define QEMU_PSCI_0_1_FN_CPU_ON QEMU_PSCI_0_1_FN(2) | |
| 47 | #define QEMU_PSCI_0_1_FN_MIGRATE QEMU_PSCI_0_1_FN(3) | |
| a22ec1e6 | 48 | |
| a65c9c17 CD |
49 | MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_SUSPEND, KVM_PSCI_FN_CPU_SUSPEND) |
| 50 | MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_OFF, KVM_PSCI_FN_CPU_OFF) | |
| 51 | MISMATCH_CHECK(QEMU_PSCI_0_1_FN_CPU_ON, KVM_PSCI_FN_CPU_ON) | |
| 52 | MISMATCH_CHECK(QEMU_PSCI_0_1_FN_MIGRATE, KVM_PSCI_FN_MIGRATE) | |
| a22ec1e6 | 53 | |
| 863714ba CD |
54 | #define QEMU_PSCI_0_2_FN_BASE 0x84000000 |
| 55 | #define QEMU_PSCI_0_2_FN(n) (QEMU_PSCI_0_2_FN_BASE + (n)) | |
| 56 | ||
| 57 | #define QEMU_PSCI_0_2_64BIT 0x40000000 | |
| 58 | #define QEMU_PSCI_0_2_FN64_BASE \ | |
| 59 | (QEMU_PSCI_0_2_FN_BASE + QEMU_PSCI_0_2_64BIT) | |
| 60 | #define QEMU_PSCI_0_2_FN64(n) (QEMU_PSCI_0_2_FN64_BASE + (n)) | |
| 61 | ||
| 3df53cdf | 62 | #define QEMU_PSCI_0_2_FN_PSCI_VERSION QEMU_PSCI_0_2_FN(0) |
| 863714ba CD |
63 | #define QEMU_PSCI_0_2_FN_CPU_SUSPEND QEMU_PSCI_0_2_FN(1) |
| 64 | #define QEMU_PSCI_0_2_FN_CPU_OFF QEMU_PSCI_0_2_FN(2) | |
| 65 | #define QEMU_PSCI_0_2_FN_CPU_ON QEMU_PSCI_0_2_FN(3) | |
| 3df53cdf | 66 | #define QEMU_PSCI_0_2_FN_AFFINITY_INFO QEMU_PSCI_0_2_FN(4) |
| 863714ba | 67 | #define QEMU_PSCI_0_2_FN_MIGRATE QEMU_PSCI_0_2_FN(5) |
| 3df53cdf AB |
68 | #define QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE QEMU_PSCI_0_2_FN(6) |
| 69 | #define QEMU_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU QEMU_PSCI_0_2_FN(7) | |
| 70 | #define QEMU_PSCI_0_2_FN_SYSTEM_OFF QEMU_PSCI_0_2_FN(8) | |
| 71 | #define QEMU_PSCI_0_2_FN_SYSTEM_RESET QEMU_PSCI_0_2_FN(9) | |
| 863714ba CD |
72 | |
| 73 | #define QEMU_PSCI_0_2_FN64_CPU_SUSPEND QEMU_PSCI_0_2_FN64(1) | |
| 74 | #define QEMU_PSCI_0_2_FN64_CPU_OFF QEMU_PSCI_0_2_FN64(2) | |
| 75 | #define QEMU_PSCI_0_2_FN64_CPU_ON QEMU_PSCI_0_2_FN64(3) | |
| 3df53cdf | 76 | #define QEMU_PSCI_0_2_FN64_AFFINITY_INFO QEMU_PSCI_0_2_FN64(4) |
| 863714ba CD |
77 | #define QEMU_PSCI_0_2_FN64_MIGRATE QEMU_PSCI_0_2_FN64(5) |
| 78 | ||
| 79 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_SUSPEND, PSCI_0_2_FN_CPU_SUSPEND) | |
| 80 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_OFF, PSCI_0_2_FN_CPU_OFF) | |
| 81 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_ON, PSCI_0_2_FN_CPU_ON) | |
| 82 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN_MIGRATE, PSCI_0_2_FN_MIGRATE) | |
| 83 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_SUSPEND, PSCI_0_2_FN64_CPU_SUSPEND) | |
| 84 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_ON, PSCI_0_2_FN64_CPU_ON) | |
| 85 | MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_MIGRATE, PSCI_0_2_FN64_MIGRATE) | |
| 86 | ||
| 3df53cdf AB |
87 | /* PSCI v0.2 return values used by TCG emulation of PSCI */ |
| 88 | ||
| 89 | /* No Trusted OS migration to worry about when offlining CPUs */ | |
| 90 | #define QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED 2 | |
| 91 | ||
| 92 | /* We implement version 0.2 only */ | |
| 93 | #define QEMU_PSCI_0_2_RET_VERSION_0_2 2 | |
| 94 | ||
| 95 | MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_MP) | |
| 96 | MISMATCH_CHECK(QEMU_PSCI_0_2_RET_VERSION_0_2, | |
| 97 | (PSCI_VERSION_MAJOR(0) | PSCI_VERSION_MINOR(2))) | |
| 98 | ||
| 99 | /* PSCI return values (inclusive of all PSCI versions) */ | |
| 100 | #define QEMU_PSCI_RET_SUCCESS 0 | |
| 101 | #define QEMU_PSCI_RET_NOT_SUPPORTED -1 | |
| 102 | #define QEMU_PSCI_RET_INVALID_PARAMS -2 | |
| 103 | #define QEMU_PSCI_RET_DENIED -3 | |
| 104 | #define QEMU_PSCI_RET_ALREADY_ON -4 | |
| 105 | #define QEMU_PSCI_RET_ON_PENDING -5 | |
| 106 | #define QEMU_PSCI_RET_INTERNAL_FAILURE -6 | |
| 107 | #define QEMU_PSCI_RET_NOT_PRESENT -7 | |
| 108 | #define QEMU_PSCI_RET_DISABLED -8 | |
| 109 | ||
| 110 | MISMATCH_CHECK(QEMU_PSCI_RET_SUCCESS, PSCI_RET_SUCCESS) | |
| 111 | MISMATCH_CHECK(QEMU_PSCI_RET_NOT_SUPPORTED, PSCI_RET_NOT_SUPPORTED) | |
| 112 | MISMATCH_CHECK(QEMU_PSCI_RET_INVALID_PARAMS, PSCI_RET_INVALID_PARAMS) | |
| 113 | MISMATCH_CHECK(QEMU_PSCI_RET_DENIED, PSCI_RET_DENIED) | |
| 114 | MISMATCH_CHECK(QEMU_PSCI_RET_ALREADY_ON, PSCI_RET_ALREADY_ON) | |
| 115 | MISMATCH_CHECK(QEMU_PSCI_RET_ON_PENDING, PSCI_RET_ON_PENDING) | |
| 116 | MISMATCH_CHECK(QEMU_PSCI_RET_INTERNAL_FAILURE, PSCI_RET_INTERNAL_FAILURE) | |
| 117 | MISMATCH_CHECK(QEMU_PSCI_RET_NOT_PRESENT, PSCI_RET_NOT_PRESENT) | |
| 118 | MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED) | |
| 119 | ||
| 83e9a4ae PM |
120 | /* Note that KVM uses overlapping values for AArch32 and AArch64 |
| 121 | * target CPU numbers. AArch32 targets: | |
| 122 | */ | |
| 3541addc | 123 | #define QEMU_KVM_ARM_TARGET_CORTEX_A15 0 |
| 83e9a4ae PM |
124 | #define QEMU_KVM_ARM_TARGET_CORTEX_A7 1 |
| 125 | ||
| 126 | /* AArch64 targets: */ | |
| 127 | #define QEMU_KVM_ARM_TARGET_AEM_V8 0 | |
| 128 | #define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1 | |
| 129 | #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2 | |
| 3541addc PM |
130 | |
| 131 | /* There's no kernel define for this: sentinel value which | |
| 132 | * matches no KVM target value for either 64 or 32 bit | |
| 133 | */ | |
| 134 | #define QEMU_KVM_ARM_TARGET_NONE UINT_MAX | |
| 135 | ||
| 83e9a4ae PM |
136 | #ifdef TARGET_AARCH64 |
| 137 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8) | |
| 138 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8) | |
| 139 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57) | |
| 140 | #else | |
| 3541addc | 141 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15) |
| 83e9a4ae | 142 | MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7) |
| 3541addc PM |
143 | #endif |
| 144 | ||
| f5a0a5a5 PM |
145 | #define CP_REG_ARM64 0x6000000000000000ULL |
| 146 | #define CP_REG_ARM_COPROC_MASK 0x000000000FFF0000 | |
| 147 | #define CP_REG_ARM_COPROC_SHIFT 16 | |
| 148 | #define CP_REG_ARM64_SYSREG (0x0013 << CP_REG_ARM_COPROC_SHIFT) | |
| 149 | #define CP_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 | |
| 150 | #define CP_REG_ARM64_SYSREG_OP0_SHIFT 14 | |
| 151 | #define CP_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 | |
| 152 | #define CP_REG_ARM64_SYSREG_OP1_SHIFT 11 | |
| 153 | #define CP_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 | |
| 154 | #define CP_REG_ARM64_SYSREG_CRN_SHIFT 7 | |
| 155 | #define CP_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 | |
| 156 | #define CP_REG_ARM64_SYSREG_CRM_SHIFT 3 | |
| 157 | #define CP_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 | |
| 158 | #define CP_REG_ARM64_SYSREG_OP2_SHIFT 0 | |
| 159 | ||
| 160 | /* No kernel define but it's useful to QEMU */ | |
| 161 | #define CP_REG_ARM64_SYSREG_CP (CP_REG_ARM64_SYSREG >> CP_REG_ARM_COPROC_SHIFT) | |
| 162 | ||
| 163 | #ifdef TARGET_AARCH64 | |
| 164 | MISMATCH_CHECK(CP_REG_ARM64, KVM_REG_ARM64) | |
| 165 | MISMATCH_CHECK(CP_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_MASK) | |
| 166 | MISMATCH_CHECK(CP_REG_ARM_COPROC_SHIFT, KVM_REG_ARM_COPROC_SHIFT) | |
| 167 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG, KVM_REG_ARM64_SYSREG) | |
| 168 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_MASK, KVM_REG_ARM64_SYSREG_OP0_MASK) | |
| 169 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP0_SHIFT, KVM_REG_ARM64_SYSREG_OP0_SHIFT) | |
| 170 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP1_MASK, KVM_REG_ARM64_SYSREG_OP1_MASK) | |
| 171 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP1_SHIFT, KVM_REG_ARM64_SYSREG_OP1_SHIFT) | |
| 172 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRN_MASK, KVM_REG_ARM64_SYSREG_CRN_MASK) | |
| 173 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRN_SHIFT, KVM_REG_ARM64_SYSREG_CRN_SHIFT) | |
| 174 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_MASK, KVM_REG_ARM64_SYSREG_CRM_MASK) | |
| 175 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_SHIFT, KVM_REG_ARM64_SYSREG_CRM_SHIFT) | |
| 176 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_MASK, KVM_REG_ARM64_SYSREG_OP2_MASK) | |
| 177 | MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_SHIFT, KVM_REG_ARM64_SYSREG_OP2_SHIFT) | |
| 178 | #endif | |
| 179 | ||
| 72b0cd35 PM |
180 | #undef MISMATCH_CHECK |
| 181 | ||
| 182 | #endif |