projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| c8a50e59 AK |
1 | #include "memory.h" |
| 2 | ||
| 87ecb68b | 3 | /* NOR flash devices */ |
| c227f099 | 4 | typedef struct pflash_t pflash_t; |
| 87ecb68b | 5 | |
| 88eeee0a | 6 | /* pflash_cfi01.c */ |
| c8a50e59 AK |
7 | extern const MemoryRegionOps pflash_cfi01_ops_be; |
| 8 | extern const MemoryRegionOps pflash_cfi01_ops_le; | |
| 9 | extern const MemoryRegionOps pflash_cfi02_ops_be; | |
| 10 | extern const MemoryRegionOps pflash_cfi02_ops_le; | |
| 11 | ||
| 12 | pflash_t *pflash_cfi01_register(target_phys_addr_t base, MemoryRegion *mem, | |
| 88eeee0a AZ |
13 | BlockDriverState *bs, |
| 14 | uint32_t sector_len, int nb_blocs, int width, | |
| 15 | uint16_t id0, uint16_t id1, | |
| c8a50e59 | 16 | uint16_t id2, uint16_t id3); |
| 88eeee0a AZ |
17 | |
| 18 | /* pflash_cfi02.c */ | |
| c8a50e59 | 19 | pflash_t *pflash_cfi02_register(target_phys_addr_t base, MemoryRegion *mem, |
| cf6d9118 | 20 | BlockDriverState *bs, uint32_t sector_len, |
| 4fbd24ba | 21 | int nb_blocs, int nb_mappings, int width, |
| 88eeee0a | 22 | uint16_t id0, uint16_t id1, |
| 6725070d | 23 | uint16_t id2, uint16_t id3, |
| c8a50e59 | 24 | uint16_t unlock_addr0, uint16_t unlock_addr1); |
| 87ecb68b PB |
25 | |
| 26 | /* nand.c */ | |
| d4220389 JR |
27 | DeviceState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id); |
| 28 | void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale, | |
| 51db57f7 | 29 | uint8_t ce, uint8_t wp, uint8_t gnd); |
| d4220389 JR |
30 | void nand_getpins(DeviceState *dev, int *rb); |
| 31 | void nand_setio(DeviceState *dev, uint32_t value); | |
| 32 | uint32_t nand_getio(DeviceState *dev); | |
| 33 | uint32_t nand_getbuswidth(DeviceState *dev); | |
| 87ecb68b PB |
34 | |
| 35 | #define NAND_MFR_TOSHIBA 0x98 | |
| 36 | #define NAND_MFR_SAMSUNG 0xec | |
| 37 | #define NAND_MFR_FUJITSU 0x04 | |
| 38 | #define NAND_MFR_NATIONAL 0x8f | |
| 39 | #define NAND_MFR_RENESAS 0x07 | |
| 40 | #define NAND_MFR_STMICRO 0x20 | |
| 41 | #define NAND_MFR_HYNIX 0xad | |
| 42 | #define NAND_MFR_MICRON 0x2c | |
| 43 | ||
| 7e7c5e4c | 44 | /* onenand.c */ |
| c227f099 | 45 | void onenand_base_update(void *opaque, target_phys_addr_t new); |
| 7e7c5e4c | 46 | void onenand_base_unmap(void *opaque); |
| 5923ba42 JR |
47 | void *onenand_init(BlockDriverState *bdrv, |
| 48 | uint16_t man_id, uint16_t dev_id, uint16_t ver_id, | |
| af5a75f4 | 49 | int regshift, qemu_irq irq); |
| c580d92b | 50 | void *onenand_raw_otp(void *opaque); |
| 7e7c5e4c | 51 | |
| 87ecb68b | 52 | /* ecc.c */ |
| bc24a225 | 53 | typedef struct { |
| 87ecb68b PB |
54 | uint8_t cp; /* Column parity */ |
| 55 | uint16_t lp[2]; /* Line parity */ | |
| 56 | uint16_t count; | |
| bc24a225 | 57 | } ECCState; |
| 87ecb68b | 58 | |
| bc24a225 PB |
59 | uint8_t ecc_digest(ECCState *s, uint8_t sample); |
| 60 | void ecc_reset(ECCState *s); | |
| 34f9f0b5 | 61 | extern VMStateDescription vmstate_ecc_state; |