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0ff596d0 PB |
1 | #ifndef QEMU_I2C_H |
2 | #define QEMU_I2C_H | |
3 | ||
4 | /* The QEMU I2C implementation only supports simple transfers that complete | |
5 | immediately. It does not support slave devices that need to be able to | |
6 | defer their response (eg. CPU slave interfaces where the data is supplied | |
7 | by the device driver in response to an interrupt). */ | |
8 | ||
9 | enum i2c_event { | |
10 | I2C_START_RECV, | |
11 | I2C_START_SEND, | |
12 | I2C_FINISH, | |
aa1f17c1 | 13 | I2C_NACK /* Masker NACKed a receive byte. */ |
0ff596d0 PB |
14 | }; |
15 | ||
0ff596d0 PB |
16 | /* Master to slave. */ |
17 | typedef int (*i2c_send_cb)(i2c_slave *s, uint8_t data); | |
18 | /* Slave to master. */ | |
19 | typedef int (*i2c_recv_cb)(i2c_slave *s); | |
20 | /* Notify the slave of a bus state change. */ | |
21 | typedef void (*i2c_event_cb)(i2c_slave *s, enum i2c_event event); | |
22 | ||
23 | struct i2c_slave | |
24 | { | |
25 | /* Callbacks to be set by the device. */ | |
26 | i2c_event_cb event; | |
27 | i2c_recv_cb recv; | |
28 | i2c_send_cb send; | |
29 | ||
30 | /* Remaining fields for internal use by the I2C code. */ | |
31 | int address; | |
32 | void *next; | |
c701b35b | 33 | i2c_bus *bus; |
0ff596d0 PB |
34 | }; |
35 | ||
0ff596d0 PB |
36 | i2c_bus *i2c_init_bus(void); |
37 | i2c_slave *i2c_slave_init(i2c_bus *bus, int address, int size); | |
38 | void i2c_set_slave_address(i2c_slave *dev, int address); | |
39 | int i2c_bus_busy(i2c_bus *bus); | |
40 | int i2c_start_transfer(i2c_bus *bus, int address, int recv); | |
41 | void i2c_end_transfer(i2c_bus *bus); | |
42 | void i2c_nack(i2c_bus *bus); | |
43 | int i2c_send(i2c_bus *bus, uint8_t data); | |
44 | int i2c_recv(i2c_bus *bus); | |
aa941b94 AZ |
45 | void i2c_slave_save(QEMUFile *f, i2c_slave *dev); |
46 | void i2c_slave_load(QEMUFile *f, i2c_slave *dev); | |
0ff596d0 | 47 | |
87ecb68b PB |
48 | /* max111x.c */ |
49 | struct max111x_s; | |
50 | uint32_t max111x_read(void *opaque); | |
51 | void max111x_write(void *opaque, uint32_t value); | |
52 | struct max111x_s *max1110_init(qemu_irq cb); | |
53 | struct max111x_s *max1111_init(qemu_irq cb); | |
54 | void max111x_set_input(struct max111x_s *s, int line, uint8_t value); | |
55 | ||
adb86c37 AZ |
56 | /* max7310.c */ |
57 | i2c_slave *max7310_init(i2c_bus *bus); | |
58 | void max7310_reset(i2c_slave *i2c); | |
59 | qemu_irq *max7310_gpio_in_get(i2c_slave *i2c); | |
60 | void max7310_gpio_out_set(i2c_slave *i2c, int line, qemu_irq handler); | |
61 | ||
62 | /* wm8750.c */ | |
63 | i2c_slave *wm8750_init(i2c_bus *bus, AudioState *audio); | |
64 | void wm8750_reset(i2c_slave *i2c); | |
65 | void wm8750_data_req_set(i2c_slave *i2c, | |
66 | void (*data_req)(void *, int, int), void *opaque); | |
67 | void wm8750_dac_dat(void *opaque, uint32_t sample); | |
68 | uint32_t wm8750_adc_dat(void *opaque); | |
662caa6f AZ |
69 | void *wm8750_dac_buffer(void *opaque, int samples); |
70 | void wm8750_dac_commit(void *opaque); | |
b0f74c87 | 71 | void wm8750_set_bclk_in(void *opaque, int new_hz); |
adb86c37 | 72 | |
87ecb68b | 73 | /* ssd0303.c */ |
3023f332 | 74 | void ssd0303_init(i2c_bus *bus, int address); |
87ecb68b | 75 | |
7e7c5e4c AZ |
76 | /* twl92230.c */ |
77 | i2c_slave *twl92230_init(i2c_bus *bus, qemu_irq irq); | |
78 | qemu_irq *twl92230_gpio_in_get(i2c_slave *i2c); | |
79 | void twl92230_gpio_out_set(i2c_slave *i2c, int line, qemu_irq handler); | |
80 | ||
81 | /* tmp105.c */ | |
82 | struct i2c_slave *tmp105_init(i2c_bus *bus, qemu_irq alarm); | |
83 | void tmp105_reset(i2c_slave *i2c); | |
84 | void tmp105_set(i2c_slave *i2c, int temp); | |
85 | ||
1d4e547b AZ |
86 | /* lm832x.c */ |
87 | struct i2c_slave *lm8323_init(i2c_bus *bus, qemu_irq nirq); | |
88 | void lm832x_key_event(struct i2c_slave *i2c, int key, int state); | |
89 | ||
0ff596d0 | 90 | #endif |