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Commit | Line | Data |
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4eb812f7 MT |
1 | /* |
2 | * Standard PCI Bridge Device | |
3 | * | |
4 | * Copyright (c) 2011 Red Hat Inc. Author: Michael S. Tsirkin <[email protected]> | |
5 | * | |
6 | * http://www.pcisig.com/specifications/conventional/pci_to_pci_bridge_architecture/ | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along | |
19 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
97d5408f | 22 | #include "qemu/osdep.h" |
da34e65c | 23 | #include "qapi/error.h" |
83c9f4ca PB |
24 | #include "hw/pci/pci_bridge.h" |
25 | #include "hw/pci/pci_ids.h" | |
26 | #include "hw/pci/msi.h" | |
27 | #include "hw/pci/shpc.h" | |
28 | #include "hw/pci/slotid_cap.h" | |
022c62cb | 29 | #include "exec/memory.h" |
83c9f4ca | 30 | #include "hw/pci/pci_bus.h" |
5d268704 | 31 | #include "hw/hotplug.h" |
4eb812f7 | 32 | |
eb6c6a60 GH |
33 | #define TYPE_PCI_BRIDGE_DEV "pci-bridge" |
34 | #define TYPE_PCI_BRIDGE_SEAT_DEV "pci-bridge-seat" | |
57524e14 AF |
35 | #define PCI_BRIDGE_DEV(obj) \ |
36 | OBJECT_CHECK(PCIBridgeDev, (obj), TYPE_PCI_BRIDGE_DEV) | |
37 | ||
4eb812f7 | 38 | struct PCIBridgeDev { |
57524e14 AF |
39 | /*< private >*/ |
40 | PCIBridge parent_obj; | |
41 | /*< public >*/ | |
42 | ||
4eb812f7 MT |
43 | MemoryRegion bar; |
44 | uint8_t chassis_nr; | |
69b205bb | 45 | #define PCI_BRIDGE_DEV_F_SHPC_REQ 0 |
4eb812f7 | 46 | uint32_t flags; |
69b205bb C |
47 | |
48 | OnOffAuto msi; | |
4eb812f7 MT |
49 | }; |
50 | typedef struct PCIBridgeDev PCIBridgeDev; | |
51 | ||
4eb812f7 MT |
52 | static int pci_bridge_dev_initfn(PCIDevice *dev) |
53 | { | |
f055e96b | 54 | PCIBridge *br = PCI_BRIDGE(dev); |
57524e14 | 55 | PCIBridgeDev *bridge_dev = PCI_BRIDGE_DEV(dev); |
f90c2bcd | 56 | int err; |
1108b2f8 | 57 | Error *local_err = NULL; |
f90c2bcd | 58 | |
9cfaa007 C |
59 | pci_bridge_initfn(dev, TYPE_PCI_BUS); |
60 | ||
4e5c9bfe LE |
61 | if (bridge_dev->flags & (1 << PCI_BRIDGE_DEV_F_SHPC_REQ)) { |
62 | dev->config[PCI_INTERRUPT_PIN] = 0x1; | |
63 | memory_region_init(&bridge_dev->bar, OBJECT(dev), "shpc-bar", | |
64 | shpc_bar_size(dev)); | |
65 | err = shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0); | |
66 | if (err) { | |
67 | goto shpc_error; | |
68 | } | |
69 | } else { | |
70 | /* MSI is not applicable without SHPC */ | |
69b205bb | 71 | bridge_dev->msi = ON_OFF_AUTO_OFF; |
4eb812f7 | 72 | } |
52ea63de | 73 | |
4eb812f7 MT |
74 | err = slotid_cap_init(dev, 0, bridge_dev->chassis_nr, 0); |
75 | if (err) { | |
76 | goto slotid_error; | |
77 | } | |
52ea63de | 78 | |
1108b2f8 C |
79 | if (bridge_dev->msi != ON_OFF_AUTO_OFF) { |
80 | /* it means SHPC exists, because MSI is needed by SHPC */ | |
81 | ||
82 | err = msi_init(dev, 0, 1, true, true, &local_err); | |
83 | /* Any error other than -ENOTSUP(board's MSI support is broken) | |
84 | * is a programming error */ | |
85 | assert(!err || err == -ENOTSUP); | |
86 | if (err && bridge_dev->msi == ON_OFF_AUTO_ON) { | |
87 | /* Can't satisfy user's explicit msi=on request, fail */ | |
88 | error_append_hint(&local_err, "You have to use msi=auto (default) " | |
89 | "or msi=off with this machine type.\n"); | |
90 | error_report_err(local_err); | |
4eb812f7 MT |
91 | goto msi_error; |
92 | } | |
1108b2f8 C |
93 | assert(!local_err || bridge_dev->msi == ON_OFF_AUTO_AUTO); |
94 | /* With msi=auto, we fall back to MSI off silently */ | |
95 | error_free(local_err); | |
4eb812f7 | 96 | } |
52ea63de | 97 | |
4e5c9bfe LE |
98 | if (shpc_present(dev)) { |
99 | /* TODO: spec recommends using 64 bit prefetcheable BAR. | |
100 | * Check whether that works well. */ | |
101 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | | |
102 | PCI_BASE_ADDRESS_MEM_TYPE_64, &bridge_dev->bar); | |
103 | } | |
4eb812f7 | 104 | return 0; |
52ea63de | 105 | |
4eb812f7 MT |
106 | msi_error: |
107 | slotid_cap_cleanup(dev); | |
108 | slotid_error: | |
4e5c9bfe LE |
109 | if (shpc_present(dev)) { |
110 | shpc_cleanup(dev, &bridge_dev->bar); | |
111 | } | |
4eb812f7 | 112 | shpc_error: |
f90c2bcd | 113 | pci_bridge_exitfn(dev); |
9cfaa007 | 114 | |
4eb812f7 MT |
115 | return err; |
116 | } | |
117 | ||
f90c2bcd | 118 | static void pci_bridge_dev_exitfn(PCIDevice *dev) |
4eb812f7 | 119 | { |
57524e14 | 120 | PCIBridgeDev *bridge_dev = PCI_BRIDGE_DEV(dev); |
4eb812f7 MT |
121 | if (msi_present(dev)) { |
122 | msi_uninit(dev); | |
123 | } | |
124 | slotid_cap_cleanup(dev); | |
4e5c9bfe LE |
125 | if (shpc_present(dev)) { |
126 | shpc_cleanup(dev, &bridge_dev->bar); | |
127 | } | |
f90c2bcd | 128 | pci_bridge_exitfn(dev); |
4eb812f7 MT |
129 | } |
130 | ||
5cd5e701 PB |
131 | static void pci_bridge_dev_instance_finalize(Object *obj) |
132 | { | |
4e5c9bfe | 133 | /* this function is idempotent and handles (PCIDevice.shpc == NULL) */ |
5cd5e701 PB |
134 | shpc_free(PCI_DEVICE(obj)); |
135 | } | |
136 | ||
4eb812f7 MT |
137 | static void pci_bridge_dev_write_config(PCIDevice *d, |
138 | uint32_t address, uint32_t val, int len) | |
139 | { | |
140 | pci_bridge_write_config(d, address, val, len); | |
141 | if (msi_present(d)) { | |
142 | msi_write_config(d, address, val, len); | |
143 | } | |
4e5c9bfe LE |
144 | if (shpc_present(d)) { |
145 | shpc_cap_write_config(d, address, val, len); | |
146 | } | |
4eb812f7 MT |
147 | } |
148 | ||
149 | static void qdev_pci_bridge_dev_reset(DeviceState *qdev) | |
150 | { | |
57524e14 | 151 | PCIDevice *dev = PCI_DEVICE(qdev); |
cbd2d434 | 152 | |
4eb812f7 | 153 | pci_bridge_reset(qdev); |
4e5c9bfe LE |
154 | if (shpc_present(dev)) { |
155 | shpc_reset(dev); | |
156 | } | |
4eb812f7 MT |
157 | } |
158 | ||
159 | static Property pci_bridge_dev_properties[] = { | |
160 | /* Note: 0 is not a legal chassis number. */ | |
3cf0ecb3 LE |
161 | DEFINE_PROP_UINT8(PCI_BRIDGE_DEV_PROP_CHASSIS_NR, PCIBridgeDev, chassis_nr, |
162 | 0), | |
69b205bb C |
163 | DEFINE_PROP_ON_OFF_AUTO(PCI_BRIDGE_DEV_PROP_MSI, PCIBridgeDev, msi, |
164 | ON_OFF_AUTO_AUTO), | |
4e5c9bfe LE |
165 | DEFINE_PROP_BIT(PCI_BRIDGE_DEV_PROP_SHPC, PCIBridgeDev, flags, |
166 | PCI_BRIDGE_DEV_F_SHPC_REQ, true), | |
4eb812f7 MT |
167 | DEFINE_PROP_END_OF_LIST(), |
168 | }; | |
169 | ||
4e5c9bfe LE |
170 | static bool pci_device_shpc_present(void *opaque, int version_id) |
171 | { | |
172 | PCIDevice *dev = opaque; | |
173 | ||
174 | return shpc_present(dev); | |
175 | } | |
176 | ||
4eb812f7 MT |
177 | static const VMStateDescription pci_bridge_dev_vmstate = { |
178 | .name = "pci_bridge", | |
179 | .fields = (VMStateField[]) { | |
57524e14 | 180 | VMSTATE_PCI_DEVICE(parent_obj, PCIBridge), |
4e5c9bfe | 181 | SHPC_VMSTATE(shpc, PCIDevice, pci_device_shpc_present), |
4eb812f7 MT |
182 | VMSTATE_END_OF_LIST() |
183 | } | |
184 | }; | |
185 | ||
4e5c9bfe LE |
186 | static void pci_bridge_dev_hotplug_cb(HotplugHandler *hotplug_dev, |
187 | DeviceState *dev, Error **errp) | |
188 | { | |
189 | PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev); | |
190 | ||
191 | if (!shpc_present(pci_hotplug_dev)) { | |
192 | error_setg(errp, "standard hotplug controller has been disabled for " | |
193 | "this %s", TYPE_PCI_BRIDGE_DEV); | |
194 | return; | |
195 | } | |
196 | shpc_device_hotplug_cb(hotplug_dev, dev, errp); | |
197 | } | |
198 | ||
199 | static void pci_bridge_dev_hot_unplug_request_cb(HotplugHandler *hotplug_dev, | |
200 | DeviceState *dev, | |
201 | Error **errp) | |
202 | { | |
203 | PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev); | |
204 | ||
205 | if (!shpc_present(pci_hotplug_dev)) { | |
206 | error_setg(errp, "standard hotplug controller has been disabled for " | |
207 | "this %s", TYPE_PCI_BRIDGE_DEV); | |
208 | return; | |
209 | } | |
210 | shpc_device_hot_unplug_request_cb(hotplug_dev, dev, errp); | |
211 | } | |
212 | ||
4eb812f7 MT |
213 | static void pci_bridge_dev_class_init(ObjectClass *klass, void *data) |
214 | { | |
215 | DeviceClass *dc = DEVICE_CLASS(klass); | |
216 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
5d268704 IM |
217 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); |
218 | ||
4eb812f7 MT |
219 | k->init = pci_bridge_dev_initfn; |
220 | k->exit = pci_bridge_dev_exitfn; | |
221 | k->config_write = pci_bridge_dev_write_config; | |
5c03a254 PB |
222 | k->vendor_id = PCI_VENDOR_ID_REDHAT; |
223 | k->device_id = PCI_DEVICE_ID_REDHAT_BRIDGE; | |
4eb812f7 MT |
224 | k->class_id = PCI_CLASS_BRIDGE_PCI; |
225 | k->is_bridge = 1, | |
226 | dc->desc = "Standard PCI Bridge"; | |
227 | dc->reset = qdev_pci_bridge_dev_reset; | |
228 | dc->props = pci_bridge_dev_properties; | |
229 | dc->vmsd = &pci_bridge_dev_vmstate; | |
125ee0ed | 230 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
4e5c9bfe LE |
231 | hc->plug = pci_bridge_dev_hotplug_cb; |
232 | hc->unplug_request = pci_bridge_dev_hot_unplug_request_cb; | |
4eb812f7 MT |
233 | } |
234 | ||
8c43a6f0 | 235 | static const TypeInfo pci_bridge_dev_info = { |
5cd5e701 PB |
236 | .name = TYPE_PCI_BRIDGE_DEV, |
237 | .parent = TYPE_PCI_BRIDGE, | |
238 | .instance_size = sizeof(PCIBridgeDev), | |
239 | .class_init = pci_bridge_dev_class_init, | |
240 | .instance_finalize = pci_bridge_dev_instance_finalize, | |
5d268704 IM |
241 | .interfaces = (InterfaceInfo[]) { |
242 | { TYPE_HOTPLUG_HANDLER }, | |
243 | { } | |
244 | } | |
4eb812f7 MT |
245 | }; |
246 | ||
eb6c6a60 GH |
247 | /* |
248 | * Multiseat bridge. Same as the standard pci bridge, only with a | |
249 | * different pci id, so we can match it easily in the guest for | |
250 | * automagic multiseat configuration. See docs/multiseat.txt for more. | |
251 | */ | |
252 | static void pci_bridge_dev_seat_class_init(ObjectClass *klass, void *data) | |
253 | { | |
254 | DeviceClass *dc = DEVICE_CLASS(klass); | |
255 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
256 | ||
257 | k->device_id = PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT; | |
258 | dc->desc = "Standard PCI Bridge (multiseat)"; | |
259 | } | |
260 | ||
261 | static const TypeInfo pci_bridge_dev_seat_info = { | |
262 | .name = TYPE_PCI_BRIDGE_SEAT_DEV, | |
263 | .parent = TYPE_PCI_BRIDGE_DEV, | |
264 | .instance_size = sizeof(PCIBridgeDev), | |
265 | .class_init = pci_bridge_dev_seat_class_init, | |
266 | }; | |
267 | ||
4eb812f7 MT |
268 | static void pci_bridge_dev_register(void) |
269 | { | |
270 | type_register_static(&pci_bridge_dev_info); | |
eb6c6a60 | 271 | type_register_static(&pci_bridge_dev_seat_info); |
4eb812f7 MT |
272 | } |
273 | ||
274 | type_init(pci_bridge_dev_register); |