[qemu.git] / target / mips / machine.c

#include "qemu/osdep.h"
#include "qemu-common.h"
#include "cpu.h"
#include "internal.h"
#include "hw/hw.h"
#include "migration/cpu.h"

static int cpu_post_load(void *opaque, int version_id)
{
    MIPSCPU *cpu = opaque;
    CPUMIPSState *env = &cpu->env;

    restore_fp_status(env);
    restore_msa_fp_status(env);
    compute_hflags(env);
    restore_pamask(env);

    return 0;
}

/* FPU state */

static int get_fpr(QEMUFile *f, void *pv, size_t size,
                   const VMStateField *field)
{
    int i;
    fpr_t *v = pv;
    /* Restore entire MSA vector register */
    for (i = 0; i < MSA_WRLEN/64; i++) {
        qemu_get_sbe64s(f, &v->wr.d[i]);
    }
    return 0;
}

static int put_fpr(QEMUFile *f, void *pv, size_t size,
                   const VMStateField *field, QJSON *vmdesc)
{
    int i;
    fpr_t *v = pv;
    /* Save entire MSA vector register */
    for (i = 0; i < MSA_WRLEN/64; i++) {
        qemu_put_sbe64s(f, &v->wr.d[i]);
    }

    return 0;
}

const VMStateInfo vmstate_info_fpr = {
    .name = "fpr",
    .get  = get_fpr,
    .put  = put_fpr,
};

#define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v)                     \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)

#define VMSTATE_FPR_ARRAY(_f, _s, _n)                           \
    VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)

static VMStateField vmstate_fpu_fields[] = {
    VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
    VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
    VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
    VMSTATE_END_OF_LIST()
};

const VMStateDescription vmstate_fpu = {
    .name = "cpu/fpu",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = vmstate_fpu_fields
};

const VMStateDescription vmstate_inactive_fpu = {
    .name = "cpu/inactive_fpu",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = vmstate_fpu_fields
};

/* TC state */

static VMStateField vmstate_tc_fields[] = {
    VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
    VMSTATE_UINTTL(PC, TCState),
    VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
    VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
    VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
    VMSTATE_UINTTL(DSPControl, TCState),
    VMSTATE_INT32(CP0_TCStatus, TCState),
    VMSTATE_INT32(CP0_TCBind, TCState),
    VMSTATE_UINTTL(CP0_TCHalt, TCState),
    VMSTATE_UINTTL(CP0_TCContext, TCState),
    VMSTATE_UINTTL(CP0_TCSchedule, TCState),
    VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
    VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
    VMSTATE_UINTTL(CP0_UserLocal, TCState),
    VMSTATE_INT32(msacsr, TCState),
    VMSTATE_END_OF_LIST()
};

const VMStateDescription vmstate_tc = {
    .name = "cpu/tc",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = vmstate_tc_fields
};

const VMStateDescription vmstate_inactive_tc = {
    .name = "cpu/inactive_tc",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = vmstate_tc_fields
};

/* MVP state */

const VMStateDescription vmstate_mvp = {
    .name = "cpu/mvp",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
        VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
        VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
        VMSTATE_END_OF_LIST()
    }
};

/* TLB state */

static int get_tlb(QEMUFile *f, void *pv, size_t size,
                   const VMStateField *field)
{
    r4k_tlb_t *v = pv;
    uint16_t flags;

    qemu_get_betls(f, &v->VPN);
    qemu_get_be32s(f, &v->PageMask);
    qemu_get_be16s(f, &v->ASID);
    qemu_get_be16s(f, &flags);
    v->G = (flags >> 10) & 1;
    v->C0 = (flags >> 7) & 3;
    v->C1 = (flags >> 4) & 3;
    v->V0 = (flags >> 3) & 1;
    v->V1 = (flags >> 2) & 1;
    v->D0 = (flags >> 1) & 1;
    v->D1 = (flags >> 0) & 1;
    v->EHINV = (flags >> 15) & 1;
    v->RI1 = (flags >> 14) & 1;
    v->RI0 = (flags >> 13) & 1;
    v->XI1 = (flags >> 12) & 1;
    v->XI0 = (flags >> 11) & 1;
    qemu_get_be64s(f, &v->PFN[0]);
    qemu_get_be64s(f, &v->PFN[1]);

    return 0;
}

static int put_tlb(QEMUFile *f, void *pv, size_t size,
                   const VMStateField *field, QJSON *vmdesc)
{
    r4k_tlb_t *v = pv;

    uint16_t asid = v->ASID;
    uint16_t flags = ((v->EHINV << 15) |
                      (v->RI1 << 14) |
                      (v->RI0 << 13) |
                      (v->XI1 << 12) |
                      (v->XI0 << 11) |
                      (v->G << 10) |
                      (v->C0 << 7) |
                      (v->C1 << 4) |
                      (v->V0 << 3) |
                      (v->V1 << 2) |
                      (v->D0 << 1) |
                      (v->D1 << 0));

    qemu_put_betls(f, &v->VPN);
    qemu_put_be32s(f, &v->PageMask);
    qemu_put_be16s(f, &asid);
    qemu_put_be16s(f, &flags);
    qemu_put_be64s(f, &v->PFN[0]);
    qemu_put_be64s(f, &v->PFN[1]);

    return 0;
}

const VMStateInfo vmstate_info_tlb = {
    .name = "tlb_entry",
    .get  = get_tlb,
    .put  = put_tlb,
};

#define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v)                     \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)

#define VMSTATE_TLB_ARRAY(_f, _s, _n)                           \
    VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)

const VMStateDescription vmstate_tlb = {
    .name = "cpu/tlb",
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
        VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
        VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
        VMSTATE_END_OF_LIST()
    }
};

/* MIPS CPU state */

const VMStateDescription vmstate_mips_cpu = {
    .name = "cpu",
    .version_id = 18,
    .minimum_version_id = 18,
    .post_load = cpu_post_load,
    .fields = (VMStateField[]) {
        /* Active TC */
        VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),

        /* Active FPU */
        VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
                       CPUMIPSFPUContext),

        /* MVP */
        VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp,
                               CPUMIPSMVPContext),

        /* TLB */
        VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
                               CPUMIPSTLBContext),

        /* CPU metastate */
        VMSTATE_UINT32(env.current_tc, MIPSCPU),
        VMSTATE_UINT32(env.current_fpu, MIPSCPU),
        VMSTATE_INT32(env.error_code, MIPSCPU),
        VMSTATE_UINTTL(env.btarget, MIPSCPU),
        VMSTATE_UINTTL(env.bcond, MIPSCPU),

        /* Remaining CP0 registers */
        VMSTATE_INT32(env.CP0_Index, MIPSCPU),
        VMSTATE_INT32(env.CP0_Random, MIPSCPU),
        VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
        VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
        VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
        VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
        VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
        VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
        VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU),
        VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
        VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU),
        VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
        VMSTATE_INT32(env.CP0_PWCtl, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
        VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
        VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
        VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
        VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
        VMSTATE_INT32(env.CP0_Count, MIPSCPU),
        VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU),
        VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2),
        VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
        VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
        VMSTATE_INT32(env.CP0_Status, MIPSCPU),
        VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
        VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
        VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_EBase, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
        VMSTATE_UINT64(env.CP0_LLAddr, MIPSCPU),
        VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX),
        VMSTATE_INT32(env.CP0_MAARI, MIPSCPU),
        VMSTATE_UINTTL(env.lladdr, MIPSCPU),
        VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
        VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
        VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
        VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
        VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
        VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
        VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU),
        VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
        VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
        VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
        VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
        VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),

        /* Inactive TC */
        VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
                             vmstate_inactive_tc, TCState),
        VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
                             vmstate_inactive_fpu, CPUMIPSFPUContext),

        VMSTATE_END_OF_LIST()
    },
};
Commit	Line	Data
c684822a	1	#include "qemu/osdep.h"
33c11879 PB	2	#include "qemu-common.h"
33c11879 PB	3	#include "cpu.h"
26aa3d9a	4	#include "internal.h"
8dd3dca3	5	#include "hw/hw.h"
1e00b8d5	6	#include "migration/cpu.h"
33a84765	7
64451111 LA	8	static int cpu_post_load(void *opaque, int version_id)
	9	{
	10	MIPSCPU *cpu = opaque;
	11	CPUMIPSState *env = &cpu->env;
	12
	13	restore_fp_status(env);
	14	restore_msa_fp_status(env);
	15	compute_hflags(env);
e117f526	16	restore_pamask(env);
64451111 LA	17
	18	return 0;
	19	}
	20
04cd7962 LA	21	/* FPU state */
04cd7962 LA	22
03fee66f MAL	23	static int get_fpr(QEMUFile f, void pv, size_t size,
03fee66f MAL	24	const VMStateField *field)
33a84765	25	{
64451111	26	int i;
04cd7962	27	fpr_t *v = pv;
64451111 LA	28	/* Restore entire MSA vector register */
	29	for (i = 0; i < MSA_WRLEN/64; i++) {
	30	qemu_get_sbe64s(f, &v->wr.d[i]);
	31	}
04cd7962	32	return 0;
33a84765 TS	33	}
33a84765 TS	34
03fee66f MAL	35	static int put_fpr(QEMUFile f, void pv, size_t size,
03fee66f MAL	36	const VMStateField field, QJSON vmdesc)
33a84765	37	{
64451111	38	int i;
04cd7962	39	fpr_t *v = pv;
64451111 LA	40	/* Save entire MSA vector register */
	41	for (i = 0; i < MSA_WRLEN/64; i++) {
	42	qemu_put_sbe64s(f, &v->wr.d[i]);
	43	}
2c21ee76 JD	44
2c21ee76 JD	45	return 0;
33a84765 TS	46	}
33a84765 TS	47
04cd7962 LA	48	const VMStateInfo vmstate_info_fpr = {
	49	.name = "fpr",
	50	.get = get_fpr,
	51	.put = put_fpr,
	52	};
	53
	54	#define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \
	55	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)
	56
	57	#define VMSTATE_FPR_ARRAY(_f, _s, _n) \
	58	VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
	59
	60	static VMStateField vmstate_fpu_fields[] = {
	61	VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
04cd7962 LA	62	VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
	63	VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
	64	VMSTATE_END_OF_LIST()
	65	};
	66
	67	const VMStateDescription vmstate_fpu = {
	68	.name = "cpu/fpu",
	69	.version_id = 1,
	70	.minimum_version_id = 1,
	71	.fields = vmstate_fpu_fields
	72	};
	73
	74	const VMStateDescription vmstate_inactive_fpu = {
	75	.name = "cpu/inactive_fpu",
	76	.version_id = 1,
	77	.minimum_version_id = 1,
	78	.fields = vmstate_fpu_fields
	79	};
33a84765	80
04cd7962 LA	81	/* TC state */
	82
	83	static VMStateField vmstate_tc_fields[] = {
	84	VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
	85	VMSTATE_UINTTL(PC, TCState),
	86	VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
	87	VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
	88	VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
	89	VMSTATE_UINTTL(DSPControl, TCState),
	90	VMSTATE_INT32(CP0_TCStatus, TCState),
	91	VMSTATE_INT32(CP0_TCBind, TCState),
	92	VMSTATE_UINTTL(CP0_TCHalt, TCState),
	93	VMSTATE_UINTTL(CP0_TCContext, TCState),
	94	VMSTATE_UINTTL(CP0_TCSchedule, TCState),
	95	VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
	96	VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
	97	VMSTATE_UINTTL(CP0_UserLocal, TCState),
64451111	98	VMSTATE_INT32(msacsr, TCState),
04cd7962 LA	99	VMSTATE_END_OF_LIST()
	100	};
	101
	102	const VMStateDescription vmstate_tc = {
	103	.name = "cpu/tc",
	104	.version_id = 1,
	105	.minimum_version_id = 1,
	106	.fields = vmstate_tc_fields
	107	};
	108
	109	const VMStateDescription vmstate_inactive_tc = {
	110	.name = "cpu/inactive_tc",
	111	.version_id = 1,
	112	.minimum_version_id = 1,
	113	.fields = vmstate_tc_fields
	114	};
	115
	116	/* MVP state */
	117
	118	const VMStateDescription vmstate_mvp = {
	119	.name = "cpu/mvp",
	120	.version_id = 1,
	121	.minimum_version_id = 1,
	122	.fields = (VMStateField[]) {
	123	VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
	124	VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
	125	VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
	126	VMSTATE_END_OF_LIST()
460c81f1	127	}
04cd7962	128	};
33a84765	129
04cd7962	130	/* TLB state */
33a84765	131
03fee66f MAL	132	static int get_tlb(QEMUFile f, void pv, size_t size,
03fee66f MAL	133	const VMStateField *field)
33a84765	134	{
04cd7962 LA	135	r4k_tlb_t *v = pv;
	136	uint16_t flags;
	137
	138	qemu_get_betls(f, &v->VPN);
	139	qemu_get_be32s(f, &v->PageMask);
2d72e7b0	140	qemu_get_be16s(f, &v->ASID);
04cd7962 LA	141	qemu_get_be16s(f, &flags);
	142	v->G = (flags >> 10) & 1;
	143	v->C0 = (flags >> 7) & 3;
	144	v->C1 = (flags >> 4) & 3;
	145	v->V0 = (flags >> 3) & 1;
	146	v->V1 = (flags >> 2) & 1;
	147	v->D0 = (flags >> 1) & 1;
	148	v->D1 = (flags >> 0) & 1;
	149	v->EHINV = (flags >> 15) & 1;
	150	v->RI1 = (flags >> 14) & 1;
	151	v->RI0 = (flags >> 13) & 1;
	152	v->XI1 = (flags >> 12) & 1;
	153	v->XI0 = (flags >> 11) & 1;
284b731a LA	154	qemu_get_be64s(f, &v->PFN[0]);
284b731a LA	155	qemu_get_be64s(f, &v->PFN[1]);
04cd7962 LA	156
04cd7962 LA	157	return 0;
33a84765 TS	158	}
33a84765 TS	159
03fee66f MAL	160	static int put_tlb(QEMUFile f, void pv, size_t size,
03fee66f MAL	161	const VMStateField field, QJSON vmdesc)
33a84765	162	{
04cd7962 LA	163	r4k_tlb_t *v = pv;
04cd7962 LA	164
2d72e7b0	165	uint16_t asid = v->ASID;
04cd7962 LA	166	uint16_t flags = ((v->EHINV << 15) \|
	167	(v->RI1 << 14) \|
	168	(v->RI0 << 13) \|
	169	(v->XI1 << 12) \|
	170	(v->XI0 << 11) \|
	171	(v->G << 10) \|
	172	(v->C0 << 7) \|
	173	(v->C1 << 4) \|
	174	(v->V0 << 3) \|
	175	(v->V1 << 2) \|
	176	(v->D0 << 1) \|
	177	(v->D1 << 0));
	178
	179	qemu_put_betls(f, &v->VPN);
	180	qemu_put_be32s(f, &v->PageMask);
2d72e7b0	181	qemu_put_be16s(f, &asid);
04cd7962	182	qemu_put_be16s(f, &flags);
284b731a LA	183	qemu_put_be64s(f, &v->PFN[0]);
284b731a LA	184	qemu_put_be64s(f, &v->PFN[1]);
2c21ee76 JD	185
2c21ee76 JD	186	return 0;
8dd3dca3 AJ	187	}
8dd3dca3 AJ	188
04cd7962 LA	189	const VMStateInfo vmstate_info_tlb = {
	190	.name = "tlb_entry",
	191	.get = get_tlb,
	192	.put = put_tlb,
	193	};
33a84765	194
04cd7962 LA	195	#define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v) \
04cd7962 LA	196	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)
33a84765	197
04cd7962 LA	198	#define VMSTATE_TLB_ARRAY(_f, _s, _n) \
04cd7962 LA	199	VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)
33a84765	200
04cd7962 LA	201	const VMStateDescription vmstate_tlb = {
04cd7962 LA	202	.name = "cpu/tlb",
2d72e7b0 PB	203	.version_id = 2,
2d72e7b0 PB	204	.minimum_version_id = 2,
04cd7962 LA	205	.fields = (VMStateField[]) {
	206	VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
	207	VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
	208	VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
	209	VMSTATE_END_OF_LIST()
460c81f1	210	}
04cd7962	211	};
33a84765	212
04cd7962	213	/* MIPS CPU state */
33a84765	214
04cd7962 LA	215	const VMStateDescription vmstate_mips_cpu = {
04cd7962 LA	216	.name = "cpu",
c7c7e1e9 LA	217	.version_id = 18,
c7c7e1e9 LA	218	.minimum_version_id = 18,
64451111	219	.post_load = cpu_post_load,
04cd7962 LA	220	.fields = (VMStateField[]) {
	221	/* Active TC */
	222	VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),
	223
	224	/* Active FPU */
	225	VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
	226	CPUMIPSFPUContext),
	227
	228	/* MVP */
	229	VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp,
	230	CPUMIPSMVPContext),
	231
	232	/* TLB */
	233	VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
	234	CPUMIPSTLBContext),
	235
	236	/* CPU metastate */
	237	VMSTATE_UINT32(env.current_tc, MIPSCPU),
	238	VMSTATE_UINT32(env.current_fpu, MIPSCPU),
	239	VMSTATE_INT32(env.error_code, MIPSCPU),
04cd7962 LA	240	VMSTATE_UINTTL(env.btarget, MIPSCPU),
	241	VMSTATE_UINTTL(env.bcond, MIPSCPU),
	242
	243	/* Remaining CP0 registers */
	244	VMSTATE_INT32(env.CP0_Index, MIPSCPU),
	245	VMSTATE_INT32(env.CP0_Random, MIPSCPU),
	246	VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
	247	VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
	248	VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
	249	VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
	250	VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
	251	VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
	252	VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
284b731a LA	253	VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
284b731a LA	254	VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
04cd7962	255	VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
3ef521ee	256	VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU),
04cd7962 LA	257	VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
04cd7962 LA	258	VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
cec56a73 JH	259	VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),
	260	VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU),
	261	VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU),
5e31fdd5	262	VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU),
fa75ad14	263	VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU),
20b28ebc	264	VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU),
04cd7962	265	VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
103be64c	266	VMSTATE_INT32(env.CP0_PWCtl, MIPSCPU),
04cd7962 LA	267	VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
	268	VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
	269	VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
	270	VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
	271	VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
	272	VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
	273	VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
	274	VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
	275	VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
25beba9b	276	VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
04cd7962	277	VMSTATE_INT32(env.CP0_Count, MIPSCPU),
167db30e YK	278	VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU),
167db30e YK	279	VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2),
04cd7962 LA	280	VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
	281	VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
	282	VMSTATE_INT32(env.CP0_Status, MIPSCPU),
	283	VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
	284	VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
	285	VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
	286	VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
	287	VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
	288	VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
74dbf824	289	VMSTATE_UINTTL(env.CP0_EBase, MIPSCPU),
04cd7962 LA	290	VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
	291	VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
	292	VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
	293	VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
	294	VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
	295	VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
c7c7e1e9	296	VMSTATE_UINT64(env.CP0_LLAddr, MIPSCPU),
f6d4dd81 YK	297	VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX),
f6d4dd81 YK	298	VMSTATE_INT32(env.CP0_MAARI, MIPSCPU),
c7c7e1e9	299	VMSTATE_UINTTL(env.lladdr, MIPSCPU),
04cd7962 LA	300	VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
	301	VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
	302	VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
	303	VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
	304	VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
	305	VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
	306	VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
284b731a	307	VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU),
04cd7962 LA	308	VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
	309	VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
	310	VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
	311	VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
	312	VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
	313	VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),
	314
	315	/* Inactive TC */
	316	VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
	317	vmstate_inactive_tc, TCState),
	318	VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
	319	vmstate_inactive_fpu, CPUMIPSFPUContext),
	320
	321	VMSTATE_END_OF_LIST()
	322	},
	323	};