[qemu.git] / target / arm / cpu64.c

/*
 * QEMU AArch64 CPU
 *
 * Copyright (c) 2013 Linaro Ltd
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see
 * <http://www.gnu.org/licenses/gpl-2.0.html>
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
#include "qemu-common.h"
#if !defined(CONFIG_USER_ONLY)
#include "hw/loader.h"
#endif
#include "hw/arm/arm.h"
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"

static inline void set_feature(CPUARMState *env, int feature)
{
    env->features |= 1ULL << feature;
}

static inline void unset_feature(CPUARMState *env, int feature)
{
    env->features &= ~(1ULL << feature);
}

#ifndef CONFIG_USER_ONLY
static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
    /* Number of processors is in [25:24]; otherwise we RAZ */
    return (smp_cpus - 1) << 24;
}
#endif

static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = {
#ifndef CONFIG_USER_ONLY
    { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
      .writefn = arm_cp_write_ignore },
    { .name = "L2CTLR",
      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
      .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
      .writefn = arm_cp_write_ignore },
#endif
    { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
    { .name = "L2ECTLR",
      .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
    { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
    { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
    { .name = "CPUACTLR",
      .cp = 15, .opc1 = 0, .crm = 15,
      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
    { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
    { .name = "CPUECTLR",
      .cp = 15, .opc1 = 1, .crm = 15,
      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
    { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
    { .name = "CPUMERRSR",
      .cp = 15, .opc1 = 2, .crm = 15,
      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
    { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
      .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
    { .name = "L2MERRSR",
      .cp = 15, .opc1 = 3, .crm = 15,
      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
    REGINFO_SENTINEL
};

static void aarch64_a57_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);

    cpu->dtb_compatible = "arm,cortex-a57";
    set_feature(&cpu->env, ARM_FEATURE_V8);
    set_feature(&cpu->env, ARM_FEATURE_VFP4);
    set_feature(&cpu->env, ARM_FEATURE_NEON);
    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
    set_feature(&cpu->env, ARM_FEATURE_V8_AES);
    set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
    set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
    set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
    set_feature(&cpu->env, ARM_FEATURE_CRC);
    set_feature(&cpu->env, ARM_FEATURE_EL2);
    set_feature(&cpu->env, ARM_FEATURE_EL3);
    set_feature(&cpu->env, ARM_FEATURE_PMU);
    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
    cpu->midr = 0x411fd070;
    cpu->revidr = 0x00000000;
    cpu->reset_fpsid = 0x41034070;
    cpu->mvfr0 = 0x10110222;
    cpu->mvfr1 = 0x12111111;
    cpu->mvfr2 = 0x00000043;
    cpu->ctr = 0x8444c004;
    cpu->reset_sctlr = 0x00c50838;
    cpu->id_pfr0 = 0x00000131;
    cpu->id_pfr1 = 0x00011011;
    cpu->id_dfr0 = 0x03010066;
    cpu->id_afr0 = 0x00000000;
    cpu->id_mmfr0 = 0x10101105;
    cpu->id_mmfr1 = 0x40000000;
    cpu->id_mmfr2 = 0x01260000;
    cpu->id_mmfr3 = 0x02102211;
    cpu->id_isar0 = 0x02101110;
    cpu->id_isar1 = 0x13112111;
    cpu->id_isar2 = 0x21232042;
    cpu->id_isar3 = 0x01112131;
    cpu->id_isar4 = 0x00011142;
    cpu->id_isar5 = 0x00011121;
    cpu->id_aa64pfr0 = 0x00002222;
    cpu->id_aa64dfr0 = 0x10305106;
    cpu->pmceid0 = 0x00000000;
    cpu->pmceid1 = 0x00000000;
    cpu->id_aa64isar0 = 0x00011120;
    cpu->id_aa64mmfr0 = 0x00001124;
    cpu->dbgdidr = 0x3516d000;
    cpu->clidr = 0x0a200023;
    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
    cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
    cpu->dcz_blocksize = 4; /* 64 bytes */
    cpu->gic_num_lrs = 4;
    cpu->gic_vpribits = 5;
    cpu->gic_vprebits = 5;
    define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
}

static void aarch64_a53_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);

    cpu->dtb_compatible = "arm,cortex-a53";
    set_feature(&cpu->env, ARM_FEATURE_V8);
    set_feature(&cpu->env, ARM_FEATURE_VFP4);
    set_feature(&cpu->env, ARM_FEATURE_NEON);
    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
    set_feature(&cpu->env, ARM_FEATURE_V8_AES);
    set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
    set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
    set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
    set_feature(&cpu->env, ARM_FEATURE_CRC);
    set_feature(&cpu->env, ARM_FEATURE_EL2);
    set_feature(&cpu->env, ARM_FEATURE_EL3);
    set_feature(&cpu->env, ARM_FEATURE_PMU);
    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
    cpu->midr = 0x410fd034;
    cpu->revidr = 0x00000000;
    cpu->reset_fpsid = 0x41034070;
    cpu->mvfr0 = 0x10110222;
    cpu->mvfr1 = 0x12111111;
    cpu->mvfr2 = 0x00000043;
    cpu->ctr = 0x84448004; /* L1Ip = VIPT */
    cpu->reset_sctlr = 0x00c50838;
    cpu->id_pfr0 = 0x00000131;
    cpu->id_pfr1 = 0x00011011;
    cpu->id_dfr0 = 0x03010066;
    cpu->id_afr0 = 0x00000000;
    cpu->id_mmfr0 = 0x10101105;
    cpu->id_mmfr1 = 0x40000000;
    cpu->id_mmfr2 = 0x01260000;
    cpu->id_mmfr3 = 0x02102211;
    cpu->id_isar0 = 0x02101110;
    cpu->id_isar1 = 0x13112111;
    cpu->id_isar2 = 0x21232042;
    cpu->id_isar3 = 0x01112131;
    cpu->id_isar4 = 0x00011142;
    cpu->id_isar5 = 0x00011121;
    cpu->id_aa64pfr0 = 0x00002222;
    cpu->id_aa64dfr0 = 0x10305106;
    cpu->id_aa64isar0 = 0x00011120;
    cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
    cpu->dbgdidr = 0x3516d000;
    cpu->clidr = 0x0a200023;
    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
    cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
    cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
    cpu->dcz_blocksize = 4; /* 64 bytes */
    cpu->gic_num_lrs = 4;
    cpu->gic_vpribits = 5;
    cpu->gic_vprebits = 5;
    define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
}

#ifdef CONFIG_USER_ONLY
static void aarch64_any_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);

    set_feature(&cpu->env, ARM_FEATURE_V8);
    set_feature(&cpu->env, ARM_FEATURE_VFP4);
    set_feature(&cpu->env, ARM_FEATURE_NEON);
    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
    set_feature(&cpu->env, ARM_FEATURE_V8_AES);
    set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
    set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
    set_feature(&cpu->env, ARM_FEATURE_V8_SHA512);
    set_feature(&cpu->env, ARM_FEATURE_V8_SHA3);
    set_feature(&cpu->env, ARM_FEATURE_V8_SM3);
    set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
    set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
    set_feature(&cpu->env, ARM_FEATURE_CRC);
    cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
    cpu->dcz_blocksize = 7; /*  512 bytes */
}
#endif

typedef struct ARMCPUInfo {
    const char *name;
    void (*initfn)(Object *obj);
    void (*class_init)(ObjectClass *oc, void *data);
} ARMCPUInfo;

static const ARMCPUInfo aarch64_cpus[] = {
    { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
    { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
#ifdef CONFIG_USER_ONLY
    { .name = "any",         .initfn = aarch64_any_initfn },
#endif
    { .name = NULL }
};

static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
{
    ARMCPU *cpu = ARM_CPU(obj);

    return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
}

static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
{
    ARMCPU *cpu = ARM_CPU(obj);

    /* At this time, this property is only allowed if KVM is enabled.  This
     * restriction allows us to avoid fixing up functionality that assumes a
     * uniform execution state like do_interrupt.
     */
    if (!kvm_enabled()) {
        error_setg(errp, "'aarch64' feature cannot be disabled "
                         "unless KVM is enabled");
        return;
    }

    if (value == false) {
        unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
    } else {
        set_feature(&cpu->env, ARM_FEATURE_AARCH64);
    }
}

static void aarch64_cpu_initfn(Object *obj)
{
    object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
                             aarch64_cpu_set_aarch64, NULL);
    object_property_set_description(obj, "aarch64",
                                    "Set on/off to enable/disable aarch64 "
                                    "execution state ",
                                    NULL);
}

static void aarch64_cpu_finalizefn(Object *obj)
{
}

static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
{
    ARMCPU *cpu = ARM_CPU(cs);
    /* It's OK to look at env for the current mode here, because it's
     * never possible for an AArch64 TB to chain to an AArch32 TB.
     * (Otherwise we would need to use synchronize_from_tb instead.)
     */
    if (is_a64(&cpu->env)) {
        cpu->env.pc = value;
    } else {
        cpu->env.regs[15] = value;
    }
}

static gchar *aarch64_gdb_arch_name(CPUState *cs)
{
    return g_strdup("aarch64");
}

static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
{
    CPUClass *cc = CPU_CLASS(oc);

    cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
    cc->set_pc = aarch64_cpu_set_pc;
    cc->gdb_read_register = aarch64_cpu_gdb_read_register;
    cc->gdb_write_register = aarch64_cpu_gdb_write_register;
    cc->gdb_num_core_regs = 34;
    cc->gdb_core_xml_file = "aarch64-core.xml";
    cc->gdb_arch_name = aarch64_gdb_arch_name;
}

static void aarch64_cpu_register(const ARMCPUInfo *info)
{
    TypeInfo type_info = {
        .parent = TYPE_AARCH64_CPU,
        .instance_size = sizeof(ARMCPU),
        .instance_init = info->initfn,
        .class_size = sizeof(ARMCPUClass),
        .class_init = info->class_init,
    };

    type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
    type_register(&type_info);
    g_free((void *)type_info.name);
}

static const TypeInfo aarch64_cpu_type_info = {
    .name = TYPE_AARCH64_CPU,
    .parent = TYPE_ARM_CPU,
    .instance_size = sizeof(ARMCPU),
    .instance_init = aarch64_cpu_initfn,
    .instance_finalize = aarch64_cpu_finalizefn,
    .abstract = true,
    .class_size = sizeof(AArch64CPUClass),
    .class_init = aarch64_cpu_class_init,
};

static void aarch64_cpu_register_types(void)
{
    const ARMCPUInfo *info = aarch64_cpus;

    type_register_static(&aarch64_cpu_type_info);

    while (info->name) {
        aarch64_cpu_register(info);
        info++;
    }
}

type_init(aarch64_cpu_register_types)
Commit	Line	Data
d14d42f1 PM	1	/*
	2	* QEMU AArch64 CPU
	3	*
	4	* Copyright (c) 2013 Linaro Ltd
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, see
	18	* <http://www.gnu.org/licenses/gpl-2.0.html>
	19	*/
	20
74c21bd0	21	#include "qemu/osdep.h"
da34e65c	22	#include "qapi/error.h"
d14d42f1 PM	23	#include "cpu.h"
	24	#include "qemu-common.h"
	25	#if !defined(CONFIG_USER_ONLY)
	26	#include "hw/loader.h"
	27	#endif
	28	#include "hw/arm/arm.h"
	29	#include "sysemu/sysemu.h"
	30	#include "sysemu/kvm.h"
	31
	32	static inline void set_feature(CPUARMState *env, int feature)
	33	{
	34	env->features \|= 1ULL << feature;
	35	}
	36
fb8d6c24 GB	37	static inline void unset_feature(CPUARMState *env, int feature)
	38	{
	39	env->features &= ~(1ULL << feature);
	40	}
	41
377a44ec	42	#ifndef CONFIG_USER_ONLY
ee804264	43	static uint64_t a57_a53_l2ctlr_read(CPUARMState env, const ARMCPRegInfo ri)
377a44ec PM	44	{
	45	/* Number of processors is in [25:24]; otherwise we RAZ */
	46	return (smp_cpus - 1) << 24;
	47	}
	48	#endif
	49
ee804264	50	static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = {
377a44ec PM	51	#ifndef CONFIG_USER_ONLY
	52	{ .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
	53	.opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
ee804264	54	.access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
377a44ec PM	55	.writefn = arm_cp_write_ignore },
	56	{ .name = "L2CTLR",
	57	.cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
ee804264	58	.access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
377a44ec PM	59	.writefn = arm_cp_write_ignore },
	60	#endif
	61	{ .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
	62	.opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
	63	.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
	64	{ .name = "L2ECTLR",
	65	.cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
	66	.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
	67	{ .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
	68	.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
	69	.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
	70	{ .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
	71	.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
	72	.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
	73	{ .name = "CPUACTLR",
	74	.cp = 15, .opc1 = 0, .crm = 15,
	75	.access = PL1_RW, .type = ARM_CP_CONST \| ARM_CP_64BIT, .resetvalue = 0 },
	76	{ .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
	77	.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
	78	.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
	79	{ .name = "CPUECTLR",
	80	.cp = 15, .opc1 = 1, .crm = 15,
	81	.access = PL1_RW, .type = ARM_CP_CONST \| ARM_CP_64BIT, .resetvalue = 0 },
	82	{ .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
	83	.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
	84	.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
	85	{ .name = "CPUMERRSR",
	86	.cp = 15, .opc1 = 2, .crm = 15,
	87	.access = PL1_RW, .type = ARM_CP_CONST \| ARM_CP_64BIT, .resetvalue = 0 },
	88	{ .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
	89	.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
	90	.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
	91	{ .name = "L2MERRSR",
	92	.cp = 15, .opc1 = 3, .crm = 15,
	93	.access = PL1_RW, .type = ARM_CP_CONST \| ARM_CP_64BIT, .resetvalue = 0 },
	94	REGINFO_SENTINEL
	95	};
	96
cb1fa941 PM	97	static void aarch64_a57_initfn(Object *obj)
	98	{
	99	ARMCPU *cpu = ARM_CPU(obj);
	100
0458b7b5	101	cpu->dtb_compatible = "arm,cortex-a57";
cb1fa941 PM	102	set_feature(&cpu->env, ARM_FEATURE_V8);
cb1fa941 PM	103	set_feature(&cpu->env, ARM_FEATURE_VFP4);
cb1fa941 PM	104	set_feature(&cpu->env, ARM_FEATURE_NEON);
	105	set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
	106	set_feature(&cpu->env, ARM_FEATURE_AARCH64);
f318cec6	107	set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
25f748e3 PM	108	set_feature(&cpu->env, ARM_FEATURE_V8_AES);
	109	set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
	110	set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
	111	set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
	112	set_feature(&cpu->env, ARM_FEATURE_CRC);
c25bd18a	113	set_feature(&cpu->env, ARM_FEATURE_EL2);
3ad901bc	114	set_feature(&cpu->env, ARM_FEATURE_EL3);
929e754d	115	set_feature(&cpu->env, ARM_FEATURE_PMU);
cb1fa941 PM	116	cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
cb1fa941 PM	117	cpu->midr = 0x411fd070;
13b72b2b	118	cpu->revidr = 0x00000000;
cb1fa941 PM	119	cpu->reset_fpsid = 0x41034070;
	120	cpu->mvfr0 = 0x10110222;
	121	cpu->mvfr1 = 0x12111111;
	122	cpu->mvfr2 = 0x00000043;
	123	cpu->ctr = 0x8444c004;
	124	cpu->reset_sctlr = 0x00c50838;
	125	cpu->id_pfr0 = 0x00000131;
	126	cpu->id_pfr1 = 0x00011011;
	127	cpu->id_dfr0 = 0x03010066;
	128	cpu->id_afr0 = 0x00000000;
	129	cpu->id_mmfr0 = 0x10101105;
	130	cpu->id_mmfr1 = 0x40000000;
	131	cpu->id_mmfr2 = 0x01260000;
	132	cpu->id_mmfr3 = 0x02102211;
	133	cpu->id_isar0 = 0x02101110;
	134	cpu->id_isar1 = 0x13112111;
	135	cpu->id_isar2 = 0x21232042;
	136	cpu->id_isar3 = 0x01112131;
	137	cpu->id_isar4 = 0x00011142;
c3796214	138	cpu->id_isar5 = 0x00011121;
cb1fa941 PM	139	cpu->id_aa64pfr0 = 0x00002222;
cb1fa941 PM	140	cpu->id_aa64dfr0 = 0x10305106;
4054bfa9 AF	141	cpu->pmceid0 = 0x00000000;
4054bfa9 AF	142	cpu->pmceid1 = 0x00000000;
c3796214	143	cpu->id_aa64isar0 = 0x00011120;
cb1fa941	144	cpu->id_aa64mmfr0 = 0x00001124;
48eb3ae6	145	cpu->dbgdidr = 0x3516d000;
cb1fa941 PM	146	cpu->clidr = 0x0a200023;
	147	cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
	148	cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
	149	cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
	150	cpu->dcz_blocksize = 4; /* 64 bytes */
e45868a3 PM	151	cpu->gic_num_lrs = 4;
	152	cpu->gic_vpribits = 5;
	153	cpu->gic_vprebits = 5;
ee804264	154	define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
cb1fa941 PM	155	}
cb1fa941 PM	156
e3531026 PC	157	static void aarch64_a53_initfn(Object *obj)
	158	{
	159	ARMCPU *cpu = ARM_CPU(obj);
	160
	161	cpu->dtb_compatible = "arm,cortex-a53";
	162	set_feature(&cpu->env, ARM_FEATURE_V8);
	163	set_feature(&cpu->env, ARM_FEATURE_VFP4);
	164	set_feature(&cpu->env, ARM_FEATURE_NEON);
	165	set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
	166	set_feature(&cpu->env, ARM_FEATURE_AARCH64);
	167	set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
	168	set_feature(&cpu->env, ARM_FEATURE_V8_AES);
	169	set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
	170	set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
	171	set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
	172	set_feature(&cpu->env, ARM_FEATURE_CRC);
c25bd18a	173	set_feature(&cpu->env, ARM_FEATURE_EL2);
3ad901bc	174	set_feature(&cpu->env, ARM_FEATURE_EL3);
929e754d	175	set_feature(&cpu->env, ARM_FEATURE_PMU);
7525465e	176	cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
e3531026	177	cpu->midr = 0x410fd034;
13b72b2b	178	cpu->revidr = 0x00000000;
e3531026 PC	179	cpu->reset_fpsid = 0x41034070;
	180	cpu->mvfr0 = 0x10110222;
	181	cpu->mvfr1 = 0x12111111;
	182	cpu->mvfr2 = 0x00000043;
	183	cpu->ctr = 0x84448004; /* L1Ip = VIPT */
	184	cpu->reset_sctlr = 0x00c50838;
	185	cpu->id_pfr0 = 0x00000131;
	186	cpu->id_pfr1 = 0x00011011;
	187	cpu->id_dfr0 = 0x03010066;
	188	cpu->id_afr0 = 0x00000000;
	189	cpu->id_mmfr0 = 0x10101105;
	190	cpu->id_mmfr1 = 0x40000000;
	191	cpu->id_mmfr2 = 0x01260000;
	192	cpu->id_mmfr3 = 0x02102211;
	193	cpu->id_isar0 = 0x02101110;
	194	cpu->id_isar1 = 0x13112111;
	195	cpu->id_isar2 = 0x21232042;
	196	cpu->id_isar3 = 0x01112131;
	197	cpu->id_isar4 = 0x00011142;
	198	cpu->id_isar5 = 0x00011121;
	199	cpu->id_aa64pfr0 = 0x00002222;
	200	cpu->id_aa64dfr0 = 0x10305106;
	201	cpu->id_aa64isar0 = 0x00011120;
	202	cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
	203	cpu->dbgdidr = 0x3516d000;
	204	cpu->clidr = 0x0a200023;
	205	cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
	206	cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
	207	cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
	208	cpu->dcz_blocksize = 4; /* 64 bytes */
e45868a3 PM	209	cpu->gic_num_lrs = 4;
	210	cpu->gic_vpribits = 5;
	211	cpu->gic_vprebits = 5;
e3531026 PC	212	define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
	213	}
	214
d14d42f1 PM	215	#ifdef CONFIG_USER_ONLY
	216	static void aarch64_any_initfn(Object *obj)
	217	{
	218	ARMCPU *cpu = ARM_CPU(obj);
	219
	220	set_feature(&cpu->env, ARM_FEATURE_V8);
	221	set_feature(&cpu->env, ARM_FEATURE_VFP4);
d14d42f1	222	set_feature(&cpu->env, ARM_FEATURE_NEON);
d14d42f1	223	set_feature(&cpu->env, ARM_FEATURE_AARCH64);
25f748e3 PM	224	set_feature(&cpu->env, ARM_FEATURE_V8_AES);
	225	set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
	226	set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
955f56d4 AB	227	set_feature(&cpu->env, ARM_FEATURE_V8_SHA512);
	228	set_feature(&cpu->env, ARM_FEATURE_V8_SHA3);
	229	set_feature(&cpu->env, ARM_FEATURE_V8_SM3);
	230	set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
25f748e3 PM	231	set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
25f748e3 PM	232	set_feature(&cpu->env, ARM_FEATURE_CRC);
0e7b176a	233	cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
aca3f40b	234	cpu->dcz_blocksize = 7; /* 512 bytes */
d14d42f1 PM	235	}
	236	#endif
	237
	238	typedef struct ARMCPUInfo {
	239	const char *name;
	240	void (initfn)(Object obj);
	241	void (class_init)(ObjectClass oc, void *data);
	242	} ARMCPUInfo;
	243
	244	static const ARMCPUInfo aarch64_cpus[] = {
cb1fa941	245	{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
e3531026	246	{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
d14d42f1 PM	247	#ifdef CONFIG_USER_ONLY
	248	{ .name = "any", .initfn = aarch64_any_initfn },
	249	#endif
83e6813a	250	{ .name = NULL }
d14d42f1 PM	251	};
d14d42f1 PM	252
fb8d6c24 GB	253	static bool aarch64_cpu_get_aarch64(Object obj, Error *errp)
	254	{
	255	ARMCPU *cpu = ARM_CPU(obj);
	256
	257	return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
	258	}
	259
	260	static void aarch64_cpu_set_aarch64(Object obj, bool value, Error *errp)
	261	{
	262	ARMCPU *cpu = ARM_CPU(obj);
	263
	264	/* At this time, this property is only allowed if KVM is enabled. This
	265	* restriction allows us to avoid fixing up functionality that assumes a
	266	* uniform execution state like do_interrupt.
	267	*/
	268	if (!kvm_enabled()) {
	269	error_setg(errp, "'aarch64' feature cannot be disabled "
	270	"unless KVM is enabled");
	271	return;
	272	}
	273
	274	if (value == false) {
	275	unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
	276	} else {
	277	set_feature(&cpu->env, ARM_FEATURE_AARCH64);
	278	}
	279	}
	280
d14d42f1 PM	281	static void aarch64_cpu_initfn(Object *obj)
d14d42f1 PM	282	{
fb8d6c24 GB	283	object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
	284	aarch64_cpu_set_aarch64, NULL);
	285	object_property_set_description(obj, "aarch64",
	286	"Set on/off to enable/disable aarch64 "
	287	"execution state ",
	288	NULL);
d14d42f1 PM	289	}
	290
	291	static void aarch64_cpu_finalizefn(Object *obj)
	292	{
	293	}
	294
5ce4f357 AG	295	static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
	296	{
	297	ARMCPU *cpu = ARM_CPU(cs);
7633378d PM	298	/* It's OK to look at env for the current mode here, because it's
	299	* never possible for an AArch64 TB to chain to an AArch32 TB.
	300	* (Otherwise we would need to use synchronize_from_tb instead.)
5ce4f357	301	*/
7633378d PM	302	if (is_a64(&cpu->env)) {
	303	cpu->env.pc = value;
	304	} else {
	305	cpu->env.regs[15] = value;
	306	}
5ce4f357 AG	307	}
5ce4f357 AG	308
b3820e6c DH	309	static gchar aarch64_gdb_arch_name(CPUState cs)
	310	{
	311	return g_strdup("aarch64");
	312	}
	313
d14d42f1 PM	314	static void aarch64_cpu_class_init(ObjectClass oc, void data)
d14d42f1 PM	315	{
14ade10f AG	316	CPUClass *cc = CPU_CLASS(oc);
14ade10f AG	317
e8925712	318	cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
5ce4f357	319	cc->set_pc = aarch64_cpu_set_pc;
96c04212 AG	320	cc->gdb_read_register = aarch64_cpu_gdb_read_register;
	321	cc->gdb_write_register = aarch64_cpu_gdb_write_register;
	322	cc->gdb_num_core_regs = 34;
	323	cc->gdb_core_xml_file = "aarch64-core.xml";
b3820e6c	324	cc->gdb_arch_name = aarch64_gdb_arch_name;
d14d42f1 PM	325	}
	326
	327	static void aarch64_cpu_register(const ARMCPUInfo *info)
	328	{
	329	TypeInfo type_info = {
	330	.parent = TYPE_AARCH64_CPU,
	331	.instance_size = sizeof(ARMCPU),
	332	.instance_init = info->initfn,
	333	.class_size = sizeof(ARMCPUClass),
	334	.class_init = info->class_init,
	335	};
	336
	337	type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
	338	type_register(&type_info);
	339	g_free((void *)type_info.name);
	340	}
	341
	342	static const TypeInfo aarch64_cpu_type_info = {
	343	.name = TYPE_AARCH64_CPU,
	344	.parent = TYPE_ARM_CPU,
	345	.instance_size = sizeof(ARMCPU),
	346	.instance_init = aarch64_cpu_initfn,
	347	.instance_finalize = aarch64_cpu_finalizefn,
	348	.abstract = true,
	349	.class_size = sizeof(AArch64CPUClass),
	350	.class_init = aarch64_cpu_class_init,
	351	};
	352
	353	static void aarch64_cpu_register_types(void)
	354	{
83e6813a	355	const ARMCPUInfo *info = aarch64_cpus;
d14d42f1 PM	356
d14d42f1 PM	357	type_register_static(&aarch64_cpu_type_info);
83e6813a PM	358
	359	while (info->name) {
	360	aarch64_cpu_register(info);
	361	info++;
d14d42f1 PM	362	}
	363	}
	364
	365	type_init(aarch64_cpu_register_types)