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e1000: Don't muck with PCI commmand register
[qemu.git] / cpu-exec.c
CommitLineData
7d13299d
FB		 1/*
2 * i386 emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB		 6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB		 11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
e4533c7a 19#include "config.h"
93ac68bc 20#include "exec.h"
956034d7 21#include "disas.h"
7cb69cae 22#include "tcg.h"
7ba1e619 23#include "kvm.h"
7d13299d 24
fbf9eeb3
FB		 25#if !defined(CONFIG_SOFTMMU)
26#undef EAX
27#undef ECX
28#undef EDX
29#undef EBX
30#undef ESP
31#undef EBP
32#undef ESI
33#undef EDI
34#undef EIP
35#include <signal.h>
84778508 36#ifdef __linux__
fbf9eeb3
FB		 37#include <sys/ucontext.h>
38#endif
84778508 39#endif
fbf9eeb3 40
dfe5fff3 41#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
572a9d4a
BS		 42// Work around ugly bugs in glibc that mangle global register contents
43#undef env
44#define env cpu_single_env
45#endif
46
36bdbe54
FB		 47int tb_invalidated_flag;
48
f0667e66 49//#define CONFIG_DEBUG_EXEC
9de5e440 50//#define DEBUG_SIGNAL
7d13299d 51
6a4955a8
AL		 52int qemu_cpu_has_work(CPUState *env)
53{
54 return cpu_has_work(env);
55}
56
e4533c7a
FB		 57void cpu_loop_exit(void)
58{
bfed01fc
TS		 59 /* NOTE: the register at this point must be saved by hand because
60 longjmp restore them */
61 regs_to_env();
e4533c7a
FB		 62 longjmp(env->jmp_env, 1);
63}
bfed01fc 64
fbf9eeb3
FB		 65/* exit the current TB from a signal handler. The host registers are
66 restored in a state compatible with the CPU emulator
67 */
5fafdf24 68void cpu_resume_from_signal(CPUState *env1, void *puc)
fbf9eeb3
FB		 69{
70#if !defined(CONFIG_SOFTMMU)
84778508 71#ifdef __linux__
fbf9eeb3 72 struct ucontext *uc = puc;
84778508
BS		 73#elif defined(__OpenBSD__)
74 struct sigcontext *uc = puc;
75#endif
fbf9eeb3
FB		 76#endif
77
78 env = env1;
79
80 /* XXX: restore cpu registers saved in host registers */
81
82#if !defined(CONFIG_SOFTMMU)
83 if (puc) {
84 /* XXX: use siglongjmp ? */
84778508 85#ifdef __linux__
fbf9eeb3 86 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
84778508
BS		 87#elif defined(__OpenBSD__)
88 sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
89#endif
fbf9eeb3
FB		 90 }
91#endif
9a3ea654 92 env->exception_index = -1;
fbf9eeb3
FB		 93 longjmp(env->jmp_env, 1);
94}
95
2e70f6ef
PB		 96/* Execute the code without caching the generated code. An interpreter
97 could be used if available. */
98static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb)
99{
100 unsigned long next_tb;
101 TranslationBlock *tb;
102
103 /* Should never happen.
104 We only end up here when an existing TB is too long. */
105 if (max_cycles > CF_COUNT_MASK)
106 max_cycles = CF_COUNT_MASK;
107
108 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
109 max_cycles);
110 env->current_tb = tb;
111 /* execute the generated code */
112 next_tb = tcg_qemu_tb_exec(tb->tc_ptr);
113
114 if ((next_tb & 3) == 2) {
115 /* Restore PC. This may happen if async event occurs before
116 the TB starts executing. */
622ed360 117 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 118 }
119 tb_phys_invalidate(tb, -1);
120 tb_free(tb);
121}
122
8a40a180
FB		 123static TranslationBlock *tb_find_slow(target_ulong pc,
124 target_ulong cs_base,
c068688b 125 uint64_t flags)
8a40a180
FB		 126{
127 TranslationBlock *tb, **ptb1;
8a40a180
FB		 128 unsigned int h;
129 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
3b46e624 130
8a40a180 131 tb_invalidated_flag = 0;
3b46e624 132
8a40a180 133 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
3b46e624 134
8a40a180
FB		 135 /* find translated block using physical mappings */
136 phys_pc = get_phys_addr_code(env, pc);
137 phys_page1 = phys_pc & TARGET_PAGE_MASK;
138 phys_page2 = -1;
139 h = tb_phys_hash_func(phys_pc);
140 ptb1 = &tb_phys_hash[h];
141 for(;;) {
142 tb = *ptb1;
143 if (!tb)
144 goto not_found;
5fafdf24 145 if (tb->pc == pc &&
8a40a180 146 tb->page_addr[0] == phys_page1 &&
5fafdf24 147 tb->cs_base == cs_base &&
8a40a180
FB		 148 tb->flags == flags) {
149 /* check next page if needed */
150 if (tb->page_addr[1] != -1) {
5fafdf24 151 virt_page2 = (pc & TARGET_PAGE_MASK) +
8a40a180
FB		 152 TARGET_PAGE_SIZE;
153 phys_page2 = get_phys_addr_code(env, virt_page2);
154 if (tb->page_addr[1] == phys_page2)
155 goto found;
156 } else {
157 goto found;
158 }
159 }
160 ptb1 = &tb->phys_hash_next;
161 }
162 not_found:
2e70f6ef
PB		 163 /* if no translated code available, then translate it now */
164 tb = tb_gen_code(env, pc, cs_base, flags, 0);
3b46e624 165
8a40a180 166 found:
8a40a180
FB		 167 /* we add the TB in the virtual pc hash table */
168 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
8a40a180
FB		 169 return tb;
170}
171
172static inline TranslationBlock *tb_find_fast(void)
173{
174 TranslationBlock *tb;
175 target_ulong cs_base, pc;
6b917547 176 int flags;
8a40a180
FB		 177
178 /* we record a subset of the CPU state. It will
179 always be the same before a given translated block
180 is executed. */
6b917547 181 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
bce61846 182 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
551bd27f
TS		 183 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
184 tb->flags != flags)) {
8a40a180
FB		 185 tb = tb_find_slow(pc, cs_base, flags);
186 }
187 return tb;
188}
189
dde2367e
AL		 190static CPUDebugExcpHandler *debug_excp_handler;
191
192CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
193{
194 CPUDebugExcpHandler *old_handler = debug_excp_handler;
195
196 debug_excp_handler = handler;
197 return old_handler;
198}
199
6e140f28
AL		 200static void cpu_handle_debug_exception(CPUState *env)
201{
202 CPUWatchpoint *wp;
203
204 if (!env->watchpoint_hit)
72cf2d4f 205 QTAILQ_FOREACH(wp, &env->watchpoints, entry)
6e140f28 206 wp->flags &= ~BP_WATCHPOINT_HIT;
dde2367e
AL		 207
208 if (debug_excp_handler)
209 debug_excp_handler(env);
6e140f28
AL		 210}
211
7d13299d
FB		 212/* main execution loop */
213
e4533c7a 214int cpu_exec(CPUState *env1)
7d13299d 215{
1057eaa7
PB		 216#define DECLARE_HOST_REGS 1
217#include "hostregs_helper.h"
8a40a180 218 int ret, interrupt_request;
8a40a180 219 TranslationBlock *tb;
c27004ec 220 uint8_t *tc_ptr;
d5975363 221 unsigned long next_tb;
8c6939c0 222
bfed01fc
TS		 223 if (cpu_halted(env1) == EXCP_HALTED)
224 return EXCP_HALTED;
5a1e3cfc 225
5fafdf24 226 cpu_single_env = env1;
6a00d601 227
7d13299d 228 /* first we save global registers */
1057eaa7
PB		 229#define SAVE_HOST_REGS 1
230#include "hostregs_helper.h"
c27004ec 231 env = env1;
e4533c7a 232
0d1a29f9 233 env_to_regs();
ecb644f4 234#if defined(TARGET_I386)
9de5e440 235 /* put eflags in CPU temporary format */
fc2b4c48
FB		 236 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
237 DF = 1 - (2 * ((env->eflags >> 10) & 1));
9de5e440 238 CC_OP = CC_OP_EFLAGS;
fc2b4c48 239 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
93ac68bc 240#elif defined(TARGET_SPARC)
e6e5906b
PB		 241#elif defined(TARGET_M68K)
242 env->cc_op = CC_OP_FLAGS;
243 env->cc_dest = env->sr & 0xf;
244 env->cc_x = (env->sr >> 4) & 1;
ecb644f4
TS		 245#elif defined(TARGET_ALPHA)
246#elif defined(TARGET_ARM)
247#elif defined(TARGET_PPC)
b779e29e 248#elif defined(TARGET_MICROBLAZE)
6af0bf9c 249#elif defined(TARGET_MIPS)
fdf9b3e8 250#elif defined(TARGET_SH4)
f1ccf904 251#elif defined(TARGET_CRIS)
10ec5117 252#elif defined(TARGET_S390X)
fdf9b3e8 253 /* XXXXX */
e4533c7a
FB		 254#else
255#error unsupported target CPU
256#endif
3fb2ded1 257 env->exception_index = -1;
9d27abd9 258
7d13299d 259 /* prepare setjmp context for exception handling */
3fb2ded1
FB		 260 for(;;) {
261 if (setjmp(env->jmp_env) == 0) {
dfe5fff3 262#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
9ddff3d2
BS		 263#undef env
264 env = cpu_single_env;
265#define env cpu_single_env
266#endif
ee8b7021 267 env->current_tb = NULL;
3fb2ded1
FB		 268 /* if an exception is pending, we execute it here */
269 if (env->exception_index >= 0) {
270 if (env->exception_index >= EXCP_INTERRUPT) {
271 /* exit request from the cpu execution loop */
272 ret = env->exception_index;
6e140f28
AL		 273 if (ret == EXCP_DEBUG)
274 cpu_handle_debug_exception(env);
3fb2ded1 275 break;
72d239ed
AJ		 276 } else {
277#if defined(CONFIG_USER_ONLY)
3fb2ded1 278 /* if user mode only, we simulate a fake exception
9f083493 279 which will be handled outside the cpu execution
3fb2ded1 280 loop */
83479e77 281#if defined(TARGET_I386)
5fafdf24
TS		 282 do_interrupt_user(env->exception_index,
283 env->exception_is_int,
284 env->error_code,
3fb2ded1 285 env->exception_next_eip);
eba01623
FB		 286 /* successfully delivered */
287 env->old_exception = -1;
83479e77 288#endif
3fb2ded1
FB		 289 ret = env->exception_index;
290 break;
72d239ed 291#else
83479e77 292#if defined(TARGET_I386)
3fb2ded1
FB		 293 /* simulate a real cpu exception. On i386, it can
294 trigger new exceptions, but we do not handle
295 double or triple faults yet. */
5fafdf24
TS		 296 do_interrupt(env->exception_index,
297 env->exception_is_int,
298 env->error_code,
d05e66d2 299 env->exception_next_eip, 0);
678dde13
TS		 300 /* successfully delivered */
301 env->old_exception = -1;
ce09776b
FB		 302#elif defined(TARGET_PPC)
303 do_interrupt(env);
b779e29e
EI		 304#elif defined(TARGET_MICROBLAZE)
305 do_interrupt(env);
6af0bf9c
FB		 306#elif defined(TARGET_MIPS)
307 do_interrupt(env);
e95c8d51 308#elif defined(TARGET_SPARC)
f2bc7e7f 309 do_interrupt(env);
b5ff1b31
FB		 310#elif defined(TARGET_ARM)
311 do_interrupt(env);
fdf9b3e8
FB		 312#elif defined(TARGET_SH4)
313 do_interrupt(env);
eddf68a6
JM		 314#elif defined(TARGET_ALPHA)
315 do_interrupt(env);
f1ccf904
TS		 316#elif defined(TARGET_CRIS)
317 do_interrupt(env);
0633879f
PB		 318#elif defined(TARGET_M68K)
319 do_interrupt(0);
72d239ed 320#endif
83479e77 321#endif
3fb2ded1
FB		 322 }
323 env->exception_index = -1;
5fafdf24 324 }
9df217a3 325
7ba1e619 326 if (kvm_enabled()) {
becfc390
AL		 327 kvm_cpu_exec(env);
328 longjmp(env->jmp_env, 1);
7ba1e619
AL		 329 }
330
b5fc09ae 331 next_tb = 0; /* force lookup of first TB */
3fb2ded1 332 for(;;) {
68a79315 333 interrupt_request = env->interrupt_request;
e1638bd8 334 if (unlikely(interrupt_request)) {
335 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
336 /* Mask out external interrupts for this step. */
337 interrupt_request &= ~(CPU_INTERRUPT_HARD |
338 CPU_INTERRUPT_FIQ |
339 CPU_INTERRUPT_SMI |
340 CPU_INTERRUPT_NMI);
341 }
6658ffb8
PB		 342 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
343 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
344 env->exception_index = EXCP_DEBUG;
345 cpu_loop_exit();
346 }
a90b7318 347#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
b779e29e
EI		 348 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
349 defined(TARGET_MICROBLAZE)
a90b7318
AZ		 350 if (interrupt_request & CPU_INTERRUPT_HALT) {
351 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
352 env->halted = 1;
353 env->exception_index = EXCP_HLT;
354 cpu_loop_exit();
355 }
356#endif
68a79315 357#if defined(TARGET_I386)
b09ea7d5
GN		 358 if (interrupt_request & CPU_INTERRUPT_INIT) {
359 svm_check_intercept(SVM_EXIT_INIT);
360 do_cpu_init(env);
361 env->exception_index = EXCP_HALTED;
362 cpu_loop_exit();
363 } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
364 do_cpu_sipi(env);
365 } else if (env->hflags2 & HF2_GIF_MASK) {
db620f46
FB		 366 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
367 !(env->hflags & HF_SMM_MASK)) {
368 svm_check_intercept(SVM_EXIT_SMI);
369 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
370 do_smm_enter();
371 next_tb = 0;
372 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
373 !(env->hflags2 & HF2_NMI_MASK)) {
374 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
375 env->hflags2 |= HF2_NMI_MASK;
376 do_interrupt(EXCP02_NMI, 0, 0, 0, 1);
377 next_tb = 0;
79c4f6b0
HY		 378 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
379 env->interrupt_request &= ~CPU_INTERRUPT_MCE;
380 do_interrupt(EXCP12_MCHK, 0, 0, 0, 0);
381 next_tb = 0;
db620f46
FB		 382 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
383 (((env->hflags2 & HF2_VINTR_MASK) &&
384 (env->hflags2 & HF2_HIF_MASK)) ||
385 (!(env->hflags2 & HF2_VINTR_MASK) &&
386 (env->eflags & IF_MASK &&
387 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
388 int intno;
389 svm_check_intercept(SVM_EXIT_INTR);
390 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
391 intno = cpu_get_pic_interrupt(env);
93fcfe39 392 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
dfe5fff3 393#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
9ddff3d2
BS		 394#undef env
395 env = cpu_single_env;
396#define env cpu_single_env
397#endif
db620f46
FB		 398 do_interrupt(intno, 0, 0, 0, 1);
399 /* ensure that no TB jump will be modified as
400 the program flow was changed */
401 next_tb = 0;
0573fbfc 402#if !defined(CONFIG_USER_ONLY)
db620f46
FB		 403 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
404 (env->eflags & IF_MASK) &&
405 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
406 int intno;
407 /* FIXME: this should respect TPR */
408 svm_check_intercept(SVM_EXIT_VINTR);
db620f46 409 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
93fcfe39 410 qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
db620f46 411 do_interrupt(intno, 0, 0, 0, 1);
d40c54d6 412 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
db620f46 413 next_tb = 0;
907a5b26 414#endif
db620f46 415 }
68a79315 416 }
ce09776b 417#elif defined(TARGET_PPC)
9fddaa0c
FB		 418#if 0
419 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
d84bda46 420 cpu_reset(env);
9fddaa0c
FB		 421 }
422#endif
47103572 423 if (interrupt_request & CPU_INTERRUPT_HARD) {
e9df014c
JM		 424 ppc_hw_interrupt(env);
425 if (env->pending_interrupts == 0)
426 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
b5fc09ae 427 next_tb = 0;
ce09776b 428 }
b779e29e
EI		 429#elif defined(TARGET_MICROBLAZE)
430 if ((interrupt_request & CPU_INTERRUPT_HARD)
431 && (env->sregs[SR_MSR] & MSR_IE)
432 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
433 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
434 env->exception_index = EXCP_IRQ;
435 do_interrupt(env);
436 next_tb = 0;
437 }
6af0bf9c
FB		 438#elif defined(TARGET_MIPS)
439 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
24c7b0e3 440 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
6af0bf9c 441 (env->CP0_Status & (1 << CP0St_IE)) &&
24c7b0e3
TS		 442 !(env->CP0_Status & (1 << CP0St_EXL)) &&
443 !(env->CP0_Status & (1 << CP0St_ERL)) &&
6af0bf9c
FB		 444 !(env->hflags & MIPS_HFLAG_DM)) {
445 /* Raise it */
446 env->exception_index = EXCP_EXT_INTERRUPT;
447 env->error_code = 0;
448 do_interrupt(env);
b5fc09ae 449 next_tb = 0;
6af0bf9c 450 }
e95c8d51 451#elif defined(TARGET_SPARC)
66321a11 452 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
5210977a 453 cpu_interrupts_enabled(env)) {
66321a11
FB		 454 int pil = env->interrupt_index & 15;
455 int type = env->interrupt_index & 0xf0;
456
457 if (((type == TT_EXTINT) &&
458 (pil == 15 || pil > env->psrpil)) ||
459 type != TT_EXTINT) {
460 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
f2bc7e7f
BS		 461 env->exception_index = env->interrupt_index;
462 do_interrupt(env);
66321a11 463 env->interrupt_index = 0;
b5fc09ae 464 next_tb = 0;
66321a11 465 }
e95c8d51
FB		 466 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
467 //do_interrupt(0, 0, 0, 0, 0);
468 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
a90b7318 469 }
b5ff1b31
FB		 470#elif defined(TARGET_ARM)
471 if (interrupt_request & CPU_INTERRUPT_FIQ
472 && !(env->uncached_cpsr & CPSR_F)) {
473 env->exception_index = EXCP_FIQ;
474 do_interrupt(env);
b5fc09ae 475 next_tb = 0;
b5ff1b31 476 }
9ee6e8bb
PB		 477 /* ARMv7-M interrupt return works by loading a magic value
478 into the PC. On real hardware the load causes the
479 return to occur. The qemu implementation performs the
480 jump normally, then does the exception return when the
481 CPU tries to execute code at the magic address.
482 This will cause the magic PC value to be pushed to
483 the stack if an interrupt occured at the wrong time.
484 We avoid this by disabling interrupts when
485 pc contains a magic address. */
b5ff1b31 486 if (interrupt_request & CPU_INTERRUPT_HARD
9ee6e8bb
PB		 487 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
488 || !(env->uncached_cpsr & CPSR_I))) {
b5ff1b31
FB		 489 env->exception_index = EXCP_IRQ;
490 do_interrupt(env);
b5fc09ae 491 next_tb = 0;
b5ff1b31 492 }
fdf9b3e8 493#elif defined(TARGET_SH4)
e96e2044
TS		 494 if (interrupt_request & CPU_INTERRUPT_HARD) {
495 do_interrupt(env);
b5fc09ae 496 next_tb = 0;
e96e2044 497 }
eddf68a6
JM		 498#elif defined(TARGET_ALPHA)
499 if (interrupt_request & CPU_INTERRUPT_HARD) {
500 do_interrupt(env);
b5fc09ae 501 next_tb = 0;
eddf68a6 502 }
f1ccf904 503#elif defined(TARGET_CRIS)
1b1a38b0
EI		 504 if (interrupt_request & CPU_INTERRUPT_HARD
505 && (env->pregs[PR_CCS] & I_FLAG)) {
506 env->exception_index = EXCP_IRQ;
507 do_interrupt(env);
508 next_tb = 0;
509 }
510 if (interrupt_request & CPU_INTERRUPT_NMI
511 && (env->pregs[PR_CCS] & M_FLAG)) {
512 env->exception_index = EXCP_NMI;
f1ccf904 513 do_interrupt(env);
b5fc09ae 514 next_tb = 0;
f1ccf904 515 }
0633879f
PB		 516#elif defined(TARGET_M68K)
517 if (interrupt_request & CPU_INTERRUPT_HARD
518 && ((env->sr & SR_I) >> SR_I_SHIFT)
519 < env->pending_level) {
520 /* Real hardware gets the interrupt vector via an
521 IACK cycle at this point. Current emulated
522 hardware doesn't rely on this, so we
523 provide/save the vector when the interrupt is
524 first signalled. */
525 env->exception_index = env->pending_vector;
526 do_interrupt(1);
b5fc09ae 527 next_tb = 0;
0633879f 528 }
68a79315 529#endif
9d05095e
FB		 530 /* Don't use the cached interupt_request value,
531 do_interrupt may have updated the EXITTB flag. */
b5ff1b31 532 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
bf3e8bf1
FB		 533 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
534 /* ensure that no TB jump will be modified as
535 the program flow was changed */
b5fc09ae 536 next_tb = 0;
bf3e8bf1 537 }
be214e6c
AJ		 538 }
539 if (unlikely(env->exit_request)) {
540 env->exit_request = 0;
541 env->exception_index = EXCP_INTERRUPT;
542 cpu_loop_exit();
3fb2ded1 543 }
f0667e66 544#ifdef CONFIG_DEBUG_EXEC
8fec2b8c 545 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
3fb2ded1 546 /* restore flags in standard format */
ecb644f4
TS		 547 regs_to_env();
548#if defined(TARGET_I386)
a7812ae4 549 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
93fcfe39 550 log_cpu_state(env, X86_DUMP_CCOP);
3fb2ded1 551 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
e4533c7a 552#elif defined(TARGET_ARM)
93fcfe39 553 log_cpu_state(env, 0);
93ac68bc 554#elif defined(TARGET_SPARC)
93fcfe39 555 log_cpu_state(env, 0);
67867308 556#elif defined(TARGET_PPC)
93fcfe39 557 log_cpu_state(env, 0);
e6e5906b
PB		 558#elif defined(TARGET_M68K)
559 cpu_m68k_flush_flags(env, env->cc_op);
560 env->cc_op = CC_OP_FLAGS;
561 env->sr = (env->sr & 0xffe0)
562 | env->cc_dest | (env->cc_x << 4);
93fcfe39 563 log_cpu_state(env, 0);
b779e29e
EI		 564#elif defined(TARGET_MICROBLAZE)
565 log_cpu_state(env, 0);
6af0bf9c 566#elif defined(TARGET_MIPS)
93fcfe39 567 log_cpu_state(env, 0);
fdf9b3e8 568#elif defined(TARGET_SH4)
93fcfe39 569 log_cpu_state(env, 0);
eddf68a6 570#elif defined(TARGET_ALPHA)
93fcfe39 571 log_cpu_state(env, 0);
f1ccf904 572#elif defined(TARGET_CRIS)
93fcfe39 573 log_cpu_state(env, 0);
e4533c7a 574#else
5fafdf24 575#error unsupported target CPU
e4533c7a 576#endif
3fb2ded1 577 }
7d13299d 578#endif
d5975363 579 spin_lock(&tb_lock);
8a40a180 580 tb = tb_find_fast();
d5975363
PB		 581 /* Note: we do it here to avoid a gcc bug on Mac OS X when
582 doing it in tb_find_slow */
583 if (tb_invalidated_flag) {
584 /* as some TB could have been invalidated because
585 of memory exceptions while generating the code, we
586 must recompute the hash index here */
587 next_tb = 0;
2e70f6ef 588 tb_invalidated_flag = 0;
d5975363 589 }
f0667e66 590#ifdef CONFIG_DEBUG_EXEC
93fcfe39
AL		 591 qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
592 (long)tb->tc_ptr, tb->pc,
593 lookup_symbol(tb->pc));
9d27abd9 594#endif
8a40a180
FB		 595 /* see if we can patch the calling TB. When the TB
596 spans two pages, we cannot safely do a direct
597 jump. */
c27004ec 598 {
4a1418e0 599 if (next_tb != 0 && tb->page_addr[1] == -1) {
b5fc09ae 600 tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
3fb2ded1 601 }
c27004ec 602 }
d5975363 603 spin_unlock(&tb_lock);
83479e77 604 env->current_tb = tb;
55e8b85e 605
606 /* cpu_interrupt might be called while translating the
607 TB, but before it is linked into a potentially
608 infinite loop and becomes env->current_tb. Avoid
609 starting execution if there is a pending interrupt. */
be214e6c 610 if (unlikely (env->exit_request))
55e8b85e 611 env->current_tb = NULL;
612
2e70f6ef
PB		 613 while (env->current_tb) {
614 tc_ptr = tb->tc_ptr;
3fb2ded1 615 /* execute the generated code */
dfe5fff3 616#if defined(__sparc__) && !defined(CONFIG_SOLARIS)
572a9d4a 617#undef env
2e70f6ef 618 env = cpu_single_env;
572a9d4a
BS		 619#define env cpu_single_env
620#endif
2e70f6ef
PB		 621 next_tb = tcg_qemu_tb_exec(tc_ptr);
622 env->current_tb = NULL;
623 if ((next_tb & 3) == 2) {
bf20dc07 624 /* Instruction counter expired. */
2e70f6ef
PB		 625 int insns_left;
626 tb = (TranslationBlock *)(long)(next_tb & ~3);
627 /* Restore PC. */
622ed360 628 cpu_pc_from_tb(env, tb);
2e70f6ef
PB		 629 insns_left = env->icount_decr.u32;
630 if (env->icount_extra && insns_left >= 0) {
631 /* Refill decrementer and continue execution. */
632 env->icount_extra += insns_left;
633 if (env->icount_extra > 0xffff) {
634 insns_left = 0xffff;
635 } else {
636 insns_left = env->icount_extra;
637 }
638 env->icount_extra -= insns_left;
639 env->icount_decr.u16.low = insns_left;
640 } else {
641 if (insns_left > 0) {
642 /* Execute remaining instructions. */
643 cpu_exec_nocache(insns_left, tb);
644 }
645 env->exception_index = EXCP_INTERRUPT;
646 next_tb = 0;
647 cpu_loop_exit();
648 }
649 }
650 }
4cbf74b6
FB		 651 /* reset soft MMU for next block (it can currently
652 only be set by a memory fault) */
50a518e3 653 } /* for(;;) */
3fb2ded1 654 } else {
0d1a29f9 655 env_to_regs();
7d13299d 656 }
3fb2ded1
FB		 657 } /* for(;;) */
658
7d13299d 659
e4533c7a 660#if defined(TARGET_I386)
9de5e440 661 /* restore flags in standard format */
a7812ae4 662 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
e4533c7a 663#elif defined(TARGET_ARM)
b7bcbe95 664 /* XXX: Save/restore host fpu exception state?. */
93ac68bc 665#elif defined(TARGET_SPARC)
67867308 666#elif defined(TARGET_PPC)
e6e5906b
PB		 667#elif defined(TARGET_M68K)
668 cpu_m68k_flush_flags(env, env->cc_op);
669 env->cc_op = CC_OP_FLAGS;
670 env->sr = (env->sr & 0xffe0)
671 | env->cc_dest | (env->cc_x << 4);
b779e29e 672#elif defined(TARGET_MICROBLAZE)
6af0bf9c 673#elif defined(TARGET_MIPS)
fdf9b3e8 674#elif defined(TARGET_SH4)
eddf68a6 675#elif defined(TARGET_ALPHA)
f1ccf904 676#elif defined(TARGET_CRIS)
10ec5117 677#elif defined(TARGET_S390X)
fdf9b3e8 678 /* XXXXX */
e4533c7a
FB		 679#else
680#error unsupported target CPU
681#endif
1057eaa7
PB		 682
683 /* restore global registers */
1057eaa7
PB		 684#include "hostregs_helper.h"
685
6a00d601 686 /* fail safe : never use cpu_single_env outside cpu_exec() */
5fafdf24 687 cpu_single_env = NULL;
7d13299d
FB		 688 return ret;
689}
6dbad63e 690
fbf9eeb3
FB		 691/* must only be called from the generated code as an exception can be
692 generated */
693void tb_invalidate_page_range(target_ulong start, target_ulong end)
694{
dc5d0b3d
FB		 695 /* XXX: cannot enable it yet because it yields to MMU exception
696 where NIP != read address on PowerPC */
697#if 0
fbf9eeb3
FB		 698 target_ulong phys_addr;
699 phys_addr = get_phys_addr_code(env, start);
700 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
dc5d0b3d 701#endif
fbf9eeb3
FB		 702}
703
1a18c71b 704#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
e4533c7a 705
6dbad63e
FB		 706void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
707{
708 CPUX86State *saved_env;
709
710 saved_env = env;
711 env = s;
a412ac57 712 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
a513fe19 713 selector &= 0xffff;
5fafdf24 714 cpu_x86_load_seg_cache(env, seg_reg, selector,
c27004ec 715 (selector << 4), 0xffff, 0);
a513fe19 716 } else {
5d97559d 717 helper_load_seg(seg_reg, selector);
a513fe19 718 }
6dbad63e
FB		 719 env = saved_env;
720}
9de5e440 721
6f12a2a6 722void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 723{
724 CPUX86State *saved_env;
725
726 saved_env = env;
727 env = s;
3b46e624 728
6f12a2a6 729 helper_fsave(ptr, data32);
d0a1ffc9
FB		 730
731 env = saved_env;
732}
733
6f12a2a6 734void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
d0a1ffc9
FB		 735{
736 CPUX86State *saved_env;
737
738 saved_env = env;
739 env = s;
3b46e624 740
6f12a2a6 741 helper_frstor(ptr, data32);
d0a1ffc9
FB		 742
743 env = saved_env;
744}
745
e4533c7a
FB		 746#endif /* TARGET_I386 */
747
67b915a5
FB		 748#if !defined(CONFIG_SOFTMMU)
749
3fb2ded1 750#if defined(TARGET_I386)
0b5c1ce8
NF		 751#define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code)
752#else
753#define EXCEPTION_ACTION cpu_loop_exit()
754#endif
3fb2ded1 755
b56dad1c 756/* 'pc' is the host PC at which the exception was raised. 'address' is
fd6ce8f6
FB		 757 the effective address of the memory exception. 'is_write' is 1 if a
758 write caused the exception and otherwise 0'. 'old_set' is the
759 signal set which should be restored */
2b413144 760static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
5fafdf24 761 int is_write, sigset_t *old_set,
bf3e8bf1 762 void *puc)
9de5e440 763{
a513fe19
FB		 764 TranslationBlock *tb;
765 int ret;
68a79315 766
83479e77
FB		 767 if (cpu_single_env)
768 env = cpu_single_env; /* XXX: find a correct solution for multithread */
fd6ce8f6 769#if defined(DEBUG_SIGNAL)
5fafdf24 770 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
bf3e8bf1 771 pc, address, is_write, *(unsigned long *)old_set);
9de5e440 772#endif
25eb4484 773 /* XXX: locking issue */
53a5960a 774 if (is_write && page_unprotect(h2g(address), pc, puc)) {
fd6ce8f6
FB		 775 return 1;
776 }
fbf9eeb3 777
3fb2ded1 778 /* see if it is an MMU fault */
0b5c1ce8 779 ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
68016c62
FB		 780 if (ret < 0)
781 return 0; /* not an MMU fault */
782 if (ret == 0)
783 return 1; /* the MMU fault was handled without causing real CPU fault */
784 /* now we have a real cpu fault */
785 tb = tb_find_pc(pc);
786 if (tb) {
787 /* the PC is inside the translated code. It means that we have
788 a virtual CPU fault */
789 cpu_restore_state(tb, env, pc, puc);
790 }
68016c62 791
68016c62
FB		 792 /* we restore the process signal mask as the sigreturn should
793 do it (XXX: use sigsetjmp) */
794 sigprocmask(SIG_SETMASK, old_set, NULL);
0b5c1ce8 795 EXCEPTION_ACTION;
e6e5906b 796
e6e5906b 797 /* never comes here */
67867308
FB		 798 return 1;
799}
6af0bf9c 800
2b413144
FB		 801#if defined(__i386__)
802
d8ecc0b9
FB		 803#if defined(__APPLE__)
804# include <sys/ucontext.h>
805
806# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
807# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
808# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
d39bb24a 809# define MASK_sig(context) ((context)->uc_sigmask)
78cfb07f
JL		 810#elif defined (__NetBSD__)
811# include <ucontext.h>
812
813# define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
814# define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
815# define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
816# define MASK_sig(context) ((context)->uc_sigmask)
817#elif defined (__FreeBSD__) || defined(__DragonFly__)
818# include <ucontext.h>
819
820# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_eip))
821# define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
822# define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
823# define MASK_sig(context) ((context)->uc_sigmask)
d39bb24a
BS		 824#elif defined(__OpenBSD__)
825# define EIP_sig(context) ((context)->sc_eip)
826# define TRAP_sig(context) ((context)->sc_trapno)
827# define ERROR_sig(context) ((context)->sc_err)
828# define MASK_sig(context) ((context)->sc_mask)
d8ecc0b9
FB		 829#else
830# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
831# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
832# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
d39bb24a 833# define MASK_sig(context) ((context)->uc_sigmask)
d8ecc0b9
FB		 834#endif
835
5fafdf24 836int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 837 void *puc)
9de5e440 838{
5a7b542b 839 siginfo_t *info = pinfo;
78cfb07f
JL		 840#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
841 ucontext_t *uc = puc;
842#elif defined(__OpenBSD__)
d39bb24a
BS		 843 struct sigcontext *uc = puc;
844#else
9de5e440 845 struct ucontext *uc = puc;
d39bb24a 846#endif
9de5e440 847 unsigned long pc;
bf3e8bf1 848 int trapno;
97eb5b14 849
d691f669
FB		 850#ifndef REG_EIP
851/* for glibc 2.1 */
fd6ce8f6
FB		 852#define REG_EIP EIP
853#define REG_ERR ERR
854#define REG_TRAPNO TRAPNO
d691f669 855#endif
d8ecc0b9
FB		 856 pc = EIP_sig(uc);
857 trapno = TRAP_sig(uc);
ec6338ba
FB		 858 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
859 trapno == 0xe ?
860 (ERROR_sig(uc) >> 1) & 1 : 0,
d39bb24a 861 &MASK_sig(uc), puc);
2b413144
FB		 862}
863
bc51c5c9
FB		 864#elif defined(__x86_64__)
865
b3efe5c8 866#ifdef __NetBSD__
d397abbd
BS		 867#define PC_sig(context) _UC_MACHINE_PC(context)
868#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
869#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
870#define MASK_sig(context) ((context)->uc_sigmask)
871#elif defined(__OpenBSD__)
872#define PC_sig(context) ((context)->sc_rip)
873#define TRAP_sig(context) ((context)->sc_trapno)
874#define ERROR_sig(context) ((context)->sc_err)
875#define MASK_sig(context) ((context)->sc_mask)
78cfb07f
JL		 876#elif defined (__FreeBSD__) || defined(__DragonFly__)
877#include <ucontext.h>
878
879#define PC_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_rip))
880#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
881#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
882#define MASK_sig(context) ((context)->uc_sigmask)
b3efe5c8 883#else
d397abbd
BS		 884#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
885#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
886#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
887#define MASK_sig(context) ((context)->uc_sigmask)
b3efe5c8
BS		 888#endif
889
5a7b542b 890int cpu_signal_handler(int host_signum, void *pinfo,
bc51c5c9
FB		 891 void *puc)
892{
5a7b542b 893 siginfo_t *info = pinfo;
bc51c5c9 894 unsigned long pc;
78cfb07f 895#if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
b3efe5c8 896 ucontext_t *uc = puc;
d397abbd
BS		 897#elif defined(__OpenBSD__)
898 struct sigcontext *uc = puc;
b3efe5c8
BS		 899#else
900 struct ucontext *uc = puc;
901#endif
bc51c5c9 902
d397abbd 903 pc = PC_sig(uc);
5fafdf24 904 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
d397abbd
BS		 905 TRAP_sig(uc) == 0xe ?
906 (ERROR_sig(uc) >> 1) & 1 : 0,
907 &MASK_sig(uc), puc);
bc51c5c9
FB		 908}
909
e58ffeb3 910#elif defined(_ARCH_PPC)
2b413144 911
83fb7adf
FB		 912/***********************************************************************
913 * signal context platform-specific definitions
914 * From Wine
915 */
916#ifdef linux
917/* All Registers access - only for local access */
918# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
919/* Gpr Registers access */
920# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
921# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
922# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
923# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
924# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
925# define LR_sig(context) REG_sig(link, context) /* Link register */
926# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
927/* Float Registers access */
928# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
929# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
930/* Exception Registers access */
931# define DAR_sig(context) REG_sig(dar, context)
932# define DSISR_sig(context) REG_sig(dsisr, context)
933# define TRAP_sig(context) REG_sig(trap, context)
934#endif /* linux */
935
936#ifdef __APPLE__
937# include <sys/ucontext.h>
938typedef struct ucontext SIGCONTEXT;
939/* All Registers access - only for local access */
940# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
941# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
942# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
943# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
944/* Gpr Registers access */
945# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
946# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
947# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
948# define CTR_sig(context) REG_sig(ctr, context)
949# define XER_sig(context) REG_sig(xer, context) /* Link register */
950# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
951# define CR_sig(context) REG_sig(cr, context) /* Condition register */
952/* Float Registers access */
953# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
954# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
955/* Exception Registers access */
956# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
957# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
958# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
959#endif /* __APPLE__ */
960
5fafdf24 961int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 962 void *puc)
2b413144 963{
5a7b542b 964 siginfo_t *info = pinfo;
25eb4484 965 struct ucontext *uc = puc;
25eb4484 966 unsigned long pc;
25eb4484
FB		 967 int is_write;
968
83fb7adf 969 pc = IAR_sig(uc);
25eb4484
FB		 970 is_write = 0;
971#if 0
972 /* ppc 4xx case */
83fb7adf 973 if (DSISR_sig(uc) & 0x00800000)
25eb4484
FB		 974 is_write = 1;
975#else
83fb7adf 976 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
25eb4484
FB		 977 is_write = 1;
978#endif
5fafdf24 979 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 980 is_write, &uc->uc_sigmask, puc);
2b413144
FB		 981}
982
2f87c607
FB		 983#elif defined(__alpha__)
984
5fafdf24 985int cpu_signal_handler(int host_signum, void *pinfo,
2f87c607
FB		 986 void *puc)
987{
5a7b542b 988 siginfo_t *info = pinfo;
2f87c607
FB		 989 struct ucontext *uc = puc;
990 uint32_t *pc = uc->uc_mcontext.sc_pc;
991 uint32_t insn = *pc;
992 int is_write = 0;
993
8c6939c0 994 /* XXX: need kernel patch to get write flag faster */
2f87c607
FB		 995 switch (insn >> 26) {
996 case 0x0d: // stw
997 case 0x0e: // stb
998 case 0x0f: // stq_u
999 case 0x24: // stf
1000 case 0x25: // stg
1001 case 0x26: // sts
1002 case 0x27: // stt
1003 case 0x2c: // stl
1004 case 0x2d: // stq
1005 case 0x2e: // stl_c
1006 case 0x2f: // stq_c
1007 is_write = 1;
1008 }
1009
5fafdf24 1010 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1011 is_write, &uc->uc_sigmask, puc);
2f87c607 1012}
8c6939c0
FB		 1013#elif defined(__sparc__)
1014
5fafdf24 1015int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1016 void *puc)
8c6939c0 1017{
5a7b542b 1018 siginfo_t *info = pinfo;
8c6939c0
FB		 1019 int is_write;
1020 uint32_t insn;
dfe5fff3 1021#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
c9e1e2b0
BS		 1022 uint32_t *regs = (uint32_t *)(info + 1);
1023 void *sigmask = (regs + 20);
8c6939c0 1024 /* XXX: is there a standard glibc define ? */
c9e1e2b0
BS		 1025 unsigned long pc = regs[1];
1026#else
84778508 1027#ifdef __linux__
c9e1e2b0
BS		 1028 struct sigcontext *sc = puc;
1029 unsigned long pc = sc->sigc_regs.tpc;
1030 void *sigmask = (void *)sc->sigc_mask;
84778508
BS		 1031#elif defined(__OpenBSD__)
1032 struct sigcontext *uc = puc;
1033 unsigned long pc = uc->sc_pc;
1034 void *sigmask = (void *)(long)uc->sc_mask;
1035#endif
c9e1e2b0
BS		 1036#endif
1037
8c6939c0
FB		 1038 /* XXX: need kernel patch to get write flag faster */
1039 is_write = 0;
1040 insn = *(uint32_t *)pc;
1041 if ((insn >> 30) == 3) {
1042 switch((insn >> 19) & 0x3f) {
1043 case 0x05: // stb
d877fa5a 1044 case 0x15: // stba
8c6939c0 1045 case 0x06: // sth
d877fa5a 1046 case 0x16: // stha
8c6939c0 1047 case 0x04: // st
d877fa5a 1048 case 0x14: // sta
8c6939c0 1049 case 0x07: // std
d877fa5a
BS		 1050 case 0x17: // stda
1051 case 0x0e: // stx
1052 case 0x1e: // stxa
8c6939c0 1053 case 0x24: // stf
d877fa5a 1054 case 0x34: // stfa
8c6939c0 1055 case 0x27: // stdf
d877fa5a
BS		 1056 case 0x37: // stdfa
1057 case 0x26: // stqf
1058 case 0x36: // stqfa
8c6939c0 1059 case 0x25: // stfsr
d877fa5a
BS		 1060 case 0x3c: // casa
1061 case 0x3e: // casxa
8c6939c0
FB		 1062 is_write = 1;
1063 break;
1064 }
1065 }
5fafdf24 1066 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
bf3e8bf1 1067 is_write, sigmask, NULL);
8c6939c0
FB		 1068}
1069
1070#elif defined(__arm__)
1071
5fafdf24 1072int cpu_signal_handler(int host_signum, void *pinfo,
e4533c7a 1073 void *puc)
8c6939c0 1074{
5a7b542b 1075 siginfo_t *info = pinfo;
8c6939c0
FB		 1076 struct ucontext *uc = puc;
1077 unsigned long pc;
1078 int is_write;
3b46e624 1079
48bbf11b 1080#if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
5c49b363
AZ		 1081 pc = uc->uc_mcontext.gregs[R15];
1082#else
4eee57f5 1083 pc = uc->uc_mcontext.arm_pc;
5c49b363 1084#endif
8c6939c0
FB		 1085 /* XXX: compute is_write */
1086 is_write = 0;
5fafdf24 1087 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
8c6939c0 1088 is_write,
f3a9676a 1089 &uc->uc_sigmask, puc);
8c6939c0
FB		 1090}
1091
38e584a0
FB		 1092#elif defined(__mc68000)
1093
5fafdf24 1094int cpu_signal_handler(int host_signum, void *pinfo,
38e584a0
FB		 1095 void *puc)
1096{
5a7b542b 1097 siginfo_t *info = pinfo;
38e584a0
FB		 1098 struct ucontext *uc = puc;
1099 unsigned long pc;
1100 int is_write;
3b46e624 1101
38e584a0
FB		 1102 pc = uc->uc_mcontext.gregs[16];
1103 /* XXX: compute is_write */
1104 is_write = 0;
5fafdf24 1105 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
38e584a0 1106 is_write,
bf3e8bf1 1107 &uc->uc_sigmask, puc);
38e584a0
FB		 1108}
1109
b8076a74
FB		 1110#elif defined(__ia64)
1111
1112#ifndef __ISR_VALID
1113 /* This ought to be in <bits/siginfo.h>... */
1114# define __ISR_VALID 1
b8076a74
FB		 1115#endif
1116
5a7b542b 1117int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
b8076a74 1118{
5a7b542b 1119 siginfo_t *info = pinfo;
b8076a74
FB		 1120 struct ucontext *uc = puc;
1121 unsigned long ip;
1122 int is_write = 0;
1123
1124 ip = uc->uc_mcontext.sc_ip;
1125 switch (host_signum) {
1126 case SIGILL:
1127 case SIGFPE:
1128 case SIGSEGV:
1129 case SIGBUS:
1130 case SIGTRAP:
fd4a43e4 1131 if (info->si_code && (info->si_segvflags & __ISR_VALID))
b8076a74
FB		 1132 /* ISR.W (write-access) is bit 33: */
1133 is_write = (info->si_isr >> 33) & 1;
1134 break;
1135
1136 default:
1137 break;
1138 }
1139 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1140 is_write,
1141 &uc->uc_sigmask, puc);
1142}
1143
90cb9493
FB		 1144#elif defined(__s390__)
1145
5fafdf24 1146int cpu_signal_handler(int host_signum, void *pinfo,
90cb9493
FB		 1147 void *puc)
1148{
5a7b542b 1149 siginfo_t *info = pinfo;
90cb9493
FB		 1150 struct ucontext *uc = puc;
1151 unsigned long pc;
1152 int is_write;
3b46e624 1153
90cb9493
FB		 1154 pc = uc->uc_mcontext.psw.addr;
1155 /* XXX: compute is_write */
1156 is_write = 0;
5fafdf24 1157 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18
TS		 1158 is_write, &uc->uc_sigmask, puc);
1159}
1160
1161#elif defined(__mips__)
1162
5fafdf24 1163int cpu_signal_handler(int host_signum, void *pinfo,
c4b89d18
TS		 1164 void *puc)
1165{
9617efe8 1166 siginfo_t *info = pinfo;
c4b89d18
TS		 1167 struct ucontext *uc = puc;
1168 greg_t pc = uc->uc_mcontext.pc;
1169 int is_write;
3b46e624 1170
c4b89d18
TS		 1171 /* XXX: compute is_write */
1172 is_write = 0;
5fafdf24 1173 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
c4b89d18 1174 is_write, &uc->uc_sigmask, puc);
90cb9493
FB		 1175}
1176
f54b3f92
AJ		 1177#elif defined(__hppa__)
1178
1179int cpu_signal_handler(int host_signum, void *pinfo,
1180 void *puc)
1181{
1182 struct siginfo *info = pinfo;
1183 struct ucontext *uc = puc;
1184 unsigned long pc;
1185 int is_write;
1186
1187 pc = uc->uc_mcontext.sc_iaoq[0];
1188 /* FIXME: compute is_write */
1189 is_write = 0;
1190 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1191 is_write,
1192 &uc->uc_sigmask, puc);
1193}
1194
9de5e440 1195#else
2b413144 1196
3fb2ded1 1197#error host CPU specific signal handler needed
2b413144 1198
9de5e440 1199#endif
67b915a5
FB		 1200
1201#endif /* !defined(CONFIG_SOFTMMU) */
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