[qemu.git] / hw / dma / pl080.c

/*
 * Arm PrimeCell PL080/PL081 DMA controller
 *
 * Copyright (c) 2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "exec/address-spaces.h"
#include "qemu/log.h"

#define PL080_MAX_CHANNELS 8
#define PL080_CONF_E    0x1
#define PL080_CONF_M1   0x2
#define PL080_CONF_M2   0x4

#define PL080_CCONF_H   0x40000
#define PL080_CCONF_A   0x20000
#define PL080_CCONF_L   0x10000
#define PL080_CCONF_ITC 0x08000
#define PL080_CCONF_IE  0x04000
#define PL080_CCONF_E   0x00001

#define PL080_CCTRL_I   0x80000000
#define PL080_CCTRL_DI  0x08000000
#define PL080_CCTRL_SI  0x04000000
#define PL080_CCTRL_D   0x02000000
#define PL080_CCTRL_S   0x01000000

typedef struct {
    uint32_t src;
    uint32_t dest;
    uint32_t lli;
    uint32_t ctrl;
    uint32_t conf;
} pl080_channel;

#define TYPE_PL080 "pl080"
#define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080)

typedef struct PL080State {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint8_t tc_int;
    uint8_t tc_mask;
    uint8_t err_int;
    uint8_t err_mask;
    uint32_t conf;
    uint32_t sync;
    uint32_t req_single;
    uint32_t req_burst;
    pl080_channel chan[PL080_MAX_CHANNELS];
    int nchannels;
    /* Flag to avoid recursive DMA invocations.  */
    int running;
    qemu_irq irq;
} PL080State;

static const VMStateDescription vmstate_pl080_channel = {
    .name = "pl080_channel",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(src, pl080_channel),
        VMSTATE_UINT32(dest, pl080_channel),
        VMSTATE_UINT32(lli, pl080_channel),
        VMSTATE_UINT32(ctrl, pl080_channel),
        VMSTATE_UINT32(conf, pl080_channel),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pl080 = {
    .name = "pl080",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_mask, PL080State),
        VMSTATE_UINT8(err_int, PL080State),
        VMSTATE_UINT8(err_mask, PL080State),
        VMSTATE_UINT32(conf, PL080State),
        VMSTATE_UINT32(sync, PL080State),
        VMSTATE_UINT32(req_single, PL080State),
        VMSTATE_UINT32(req_burst, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_UINT8(tc_int, PL080State),
        VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS,
                             1, vmstate_pl080_channel, pl080_channel),
        VMSTATE_INT32(running, PL080State),
        VMSTATE_END_OF_LIST()
    }
};

static const unsigned char pl080_id[] =
{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };

static const unsigned char pl081_id[] =
{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };

static void pl080_update(PL080State *s)
{
    if ((s->tc_int & s->tc_mask)
            || (s->err_int & s->err_mask))
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static void pl080_run(PL080State *s)
{
    int c;
    int flow;
    pl080_channel *ch;
    int swidth;
    int dwidth;
    int xsize;
    int n;
    int src_id;
    int dest_id;
    int size;
    uint8_t buff[4];
    uint32_t req;

    s->tc_mask = 0;
    for (c = 0; c < s->nchannels; c++) {
        if (s->chan[c].conf & PL080_CCONF_ITC)
            s->tc_mask |= 1 << c;
        if (s->chan[c].conf & PL080_CCONF_IE)
            s->err_mask |= 1 << c;
    }

    if ((s->conf & PL080_CONF_E) == 0)
        return;

hw_error("DMA active\n");
    /* If we are already in the middle of a DMA operation then indicate that
       there may be new DMA requests and return immediately.  */
    if (s->running) {
        s->running++;
        return;
    }
    s->running = 1;
    while (s->running) {
        for (c = 0; c < s->nchannels; c++) {
            ch = &s->chan[c];
again:
            /* Test if thiws channel has any pending DMA requests.  */
            if ((ch->conf & (PL080_CCONF_H | PL080_CCONF_E))
                    != PL080_CCONF_E)
                continue;
            flow = (ch->conf >> 11) & 7;
            if (flow >= 4) {
                hw_error(
                    "pl080_run: Peripheral flow control not implemented\n");
            }
            src_id = (ch->conf >> 1) & 0x1f;
            dest_id = (ch->conf >> 6) & 0x1f;
            size = ch->ctrl & 0xfff;
            req = s->req_single | s->req_burst;
            switch (flow) {
            case 0:
                break;
            case 1:
                if ((req & (1u << dest_id)) == 0)
                    size = 0;
                break;
            case 2:
                if ((req & (1u << src_id)) == 0)
                    size = 0;
                break;
            case 3:
                if ((req & (1u << src_id)) == 0
                        || (req & (1u << dest_id)) == 0)
                    size = 0;
                break;
            }
            if (!size)
                continue;

            /* Transfer one element.  */
            /* ??? Should transfer multiple elements for a burst request.  */
            /* ??? Unclear what the proper behavior is when source and
               destination widths are different.  */
            swidth = 1 << ((ch->ctrl >> 18) & 7);
            dwidth = 1 << ((ch->ctrl >> 21) & 7);
            for (n = 0; n < dwidth; n+= swidth) {
                cpu_physical_memory_read(ch->src, buff + n, swidth);
                if (ch->ctrl & PL080_CCTRL_SI)
                    ch->src += swidth;
            }
            xsize = (dwidth < swidth) ? swidth : dwidth;
            /* ??? This may pad the value incorrectly for dwidth < 32.  */
            for (n = 0; n < xsize; n += dwidth) {
                cpu_physical_memory_write(ch->dest + n, buff + n, dwidth);
                if (ch->ctrl & PL080_CCTRL_DI)
                    ch->dest += swidth;
            }

            size--;
            ch->ctrl = (ch->ctrl & 0xfffff000) | size;
            if (size == 0) {
                /* Transfer complete.  */
                if (ch->lli) {
                    ch->src = address_space_ldl_le(&address_space_memory,
                                                   ch->lli,
                                                   MEMTXATTRS_UNSPECIFIED,
                                                   NULL);
                    ch->dest = address_space_ldl_le(&address_space_memory,
                                                    ch->lli + 4,
                                                    MEMTXATTRS_UNSPECIFIED,
                                                    NULL);
                    ch->ctrl = address_space_ldl_le(&address_space_memory,
                                                    ch->lli + 12,
                                                    MEMTXATTRS_UNSPECIFIED,
                                                    NULL);
                    ch->lli = address_space_ldl_le(&address_space_memory,
                                                   ch->lli + 8,
                                                   MEMTXATTRS_UNSPECIFIED,
                                                   NULL);
                } else {
                    ch->conf &= ~PL080_CCONF_E;
                }
                if (ch->ctrl & PL080_CCTRL_I) {
                    s->tc_int |= 1 << c;
                }
            }
            goto again;
        }
        if (--s->running)
            s->running = 1;
    }
}

static uint64_t pl080_read(void *opaque, hwaddr offset,
                           unsigned size)
{
    PL080State *s = (PL080State *)opaque;
    uint32_t i;
    uint32_t mask;

    if (offset >= 0xfe0 && offset < 0x1000) {
        if (s->nchannels == 8) {
            return pl080_id[(offset - 0xfe0) >> 2];
        } else {
            return pl081_id[(offset - 0xfe0) >> 2];
        }
    }
    if (offset >= 0x100 && offset < 0x200) {
        i = (offset & 0xe0) >> 5;
        if (i >= s->nchannels)
            goto bad_offset;
        switch (offset >> 2) {
        case 0: /* SrcAddr */
            return s->chan[i].src;
        case 1: /* DestAddr */
            return s->chan[i].dest;
        case 2: /* LLI */
            return s->chan[i].lli;
        case 3: /* Control */
            return s->chan[i].ctrl;
        case 4: /* Configuration */
            return s->chan[i].conf;
        default:
            goto bad_offset;
        }
    }
    switch (offset >> 2) {
    case 0: /* IntStatus */
        return (s->tc_int & s->tc_mask) | (s->err_int & s->err_mask);
    case 1: /* IntTCStatus */
        return (s->tc_int & s->tc_mask);
    case 3: /* IntErrorStatus */
        return (s->err_int & s->err_mask);
    case 5: /* RawIntTCStatus */
        return s->tc_int;
    case 6: /* RawIntErrorStatus */
        return s->err_int;
    case 7: /* EnbldChns */
        mask = 0;
        for (i = 0; i < s->nchannels; i++) {
            if (s->chan[i].conf & PL080_CCONF_E)
                mask |= 1 << i;
        }
        return mask;
    case 8: /* SoftBReq */
    case 9: /* SoftSReq */
    case 10: /* SoftLBReq */
    case 11: /* SoftLSReq */
        /* ??? Implement these. */
        return 0;
    case 12: /* Configuration */
        return s->conf;
    case 13: /* Sync */
        return s->sync;
    default:
    bad_offset:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl080_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl080_write(void *opaque, hwaddr offset,
                        uint64_t value, unsigned size)
{
    PL080State *s = (PL080State *)opaque;
    int i;

    if (offset >= 0x100 && offset < 0x200) {
        i = (offset & 0xe0) >> 5;
        if (i >= s->nchannels)
            goto bad_offset;
        switch (offset >> 2) {
        case 0: /* SrcAddr */
            s->chan[i].src = value;
            break;
        case 1: /* DestAddr */
            s->chan[i].dest = value;
            break;
        case 2: /* LLI */
            s->chan[i].lli = value;
            break;
        case 3: /* Control */
            s->chan[i].ctrl = value;
            break;
        case 4: /* Configuration */
            s->chan[i].conf = value;
            pl080_run(s);
            break;
        }
    }
    switch (offset >> 2) {
    case 2: /* IntTCClear */
        s->tc_int &= ~value;
        break;
    case 4: /* IntErrorClear */
        s->err_int &= ~value;
        break;
    case 8: /* SoftBReq */
    case 9: /* SoftSReq */
    case 10: /* SoftLBReq */
    case 11: /* SoftLSReq */
        /* ??? Implement these.  */
        qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n");
        break;
    case 12: /* Configuration */
        s->conf = value;
        if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) {
            qemu_log_mask(LOG_UNIMP,
                          "pl080_write: Big-endian DMA not implemented\n");
        }
        pl080_run(s);
        break;
    case 13: /* Sync */
        s->sync = value;
        break;
    default:
    bad_offset:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl080_write: Bad offset %x\n", (int)offset);
    }
    pl080_update(s);
}

static const MemoryRegionOps pl080_ops = {
    .read = pl080_read,
    .write = pl080_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pl080_init(Object *obj)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    PL080State *s = PL080(obj);

    memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
    s->nchannels = 8;
}

static void pl081_init(Object *obj)
{
    PL080State *s = PL080(obj);

    s->nchannels = 2;
}

static void pl080_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->vmsd = &vmstate_pl080;
}

static const TypeInfo pl080_info = {
    .name          = TYPE_PL080,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PL080State),
    .instance_init = pl080_init,
    .class_init    = pl080_class_init,
};

static const TypeInfo pl081_info = {
    .name          = "pl081",
    .parent        = TYPE_PL080,
    .instance_init = pl081_init,
};

/* The PL080 and PL081 are the same except for the number of channels
   they implement (8 and 2 respectively).  */
static void pl080_register_types(void)
{
    type_register_static(&pl080_info);
    type_register_static(&pl081_info);
}

type_init(pl080_register_types)
Commit	Line	Data
5fafdf24	1	/*
e69954b9	2	* Arm PrimeCell PL080/PL081 DMA controller
cdbdb648 PB	3	*
	4	* Copyright (c) 2006 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
cdbdb648 PB	8	*/
cdbdb648 PB	9
8ef94f0b	10	#include "qemu/osdep.h"
83c9f4ca	11	#include "hw/sysbus.h"
fdfba1a2	12	#include "exec/address-spaces.h"
03dd024f	13	#include "qemu/log.h"
cdbdb648	14
e69954b9	15	#define PL080_MAX_CHANNELS 8
cdbdb648 PB	16	#define PL080_CONF_E 0x1
	17	#define PL080_CONF_M1 0x2
	18	#define PL080_CONF_M2 0x4
	19
	20	#define PL080_CCONF_H 0x40000
	21	#define PL080_CCONF_A 0x20000
	22	#define PL080_CCONF_L 0x10000
	23	#define PL080_CCONF_ITC 0x08000
	24	#define PL080_CCONF_IE 0x04000
	25	#define PL080_CCONF_E 0x00001
	26
	27	#define PL080_CCTRL_I 0x80000000
	28	#define PL080_CCTRL_DI 0x08000000
	29	#define PL080_CCTRL_SI 0x04000000
	30	#define PL080_CCTRL_D 0x02000000
	31	#define PL080_CCTRL_S 0x01000000
	32
	33	typedef struct {
	34	uint32_t src;
	35	uint32_t dest;
	36	uint32_t lli;
	37	uint32_t ctrl;
	38	uint32_t conf;
	39	} pl080_channel;
	40
4f800554 AF	41	#define TYPE_PL080 "pl080"
	42	#define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080)
	43
d7ba0a62	44	typedef struct PL080State {
4f800554 AF	45	SysBusDevice parent_obj;
4f800554 AF	46
63b02e04	47	MemoryRegion iomem;
cdbdb648 PB	48	uint8_t tc_int;
	49	uint8_t tc_mask;
	50	uint8_t err_int;
	51	uint8_t err_mask;
	52	uint32_t conf;
	53	uint32_t sync;
	54	uint32_t req_single;
	55	uint32_t req_burst;
e69954b9 PB	56	pl080_channel chan[PL080_MAX_CHANNELS];
e69954b9 PB	57	int nchannels;
cdbdb648 PB	58	/* Flag to avoid recursive DMA invocations. */
cdbdb648 PB	59	int running;
d537cf6c	60	qemu_irq irq;
d7ba0a62	61	} PL080State;
cdbdb648	62
ff175853 PM	63	static const VMStateDescription vmstate_pl080_channel = {
	64	.name = "pl080_channel",
	65	.version_id = 1,
	66	.minimum_version_id = 1,
	67	.fields = (VMStateField[]) {
	68	VMSTATE_UINT32(src, pl080_channel),
	69	VMSTATE_UINT32(dest, pl080_channel),
	70	VMSTATE_UINT32(lli, pl080_channel),
	71	VMSTATE_UINT32(ctrl, pl080_channel),
	72	VMSTATE_UINT32(conf, pl080_channel),
	73	VMSTATE_END_OF_LIST()
	74	}
	75	};
	76
	77	static const VMStateDescription vmstate_pl080 = {
	78	.name = "pl080",
	79	.version_id = 1,
	80	.minimum_version_id = 1,
	81	.fields = (VMStateField[]) {
d7ba0a62 AF	82	VMSTATE_UINT8(tc_int, PL080State),
	83	VMSTATE_UINT8(tc_mask, PL080State),
	84	VMSTATE_UINT8(err_int, PL080State),
	85	VMSTATE_UINT8(err_mask, PL080State),
	86	VMSTATE_UINT32(conf, PL080State),
	87	VMSTATE_UINT32(sync, PL080State),
	88	VMSTATE_UINT32(req_single, PL080State),
	89	VMSTATE_UINT32(req_burst, PL080State),
	90	VMSTATE_UINT8(tc_int, PL080State),
	91	VMSTATE_UINT8(tc_int, PL080State),
	92	VMSTATE_UINT8(tc_int, PL080State),
	93	VMSTATE_STRUCT_ARRAY(chan, PL080State, PL080_MAX_CHANNELS,
ff175853	94	1, vmstate_pl080_channel, pl080_channel),
d7ba0a62	95	VMSTATE_INT32(running, PL080State),
ff175853 PM	96	VMSTATE_END_OF_LIST()
	97	}
	98	};
	99
cdbdb648 PB	100	static const unsigned char pl080_id[] =
	101	{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
	102
e69954b9 PB	103	static const unsigned char pl081_id[] =
	104	{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
	105
d7ba0a62	106	static void pl080_update(PL080State *s)
cdbdb648 PB	107	{
	108	if ((s->tc_int & s->tc_mask)
	109	\|\| (s->err_int & s->err_mask))
d537cf6c	110	qemu_irq_raise(s->irq);
cdbdb648	111	else
d537cf6c	112	qemu_irq_lower(s->irq);
cdbdb648 PB	113	}
cdbdb648 PB	114
d7ba0a62	115	static void pl080_run(PL080State *s)
cdbdb648 PB	116	{
	117	int c;
	118	int flow;
	119	pl080_channel *ch;
	120	int swidth;
	121	int dwidth;
	122	int xsize;
	123	int n;
	124	int src_id;
	125	int dest_id;
	126	int size;
b55266b5	127	uint8_t buff[4];
cdbdb648 PB	128	uint32_t req;
	129
	130	s->tc_mask = 0;
e69954b9	131	for (c = 0; c < s->nchannels; c++) {
cdbdb648 PB	132	if (s->chan[c].conf & PL080_CCONF_ITC)
	133	s->tc_mask \|= 1 << c;
	134	if (s->chan[c].conf & PL080_CCONF_IE)
	135	s->err_mask \|= 1 << c;
	136	}
	137
	138	if ((s->conf & PL080_CONF_E) == 0)
	139	return;
	140
2ac71179	141	hw_error("DMA active\n");
cdbdb648 PB	142	/* If we are already in the middle of a DMA operation then indicate that
	143	there may be new DMA requests and return immediately. */
	144	if (s->running) {
	145	s->running++;
	146	return;
	147	}
	148	s->running = 1;
	149	while (s->running) {
e69954b9	150	for (c = 0; c < s->nchannels; c++) {
cdbdb648 PB	151	ch = &s->chan[c];
	152	again:
	153	/* Test if thiws channel has any pending DMA requests. */
	154	if ((ch->conf & (PL080_CCONF_H \| PL080_CCONF_E))
	155	!= PL080_CCONF_E)
	156	continue;
	157	flow = (ch->conf >> 11) & 7;
	158	if (flow >= 4) {
2ac71179	159	hw_error(
cdbdb648 PB	160	"pl080_run: Peripheral flow control not implemented\n");
	161	}
	162	src_id = (ch->conf >> 1) & 0x1f;
	163	dest_id = (ch->conf >> 6) & 0x1f;
	164	size = ch->ctrl & 0xfff;
	165	req = s->req_single \| s->req_burst;
	166	switch (flow) {
	167	case 0:
	168	break;
	169	case 1:
	170	if ((req & (1u << dest_id)) == 0)
	171	size = 0;
	172	break;
	173	case 2:
	174	if ((req & (1u << src_id)) == 0)
	175	size = 0;
	176	break;
	177	case 3:
	178	if ((req & (1u << src_id)) == 0
	179	\|\| (req & (1u << dest_id)) == 0)
	180	size = 0;
	181	break;
	182	}
	183	if (!size)
	184	continue;
	185
	186	/* Transfer one element. */
	187	/* ??? Should transfer multiple elements for a burst request. */
	188	/* ??? Unclear what the proper behavior is when source and
	189	destination widths are different. */
	190	swidth = 1 << ((ch->ctrl >> 18) & 7);
	191	dwidth = 1 << ((ch->ctrl >> 21) & 7);
	192	for (n = 0; n < dwidth; n+= swidth) {
	193	cpu_physical_memory_read(ch->src, buff + n, swidth);
	194	if (ch->ctrl & PL080_CCTRL_SI)
	195	ch->src += swidth;
	196	}
	197	xsize = (dwidth < swidth) ? swidth : dwidth;
	198	/* ??? This may pad the value incorrectly for dwidth < 32. */
	199	for (n = 0; n < xsize; n += dwidth) {
	200	cpu_physical_memory_write(ch->dest + n, buff + n, dwidth);
	201	if (ch->ctrl & PL080_CCTRL_DI)
	202	ch->dest += swidth;
	203	}
	204
	205	size--;
	206	ch->ctrl = (ch->ctrl & 0xfffff000) \| size;
	207	if (size == 0) {
	208	/* Transfer complete. */
	209	if (ch->lli) {
42874d3a PM	210	ch->src = address_space_ldl_le(&address_space_memory,
	211	ch->lli,
	212	MEMTXATTRS_UNSPECIFIED,
	213	NULL);
	214	ch->dest = address_space_ldl_le(&address_space_memory,
	215	ch->lli + 4,
	216	MEMTXATTRS_UNSPECIFIED,
	217	NULL);
	218	ch->ctrl = address_space_ldl_le(&address_space_memory,
	219	ch->lli + 12,
	220	MEMTXATTRS_UNSPECIFIED,
	221	NULL);
	222	ch->lli = address_space_ldl_le(&address_space_memory,
	223	ch->lli + 8,
	224	MEMTXATTRS_UNSPECIFIED,
	225	NULL);
cdbdb648 PB	226	} else {
	227	ch->conf &= ~PL080_CCONF_E;
	228	}
	229	if (ch->ctrl & PL080_CCTRL_I) {
	230	s->tc_int \|= 1 << c;
	231	}
	232	}
	233	goto again;
	234	}
	235	if (--s->running)
	236	s->running = 1;
	237	}
	238	}
	239
a8170e5e	240	static uint64_t pl080_read(void *opaque, hwaddr offset,
63b02e04	241	unsigned size)
cdbdb648	242	{
d7ba0a62	243	PL080State s = (PL080State )opaque;
cdbdb648 PB	244	uint32_t i;
	245	uint32_t mask;
	246
cdbdb648	247	if (offset >= 0xfe0 && offset < 0x1000) {
e69954b9 PB	248	if (s->nchannels == 8) {
	249	return pl080_id[(offset - 0xfe0) >> 2];
	250	} else {
	251	return pl081_id[(offset - 0xfe0) >> 2];
	252	}
cdbdb648 PB	253	}
	254	if (offset >= 0x100 && offset < 0x200) {
	255	i = (offset & 0xe0) >> 5;
e69954b9 PB	256	if (i >= s->nchannels)
e69954b9 PB	257	goto bad_offset;
cdbdb648 PB	258	switch (offset >> 2) {
	259	case 0: /* SrcAddr */
	260	return s->chan[i].src;
	261	case 1: /* DestAddr */
	262	return s->chan[i].dest;
	263	case 2: /* LLI */
	264	return s->chan[i].lli;
	265	case 3: /* Control */
	266	return s->chan[i].ctrl;
	267	case 4: /* Configuration */
	268	return s->chan[i].conf;
	269	default:
	270	goto bad_offset;
	271	}
	272	}
	273	switch (offset >> 2) {
	274	case 0: /* IntStatus */
	275	return (s->tc_int & s->tc_mask) \| (s->err_int & s->err_mask);
	276	case 1: /* IntTCStatus */
	277	return (s->tc_int & s->tc_mask);
	278	case 3: /* IntErrorStatus */
	279	return (s->err_int & s->err_mask);
	280	case 5: /* RawIntTCStatus */
	281	return s->tc_int;
	282	case 6: /* RawIntErrorStatus */
	283	return s->err_int;
	284	case 7: /* EnbldChns */
	285	mask = 0;
e69954b9	286	for (i = 0; i < s->nchannels; i++) {
cdbdb648 PB	287	if (s->chan[i].conf & PL080_CCONF_E)
	288	mask \|= 1 << i;
	289	}
	290	return mask;
	291	case 8: /* SoftBReq */
	292	case 9: /* SoftSReq */
	293	case 10: /* SoftLBReq */
	294	case 11: /* SoftLSReq */
	295	/* ??? Implement these. */
	296	return 0;
	297	case 12: /* Configuration */
	298	return s->conf;
	299	case 13: /* Sync */
	300	return s->sync;
	301	default:
	302	bad_offset:
df374162 PM	303	qemu_log_mask(LOG_GUEST_ERROR,
df374162 PM	304	"pl080_read: Bad offset %x\n", (int)offset);
cdbdb648 PB	305	return 0;
	306	}
	307	}
	308
a8170e5e	309	static void pl080_write(void *opaque, hwaddr offset,
63b02e04	310	uint64_t value, unsigned size)
cdbdb648	311	{
d7ba0a62	312	PL080State s = (PL080State )opaque;
cdbdb648 PB	313	int i;
cdbdb648 PB	314
cdbdb648 PB	315	if (offset >= 0x100 && offset < 0x200) {
cdbdb648 PB	316	i = (offset & 0xe0) >> 5;
e69954b9 PB	317	if (i >= s->nchannels)
e69954b9 PB	318	goto bad_offset;
cdbdb648 PB	319	switch (offset >> 2) {
	320	case 0: /* SrcAddr */
	321	s->chan[i].src = value;
	322	break;
	323	case 1: /* DestAddr */
	324	s->chan[i].dest = value;
	325	break;
	326	case 2: /* LLI */
	327	s->chan[i].lli = value;
	328	break;
	329	case 3: /* Control */
	330	s->chan[i].ctrl = value;
	331	break;
	332	case 4: /* Configuration */
	333	s->chan[i].conf = value;
	334	pl080_run(s);
	335	break;
	336	}
	337	}
	338	switch (offset >> 2) {
	339	case 2: /* IntTCClear */
	340	s->tc_int &= ~value;
	341	break;
	342	case 4: /* IntErrorClear */
	343	s->err_int &= ~value;
	344	break;
	345	case 8: /* SoftBReq */
	346	case 9: /* SoftSReq */
	347	case 10: /* SoftLBReq */
	348	case 11: /* SoftLSReq */
	349	/* ??? Implement these. */
df374162	350	qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n");
cdbdb648 PB	351	break;
	352	case 12: /* Configuration */
	353	s->conf = value;
	354	if (s->conf & (PL080_CONF_M1 \| PL080_CONF_M1)) {
df374162 PM	355	qemu_log_mask(LOG_UNIMP,
df374162 PM	356	"pl080_write: Big-endian DMA not implemented\n");
cdbdb648 PB	357	}
	358	pl080_run(s);
	359	break;
	360	case 13: /* Sync */
	361	s->sync = value;
	362	break;
	363	default:
e69954b9	364	bad_offset:
df374162 PM	365	qemu_log_mask(LOG_GUEST_ERROR,
df374162 PM	366	"pl080_write: Bad offset %x\n", (int)offset);
cdbdb648 PB	367	}
	368	pl080_update(s);
	369	}
	370
63b02e04 AK	371	static const MemoryRegionOps pl080_ops = {
	372	.read = pl080_read,
	373	.write = pl080_write,
	374	.endianness = DEVICE_NATIVE_ENDIAN,
cdbdb648 PB	375	};
cdbdb648 PB	376
4f800554	377	static void pl080_init(Object *obj)
cdbdb648	378	{
4f800554 AF	379	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
4f800554 AF	380	PL080State *s = PL080(obj);
cdbdb648	381
3eadad55	382	memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);
4f800554 AF	383	sysbus_init_mmio(sbd, &s->iomem);
	384	sysbus_init_irq(sbd, &s->irq);
	385	s->nchannels = 8;
cdbdb648	386	}
b4496b13	387
4f800554	388	static void pl081_init(Object *obj)
b4496b13	389	{
4f800554	390	PL080State *s = PL080(obj);
b4496b13	391
4f800554	392	s->nchannels = 2;
b4496b13 PB	393	}
b4496b13 PB	394
4f800554	395	static void pl080_class_init(ObjectClass oc, void data)
999e12bb	396	{
4f800554	397	DeviceClass *dc = DEVICE_CLASS(oc);
999e12bb	398
39bffca2	399	dc->vmsd = &vmstate_pl080;
999e12bb AL	400	}
999e12bb AL	401
8c43a6f0	402	static const TypeInfo pl080_info = {
4f800554	403	.name = TYPE_PL080,
39bffca2	404	.parent = TYPE_SYS_BUS_DEVICE,
d7ba0a62	405	.instance_size = sizeof(PL080State),
4f800554	406	.instance_init = pl080_init,
39bffca2	407	.class_init = pl080_class_init,
ff175853 PM	408	};
ff175853 PM	409
8c43a6f0	410	static const TypeInfo pl081_info = {
39bffca2	411	.name = "pl081",
4f800554 AF	412	.parent = TYPE_PL080,
4f800554 AF	413	.instance_init = pl081_init,
ff175853 PM	414	};
ff175853 PM	415
b4496b13 PB	416	/* The PL080 and PL081 are the same except for the number of channels
b4496b13 PB	417	they implement (8 and 2 respectively). */
83f7d43a	418	static void pl080_register_types(void)
b4496b13	419	{
39bffca2 AL	420	type_register_static(&pl080_info);
39bffca2 AL	421	type_register_static(&pl081_info);
b4496b13 PB	422	}
b4496b13 PB	423
83f7d43a	424	type_init(pl080_register_types)