[qemu.git] / hw / a9mpcore.c

/*
 * Cortex-A9MPCore internal peripheral emulation.
 *
 * Copyright (c) 2009 CodeSourcery.
 * Copyright (c) 2011 Linaro Limited.
 * Written by Paul Brook, Peter Maydell.
 *
 * This code is licensed under the GPL.
 */

#include "sysbus.h"

/* A9MP private memory region.  */

typedef struct a9mp_priv_state {
    SysBusDevice busdev;
    uint32_t scu_control;
    uint32_t scu_status;
    uint32_t old_timer_status[8];
    uint32_t num_cpu;
    MemoryRegion scu_iomem;
    MemoryRegion container;
    DeviceState *mptimer;
    DeviceState *gic;
    uint32_t num_irq;
} a9mp_priv_state;

static uint64_t a9_scu_read(void *opaque, hwaddr offset,
                            unsigned size)
{
    a9mp_priv_state *s = (a9mp_priv_state *)opaque;
    switch (offset) {
    case 0x00: /* Control */
        return s->scu_control;
    case 0x04: /* Configuration */
        return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1);
    case 0x08: /* CPU Power Status */
        return s->scu_status;
    case 0x09: /* CPU status.  */
        return s->scu_status >> 8;
    case 0x0a: /* CPU status.  */
        return s->scu_status >> 16;
    case 0x0b: /* CPU status.  */
        return s->scu_status >> 24;
    case 0x0c: /* Invalidate All Registers In Secure State */
        return 0;
    case 0x40: /* Filtering Start Address Register */
    case 0x44: /* Filtering End Address Register */
        /* RAZ/WI, like an implementation with only one AXI master */
        return 0;
    case 0x50: /* SCU Access Control Register */
    case 0x54: /* SCU Non-secure Access Control Register */
        /* unimplemented, fall through */
    default:
        return 0;
    }
}

static void a9_scu_write(void *opaque, hwaddr offset,
                         uint64_t value, unsigned size)
{
    a9mp_priv_state *s = (a9mp_priv_state *)opaque;
    uint32_t mask;
    uint32_t shift;
    switch (size) {
    case 1:
        mask = 0xff;
        break;
    case 2:
        mask = 0xffff;
        break;
    case 4:
        mask = 0xffffffff;
        break;
    default:
        fprintf(stderr, "Invalid size %u in write to a9 scu register %x\n",
                size, (unsigned)offset);
        return;
    }

    switch (offset) {
    case 0x00: /* Control */
        s->scu_control = value & 1;
        break;
    case 0x4: /* Configuration: RO */
        break;
    case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */
        shift = (offset - 0x8) * 8;
        s->scu_status &= ~(mask << shift);
        s->scu_status |= ((value & mask) << shift);
        break;
    case 0x0c: /* Invalidate All Registers In Secure State */
        /* no-op as we do not implement caches */
        break;
    case 0x40: /* Filtering Start Address Register */
    case 0x44: /* Filtering End Address Register */
        /* RAZ/WI, like an implementation with only one AXI master */
        break;
    case 0x50: /* SCU Access Control Register */
    case 0x54: /* SCU Non-secure Access Control Register */
        /* unimplemented, fall through */
    default:
        break;
    }
}

static const MemoryRegionOps a9_scu_ops = {
    .read = a9_scu_read,
    .write = a9_scu_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void a9mp_priv_reset(DeviceState *dev)
{
    a9mp_priv_state *s = FROM_SYSBUS(a9mp_priv_state, SYS_BUS_DEVICE(dev));
    int i;
    s->scu_control = 0;
    for (i = 0; i < ARRAY_SIZE(s->old_timer_status); i++) {
        s->old_timer_status[i] = 0;
    }
}

static void a9mp_priv_set_irq(void *opaque, int irq, int level)
{
    a9mp_priv_state *s = (a9mp_priv_state *)opaque;
    qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
}

static int a9mp_priv_init(SysBusDevice *dev)
{
    a9mp_priv_state *s = FROM_SYSBUS(a9mp_priv_state, dev);
    SysBusDevice *busdev, *gicbusdev;
    int i;

    s->gic = qdev_create(NULL, "arm_gic");
    qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
    qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
    qdev_init_nofail(s->gic);
    gicbusdev = SYS_BUS_DEVICE(s->gic);

    /* Pass through outbound IRQ lines from the GIC */
    sysbus_pass_irq(dev, gicbusdev);

    /* Pass through inbound GPIO lines to the GIC */
    qdev_init_gpio_in(&s->busdev.qdev, a9mp_priv_set_irq, s->num_irq - 32);

    s->mptimer = qdev_create(NULL, "arm_mptimer");
    qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
    qdev_init_nofail(s->mptimer);
    busdev = SYS_BUS_DEVICE(s->mptimer);

    /* Memory map (addresses are offsets from PERIPHBASE):
     *  0x0000-0x00ff -- Snoop Control Unit
     *  0x0100-0x01ff -- GIC CPU interface
     *  0x0200-0x02ff -- Global Timer
     *  0x0300-0x05ff -- nothing
     *  0x0600-0x06ff -- private timers and watchdogs
     *  0x0700-0x0fff -- nothing
     *  0x1000-0x1fff -- GIC Distributor
     *
     * We should implement the global timer but don't currently do so.
     */
    memory_region_init(&s->container, "a9mp-priv-container", 0x2000);
    memory_region_init_io(&s->scu_iomem, &a9_scu_ops, s, "a9mp-scu", 0x100);
    memory_region_add_subregion(&s->container, 0, &s->scu_iomem);
    /* GIC CPU interface */
    memory_region_add_subregion(&s->container, 0x100,
                                sysbus_mmio_get_region(gicbusdev, 1));
    /* Note that the A9 exposes only the "timer/watchdog for this core"
     * memory region, not the "timer/watchdog for core X" ones 11MPcore has.
     */
    memory_region_add_subregion(&s->container, 0x600,
                                sysbus_mmio_get_region(busdev, 0));
    memory_region_add_subregion(&s->container, 0x620,
                                sysbus_mmio_get_region(busdev, 1));
    memory_region_add_subregion(&s->container, 0x1000,
                                sysbus_mmio_get_region(gicbusdev, 0));

    sysbus_init_mmio(dev, &s->container);

    /* Wire up the interrupt from each watchdog and timer.
     * For each core the timer is PPI 29 and the watchdog PPI 30.
     */
    for (i = 0; i < s->num_cpu; i++) {
        int ppibase = (s->num_irq - 32) + i * 32;
        sysbus_connect_irq(busdev, i * 2,
                           qdev_get_gpio_in(s->gic, ppibase + 29));
        sysbus_connect_irq(busdev, i * 2 + 1,
                           qdev_get_gpio_in(s->gic, ppibase + 30));
    }
    return 0;
}

static const VMStateDescription vmstate_a9mp_priv = {
    .name = "a9mpcore_priv",
    .version_id = 2,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(scu_control, a9mp_priv_state),
        VMSTATE_UINT32_ARRAY(old_timer_status, a9mp_priv_state, 8),
        VMSTATE_UINT32_V(scu_status, a9mp_priv_state, 2),
        VMSTATE_END_OF_LIST()
    }
};

static Property a9mp_priv_properties[] = {
    DEFINE_PROP_UINT32("num-cpu", a9mp_priv_state, num_cpu, 1),
    /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
     * IRQ lines (with another 32 internal). We default to 64+32, which
     * is the number provided by the Cortex-A9MP test chip in the
     * Realview PBX-A9 and Versatile Express A9 development boards.
     * Other boards may differ and should set this property appropriately.
     */
    DEFINE_PROP_UINT32("num-irq", a9mp_priv_state, num_irq, 96),
    DEFINE_PROP_END_OF_LIST(),
};

static void a9mp_priv_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = a9mp_priv_init;
    dc->props = a9mp_priv_properties;
    dc->vmsd = &vmstate_a9mp_priv;
    dc->reset = a9mp_priv_reset;
}

static const TypeInfo a9mp_priv_info = {
    .name          = "a9mpcore_priv",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(a9mp_priv_state),
    .class_init    = a9mp_priv_class_init,
};

static void a9mp_register_types(void)
{
    type_register_static(&a9mp_priv_info);
}

type_init(a9mp_register_types)
Commit	Line	Data
f7c70325 PB	1	/*
	2	* Cortex-A9MPCore internal peripheral emulation.
	3	*
	4	* Copyright (c) 2009 CodeSourcery.
b12080cd PM	5	* Copyright (c) 2011 Linaro Limited.
b12080cd PM	6	* Written by Paul Brook, Peter Maydell.
f7c70325	7	*
8e31bf38	8	* This code is licensed under the GPL.
f7c70325 PB	9	*/
f7c70325 PB	10
b12080cd PM	11	#include "sysbus.h"
b12080cd PM	12
b12080cd PM	13	/* A9MP private memory region. */
	14
	15	typedef struct a9mp_priv_state {
ddd76165	16	SysBusDevice busdev;
b12080cd	17	uint32_t scu_control;
78aca8a7	18	uint32_t scu_status;
b12080cd PM	19	uint32_t old_timer_status[8];
b12080cd PM	20	uint32_t num_cpu;
b12080cd	21	MemoryRegion scu_iomem;
b12080cd PM	22	MemoryRegion container;
b12080cd PM	23	DeviceState *mptimer;
ddd76165	24	DeviceState *gic;
a32134aa	25	uint32_t num_irq;
b12080cd PM	26	} a9mp_priv_state;
b12080cd PM	27
a8170e5e	28	static uint64_t a9_scu_read(void *opaque, hwaddr offset,
b12080cd PM	29	unsigned size)
	30	{
	31	a9mp_priv_state s = (a9mp_priv_state )opaque;
	32	switch (offset) {
	33	case 0x00: /* Control */
	34	return s->scu_control;
	35	case 0x04: /* Configuration */
	36	return (((1 << s->num_cpu) - 1) << 4) \| (s->num_cpu - 1);
	37	case 0x08: /* CPU Power Status */
78aca8a7 RH	38	return s->scu_status;
	39	case 0x09: /* CPU status. */
	40	return s->scu_status >> 8;
	41	case 0x0a: /* CPU status. */
	42	return s->scu_status >> 16;
	43	case 0x0b: /* CPU status. */
	44	return s->scu_status >> 24;
b12080cd PM	45	case 0x0c: /* Invalidate All Registers In Secure State */
	46	return 0;
	47	case 0x40: /* Filtering Start Address Register */
	48	case 0x44: /* Filtering End Address Register */
	49	/* RAZ/WI, like an implementation with only one AXI master */
	50	return 0;
	51	case 0x50: /* SCU Access Control Register */
	52	case 0x54: /* SCU Non-secure Access Control Register */
	53	/* unimplemented, fall through */
	54	default:
	55	return 0;
	56	}
	57	}
	58
a8170e5e	59	static void a9_scu_write(void *opaque, hwaddr offset,
b12080cd PM	60	uint64_t value, unsigned size)
	61	{
	62	a9mp_priv_state s = (a9mp_priv_state )opaque;
78aca8a7 RH	63	uint32_t mask;
	64	uint32_t shift;
	65	switch (size) {
	66	case 1:
	67	mask = 0xff;
	68	break;
	69	case 2:
	70	mask = 0xffff;
	71	break;
	72	case 4:
	73	mask = 0xffffffff;
	74	break;
	75	default:
	76	fprintf(stderr, "Invalid size %u in write to a9 scu register %x\n",
c97338dc	77	size, (unsigned)offset);
78aca8a7 RH	78	return;
	79	}
	80
b12080cd PM	81	switch (offset) {
	82	case 0x00: /* Control */
	83	s->scu_control = value & 1;
	84	break;
	85	case 0x4: /* Configuration: RO */
	86	break;
78aca8a7 RH	87	case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */
	88	shift = (offset - 0x8) * 8;
	89	s->scu_status &= ~(mask << shift);
	90	s->scu_status \|= ((value & mask) << shift);
	91	break;
b12080cd PM	92	case 0x0c: /* Invalidate All Registers In Secure State */
	93	/* no-op as we do not implement caches */
	94	break;
	95	case 0x40: /* Filtering Start Address Register */
	96	case 0x44: /* Filtering End Address Register */
	97	/* RAZ/WI, like an implementation with only one AXI master */
	98	break;
b12080cd PM	99	case 0x50: /* SCU Access Control Register */
	100	case 0x54: /* SCU Non-secure Access Control Register */
	101	/* unimplemented, fall through */
	102	default:
	103	break;
	104	}
	105	}
	106
	107	static const MemoryRegionOps a9_scu_ops = {
	108	.read = a9_scu_read,
	109	.write = a9_scu_write,
	110	.endianness = DEVICE_NATIVE_ENDIAN,
	111	};
	112
b12080cd PM	113	static void a9mp_priv_reset(DeviceState *dev)
b12080cd PM	114	{
1356b98d	115	a9mp_priv_state *s = FROM_SYSBUS(a9mp_priv_state, SYS_BUS_DEVICE(dev));
b12080cd PM	116	int i;
	117	s->scu_control = 0;
	118	for (i = 0; i < ARRAY_SIZE(s->old_timer_status); i++) {
	119	s->old_timer_status[i] = 0;
	120	}
	121	}
	122
ddd76165 PM	123	static void a9mp_priv_set_irq(void *opaque, int irq, int level)
	124	{
	125	a9mp_priv_state s = (a9mp_priv_state )opaque;
	126	qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
	127	}
	128
b12080cd PM	129	static int a9mp_priv_init(SysBusDevice *dev)
b12080cd PM	130	{
ddd76165 PM	131	a9mp_priv_state *s = FROM_SYSBUS(a9mp_priv_state, dev);
ddd76165 PM	132	SysBusDevice busdev, gicbusdev;
b12080cd PM	133	int i;
b12080cd PM	134
ddd76165 PM	135	s->gic = qdev_create(NULL, "arm_gic");
	136	qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
	137	qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
	138	qdev_init_nofail(s->gic);
1356b98d	139	gicbusdev = SYS_BUS_DEVICE(s->gic);
ddd76165 PM	140
	141	/* Pass through outbound IRQ lines from the GIC */
	142	sysbus_pass_irq(dev, gicbusdev);
	143
	144	/* Pass through inbound GPIO lines to the GIC */
	145	qdev_init_gpio_in(&s->busdev.qdev, a9mp_priv_set_irq, s->num_irq - 32);
b12080cd PM	146
	147	s->mptimer = qdev_create(NULL, "arm_mptimer");
	148	qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
	149	qdev_init_nofail(s->mptimer);
1356b98d	150	busdev = SYS_BUS_DEVICE(s->mptimer);
b12080cd PM	151
	152	/* Memory map (addresses are offsets from PERIPHBASE):
	153	* 0x0000-0x00ff -- Snoop Control Unit
	154	* 0x0100-0x01ff -- GIC CPU interface
	155	* 0x0200-0x02ff -- Global Timer
	156	* 0x0300-0x05ff -- nothing
	157	* 0x0600-0x06ff -- private timers and watchdogs
	158	* 0x0700-0x0fff -- nothing
	159	* 0x1000-0x1fff -- GIC Distributor
	160	*
	161	* We should implement the global timer but don't currently do so.
	162	*/
	163	memory_region_init(&s->container, "a9mp-priv-container", 0x2000);
	164	memory_region_init_io(&s->scu_iomem, &a9_scu_ops, s, "a9mp-scu", 0x100);
	165	memory_region_add_subregion(&s->container, 0, &s->scu_iomem);
	166	/* GIC CPU interface */
ddd76165 PM	167	memory_region_add_subregion(&s->container, 0x100,
ddd76165 PM	168	sysbus_mmio_get_region(gicbusdev, 1));
b12080cd PM	169	/* Note that the A9 exposes only the "timer/watchdog for this core"
	170	* memory region, not the "timer/watchdog for core X" ones 11MPcore has.
	171	*/
	172	memory_region_add_subregion(&s->container, 0x600,
	173	sysbus_mmio_get_region(busdev, 0));
	174	memory_region_add_subregion(&s->container, 0x620,
	175	sysbus_mmio_get_region(busdev, 1));
ddd76165 PM	176	memory_region_add_subregion(&s->container, 0x1000,
ddd76165 PM	177	sysbus_mmio_get_region(gicbusdev, 0));
b12080cd PM	178
	179	sysbus_init_mmio(dev, &s->container);
	180
ddd76165 PM	181	/* Wire up the interrupt from each watchdog and timer.
	182	* For each core the timer is PPI 29 and the watchdog PPI 30.
	183	*/
	184	for (i = 0; i < s->num_cpu; i++) {
	185	int ppibase = (s->num_irq - 32) + i * 32;
	186	sysbus_connect_irq(busdev, i * 2,
	187	qdev_get_gpio_in(s->gic, ppibase + 29));
	188	sysbus_connect_irq(busdev, i * 2 + 1,
	189	qdev_get_gpio_in(s->gic, ppibase + 30));
b12080cd PM	190	}
	191	return 0;
	192	}
	193
	194	static const VMStateDescription vmstate_a9mp_priv = {
	195	.name = "a9mpcore_priv",
78aca8a7	196	.version_id = 2,
b12080cd PM	197	.minimum_version_id = 1,
	198	.fields = (VMStateField[]) {
	199	VMSTATE_UINT32(scu_control, a9mp_priv_state),
	200	VMSTATE_UINT32_ARRAY(old_timer_status, a9mp_priv_state, 8),
78aca8a7	201	VMSTATE_UINT32_V(scu_status, a9mp_priv_state, 2),
b12080cd PM	202	VMSTATE_END_OF_LIST()
	203	}
	204	};
f7c70325	205
39bffca2 AL	206	static Property a9mp_priv_properties[] = {
	207	DEFINE_PROP_UINT32("num-cpu", a9mp_priv_state, num_cpu, 1),
	208	/* The Cortex-A9MP may have anything from 0 to 224 external interrupt
	209	* IRQ lines (with another 32 internal). We default to 64+32, which
	210	* is the number provided by the Cortex-A9MP test chip in the
	211	* Realview PBX-A9 and Versatile Express A9 development boards.
	212	* Other boards may differ and should set this property appropriately.
	213	*/
	214	DEFINE_PROP_UINT32("num-irq", a9mp_priv_state, num_irq, 96),
	215	DEFINE_PROP_END_OF_LIST(),
	216	};
	217
999e12bb AL	218	static void a9mp_priv_class_init(ObjectClass klass, void data)
999e12bb AL	219	{
39bffca2	220	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	221	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	222
	223	k->init = a9mp_priv_init;
39bffca2 AL	224	dc->props = a9mp_priv_properties;
	225	dc->vmsd = &vmstate_a9mp_priv;
	226	dc->reset = a9mp_priv_reset;
999e12bb AL	227	}
999e12bb AL	228
8c43a6f0	229	static const TypeInfo a9mp_priv_info = {
39bffca2 AL	230	.name = "a9mpcore_priv",
	231	.parent = TYPE_SYS_BUS_DEVICE,
	232	.instance_size = sizeof(a9mp_priv_state),
	233	.class_init = a9mp_priv_class_init,
f7c70325 PB	234	};
f7c70325 PB	235
83f7d43a	236	static void a9mp_register_types(void)
f7c70325	237	{
39bffca2	238	type_register_static(&a9mp_priv_info);
f7c70325 PB	239	}
f7c70325 PB	240
83f7d43a	241	type_init(a9mp_register_types)