[qemu.git] / target-i386 / machine.c

#include "hw/hw.h"
#include "hw/boards.h"
#include "hw/pc.h"
#include "hw/isa.h"

#include "exec-all.h"

void register_machines(void)
{
    qemu_register_machine(&pc_machine);
    qemu_register_machine(&isapc_machine);
}

static void cpu_put_seg(QEMUFile *f, SegmentCache *dt)
{
    qemu_put_be32(f, dt->selector);
    qemu_put_betl(f, dt->base);
    qemu_put_be32(f, dt->limit);
    qemu_put_be32(f, dt->flags);
}

static void cpu_get_seg(QEMUFile *f, SegmentCache *dt)
{
    dt->selector = qemu_get_be32(f);
    dt->base = qemu_get_betl(f);
    dt->limit = qemu_get_be32(f);
    dt->flags = qemu_get_be32(f);
}

void cpu_save(QEMUFile *f, void *opaque)
{
    CPUState *env = opaque;
    uint16_t fptag, fpus, fpuc, fpregs_format;
    uint32_t hflags;
    int32_t a20_mask;
    int i;

    for(i = 0; i < CPU_NB_REGS; i++)
        qemu_put_betls(f, &env->regs[i]);
    qemu_put_betls(f, &env->eip);
    qemu_put_betls(f, &env->eflags);
    hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
    qemu_put_be32s(f, &hflags);

    /* FPU */
    fpuc = env->fpuc;
    fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
    fptag = 0;
    for(i = 0; i < 8; i++) {
        fptag |= ((!env->fptags[i]) << i);
    }

    qemu_put_be16s(f, &fpuc);
    qemu_put_be16s(f, &fpus);
    qemu_put_be16s(f, &fptag);

#ifdef USE_X86LDOUBLE
    fpregs_format = 0;
#else
    fpregs_format = 1;
#endif
    qemu_put_be16s(f, &fpregs_format);

    for(i = 0; i < 8; i++) {
#ifdef USE_X86LDOUBLE
        {
            uint64_t mant;
            uint16_t exp;
            /* we save the real CPU data (in case of MMX usage only 'mant'
               contains the MMX register */
            cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
            qemu_put_be64(f, mant);
            qemu_put_be16(f, exp);
        }
#else
        /* if we use doubles for float emulation, we save the doubles to
           avoid losing information in case of MMX usage. It can give
           problems if the image is restored on a CPU where long
           doubles are used instead. */
        qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
#endif
    }

    for(i = 0; i < 6; i++)
        cpu_put_seg(f, &env->segs[i]);
    cpu_put_seg(f, &env->ldt);
    cpu_put_seg(f, &env->tr);
    cpu_put_seg(f, &env->gdt);
    cpu_put_seg(f, &env->idt);

    qemu_put_be32s(f, &env->sysenter_cs);
    qemu_put_betls(f, &env->sysenter_esp);
    qemu_put_betls(f, &env->sysenter_eip);

    qemu_put_betls(f, &env->cr[0]);
    qemu_put_betls(f, &env->cr[2]);
    qemu_put_betls(f, &env->cr[3]);
    qemu_put_betls(f, &env->cr[4]);

    for(i = 0; i < 8; i++)
        qemu_put_betls(f, &env->dr[i]);

    /* MMU */
    a20_mask = (int32_t) env->a20_mask;
    qemu_put_sbe32s(f, &a20_mask);

    /* XMM */
    qemu_put_be32s(f, &env->mxcsr);
    for(i = 0; i < CPU_NB_REGS; i++) {
        qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
        qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
    }

#ifdef TARGET_X86_64
    qemu_put_be64s(f, &env->efer);
    qemu_put_be64s(f, &env->star);
    qemu_put_be64s(f, &env->lstar);
    qemu_put_be64s(f, &env->cstar);
    qemu_put_be64s(f, &env->fmask);
    qemu_put_be64s(f, &env->kernelgsbase);
#endif
    qemu_put_be32s(f, &env->smbase);

    qemu_put_be64s(f, &env->pat);
    qemu_put_be32s(f, &env->hflags2);
    
    qemu_put_be64s(f, &env->vm_hsave);
    qemu_put_be64s(f, &env->vm_vmcb);
    qemu_put_be64s(f, &env->tsc_offset);
    qemu_put_be64s(f, &env->intercept);
    qemu_put_be16s(f, &env->intercept_cr_read);
    qemu_put_be16s(f, &env->intercept_cr_write);
    qemu_put_be16s(f, &env->intercept_dr_read);
    qemu_put_be16s(f, &env->intercept_dr_write);
    qemu_put_be32s(f, &env->intercept_exceptions);
    qemu_put_8s(f, &env->v_tpr);

    /* MTRRs */
    for(i = 0; i < 11; i++)
        qemu_put_be64s(f, &env->mtrr_fixed[i]);
    qemu_put_be64s(f, &env->mtrr_deftype);
    for(i = 0; i < 8; i++) {
        qemu_put_be64s(f, &env->mtrr_var[i].base);
        qemu_put_be64s(f, &env->mtrr_var[i].mask);
    }
}

#ifdef USE_X86LDOUBLE
/* XXX: add that in a FPU generic layer */
union x86_longdouble {
    uint64_t mant;
    uint16_t exp;
};

#define MANTD1(fp)	(fp & ((1LL << 52) - 1))
#define EXPBIAS1 1023
#define EXPD1(fp)	((fp >> 52) & 0x7FF)
#define SIGND1(fp)	((fp >> 32) & 0x80000000)

static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
{
    int e;
    /* mantissa */
    p->mant = (MANTD1(temp) << 11) | (1LL << 63);
    /* exponent + sign */
    e = EXPD1(temp) - EXPBIAS1 + 16383;
    e |= SIGND1(temp) >> 16;
    p->exp = e;
}
#endif

int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
    CPUState *env = opaque;
    int i, guess_mmx;
    uint32_t hflags;
    uint16_t fpus, fpuc, fptag, fpregs_format;
    int32_t a20_mask;

    if (version_id != 3 && version_id != 4 && version_id != 5
        && version_id != 6 && version_id != 7 && version_id != 8)
        return -EINVAL;
    for(i = 0; i < CPU_NB_REGS; i++)
        qemu_get_betls(f, &env->regs[i]);
    qemu_get_betls(f, &env->eip);
    qemu_get_betls(f, &env->eflags);
    qemu_get_be32s(f, &hflags);

    qemu_get_be16s(f, &fpuc);
    qemu_get_be16s(f, &fpus);
    qemu_get_be16s(f, &fptag);
    qemu_get_be16s(f, &fpregs_format);

    /* NOTE: we cannot always restore the FPU state if the image come
       from a host with a different 'USE_X86LDOUBLE' define. We guess
       if we are in an MMX state to restore correctly in that case. */
    guess_mmx = ((fptag == 0xff) && (fpus & 0x3800) == 0);
    for(i = 0; i < 8; i++) {
        uint64_t mant;
        uint16_t exp;

        switch(fpregs_format) {
        case 0:
            mant = qemu_get_be64(f);
            exp = qemu_get_be16(f);
#ifdef USE_X86LDOUBLE
            env->fpregs[i].d = cpu_set_fp80(mant, exp);
#else
            /* difficult case */
            if (guess_mmx)
                env->fpregs[i].mmx.MMX_Q(0) = mant;
            else
                env->fpregs[i].d = cpu_set_fp80(mant, exp);
#endif
            break;
        case 1:
            mant = qemu_get_be64(f);
#ifdef USE_X86LDOUBLE
            {
                union x86_longdouble *p;
                /* difficult case */
                p = (void *)&env->fpregs[i];
                if (guess_mmx) {
                    p->mant = mant;
                    p->exp = 0xffff;
                } else {
                    fp64_to_fp80(p, mant);
                }
            }
#else
            env->fpregs[i].mmx.MMX_Q(0) = mant;
#endif
            break;
        default:
            return -EINVAL;
        }
    }

    env->fpuc = fpuc;
    /* XXX: restore FPU round state */
    env->fpstt = (fpus >> 11) & 7;
    env->fpus = fpus & ~0x3800;
    fptag ^= 0xff;
    for(i = 0; i < 8; i++) {
        env->fptags[i] = (fptag >> i) & 1;
    }

    for(i = 0; i < 6; i++)
        cpu_get_seg(f, &env->segs[i]);
    cpu_get_seg(f, &env->ldt);
    cpu_get_seg(f, &env->tr);
    cpu_get_seg(f, &env->gdt);
    cpu_get_seg(f, &env->idt);

    qemu_get_be32s(f, &env->sysenter_cs);
    if (version_id >= 7) {
        qemu_get_betls(f, &env->sysenter_esp);
        qemu_get_betls(f, &env->sysenter_eip);
    } else {
        env->sysenter_esp = qemu_get_be32(f);
        env->sysenter_eip = qemu_get_be32(f);
    }

    qemu_get_betls(f, &env->cr[0]);
    qemu_get_betls(f, &env->cr[2]);
    qemu_get_betls(f, &env->cr[3]);
    qemu_get_betls(f, &env->cr[4]);

    for(i = 0; i < 8; i++)
        qemu_get_betls(f, &env->dr[i]);
    cpu_breakpoint_remove_all(env, BP_CPU);
    cpu_watchpoint_remove_all(env, BP_CPU);
    for (i = 0; i < 4; i++)
        hw_breakpoint_insert(env, i);

    /* MMU */
    qemu_get_sbe32s(f, &a20_mask);
    env->a20_mask = a20_mask;

    qemu_get_be32s(f, &env->mxcsr);
    for(i = 0; i < CPU_NB_REGS; i++) {
        qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));
        qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));
    }

#ifdef TARGET_X86_64
    qemu_get_be64s(f, &env->efer);
    qemu_get_be64s(f, &env->star);
    qemu_get_be64s(f, &env->lstar);
    qemu_get_be64s(f, &env->cstar);
    qemu_get_be64s(f, &env->fmask);
    qemu_get_be64s(f, &env->kernelgsbase);
#endif
    if (version_id >= 4) {
        qemu_get_be32s(f, &env->smbase);
    }
    if (version_id >= 5) {
        qemu_get_be64s(f, &env->pat);
        qemu_get_be32s(f, &env->hflags2);
        if (version_id < 6)
            qemu_get_be32s(f, &env->halted);

        qemu_get_be64s(f, &env->vm_hsave);
        qemu_get_be64s(f, &env->vm_vmcb);
        qemu_get_be64s(f, &env->tsc_offset);
        qemu_get_be64s(f, &env->intercept);
        qemu_get_be16s(f, &env->intercept_cr_read);
        qemu_get_be16s(f, &env->intercept_cr_write);
        qemu_get_be16s(f, &env->intercept_dr_read);
        qemu_get_be16s(f, &env->intercept_dr_write);
        qemu_get_be32s(f, &env->intercept_exceptions);
        qemu_get_8s(f, &env->v_tpr);
    }

    if (version_id >= 8) {
        /* MTRRs */
        for(i = 0; i < 11; i++)
            qemu_get_be64s(f, &env->mtrr_fixed[i]);
        qemu_get_be64s(f, &env->mtrr_deftype);
        for(i = 0; i < 8; i++) {
            qemu_get_be64s(f, &env->mtrr_var[i].base);
            qemu_get_be64s(f, &env->mtrr_var[i].mask);
        }
    }

    /* XXX: ensure compatiblity for halted bit ? */
    /* XXX: compute redundant hflags bits */
    env->hflags = hflags;
    tlb_flush(env, 1);
    return 0;
}
Commit	Line	Data
8dd3dca3 AJ	1	#include "hw/hw.h"
	2	#include "hw/boards.h"
	3	#include "hw/pc.h"
	4	#include "hw/isa.h"
	5
	6	#include "exec-all.h"
	7
	8	void register_machines(void)
	9	{
	10	qemu_register_machine(&pc_machine);
	11	qemu_register_machine(&isapc_machine);
	12	}
	13
	14	static void cpu_put_seg(QEMUFile f, SegmentCache dt)
	15	{
	16	qemu_put_be32(f, dt->selector);
	17	qemu_put_betl(f, dt->base);
	18	qemu_put_be32(f, dt->limit);
	19	qemu_put_be32(f, dt->flags);
	20	}
	21
	22	static void cpu_get_seg(QEMUFile f, SegmentCache dt)
	23	{
	24	dt->selector = qemu_get_be32(f);
	25	dt->base = qemu_get_betl(f);
	26	dt->limit = qemu_get_be32(f);
	27	dt->flags = qemu_get_be32(f);
	28	}
	29
	30	void cpu_save(QEMUFile f, void opaque)
	31	{
	32	CPUState *env = opaque;
	33	uint16_t fptag, fpus, fpuc, fpregs_format;
	34	uint32_t hflags;
7caa33f7	35	int32_t a20_mask;
8dd3dca3 AJ	36	int i;
	37
	38	for(i = 0; i < CPU_NB_REGS; i++)
	39	qemu_put_betls(f, &env->regs[i]);
	40	qemu_put_betls(f, &env->eip);
	41	qemu_put_betls(f, &env->eflags);
	42	hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
	43	qemu_put_be32s(f, &hflags);
	44
	45	/* FPU */
	46	fpuc = env->fpuc;
	47	fpus = (env->fpus & ~0x3800) \| (env->fpstt & 0x7) << 11;
	48	fptag = 0;
	49	for(i = 0; i < 8; i++) {
	50	fptag \|= ((!env->fptags[i]) << i);
	51	}
	52
	53	qemu_put_be16s(f, &fpuc);
	54	qemu_put_be16s(f, &fpus);
	55	qemu_put_be16s(f, &fptag);
	56
	57	#ifdef USE_X86LDOUBLE
	58	fpregs_format = 0;
	59	#else
	60	fpregs_format = 1;
	61	#endif
	62	qemu_put_be16s(f, &fpregs_format);
	63
	64	for(i = 0; i < 8; i++) {
	65	#ifdef USE_X86LDOUBLE
	66	{
	67	uint64_t mant;
	68	uint16_t exp;
	69	/* we save the real CPU data (in case of MMX usage only 'mant'
	70	contains the MMX register */
	71	cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
	72	qemu_put_be64(f, mant);
	73	qemu_put_be16(f, exp);
	74	}
	75	#else
	76	/* if we use doubles for float emulation, we save the doubles to
	77	avoid losing information in case of MMX usage. It can give
	78	problems if the image is restored on a CPU where long
	79	doubles are used instead. */
	80	qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
	81	#endif
	82	}
	83
	84	for(i = 0; i < 6; i++)
	85	cpu_put_seg(f, &env->segs[i]);
	86	cpu_put_seg(f, &env->ldt);
	87	cpu_put_seg(f, &env->tr);
	88	cpu_put_seg(f, &env->gdt);
	89	cpu_put_seg(f, &env->idt);
	90
f5049756	91	qemu_put_be32s(f, &env->sysenter_cs);
2436b61a AZ	92	qemu_put_betls(f, &env->sysenter_esp);
2436b61a AZ	93	qemu_put_betls(f, &env->sysenter_eip);
8dd3dca3 AJ	94
	95	qemu_put_betls(f, &env->cr[0]);
	96	qemu_put_betls(f, &env->cr[2]);
	97	qemu_put_betls(f, &env->cr[3]);
	98	qemu_put_betls(f, &env->cr[4]);
	99
	100	for(i = 0; i < 8; i++)
	101	qemu_put_betls(f, &env->dr[i]);
	102
	103	/* MMU */
7caa33f7	104	a20_mask = (int32_t) env->a20_mask;
b6c4f71f	105	qemu_put_sbe32s(f, &a20_mask);
8dd3dca3 AJ	106
	107	/* XMM */
	108	qemu_put_be32s(f, &env->mxcsr);
	109	for(i = 0; i < CPU_NB_REGS; i++) {
	110	qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
	111	qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
	112	}
	113
	114	#ifdef TARGET_X86_64
	115	qemu_put_be64s(f, &env->efer);
	116	qemu_put_be64s(f, &env->star);
	117	qemu_put_be64s(f, &env->lstar);
	118	qemu_put_be64s(f, &env->cstar);
	119	qemu_put_be64s(f, &env->fmask);
	120	qemu_put_be64s(f, &env->kernelgsbase);
	121	#endif
	122	qemu_put_be32s(f, &env->smbase);
5cc1d1e6 FB	123
	124	qemu_put_be64s(f, &env->pat);
	125	qemu_put_be32s(f, &env->hflags2);
5cc1d1e6 FB	126
	127	qemu_put_be64s(f, &env->vm_hsave);
	128	qemu_put_be64s(f, &env->vm_vmcb);
	129	qemu_put_be64s(f, &env->tsc_offset);
	130	qemu_put_be64s(f, &env->intercept);
	131	qemu_put_be16s(f, &env->intercept_cr_read);
	132	qemu_put_be16s(f, &env->intercept_cr_write);
	133	qemu_put_be16s(f, &env->intercept_dr_read);
	134	qemu_put_be16s(f, &env->intercept_dr_write);
	135	qemu_put_be32s(f, &env->intercept_exceptions);
	136	qemu_put_8s(f, &env->v_tpr);
dd5e3b17 AL	137
	138	/* MTRRs */
	139	for(i = 0; i < 11; i++)
	140	qemu_put_be64s(f, &env->mtrr_fixed[i]);
	141	qemu_put_be64s(f, &env->mtrr_deftype);
	142	for(i = 0; i < 8; i++) {
	143	qemu_put_be64s(f, &env->mtrr_var[i].base);
	144	qemu_put_be64s(f, &env->mtrr_var[i].mask);
	145	}
8dd3dca3 AJ	146	}
	147
	148	#ifdef USE_X86LDOUBLE
	149	/* XXX: add that in a FPU generic layer */
	150	union x86_longdouble {
	151	uint64_t mant;
	152	uint16_t exp;
	153	};
	154
	155	#define MANTD1(fp) (fp & ((1LL << 52) - 1))
	156	#define EXPBIAS1 1023
	157	#define EXPD1(fp) ((fp >> 52) & 0x7FF)
	158	#define SIGND1(fp) ((fp >> 32) & 0x80000000)
	159
	160	static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
	161	{
	162	int e;
	163	/* mantissa */
	164	p->mant = (MANTD1(temp) << 11) \| (1LL << 63);
	165	/* exponent + sign */
	166	e = EXPD1(temp) - EXPBIAS1 + 16383;
	167	e \|= SIGND1(temp) >> 16;
	168	p->exp = e;
	169	}
	170	#endif
	171
	172	int cpu_load(QEMUFile f, void opaque, int version_id)
	173	{
	174	CPUState *env = opaque;
	175	int i, guess_mmx;
	176	uint32_t hflags;
	177	uint16_t fpus, fpuc, fptag, fpregs_format;
7caa33f7	178	int32_t a20_mask;
8dd3dca3	179
9656f324	180	if (version_id != 3 && version_id != 4 && version_id != 5
dd5e3b17	181	&& version_id != 6 && version_id != 7 && version_id != 8)
8dd3dca3 AJ	182	return -EINVAL;
	183	for(i = 0; i < CPU_NB_REGS; i++)
	184	qemu_get_betls(f, &env->regs[i]);
	185	qemu_get_betls(f, &env->eip);
	186	qemu_get_betls(f, &env->eflags);
	187	qemu_get_be32s(f, &hflags);
	188
	189	qemu_get_be16s(f, &fpuc);
	190	qemu_get_be16s(f, &fpus);
	191	qemu_get_be16s(f, &fptag);
	192	qemu_get_be16s(f, &fpregs_format);
	193
	194	/* NOTE: we cannot always restore the FPU state if the image come
	195	from a host with a different 'USE_X86LDOUBLE' define. We guess
	196	if we are in an MMX state to restore correctly in that case. */
	197	guess_mmx = ((fptag == 0xff) && (fpus & 0x3800) == 0);
	198	for(i = 0; i < 8; i++) {
	199	uint64_t mant;
	200	uint16_t exp;
	201
	202	switch(fpregs_format) {
	203	case 0:
	204	mant = qemu_get_be64(f);
	205	exp = qemu_get_be16(f);
	206	#ifdef USE_X86LDOUBLE
	207	env->fpregs[i].d = cpu_set_fp80(mant, exp);
	208	#else
	209	/* difficult case */
	210	if (guess_mmx)
	211	env->fpregs[i].mmx.MMX_Q(0) = mant;
	212	else
	213	env->fpregs[i].d = cpu_set_fp80(mant, exp);
	214	#endif
	215	break;
	216	case 1:
	217	mant = qemu_get_be64(f);
	218	#ifdef USE_X86LDOUBLE
	219	{
	220	union x86_longdouble *p;
	221	/* difficult case */
	222	p = (void *)&env->fpregs[i];
	223	if (guess_mmx) {
	224	p->mant = mant;
	225	p->exp = 0xffff;
	226	} else {
	227	fp64_to_fp80(p, mant);
	228	}
	229	}
	230	#else
	231	env->fpregs[i].mmx.MMX_Q(0) = mant;
	232	#endif
	233	break;
	234	default:
	235	return -EINVAL;
	236	}
	237	}
	238
	239	env->fpuc = fpuc;
	240	/* XXX: restore FPU round state */
	241	env->fpstt = (fpus >> 11) & 7;
	242	env->fpus = fpus & ~0x3800;
	243	fptag ^= 0xff;
	244	for(i = 0; i < 8; i++) {
	245	env->fptags[i] = (fptag >> i) & 1;
246	}
247
248	for(i = 0; i < 6; i++)
249	cpu_get_seg(f, &env->segs[i]);
250	cpu_get_seg(f, &env->ldt);
251	cpu_get_seg(f, &env->tr);
252	cpu_get_seg(f, &env->gdt);
253	cpu_get_seg(f, &env->idt);
254
255	qemu_get_be32s(f, &env->sysenter_cs);
2436b61a AZ	256	if (version_id >= 7) {
	257	qemu_get_betls(f, &env->sysenter_esp);
	258	qemu_get_betls(f, &env->sysenter_eip);
	259	} else {
e5ceb244 AL	260	env->sysenter_esp = qemu_get_be32(f);
e5ceb244 AL	261	env->sysenter_eip = qemu_get_be32(f);
2436b61a	262	}
8dd3dca3 AJ	263
	264	qemu_get_betls(f, &env->cr[0]);
	265	qemu_get_betls(f, &env->cr[2]);
	266	qemu_get_betls(f, &env->cr[3]);
	267	qemu_get_betls(f, &env->cr[4]);
	268
	269	for(i = 0; i < 8; i++)
	270	qemu_get_betls(f, &env->dr[i]);
01df040b AL	271	cpu_breakpoint_remove_all(env, BP_CPU);
	272	cpu_watchpoint_remove_all(env, BP_CPU);
	273	for (i = 0; i < 4; i++)
	274	hw_breakpoint_insert(env, i);
8dd3dca3 AJ	275
8dd3dca3 AJ	276	/* MMU */
b6c4f71f	277	qemu_get_sbe32s(f, &a20_mask);
7caa33f7	278	env->a20_mask = a20_mask;
8dd3dca3 AJ	279
	280	qemu_get_be32s(f, &env->mxcsr);
	281	for(i = 0; i < CPU_NB_REGS; i++) {
	282	qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));
	283	qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));
	284	}
	285
	286	#ifdef TARGET_X86_64
	287	qemu_get_be64s(f, &env->efer);
	288	qemu_get_be64s(f, &env->star);
	289	qemu_get_be64s(f, &env->lstar);
	290	qemu_get_be64s(f, &env->cstar);
	291	qemu_get_be64s(f, &env->fmask);
	292	qemu_get_be64s(f, &env->kernelgsbase);
	293	#endif
5cc1d1e6	294	if (version_id >= 4) {
8dd3dca3	295	qemu_get_be32s(f, &env->smbase);
5cc1d1e6 FB	296	}
	297	if (version_id >= 5) {
	298	qemu_get_be64s(f, &env->pat);
	299	qemu_get_be32s(f, &env->hflags2);
9656f324 PB	300	if (version_id < 6)
9656f324 PB	301	qemu_get_be32s(f, &env->halted);
5cc1d1e6 FB	302
	303	qemu_get_be64s(f, &env->vm_hsave);
	304	qemu_get_be64s(f, &env->vm_vmcb);
	305	qemu_get_be64s(f, &env->tsc_offset);
	306	qemu_get_be64s(f, &env->intercept);
	307	qemu_get_be16s(f, &env->intercept_cr_read);
	308	qemu_get_be16s(f, &env->intercept_cr_write);
	309	qemu_get_be16s(f, &env->intercept_dr_read);
	310	qemu_get_be16s(f, &env->intercept_dr_write);
	311	qemu_get_be32s(f, &env->intercept_exceptions);
	312	qemu_get_8s(f, &env->v_tpr);
	313	}
dd5e3b17 AL	314
	315	if (version_id >= 8) {
	316	/* MTRRs */
	317	for(i = 0; i < 11; i++)
	318	qemu_get_be64s(f, &env->mtrr_fixed[i]);
	319	qemu_get_be64s(f, &env->mtrr_deftype);
	320	for(i = 0; i < 8; i++) {
	321	qemu_get_be64s(f, &env->mtrr_var[i].base);
	322	qemu_get_be64s(f, &env->mtrr_var[i].mask);
	323	}
	324	}
	325
5cc1d1e6 FB	326	/* XXX: ensure compatiblity for halted bit ? */
5cc1d1e6 FB	327	/* XXX: compute redundant hflags bits */
8dd3dca3 AJ	328	env->hflags = hflags;
	329	tlb_flush(env, 1);
	330	return 0;
	331	}