[qemu.git] / softmmu_header.h

/*
 *  Software MMU support
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#define DATA_STYPE int16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#define DATA_STYPE int8_t
#else
#error unsupported data size
#endif

#if ACCESS_TYPE < (NB_MMU_MODES)

#define CPU_MMU_INDEX ACCESS_TYPE
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == (NB_MMU_MODES)

#define CPU_MMU_INDEX (cpu_mmu_index(env))
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == (NB_MMU_MODES + 1)

#define CPU_MMU_INDEX (cpu_mmu_index(env))
#define MMUSUFFIX _cmmu

#else
#error invalid ACCESS_TYPE
#endif

#if DATA_SIZE == 8
#define RES_TYPE uint64_t
#else
#define RES_TYPE int
#endif

#if ACCESS_TYPE == (NB_MMU_MODES + 1)
#define ADDR_READ addr_code
#else
#define ADDR_READ addr_read
#endif

DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                         int mmu_idx);
void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int mmu_idx);

#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
    (ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU)

#define CPU_TLB_ENTRY_BITS 4

static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res;

    asm volatile ("movl %1, %%edx\n"
                  "movl %1, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %1, %%eax\n"
                  "je 1f\n"
                  "pushl %6\n"
                  "call %7\n"
                  "popl %%edx\n"
                  "movl %%eax, %0\n"
                  "jmp 2f\n"
                  "1:\n"
                  "addl 12(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movzbl (%%eax), %0\n"
#elif DATA_SIZE == 2
                  "movzwl (%%eax), %0\n"
#elif DATA_SIZE == 4
                  "movl (%%eax), %0\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : "=r" (res)
                  : "r" (ptr),
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
                  "i" (CPU_MMU_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
    return res;
}

#if DATA_SIZE <= 2
static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res;

    asm volatile ("movl %1, %%edx\n"
                  "movl %1, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %1, %%eax\n"
                  "je 1f\n"
                  "pushl %6\n"
                  "call %7\n"
                  "popl %%edx\n"
#if DATA_SIZE == 1
                  "movsbl %%al, %0\n"
#elif DATA_SIZE == 2
                  "movswl %%ax, %0\n"
#else
#error unsupported size
#endif
                  "jmp 2f\n"
                  "1:\n"
                  "addl 12(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movsbl (%%eax), %0\n"
#elif DATA_SIZE == 2
                  "movswl (%%eax), %0\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : "=r" (res)
                  : "r" (ptr),
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
                  "i" (CPU_MMU_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
    return res;
}
#endif

static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
{
    asm volatile ("movl %0, %%edx\n"
                  "movl %0, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %0, %%eax\n"
                  "je 1f\n"
#if DATA_SIZE == 1
                  "movzbl %b1, %%edx\n"
#elif DATA_SIZE == 2
                  "movzwl %w1, %%edx\n"
#elif DATA_SIZE == 4
                  "movl %1, %%edx\n"
#else
#error unsupported size
#endif
                  "pushl %6\n"
                  "call %7\n"
                  "popl %%eax\n"
                  "jmp 2f\n"
                  "1:\n"
                  "addl 8(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movb %b1, (%%eax)\n"
#elif DATA_SIZE == 2
                  "movw %w1, (%%eax)\n"
#elif DATA_SIZE == 4
                  "movl %1, (%%eax)\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  :
                  : "r" (ptr),
/* NOTE: 'q' would be needed as constraint, but we could not use it
   with T1 ! */
                  "r" (v),
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_write)),
                  "i" (CPU_MMU_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
}

#else

/* generic load/store macros */

static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int index;
    RES_TYPE res;
    target_ulong addr;
    unsigned long physaddr;
    int mmu_idx;

    addr = ptr;
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    mmu_idx = CPU_MMU_INDEX;
    if (__builtin_expect(env->tlb_table[mmu_idx][index].ADDR_READ !=
                         (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
        res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
    } else {
        physaddr = addr + env->tlb_table[mmu_idx][index].addend;
        res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
    }
    return res;
}

#if DATA_SIZE <= 2
static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res, index;
    target_ulong addr;
    unsigned long physaddr;
    int mmu_idx;

    addr = ptr;
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    mmu_idx = CPU_MMU_INDEX;
    if (__builtin_expect(env->tlb_table[mmu_idx][index].ADDR_READ !=
                         (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
        res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
    } else {
        physaddr = addr + env->tlb_table[mmu_idx][index].addend;
        res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
    }
    return res;
}
#endif

#if ACCESS_TYPE != (NB_MMU_MODES + 1)

/* generic store macro */

static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
{
    int index;
    target_ulong addr;
    unsigned long physaddr;
    int mmu_idx;

    addr = ptr;
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    mmu_idx = CPU_MMU_INDEX;
    if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_write !=
                         (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
        glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx);
    } else {
        physaddr = addr + env->tlb_table[mmu_idx][index].addend;
        glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
    }
}

#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */

#endif /* !asm */

#if ACCESS_TYPE != (NB_MMU_MODES + 1)

#if DATA_SIZE == 8
static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
{
    union {
        float64 d;
        uint64_t i;
    } u;
    u.i = glue(ldq, MEMSUFFIX)(ptr);
    return u.d;
}

static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
{
    union {
        float64 d;
        uint64_t i;
    } u;
    u.d = v;
    glue(stq, MEMSUFFIX)(ptr, u.i);
}
#endif /* DATA_SIZE == 8 */

#if DATA_SIZE == 4
static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
{
    union {
        float32 f;
        uint32_t i;
    } u;
    u.i = glue(ldl, MEMSUFFIX)(ptr);
    return u.f;
}

static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
{
    union {
        float32 f;
        uint32_t i;
    } u;
    u.f = v;
    glue(stl, MEMSUFFIX)(ptr, u.i);
}
#endif /* DATA_SIZE == 4 */

#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */

#undef RES_TYPE
#undef DATA_TYPE
#undef DATA_STYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
#undef CPU_MMU_INDEX
#undef MMUSUFFIX
#undef ADDR_READ
Commit	Line	Data
b92e5a22 FB	1	/*
b92e5a22 FB	2	* Software MMU support
5fafdf24	3	*
b92e5a22 FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#if DATA_SIZE == 8
	21	#define SUFFIX q
61382a50	22	#define USUFFIX q
b92e5a22 FB	23	#define DATA_TYPE uint64_t
	24	#elif DATA_SIZE == 4
	25	#define SUFFIX l
61382a50	26	#define USUFFIX l
b92e5a22 FB	27	#define DATA_TYPE uint32_t
	28	#elif DATA_SIZE == 2
	29	#define SUFFIX w
61382a50	30	#define USUFFIX uw
b92e5a22 FB	31	#define DATA_TYPE uint16_t
	32	#define DATA_STYPE int16_t
	33	#elif DATA_SIZE == 1
	34	#define SUFFIX b
61382a50	35	#define USUFFIX ub
b92e5a22 FB	36	#define DATA_TYPE uint8_t
	37	#define DATA_STYPE int8_t
	38	#else
	39	#error unsupported data size
	40	#endif
	41
6ebbf390	42	#if ACCESS_TYPE < (NB_MMU_MODES)
61382a50	43
6ebbf390	44	#define CPU_MMU_INDEX ACCESS_TYPE
61382a50 FB	45	#define MMUSUFFIX _mmu
61382a50 FB	46
6ebbf390	47	#elif ACCESS_TYPE == (NB_MMU_MODES)
61382a50	48
6ebbf390	49	#define CPU_MMU_INDEX (cpu_mmu_index(env))
61382a50 FB	50	#define MMUSUFFIX _mmu
61382a50 FB	51
6ebbf390	52	#elif ACCESS_TYPE == (NB_MMU_MODES + 1)
61382a50	53
6ebbf390	54	#define CPU_MMU_INDEX (cpu_mmu_index(env))
61382a50 FB	55	#define MMUSUFFIX _cmmu
61382a50 FB	56
b92e5a22	57	#else
61382a50	58	#error invalid ACCESS_TYPE
b92e5a22 FB	59	#endif
	60
	61	#if DATA_SIZE == 8
	62	#define RES_TYPE uint64_t
	63	#else
	64	#define RES_TYPE int
	65	#endif
	66
6ebbf390	67	#if ACCESS_TYPE == (NB_MMU_MODES + 1)
84b7b8e7 FB	68	#define ADDR_READ addr_code
	69	#else
	70	#define ADDR_READ addr_read
	71	#endif
b92e5a22	72
c27004ec	73	DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
6ebbf390 JM	74	int mmu_idx);
6ebbf390 JM	75	void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int mmu_idx);
b92e5a22	76
c27004ec	77	#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
6ebbf390	78	(ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU)
e16c53fa	79
84b7b8e7 FB	80	#define CPU_TLB_ENTRY_BITS 4
84b7b8e7 FB	81
c27004ec	82	static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
e16c53fa FB	83	{
	84	int res;
	85
	86	asm volatile ("movl %1, %%edx\n"
	87	"movl %1, %%eax\n"
	88	"shrl %3, %%edx\n"
	89	"andl %4, %%eax\n"
	90	"andl %2, %%edx\n"
	91	"leal %5(%%edx, %%ebp), %%edx\n"
	92	"cmpl (%%edx), %%eax\n"
	93	"movl %1, %%eax\n"
	94	"je 1f\n"
	95	"pushl %6\n"
	96	"call %7\n"
	97	"popl %%edx\n"
	98	"movl %%eax, %0\n"
	99	"jmp 2f\n"
	100	"1:\n"
84b7b8e7	101	"addl 12(%%edx), %%eax\n"
e16c53fa FB	102	#if DATA_SIZE == 1
	103	"movzbl (%%eax), %0\n"
	104	#elif DATA_SIZE == 2
	105	"movzwl (%%eax), %0\n"
	106	#elif DATA_SIZE == 4
	107	"movl (%%eax), %0\n"
	108	#else
	109	#error unsupported size
	110	#endif
	111	"2:\n"
	112	: "=r" (res)
5fafdf24 TS	113	: "r" (ptr),
	114	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
	115	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	116	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
6ebbf390 JM	117	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
6ebbf390 JM	118	"i" (CPU_MMU_INDEX),
e16c53fa FB	119	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))
	120	: "%eax", "%ecx", "%edx", "memory", "cc");
	121	return res;
	122	}
	123
	124	#if DATA_SIZE <= 2
c27004ec	125	static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
e16c53fa FB	126	{
	127	int res;
	128
	129	asm volatile ("movl %1, %%edx\n"
	130	"movl %1, %%eax\n"
	131	"shrl %3, %%edx\n"
	132	"andl %4, %%eax\n"
	133	"andl %2, %%edx\n"
	134	"leal %5(%%edx, %%ebp), %%edx\n"
	135	"cmpl (%%edx), %%eax\n"
	136	"movl %1, %%eax\n"
	137	"je 1f\n"
	138	"pushl %6\n"
	139	"call %7\n"
	140	"popl %%edx\n"
	141	#if DATA_SIZE == 1
	142	"movsbl %%al, %0\n"
	143	#elif DATA_SIZE == 2
	144	"movswl %%ax, %0\n"
	145	#else
	146	#error unsupported size
	147	#endif
	148	"jmp 2f\n"
	149	"1:\n"
84b7b8e7	150	"addl 12(%%edx), %%eax\n"
e16c53fa FB	151	#if DATA_SIZE == 1
	152	"movsbl (%%eax), %0\n"
	153	#elif DATA_SIZE == 2
	154	"movswl (%%eax), %0\n"
	155	#else
	156	#error unsupported size
	157	#endif
	158	"2:\n"
	159	: "=r" (res)
5fafdf24 TS	160	: "r" (ptr),
	161	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
	162	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	163	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
6ebbf390 JM	164	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
6ebbf390 JM	165	"i" (CPU_MMU_INDEX),
e16c53fa FB	166	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))
	167	: "%eax", "%ecx", "%edx", "memory", "cc");
	168	return res;
	169	}
	170	#endif
	171
c27004ec	172	static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
e16c53fa FB	173	{
	174	asm volatile ("movl %0, %%edx\n"
	175	"movl %0, %%eax\n"
	176	"shrl %3, %%edx\n"
	177	"andl %4, %%eax\n"
	178	"andl %2, %%edx\n"
	179	"leal %5(%%edx, %%ebp), %%edx\n"
	180	"cmpl (%%edx), %%eax\n"
	181	"movl %0, %%eax\n"
	182	"je 1f\n"
	183	#if DATA_SIZE == 1
	184	"movzbl %b1, %%edx\n"
	185	#elif DATA_SIZE == 2
	186	"movzwl %w1, %%edx\n"
	187	#elif DATA_SIZE == 4
	188	"movl %1, %%edx\n"
	189	#else
	190	#error unsupported size
	191	#endif
	192	"pushl %6\n"
	193	"call %7\n"
	194	"popl %%eax\n"
	195	"jmp 2f\n"
	196	"1:\n"
84b7b8e7	197	"addl 8(%%edx), %%eax\n"
e16c53fa FB	198	#if DATA_SIZE == 1
	199	"movb %b1, (%%eax)\n"
	200	#elif DATA_SIZE == 2
	201	"movw %w1, (%%eax)\n"
	202	#elif DATA_SIZE == 4
	203	"movl %1, (%%eax)\n"
	204	#else
	205	#error unsupported size
	206	#endif
	207	"2:\n"
5fafdf24 TS	208	:
5fafdf24 TS	209	: "r" (ptr),
e16c53fa FB	210	/* NOTE: 'q' would be needed as constraint, but we could not use it
e16c53fa FB	211	with T1 ! */
5fafdf24 TS	212	"r" (v),
	213	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
	214	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	215	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
6ebbf390 JM	216	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_write)),
6ebbf390 JM	217	"i" (CPU_MMU_INDEX),
e16c53fa FB	218	"m" ((uint8_t )&glue(glue(__st, SUFFIX), MMUSUFFIX))
	219	: "%eax", "%ecx", "%edx", "memory", "cc");
	220	}
	221
	222	#else
	223
	224	/* generic load/store macros */
	225
c27004ec	226	static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
b92e5a22 FB	227	{
	228	int index;
	229	RES_TYPE res;
c27004ec FB	230	target_ulong addr;
c27004ec FB	231	unsigned long physaddr;
6ebbf390	232	int mmu_idx;
61382a50	233
c27004ec	234	addr = ptr;
b92e5a22	235	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
6ebbf390 JM	236	mmu_idx = CPU_MMU_INDEX;
6ebbf390 JM	237	if (__builtin_expect(env->tlb_table[mmu_idx][index].ADDR_READ !=
b92e5a22	238	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))), 0)) {
6ebbf390	239	res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
b92e5a22	240	} else {
6ebbf390	241	physaddr = addr + env->tlb_table[mmu_idx][index].addend;
61382a50	242	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
b92e5a22 FB	243	}
	244	return res;
	245	}
	246
	247	#if DATA_SIZE <= 2
c27004ec	248	static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
b92e5a22 FB	249	{
b92e5a22 FB	250	int res, index;
c27004ec FB	251	target_ulong addr;
c27004ec FB	252	unsigned long physaddr;
6ebbf390	253	int mmu_idx;
61382a50	254
c27004ec	255	addr = ptr;
b92e5a22	256	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
6ebbf390 JM	257	mmu_idx = CPU_MMU_INDEX;
6ebbf390 JM	258	if (__builtin_expect(env->tlb_table[mmu_idx][index].ADDR_READ !=
b92e5a22	259	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))), 0)) {
6ebbf390	260	res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
b92e5a22	261	} else {
6ebbf390	262	physaddr = addr + env->tlb_table[mmu_idx][index].addend;
b92e5a22 FB	263	res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
	264	}
	265	return res;
	266	}
	267	#endif
	268
6ebbf390	269	#if ACCESS_TYPE != (NB_MMU_MODES + 1)
84b7b8e7	270
e16c53fa FB	271	/* generic store macro */
e16c53fa FB	272
c27004ec	273	static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
b92e5a22 FB	274	{
b92e5a22 FB	275	int index;
c27004ec FB	276	target_ulong addr;
c27004ec FB	277	unsigned long physaddr;
6ebbf390	278	int mmu_idx;
61382a50	279
c27004ec	280	addr = ptr;
b92e5a22	281	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
6ebbf390 JM	282	mmu_idx = CPU_MMU_INDEX;
6ebbf390 JM	283	if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_write !=
b92e5a22	284	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))), 0)) {
6ebbf390	285	glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx);
b92e5a22	286	} else {
6ebbf390	287	physaddr = addr + env->tlb_table[mmu_idx][index].addend;
b92e5a22 FB	288	glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
	289	}
	290	}
	291
6ebbf390	292	#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
84b7b8e7 FB	293
	294	#endif /* !asm */
	295
6ebbf390	296	#if ACCESS_TYPE != (NB_MMU_MODES + 1)
e16c53fa	297
2d603d22	298	#if DATA_SIZE == 8
3f87bf69	299	static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
2d603d22 FB	300	{
2d603d22 FB	301	union {
3f87bf69	302	float64 d;
2d603d22 FB	303	uint64_t i;
	304	} u;
	305	u.i = glue(ldq, MEMSUFFIX)(ptr);
	306	return u.d;
	307	}
	308
3f87bf69	309	static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
2d603d22 FB	310	{
2d603d22 FB	311	union {
3f87bf69	312	float64 d;
2d603d22 FB	313	uint64_t i;
	314	} u;
	315	u.d = v;
	316	glue(stq, MEMSUFFIX)(ptr, u.i);
	317	}
	318	#endif /* DATA_SIZE == 8 */
	319
	320	#if DATA_SIZE == 4
3f87bf69	321	static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
2d603d22 FB	322	{
2d603d22 FB	323	union {
3f87bf69	324	float32 f;
2d603d22 FB	325	uint32_t i;
	326	} u;
	327	u.i = glue(ldl, MEMSUFFIX)(ptr);
	328	return u.f;
	329	}
	330
3f87bf69	331	static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
2d603d22 FB	332	{
2d603d22 FB	333	union {
3f87bf69	334	float32 f;
2d603d22 FB	335	uint32_t i;
	336	} u;
	337	u.f = v;
	338	glue(stl, MEMSUFFIX)(ptr, u.i);
	339	}
	340	#endif /* DATA_SIZE == 4 */
	341
6ebbf390	342	#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
84b7b8e7	343
b92e5a22 FB	344	#undef RES_TYPE
	345	#undef DATA_TYPE
	346	#undef DATA_STYPE
	347	#undef SUFFIX
61382a50	348	#undef USUFFIX
b92e5a22	349	#undef DATA_SIZE
6ebbf390	350	#undef CPU_MMU_INDEX
61382a50	351	#undef MMUSUFFIX
84b7b8e7	352	#undef ADDR_READ