[qemu.git] / hw / timer / grlib_gptimer.c

/*
 * QEMU GRLIB GPTimer Emulator
 *
 * Copyright (c) 2010-2011 AdaCore
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"
#include "qemu/main-loop.h"

#include "trace.h"

#define UNIT_REG_SIZE    16     /* Size of memory mapped regs for the unit */
#define GPTIMER_REG_SIZE 16     /* Size of memory mapped regs for a GPTimer */

#define GPTIMER_MAX_TIMERS 8

/* GPTimer Config register fields */
#define GPTIMER_ENABLE      (1 << 0)
#define GPTIMER_RESTART     (1 << 1)
#define GPTIMER_LOAD        (1 << 2)
#define GPTIMER_INT_ENABLE  (1 << 3)
#define GPTIMER_INT_PENDING (1 << 4)
#define GPTIMER_CHAIN       (1 << 5) /* Not supported */
#define GPTIMER_DEBUG_HALT  (1 << 6) /* Not supported */

/* Memory mapped register offsets */
#define SCALER_OFFSET         0x00
#define SCALER_RELOAD_OFFSET  0x04
#define CONFIG_OFFSET         0x08
#define COUNTER_OFFSET        0x00
#define COUNTER_RELOAD_OFFSET 0x04
#define TIMER_BASE            0x10

#define TYPE_GRLIB_GPTIMER "grlib,gptimer"
#define GRLIB_GPTIMER(obj) \
    OBJECT_CHECK(GPTimerUnit, (obj), TYPE_GRLIB_GPTIMER)

typedef struct GPTimer     GPTimer;
typedef struct GPTimerUnit GPTimerUnit;

struct GPTimer {
    QEMUBH *bh;
    struct ptimer_state *ptimer;

    qemu_irq     irq;
    int          id;
    GPTimerUnit *unit;

    /* registers */
    uint32_t counter;
    uint32_t reload;
    uint32_t config;
};

struct GPTimerUnit {
    SysBusDevice  parent_obj;

    MemoryRegion iomem;

    uint32_t nr_timers;         /* Number of timers available */
    uint32_t freq_hz;           /* System frequency */
    uint32_t irq_line;          /* Base irq line */

    GPTimer *timers;

    /* registers */
    uint32_t scaler;
    uint32_t reload;
    uint32_t config;
};

static void grlib_gptimer_enable(GPTimer *timer)
{
    assert(timer != NULL);


    ptimer_stop(timer->ptimer);

    if (!(timer->config & GPTIMER_ENABLE)) {
        /* Timer disabled */
        trace_grlib_gptimer_disabled(timer->id, timer->config);
        return;
    }

    /* ptimer is triggered when the counter reach 0 but GPTimer is triggered at
       underflow. Set count + 1 to simulate the GPTimer behavior. */

    trace_grlib_gptimer_enable(timer->id, timer->counter);

    ptimer_set_count(timer->ptimer, (uint64_t)timer->counter + 1);
    ptimer_run(timer->ptimer, 1);
}

static void grlib_gptimer_restart(GPTimer *timer)
{
    assert(timer != NULL);

    trace_grlib_gptimer_restart(timer->id, timer->reload);

    timer->counter = timer->reload;
    grlib_gptimer_enable(timer);
}

static void grlib_gptimer_set_scaler(GPTimerUnit *unit, uint32_t scaler)
{
    int i = 0;
    uint32_t value = 0;

    assert(unit != NULL);

    if (scaler > 0) {
        value = unit->freq_hz / (scaler + 1);
    } else {
        value = unit->freq_hz;
    }

    trace_grlib_gptimer_set_scaler(scaler, value);

    for (i = 0; i < unit->nr_timers; i++) {
        ptimer_set_freq(unit->timers[i].ptimer, value);
    }
}

static void grlib_gptimer_hit(void *opaque)
{
    GPTimer *timer = opaque;
    assert(timer != NULL);

    trace_grlib_gptimer_hit(timer->id);

    /* Timer expired */

    if (timer->config & GPTIMER_INT_ENABLE) {
        /* Set the pending bit (only unset by write in the config register) */
        timer->config |= GPTIMER_INT_PENDING;
        qemu_irq_pulse(timer->irq);
    }

    if (timer->config & GPTIMER_RESTART) {
        grlib_gptimer_restart(timer);
    }
}

static uint64_t grlib_gptimer_read(void *opaque, hwaddr addr,
                                   unsigned size)
{
    GPTimerUnit        *unit  = opaque;
    hwaddr  timer_addr;
    int                 id;
    uint32_t            value = 0;

    addr &= 0xff;

    /* Unit registers */
    switch (addr) {
    case SCALER_OFFSET:
        trace_grlib_gptimer_readl(-1, addr, unit->scaler);
        return unit->scaler;

    case SCALER_RELOAD_OFFSET:
        trace_grlib_gptimer_readl(-1, addr, unit->reload);
        return unit->reload;

    case CONFIG_OFFSET:
        trace_grlib_gptimer_readl(-1, addr, unit->config);
        return unit->config;

    default:
        break;
    }

    timer_addr = (addr % TIMER_BASE);
    id         = (addr - TIMER_BASE) / TIMER_BASE;

    if (id >= 0 && id < unit->nr_timers) {

        /* GPTimer registers */
        switch (timer_addr) {
        case COUNTER_OFFSET:
            value = ptimer_get_count(unit->timers[id].ptimer);
            trace_grlib_gptimer_readl(id, addr, value);
            return value;

        case COUNTER_RELOAD_OFFSET:
            value = unit->timers[id].reload;
            trace_grlib_gptimer_readl(id, addr, value);
            return value;

        case CONFIG_OFFSET:
            trace_grlib_gptimer_readl(id, addr, unit->timers[id].config);
            return unit->timers[id].config;

        default:
            break;
        }

    }

    trace_grlib_gptimer_readl(-1, addr, 0);
    return 0;
}

static void grlib_gptimer_write(void *opaque, hwaddr addr,
                                uint64_t value, unsigned size)
{
    GPTimerUnit        *unit = opaque;
    hwaddr  timer_addr;
    int                 id;

    addr &= 0xff;

    /* Unit registers */
    switch (addr) {
    case SCALER_OFFSET:
        value &= 0xFFFF; /* clean up the value */
        unit->scaler = value;
        trace_grlib_gptimer_writel(-1, addr, unit->scaler);
        return;

    case SCALER_RELOAD_OFFSET:
        value &= 0xFFFF; /* clean up the value */
        unit->reload = value;
        trace_grlib_gptimer_writel(-1, addr, unit->reload);
        grlib_gptimer_set_scaler(unit, value);
        return;

    case CONFIG_OFFSET:
        /* Read Only (disable timer freeze not supported) */
        trace_grlib_gptimer_writel(-1, addr, 0);
        return;

    default:
        break;
    }

    timer_addr = (addr % TIMER_BASE);
    id         = (addr - TIMER_BASE) / TIMER_BASE;

    if (id >= 0 && id < unit->nr_timers) {

        /* GPTimer registers */
        switch (timer_addr) {
        case COUNTER_OFFSET:
            trace_grlib_gptimer_writel(id, addr, value);
            unit->timers[id].counter = value;
            grlib_gptimer_enable(&unit->timers[id]);
            return;

        case COUNTER_RELOAD_OFFSET:
            trace_grlib_gptimer_writel(id, addr, value);
            unit->timers[id].reload = value;
            return;

        case CONFIG_OFFSET:
            trace_grlib_gptimer_writel(id, addr, value);

            if (value & GPTIMER_INT_PENDING) {
                /* clear pending bit */
                value &= ~GPTIMER_INT_PENDING;
            } else {
                /* keep pending bit */
                value |= unit->timers[id].config & GPTIMER_INT_PENDING;
            }

            unit->timers[id].config = value;

            /* gptimer_restart calls gptimer_enable, so if "enable" and "load"
               bits are present, we just have to call restart. */

            if (value & GPTIMER_LOAD) {
                grlib_gptimer_restart(&unit->timers[id]);
            } else if (value & GPTIMER_ENABLE) {
                grlib_gptimer_enable(&unit->timers[id]);
            }

            /* These fields must always be read as 0 */
            value &= ~(GPTIMER_LOAD & GPTIMER_DEBUG_HALT);

            unit->timers[id].config = value;
            return;

        default:
            break;
        }

    }

    trace_grlib_gptimer_writel(-1, addr, value);
}

static const MemoryRegionOps grlib_gptimer_ops = {
    .read = grlib_gptimer_read,
    .write = grlib_gptimer_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void grlib_gptimer_reset(DeviceState *d)
{
    GPTimerUnit *unit = GRLIB_GPTIMER(d);
    int          i    = 0;

    assert(unit != NULL);

    unit->scaler = 0;
    unit->reload = 0;

    unit->config  = unit->nr_timers;
    unit->config |= unit->irq_line << 3;
    unit->config |= 1 << 8;     /* separate interrupt */
    unit->config |= 1 << 9;     /* Disable timer freeze */


    for (i = 0; i < unit->nr_timers; i++) {
        GPTimer *timer = &unit->timers[i];

        timer->counter = 0;
        timer->reload = 0;
        timer->config = 0;
        ptimer_stop(timer->ptimer);
        ptimer_set_count(timer->ptimer, 0);
        ptimer_set_freq(timer->ptimer, unit->freq_hz);
    }
}

static int grlib_gptimer_init(SysBusDevice *dev)
{
    GPTimerUnit  *unit = GRLIB_GPTIMER(dev);
    unsigned int  i;

    assert(unit->nr_timers > 0);
    assert(unit->nr_timers <= GPTIMER_MAX_TIMERS);

    unit->timers = g_malloc0(sizeof unit->timers[0] * unit->nr_timers);

    for (i = 0; i < unit->nr_timers; i++) {
        GPTimer *timer = &unit->timers[i];

        timer->unit   = unit;
        timer->bh     = qemu_bh_new(grlib_gptimer_hit, timer);
        timer->ptimer = ptimer_init(timer->bh, PTIMER_POLICY_DEFAULT);
        timer->id     = i;

        /* One IRQ line for each timer */
        sysbus_init_irq(dev, &timer->irq);

        ptimer_set_freq(timer->ptimer, unit->freq_hz);
    }

    memory_region_init_io(&unit->iomem, OBJECT(unit), &grlib_gptimer_ops,
                          unit, "gptimer",
                          UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers);

    sysbus_init_mmio(dev, &unit->iomem);
    return 0;
}

static Property grlib_gptimer_properties[] = {
    DEFINE_PROP_UINT32("frequency", GPTimerUnit, freq_hz,   40000000),
    DEFINE_PROP_UINT32("irq-line",  GPTimerUnit, irq_line,  8),
    DEFINE_PROP_UINT32("nr-timers", GPTimerUnit, nr_timers, 2),
    DEFINE_PROP_END_OF_LIST(),
};

static void grlib_gptimer_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = grlib_gptimer_init;
    dc->reset = grlib_gptimer_reset;
    dc->props = grlib_gptimer_properties;
}

static const TypeInfo grlib_gptimer_info = {
    .name          = TYPE_GRLIB_GPTIMER,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(GPTimerUnit),
    .class_init    = grlib_gptimer_class_init,
};

static void grlib_gptimer_register_types(void)
{
    type_register_static(&grlib_gptimer_info);
}

type_init(grlib_gptimer_register_types)
Commit	Line	Data
0f3a4a01 FC	1	/*
	2	* QEMU GRLIB GPTimer Emulator
	3	*
	4	* Copyright (c) 2010-2011 AdaCore
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
db5ebe5f	25	#include "qemu/osdep.h"
83c9f4ca	26	#include "hw/sysbus.h"
1de7afc9	27	#include "qemu/timer.h"
83c9f4ca	28	#include "hw/ptimer.h"
6a1751b7	29	#include "qemu/main-loop.h"
0f3a4a01 FC	30
	31	#include "trace.h"
	32
	33	#define UNIT_REG_SIZE 16 /* Size of memory mapped regs for the unit */
	34	#define GPTIMER_REG_SIZE 16 /* Size of memory mapped regs for a GPTimer */
	35
	36	#define GPTIMER_MAX_TIMERS 8
	37
	38	/* GPTimer Config register fields */
	39	#define GPTIMER_ENABLE (1 << 0)
	40	#define GPTIMER_RESTART (1 << 1)
	41	#define GPTIMER_LOAD (1 << 2)
	42	#define GPTIMER_INT_ENABLE (1 << 3)
	43	#define GPTIMER_INT_PENDING (1 << 4)
	44	#define GPTIMER_CHAIN (1 << 5) /* Not supported */
	45	#define GPTIMER_DEBUG_HALT (1 << 6) /* Not supported */
	46
	47	/* Memory mapped register offsets */
	48	#define SCALER_OFFSET 0x00
	49	#define SCALER_RELOAD_OFFSET 0x04
	50	#define CONFIG_OFFSET 0x08
	51	#define COUNTER_OFFSET 0x00
	52	#define COUNTER_RELOAD_OFFSET 0x04
	53	#define TIMER_BASE 0x10
	54
541ab55f AF	55	#define TYPE_GRLIB_GPTIMER "grlib,gptimer"
	56	#define GRLIB_GPTIMER(obj) \
	57	OBJECT_CHECK(GPTimerUnit, (obj), TYPE_GRLIB_GPTIMER)
	58
0f3a4a01 FC	59	typedef struct GPTimer GPTimer;
	60	typedef struct GPTimerUnit GPTimerUnit;
	61
	62	struct GPTimer {
	63	QEMUBH *bh;
	64	struct ptimer_state *ptimer;
	65
	66	qemu_irq irq;
	67	int id;
	68	GPTimerUnit *unit;
	69
	70	/* registers */
	71	uint32_t counter;
	72	uint32_t reload;
	73	uint32_t config;
	74	};
	75
	76	struct GPTimerUnit {
541ab55f AF	77	SysBusDevice parent_obj;
541ab55f AF	78
cde844fa	79	MemoryRegion iomem;
0f3a4a01 FC	80
	81	uint32_t nr_timers; /* Number of timers available */
	82	uint32_t freq_hz; /* System frequency */
	83	uint32_t irq_line; /* Base irq line */
	84
	85	GPTimer *timers;
	86
	87	/* registers */
	88	uint32_t scaler;
	89	uint32_t reload;
	90	uint32_t config;
	91	};
	92
	93	static void grlib_gptimer_enable(GPTimer *timer)
	94	{
	95	assert(timer != NULL);
	96
	97
	98	ptimer_stop(timer->ptimer);
	99
	100	if (!(timer->config & GPTIMER_ENABLE)) {
	101	/* Timer disabled */
	102	trace_grlib_gptimer_disabled(timer->id, timer->config);
	103	return;
	104	}
	105
	106	/* ptimer is triggered when the counter reach 0 but GPTimer is triggered at
	107	underflow. Set count + 1 to simulate the GPTimer behavior. */
	108
9d5614d5	109	trace_grlib_gptimer_enable(timer->id, timer->counter);
0f3a4a01	110
9d5614d5	111	ptimer_set_count(timer->ptimer, (uint64_t)timer->counter + 1);
0f3a4a01 FC	112	ptimer_run(timer->ptimer, 1);
	113	}
	114
	115	static void grlib_gptimer_restart(GPTimer *timer)
	116	{
	117	assert(timer != NULL);
	118
	119	trace_grlib_gptimer_restart(timer->id, timer->reload);
	120
	121	timer->counter = timer->reload;
	122	grlib_gptimer_enable(timer);
	123	}
	124
	125	static void grlib_gptimer_set_scaler(GPTimerUnit *unit, uint32_t scaler)
	126	{
	127	int i = 0;
	128	uint32_t value = 0;
	129
	130	assert(unit != NULL);
	131
	132	if (scaler > 0) {
	133	value = unit->freq_hz / (scaler + 1);
	134	} else {
	135	value = unit->freq_hz;
	136	}
	137
	138	trace_grlib_gptimer_set_scaler(scaler, value);
	139
	140	for (i = 0; i < unit->nr_timers; i++) {
	141	ptimer_set_freq(unit->timers[i].ptimer, value);
	142	}
	143	}
	144
	145	static void grlib_gptimer_hit(void *opaque)
	146	{
	147	GPTimer *timer = opaque;
	148	assert(timer != NULL);
	149
	150	trace_grlib_gptimer_hit(timer->id);
	151
	152	/* Timer expired */
	153
	154	if (timer->config & GPTIMER_INT_ENABLE) {
	155	/* Set the pending bit (only unset by write in the config register) */
	156	timer->config \|= GPTIMER_INT_PENDING;
	157	qemu_irq_pulse(timer->irq);
	158	}
	159
	160	if (timer->config & GPTIMER_RESTART) {
	161	grlib_gptimer_restart(timer);
	162	}
	163	}
	164
a8170e5e	165	static uint64_t grlib_gptimer_read(void *opaque, hwaddr addr,
cde844fa	166	unsigned size)
0f3a4a01 FC	167	{
0f3a4a01 FC	168	GPTimerUnit *unit = opaque;
a8170e5e	169	hwaddr timer_addr;
0f3a4a01 FC	170	int id;
	171	uint32_t value = 0;
	172
	173	addr &= 0xff;
	174
	175	/* Unit registers */
	176	switch (addr) {
	177	case SCALER_OFFSET:
b4548fcc	178	trace_grlib_gptimer_readl(-1, addr, unit->scaler);
0f3a4a01 FC	179	return unit->scaler;
	180
	181	case SCALER_RELOAD_OFFSET:
b4548fcc	182	trace_grlib_gptimer_readl(-1, addr, unit->reload);
0f3a4a01 FC	183	return unit->reload;
	184
	185	case CONFIG_OFFSET:
b4548fcc	186	trace_grlib_gptimer_readl(-1, addr, unit->config);
0f3a4a01 FC	187	return unit->config;
	188
	189	default:
	190	break;
	191	}
	192
	193	timer_addr = (addr % TIMER_BASE);
	194	id = (addr - TIMER_BASE) / TIMER_BASE;
	195
	196	if (id >= 0 && id < unit->nr_timers) {
	197
	198	/* GPTimer registers */
	199	switch (timer_addr) {
	200	case COUNTER_OFFSET:
	201	value = ptimer_get_count(unit->timers[id].ptimer);
b4548fcc	202	trace_grlib_gptimer_readl(id, addr, value);
0f3a4a01 FC	203	return value;
	204
	205	case COUNTER_RELOAD_OFFSET:
	206	value = unit->timers[id].reload;
b4548fcc	207	trace_grlib_gptimer_readl(id, addr, value);
0f3a4a01 FC	208	return value;
	209
	210	case CONFIG_OFFSET:
b4548fcc	211	trace_grlib_gptimer_readl(id, addr, unit->timers[id].config);
0f3a4a01 FC	212	return unit->timers[id].config;
	213
	214	default:
	215	break;
	216	}
	217
	218	}
	219
b4548fcc	220	trace_grlib_gptimer_readl(-1, addr, 0);
0f3a4a01 FC	221	return 0;
	222	}
	223
a8170e5e	224	static void grlib_gptimer_write(void *opaque, hwaddr addr,
cde844fa	225	uint64_t value, unsigned size)
0f3a4a01 FC	226	{
0f3a4a01 FC	227	GPTimerUnit *unit = opaque;
a8170e5e	228	hwaddr timer_addr;
0f3a4a01 FC	229	int id;
	230
	231	addr &= 0xff;
	232
	233	/* Unit registers */
	234	switch (addr) {
	235	case SCALER_OFFSET:
	236	value &= 0xFFFF; /* clean up the value */
	237	unit->scaler = value;
b4548fcc	238	trace_grlib_gptimer_writel(-1, addr, unit->scaler);
0f3a4a01 FC	239	return;
	240
	241	case SCALER_RELOAD_OFFSET:
	242	value &= 0xFFFF; /* clean up the value */
	243	unit->reload = value;
b4548fcc	244	trace_grlib_gptimer_writel(-1, addr, unit->reload);
0f3a4a01 FC	245	grlib_gptimer_set_scaler(unit, value);
	246	return;
	247
	248	case CONFIG_OFFSET:
	249	/* Read Only (disable timer freeze not supported) */
b4548fcc	250	trace_grlib_gptimer_writel(-1, addr, 0);
0f3a4a01 FC	251	return;
	252
	253	default:
	254	break;
	255	}
	256
	257	timer_addr = (addr % TIMER_BASE);
	258	id = (addr - TIMER_BASE) / TIMER_BASE;
	259
	260	if (id >= 0 && id < unit->nr_timers) {
	261
	262	/* GPTimer registers */
	263	switch (timer_addr) {
	264	case COUNTER_OFFSET:
b4548fcc	265	trace_grlib_gptimer_writel(id, addr, value);
0f3a4a01 FC	266	unit->timers[id].counter = value;
	267	grlib_gptimer_enable(&unit->timers[id]);
	268	return;
	269
	270	case COUNTER_RELOAD_OFFSET:
b4548fcc	271	trace_grlib_gptimer_writel(id, addr, value);
0f3a4a01 FC	272	unit->timers[id].reload = value;
	273	return;
	274
	275	case CONFIG_OFFSET:
b4548fcc	276	trace_grlib_gptimer_writel(id, addr, value);
0f3a4a01 FC	277
	278	if (value & GPTIMER_INT_PENDING) {
	279	/* clear pending bit */
	280	value &= ~GPTIMER_INT_PENDING;
	281	} else {
	282	/* keep pending bit */
	283	value \|= unit->timers[id].config & GPTIMER_INT_PENDING;
	284	}
	285
	286	unit->timers[id].config = value;
	287
	288	/* gptimer_restart calls gptimer_enable, so if "enable" and "load"
	289	bits are present, we just have to call restart. */
	290
	291	if (value & GPTIMER_LOAD) {
	292	grlib_gptimer_restart(&unit->timers[id]);
	293	} else if (value & GPTIMER_ENABLE) {
	294	grlib_gptimer_enable(&unit->timers[id]);
	295	}
	296
	297	/* These fields must always be read as 0 */
	298	value &= ~(GPTIMER_LOAD & GPTIMER_DEBUG_HALT);
	299
	300	unit->timers[id].config = value;
	301	return;
	302
	303	default:
	304	break;
	305	}
	306
	307	}
	308
b4548fcc	309	trace_grlib_gptimer_writel(-1, addr, value);
0f3a4a01 FC	310	}
0f3a4a01 FC	311
cde844fa AK	312	static const MemoryRegionOps grlib_gptimer_ops = {
	313	.read = grlib_gptimer_read,
	314	.write = grlib_gptimer_write,
	315	.endianness = DEVICE_NATIVE_ENDIAN,
	316	.valid = {
	317	.min_access_size = 4,
	318	.max_access_size = 4,
	319	},
0f3a4a01 FC	320	};
	321
	322	static void grlib_gptimer_reset(DeviceState *d)
	323	{
541ab55f	324	GPTimerUnit *unit = GRLIB_GPTIMER(d);
0f3a4a01 FC	325	int i = 0;
	326
	327	assert(unit != NULL);
	328
	329	unit->scaler = 0;
	330	unit->reload = 0;
0f3a4a01 FC	331
	332	unit->config = unit->nr_timers;
	333	unit->config \|= unit->irq_line << 3;
	334	unit->config \|= 1 << 8; /* separate interrupt */
	335	unit->config \|= 1 << 9; /* Disable timer freeze */
	336
	337
	338	for (i = 0; i < unit->nr_timers; i++) {
	339	GPTimer *timer = &unit->timers[i];
	340
	341	timer->counter = 0;
	342	timer->reload = 0;
	343	timer->config = 0;
	344	ptimer_stop(timer->ptimer);
	345	ptimer_set_count(timer->ptimer, 0);
	346	ptimer_set_freq(timer->ptimer, unit->freq_hz);
	347	}
	348	}
	349
	350	static int grlib_gptimer_init(SysBusDevice *dev)
	351	{
541ab55f	352	GPTimerUnit *unit = GRLIB_GPTIMER(dev);
0f3a4a01	353	unsigned int i;
0f3a4a01 FC	354
	355	assert(unit->nr_timers > 0);
	356	assert(unit->nr_timers <= GPTIMER_MAX_TIMERS);
	357
7267c094	358	unit->timers = g_malloc0(sizeof unit->timers[0] * unit->nr_timers);
0f3a4a01 FC	359
	360	for (i = 0; i < unit->nr_timers; i++) {
	361	GPTimer *timer = &unit->timers[i];
	362
	363	timer->unit = unit;
	364	timer->bh = qemu_bh_new(grlib_gptimer_hit, timer);
e7ea81c3	365	timer->ptimer = ptimer_init(timer->bh, PTIMER_POLICY_DEFAULT);
0f3a4a01 FC	366	timer->id = i;
	367
	368	/* One IRQ line for each timer */
	369	sysbus_init_irq(dev, &timer->irq);
	370
	371	ptimer_set_freq(timer->ptimer, unit->freq_hz);
	372	}
	373
853dca12 PB	374	memory_region_init_io(&unit->iomem, OBJECT(unit), &grlib_gptimer_ops,
853dca12 PB	375	unit, "gptimer",
cde844fa	376	UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers);
0f3a4a01	377
750ecd44	378	sysbus_init_mmio(dev, &unit->iomem);
0f3a4a01 FC	379	return 0;
	380	}
	381
999e12bb AL	382	static Property grlib_gptimer_properties[] = {
	383	DEFINE_PROP_UINT32("frequency", GPTimerUnit, freq_hz, 40000000),
	384	DEFINE_PROP_UINT32("irq-line", GPTimerUnit, irq_line, 8),
	385	DEFINE_PROP_UINT32("nr-timers", GPTimerUnit, nr_timers, 2),
	386	DEFINE_PROP_END_OF_LIST(),
	387	};
	388
	389	static void grlib_gptimer_class_init(ObjectClass klass, void data)
	390	{
39bffca2	391	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	392	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	393
	394	k->init = grlib_gptimer_init;
39bffca2 AL	395	dc->reset = grlib_gptimer_reset;
39bffca2 AL	396	dc->props = grlib_gptimer_properties;
999e12bb AL	397	}
999e12bb AL	398
8c43a6f0	399	static const TypeInfo grlib_gptimer_info = {
541ab55f	400	.name = TYPE_GRLIB_GPTIMER,
39bffca2 AL	401	.parent = TYPE_SYS_BUS_DEVICE,
	402	.instance_size = sizeof(GPTimerUnit),
	403	.class_init = grlib_gptimer_class_init,
0f3a4a01 FC	404	};
0f3a4a01 FC	405
83f7d43a	406	static void grlib_gptimer_register_types(void)
0f3a4a01	407	{
39bffca2	408	type_register_static(&grlib_gptimer_info);
0f3a4a01 FC	409	}
0f3a4a01 FC	410
83f7d43a	411	type_init(grlib_gptimer_register_types)