[qemu.git] / target-arm / kvm.c

/*
 * ARM implementation of KVM hooks
 *
 * Copyright Christoffer Dall 2009-2010
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 *
 */

#include <stdio.h>
#include <sys/types.h>
#include <sys/ioctl.h>
#include <sys/mman.h>

#include <linux/kvm.h>

#include "qemu-common.h"
#include "qemu/timer.h"
#include "sysemu/sysemu.h"
#include "sysemu/kvm.h"
#include "kvm_arm.h"
#include "cpu.h"
#include "hw/arm/arm.h"

const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
    KVM_CAP_LAST_INFO
};

int kvm_arm_vcpu_init(CPUState *cs)
{
    ARMCPU *cpu = ARM_CPU(cs);
    struct kvm_vcpu_init init;

    init.target = cpu->kvm_target;
    memcpy(init.features, cpu->kvm_init_features, sizeof(init.features));

    return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
}

bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
                                      int *fdarray,
                                      struct kvm_vcpu_init *init)
{
    int ret, kvmfd = -1, vmfd = -1, cpufd = -1;

    kvmfd = qemu_open("/dev/kvm", O_RDWR);
    if (kvmfd < 0) {
        goto err;
    }
    vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0);
    if (vmfd < 0) {
        goto err;
    }
    cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0);
    if (cpufd < 0) {
        goto err;
    }

    ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, init);
    if (ret >= 0) {
        ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
        if (ret < 0) {
            goto err;
        }
    } else {
        /* Old kernel which doesn't know about the
         * PREFERRED_TARGET ioctl: we know it will only support
         * creating one kind of guest CPU which is its preferred
         * CPU type.
         */
        while (*cpus_to_try != QEMU_KVM_ARM_TARGET_NONE) {
            init->target = *cpus_to_try++;
            memset(init->features, 0, sizeof(init->features));
            ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
            if (ret >= 0) {
                break;
            }
        }
        if (ret < 0) {
            goto err;
        }
    }

    fdarray[0] = kvmfd;
    fdarray[1] = vmfd;
    fdarray[2] = cpufd;

    return true;

err:
    if (cpufd >= 0) {
        close(cpufd);
    }
    if (vmfd >= 0) {
        close(vmfd);
    }
    if (kvmfd >= 0) {
        close(kvmfd);
    }

    return false;
}

void kvm_arm_destroy_scratch_host_vcpu(int *fdarray)
{
    int i;

    for (i = 2; i >= 0; i--) {
        close(fdarray[i]);
    }
}

static void kvm_arm_host_cpu_class_init(ObjectClass *oc, void *data)
{
    ARMHostCPUClass *ahcc = ARM_HOST_CPU_CLASS(oc);

    /* All we really need to set up for the 'host' CPU
     * is the feature bits -- we rely on the fact that the
     * various ID register values in ARMCPU are only used for
     * TCG CPUs.
     */
    if (!kvm_arm_get_host_cpu_features(ahcc)) {
        fprintf(stderr, "Failed to retrieve host CPU features!\n");
        abort();
    }
}

static void kvm_arm_host_cpu_initfn(Object *obj)
{
    ARMHostCPUClass *ahcc = ARM_HOST_CPU_GET_CLASS(obj);
    ARMCPU *cpu = ARM_CPU(obj);
    CPUARMState *env = &cpu->env;

    cpu->kvm_target = ahcc->target;
    cpu->dtb_compatible = ahcc->dtb_compatible;
    env->features = ahcc->features;
}

static const TypeInfo host_arm_cpu_type_info = {
    .name = TYPE_ARM_HOST_CPU,
#ifdef TARGET_AARCH64
    .parent = TYPE_AARCH64_CPU,
#else
    .parent = TYPE_ARM_CPU,
#endif
    .instance_init = kvm_arm_host_cpu_initfn,
    .class_init = kvm_arm_host_cpu_class_init,
    .class_size = sizeof(ARMHostCPUClass),
};

int kvm_arch_init(KVMState *s)
{
    /* For ARM interrupt delivery is always asynchronous,
     * whether we are using an in-kernel VGIC or not.
     */
    kvm_async_interrupts_allowed = true;

    type_register_static(&host_arm_cpu_type_info);

    return 0;
}

unsigned long kvm_arch_vcpu_id(CPUState *cpu)
{
    return cpu->cpu_index;
}

/* We track all the KVM devices which need their memory addresses
 * passing to the kernel in a list of these structures.
 * When board init is complete we run through the list and
 * tell the kernel the base addresses of the memory regions.
 * We use a MemoryListener to track mapping and unmapping of
 * the regions during board creation, so the board models don't
 * need to do anything special for the KVM case.
 */
typedef struct KVMDevice {
    struct kvm_arm_device_addr kda;
    struct kvm_device_attr kdattr;
    MemoryRegion *mr;
    QSLIST_ENTRY(KVMDevice) entries;
    int dev_fd;
} KVMDevice;

static QSLIST_HEAD(kvm_devices_head, KVMDevice) kvm_devices_head;

static void kvm_arm_devlistener_add(MemoryListener *listener,
                                    MemoryRegionSection *section)
{
    KVMDevice *kd;

    QSLIST_FOREACH(kd, &kvm_devices_head, entries) {
        if (section->mr == kd->mr) {
            kd->kda.addr = section->offset_within_address_space;
        }
    }
}

static void kvm_arm_devlistener_del(MemoryListener *listener,
                                    MemoryRegionSection *section)
{
    KVMDevice *kd;

    QSLIST_FOREACH(kd, &kvm_devices_head, entries) {
        if (section->mr == kd->mr) {
            kd->kda.addr = -1;
        }
    }
}

static MemoryListener devlistener = {
    .region_add = kvm_arm_devlistener_add,
    .region_del = kvm_arm_devlistener_del,
};

static void kvm_arm_set_device_addr(KVMDevice *kd)
{
    struct kvm_device_attr *attr = &kd->kdattr;
    int ret;

    /* If the device control API is available and we have a device fd on the
     * KVMDevice struct, let's use the newer API
     */
    if (kd->dev_fd >= 0) {
        uint64_t addr = kd->kda.addr;
        attr->addr = (uintptr_t)&addr;
        ret = kvm_device_ioctl(kd->dev_fd, KVM_SET_DEVICE_ATTR, attr);
    } else {
        ret = kvm_vm_ioctl(kvm_state, KVM_ARM_SET_DEVICE_ADDR, &kd->kda);
    }

    if (ret < 0) {
        fprintf(stderr, "Failed to set device address: %s\n",
                strerror(-ret));
        abort();
    }
}

static void kvm_arm_machine_init_done(Notifier *notifier, void *data)
{
    KVMDevice *kd, *tkd;

    memory_listener_unregister(&devlistener);
    QSLIST_FOREACH_SAFE(kd, &kvm_devices_head, entries, tkd) {
        if (kd->kda.addr != -1) {
            kvm_arm_set_device_addr(kd);
        }
        memory_region_unref(kd->mr);
        g_free(kd);
    }
}

static Notifier notify = {
    .notify = kvm_arm_machine_init_done,
};

void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group,
                             uint64_t attr, int dev_fd)
{
    KVMDevice *kd;

    if (!kvm_irqchip_in_kernel()) {
        return;
    }

    if (QSLIST_EMPTY(&kvm_devices_head)) {
        memory_listener_register(&devlistener, NULL);
        qemu_add_machine_init_done_notifier(&notify);
    }
    kd = g_new0(KVMDevice, 1);
    kd->mr = mr;
    kd->kda.id = devid;
    kd->kda.addr = -1;
    kd->kdattr.flags = 0;
    kd->kdattr.group = group;
    kd->kdattr.attr = attr;
    kd->dev_fd = dev_fd;
    QSLIST_INSERT_HEAD(&kvm_devices_head, kd, entries);
    memory_region_ref(kd->mr);
}

bool write_kvmstate_to_list(ARMCPU *cpu)
{
    CPUState *cs = CPU(cpu);
    int i;
    bool ok = true;

    for (i = 0; i < cpu->cpreg_array_len; i++) {
        struct kvm_one_reg r;
        uint64_t regidx = cpu->cpreg_indexes[i];
        uint32_t v32;
        int ret;

        r.id = regidx;

        switch (regidx & KVM_REG_SIZE_MASK) {
        case KVM_REG_SIZE_U32:
            r.addr = (uintptr_t)&v32;
            ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
            if (!ret) {
                cpu->cpreg_values[i] = v32;
            }
            break;
        case KVM_REG_SIZE_U64:
            r.addr = (uintptr_t)(cpu->cpreg_values + i);
            ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
            break;
        default:
            abort();
        }
        if (ret) {
            ok = false;
        }
    }
    return ok;
}

bool write_list_to_kvmstate(ARMCPU *cpu)
{
    CPUState *cs = CPU(cpu);
    int i;
    bool ok = true;

    for (i = 0; i < cpu->cpreg_array_len; i++) {
        struct kvm_one_reg r;
        uint64_t regidx = cpu->cpreg_indexes[i];
        uint32_t v32;
        int ret;

        r.id = regidx;
        switch (regidx & KVM_REG_SIZE_MASK) {
        case KVM_REG_SIZE_U32:
            v32 = cpu->cpreg_values[i];
            r.addr = (uintptr_t)&v32;
            break;
        case KVM_REG_SIZE_U64:
            r.addr = (uintptr_t)(cpu->cpreg_values + i);
            break;
        default:
            abort();
        }
        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
        if (ret) {
            /* We might fail for "unknown register" and also for
             * "you tried to set a register which is constant with
             * a different value from what it actually contains".
             */
            ok = false;
        }
    }
    return ok;
}

void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
{
}

void kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
{
}

int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
{
    return 0;
}

bool kvm_arch_stop_on_emulation_error(CPUState *cs)
{
    return true;
}

int kvm_arch_process_async_events(CPUState *cs)
{
    return 0;
}

int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr)
{
    return 1;
}

int kvm_arch_on_sigbus(int code, void *addr)
{
    return 1;
}

void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
{
    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
}

int kvm_arch_insert_sw_breakpoint(CPUState *cs,
                                  struct kvm_sw_breakpoint *bp)
{
    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
    return -EINVAL;
}

int kvm_arch_insert_hw_breakpoint(target_ulong addr,
                                  target_ulong len, int type)
{
    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
    return -EINVAL;
}

int kvm_arch_remove_hw_breakpoint(target_ulong addr,
                                  target_ulong len, int type)
{
    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
    return -EINVAL;
}

int kvm_arch_remove_sw_breakpoint(CPUState *cs,
                                  struct kvm_sw_breakpoint *bp)
{
    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
    return -EINVAL;
}

void kvm_arch_remove_all_hw_breakpoints(void)
{
    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
}

void kvm_arch_init_irq_routing(KVMState *s)
{
}

int kvm_arch_irqchip_create(KVMState *s)
{
    int ret;

    /* If we can create the VGIC using the newer device control API, we
     * let the device do this when it initializes itself, otherwise we
     * fall back to the old API */

    ret = kvm_create_device(s, KVM_DEV_TYPE_ARM_VGIC_V2, true);
    if (ret == 0) {
        return 1;
    }

    return 0;
}
Commit	Line	Data
494b00c7 CD	1	/*
	2	* ARM implementation of KVM hooks
	3	*
	4	* Copyright Christoffer Dall 2009-2010
	5	*
	6	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	7	* See the COPYING file in the top-level directory.
	8	*
	9	*/
	10
	11	#include <stdio.h>
	12	#include <sys/types.h>
	13	#include <sys/ioctl.h>
	14	#include <sys/mman.h>
	15
	16	#include <linux/kvm.h>
	17
	18	#include "qemu-common.h"
	19	#include "qemu/timer.h"
	20	#include "sysemu/sysemu.h"
	21	#include "sysemu/kvm.h"
eb035b48	22	#include "kvm_arm.h"
494b00c7	23	#include "cpu.h"
bd2be150	24	#include "hw/arm/arm.h"
494b00c7 CD	25
	26	const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
	27	KVM_CAP_LAST_INFO
	28	};
	29
228d5e04 PS	30	int kvm_arm_vcpu_init(CPUState *cs)
	31	{
	32	ARMCPU *cpu = ARM_CPU(cs);
	33	struct kvm_vcpu_init init;
	34
	35	init.target = cpu->kvm_target;
	36	memcpy(init.features, cpu->kvm_init_features, sizeof(init.features));
	37
	38	return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
	39	}
	40
a96c0514 PM	41	bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
	42	int *fdarray,
	43	struct kvm_vcpu_init *init)
	44	{
	45	int ret, kvmfd = -1, vmfd = -1, cpufd = -1;
	46
	47	kvmfd = qemu_open("/dev/kvm", O_RDWR);
	48	if (kvmfd < 0) {
	49	goto err;
	50	}
	51	vmfd = ioctl(kvmfd, KVM_CREATE_VM, 0);
	52	if (vmfd < 0) {
	53	goto err;
	54	}
	55	cpufd = ioctl(vmfd, KVM_CREATE_VCPU, 0);
	56	if (cpufd < 0) {
	57	goto err;
	58	}
	59
	60	ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, init);
	61	if (ret >= 0) {
	62	ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
	63	if (ret < 0) {
	64	goto err;
	65	}
	66	} else {
	67	/* Old kernel which doesn't know about the
	68	* PREFERRED_TARGET ioctl: we know it will only support
	69	* creating one kind of guest CPU which is its preferred
	70	* CPU type.
	71	*/
	72	while (*cpus_to_try != QEMU_KVM_ARM_TARGET_NONE) {
	73	init->target = *cpus_to_try++;
	74	memset(init->features, 0, sizeof(init->features));
	75	ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
	76	if (ret >= 0) {
	77	break;
	78	}
	79	}
	80	if (ret < 0) {
	81	goto err;
	82	}
	83	}
	84
	85	fdarray[0] = kvmfd;
	86	fdarray[1] = vmfd;
	87	fdarray[2] = cpufd;
	88
	89	return true;
	90
	91	err:
	92	if (cpufd >= 0) {
	93	close(cpufd);
	94	}
	95	if (vmfd >= 0) {
	96	close(vmfd);
	97	}
	98	if (kvmfd >= 0) {
	99	close(kvmfd);
	100	}
	101
	102	return false;
	103	}
	104
105	void kvm_arm_destroy_scratch_host_vcpu(int *fdarray)
106	{
107	int i;
108
109	for (i = 2; i >= 0; i--) {
110	close(fdarray[i]);
111	}
112	}
113
a96c0514 PM	114	static void kvm_arm_host_cpu_class_init(ObjectClass oc, void data)
	115	{
	116	ARMHostCPUClass *ahcc = ARM_HOST_CPU_CLASS(oc);
	117
	118	/* All we really need to set up for the 'host' CPU
	119	* is the feature bits -- we rely on the fact that the
	120	* various ID register values in ARMCPU are only used for
	121	* TCG CPUs.
	122	*/
	123	if (!kvm_arm_get_host_cpu_features(ahcc)) {
	124	fprintf(stderr, "Failed to retrieve host CPU features!\n");
	125	abort();
	126	}
	127	}
	128
	129	static void kvm_arm_host_cpu_initfn(Object *obj)
	130	{
	131	ARMHostCPUClass *ahcc = ARM_HOST_CPU_GET_CLASS(obj);
	132	ARMCPU *cpu = ARM_CPU(obj);
	133	CPUARMState *env = &cpu->env;
	134
	135	cpu->kvm_target = ahcc->target;
	136	cpu->dtb_compatible = ahcc->dtb_compatible;
	137	env->features = ahcc->features;
	138	}
	139
	140	static const TypeInfo host_arm_cpu_type_info = {
	141	.name = TYPE_ARM_HOST_CPU,
26861c7c MH	142	#ifdef TARGET_AARCH64
	143	.parent = TYPE_AARCH64_CPU,
	144	#else
a96c0514	145	.parent = TYPE_ARM_CPU,
26861c7c	146	#endif
a96c0514 PM	147	.instance_init = kvm_arm_host_cpu_initfn,
	148	.class_init = kvm_arm_host_cpu_class_init,
	149	.class_size = sizeof(ARMHostCPUClass),
	150	};
	151
494b00c7 CD	152	int kvm_arch_init(KVMState *s)
	153	{
	154	/* For ARM interrupt delivery is always asynchronous,
	155	* whether we are using an in-kernel VGIC or not.
	156	*/
	157	kvm_async_interrupts_allowed = true;
a96c0514 PM	158
	159	type_register_static(&host_arm_cpu_type_info);
	160
494b00c7 CD	161	return 0;
	162	}
	163
	164	unsigned long kvm_arch_vcpu_id(CPUState *cpu)
	165	{
	166	return cpu->cpu_index;
	167	}
	168
eb035b48 PM	169	/* We track all the KVM devices which need their memory addresses
	170	* passing to the kernel in a list of these structures.
	171	* When board init is complete we run through the list and
	172	* tell the kernel the base addresses of the memory regions.
	173	* We use a MemoryListener to track mapping and unmapping of
	174	* the regions during board creation, so the board models don't
	175	* need to do anything special for the KVM case.
	176	*/
	177	typedef struct KVMDevice {
	178	struct kvm_arm_device_addr kda;
1da41cc1	179	struct kvm_device_attr kdattr;
eb035b48 PM	180	MemoryRegion *mr;
eb035b48 PM	181	QSLIST_ENTRY(KVMDevice) entries;
1da41cc1	182	int dev_fd;
eb035b48 PM	183	} KVMDevice;
	184
	185	static QSLIST_HEAD(kvm_devices_head, KVMDevice) kvm_devices_head;
	186
	187	static void kvm_arm_devlistener_add(MemoryListener *listener,
	188	MemoryRegionSection *section)
	189	{
	190	KVMDevice *kd;
	191
	192	QSLIST_FOREACH(kd, &kvm_devices_head, entries) {
	193	if (section->mr == kd->mr) {
	194	kd->kda.addr = section->offset_within_address_space;
	195	}
	196	}
	197	}
	198
	199	static void kvm_arm_devlistener_del(MemoryListener *listener,
	200	MemoryRegionSection *section)
	201	{
	202	KVMDevice *kd;
	203
	204	QSLIST_FOREACH(kd, &kvm_devices_head, entries) {
	205	if (section->mr == kd->mr) {
	206	kd->kda.addr = -1;
	207	}
	208	}
	209	}
	210
	211	static MemoryListener devlistener = {
	212	.region_add = kvm_arm_devlistener_add,
	213	.region_del = kvm_arm_devlistener_del,
	214	};
	215
1da41cc1 CD	216	static void kvm_arm_set_device_addr(KVMDevice *kd)
	217	{
	218	struct kvm_device_attr *attr = &kd->kdattr;
	219	int ret;
	220
	221	/* If the device control API is available and we have a device fd on the
	222	* KVMDevice struct, let's use the newer API
	223	*/
	224	if (kd->dev_fd >= 0) {
	225	uint64_t addr = kd->kda.addr;
	226	attr->addr = (uintptr_t)&addr;
	227	ret = kvm_device_ioctl(kd->dev_fd, KVM_SET_DEVICE_ATTR, attr);
	228	} else {
	229	ret = kvm_vm_ioctl(kvm_state, KVM_ARM_SET_DEVICE_ADDR, &kd->kda);
	230	}
	231
	232	if (ret < 0) {
	233	fprintf(stderr, "Failed to set device address: %s\n",
	234	strerror(-ret));
	235	abort();
	236	}
	237	}
	238
eb035b48 PM	239	static void kvm_arm_machine_init_done(Notifier notifier, void data)
	240	{
	241	KVMDevice kd, tkd;
	242
	243	memory_listener_unregister(&devlistener);
	244	QSLIST_FOREACH_SAFE(kd, &kvm_devices_head, entries, tkd) {
	245	if (kd->kda.addr != -1) {
1da41cc1	246	kvm_arm_set_device_addr(kd);
eb035b48	247	}
dfde4e6e	248	memory_region_unref(kd->mr);
eb035b48 PM	249	g_free(kd);
	250	}
	251	}
	252
	253	static Notifier notify = {
	254	.notify = kvm_arm_machine_init_done,
	255	};
	256
1da41cc1 CD	257	void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group,
1da41cc1 CD	258	uint64_t attr, int dev_fd)
eb035b48 PM	259	{
	260	KVMDevice *kd;
	261
	262	if (!kvm_irqchip_in_kernel()) {
	263	return;
	264	}
	265
	266	if (QSLIST_EMPTY(&kvm_devices_head)) {
	267	memory_listener_register(&devlistener, NULL);
	268	qemu_add_machine_init_done_notifier(&notify);
	269	}
	270	kd = g_new0(KVMDevice, 1);
	271	kd->mr = mr;
	272	kd->kda.id = devid;
	273	kd->kda.addr = -1;
1da41cc1 CD	274	kd->kdattr.flags = 0;
	275	kd->kdattr.group = group;
	276	kd->kdattr.attr = attr;
	277	kd->dev_fd = dev_fd;
eb035b48	278	QSLIST_INSERT_HEAD(&kvm_devices_head, kd, entries);
dfde4e6e	279	memory_region_ref(kd->mr);
eb035b48 PM	280	}
eb035b48 PM	281
ff047453 PM	282	bool write_kvmstate_to_list(ARMCPU *cpu)
	283	{
	284	CPUState *cs = CPU(cpu);
	285	int i;
	286	bool ok = true;
	287
	288	for (i = 0; i < cpu->cpreg_array_len; i++) {
	289	struct kvm_one_reg r;
	290	uint64_t regidx = cpu->cpreg_indexes[i];
	291	uint32_t v32;
	292	int ret;
	293
	294	r.id = regidx;
	295
	296	switch (regidx & KVM_REG_SIZE_MASK) {
	297	case KVM_REG_SIZE_U32:
	298	r.addr = (uintptr_t)&v32;
	299	ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
	300	if (!ret) {
	301	cpu->cpreg_values[i] = v32;
	302	}
	303	break;
	304	case KVM_REG_SIZE_U64:
	305	r.addr = (uintptr_t)(cpu->cpreg_values + i);
	306	ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
	307	break;
	308	default:
	309	abort();
	310	}
	311	if (ret) {
	312	ok = false;
	313	}
	314	}
	315	return ok;
	316	}
	317
	318	bool write_list_to_kvmstate(ARMCPU *cpu)
	319	{
	320	CPUState *cs = CPU(cpu);
	321	int i;
	322	bool ok = true;
	323
	324	for (i = 0; i < cpu->cpreg_array_len; i++) {
	325	struct kvm_one_reg r;
	326	uint64_t regidx = cpu->cpreg_indexes[i];
	327	uint32_t v32;
	328	int ret;
	329
	330	r.id = regidx;
	331	switch (regidx & KVM_REG_SIZE_MASK) {
	332	case KVM_REG_SIZE_U32:
	333	v32 = cpu->cpreg_values[i];
	334	r.addr = (uintptr_t)&v32;
	335	break;
	336	case KVM_REG_SIZE_U64:
	337	r.addr = (uintptr_t)(cpu->cpreg_values + i);
	338	break;
	339	default:
	340	abort();
	341	}
	342	ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
	343	if (ret) {
	344	/* We might fail for "unknown register" and also for
	345	* "you tried to set a register which is constant with
346	* a different value from what it actually contains".
347	*/
348	ok = false;
349	}
350	}
351	return ok;
352	}
353
494b00c7 CD	354	void kvm_arch_pre_run(CPUState cs, struct kvm_run run)
	355	{
	356	}
	357
	358	void kvm_arch_post_run(CPUState cs, struct kvm_run run)
	359	{
	360	}
	361
	362	int kvm_arch_handle_exit(CPUState cs, struct kvm_run run)
	363	{
	364	return 0;
	365	}
	366
494b00c7 CD	367	bool kvm_arch_stop_on_emulation_error(CPUState *cs)
	368	{
	369	return true;
	370	}
	371
	372	int kvm_arch_process_async_events(CPUState *cs)
	373	{
	374	return 0;
	375	}
	376
	377	int kvm_arch_on_sigbus_vcpu(CPUState cs, int code, void addr)
	378	{
	379	return 1;
	380	}
	381
	382	int kvm_arch_on_sigbus(int code, void *addr)
	383	{
	384	return 1;
	385	}
	386
	387	void kvm_arch_update_guest_debug(CPUState cs, struct kvm_guest_debug dbg)
	388	{
	389	qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
	390	}
	391
	392	int kvm_arch_insert_sw_breakpoint(CPUState *cs,
	393	struct kvm_sw_breakpoint *bp)
	394	{
	395	qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
	396	return -EINVAL;
	397	}
	398
	399	int kvm_arch_insert_hw_breakpoint(target_ulong addr,
	400	target_ulong len, int type)
	401	{
	402	qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
	403	return -EINVAL;
	404	}
	405
	406	int kvm_arch_remove_hw_breakpoint(target_ulong addr,
	407	target_ulong len, int type)
	408	{
	409	qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
	410	return -EINVAL;
	411	}
	412
	413	int kvm_arch_remove_sw_breakpoint(CPUState *cs,
	414	struct kvm_sw_breakpoint *bp)
	415	{
	416	qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
	417	return -EINVAL;
	418	}
	419
	420	void kvm_arch_remove_all_hw_breakpoints(void)
	421	{
	422	qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
	423	}
b3a1c626 AK	424
	425	void kvm_arch_init_irq_routing(KVMState *s)
	426	{
	427	}
1da41cc1 CD	428
	429	int kvm_arch_irqchip_create(KVMState *s)
	430	{
	431	int ret;
	432
	433	/* If we can create the VGIC using the newer device control API, we
	434	* let the device do this when it initializes itself, otherwise we
	435	* fall back to the old API */
	436
	437	ret = kvm_create_device(s, KVM_DEV_TYPE_ARM_VGIC_V2, true);
	438	if (ret == 0) {
	439	return 1;
	440	}
	441
	442	return 0;
	443	}