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Improve PowerPC 405 MMU model / share more code for other embedded targets
[qemu.git] / target-ppc / translate_init.c
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3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
3fc6c082
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26//#define PPC_DUMP_CPU
27//#define PPC_DEBUG_SPR
a496775f 28//#define PPC_DEBUG_IRQ
3fc6c082
FB		 29
30struct ppc_def_t {
31 const unsigned char *name;
32 uint32_t pvr;
33 uint32_t pvr_mask;
0487d6a8 34 uint64_t insns_flags;
3fc6c082
FB		 35 uint32_t flags;
36 uint64_t msr_mask;
37};
38
e9df014c
JM		 39/* For user-mode emulation, we don't emulate any IRQ controller */
40#if defined(CONFIG_USER_ONLY)
41#define PPC_IRQ_INIT_FN(name) \
42static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
43{ \
44}
45#else
46#define PPC_IRQ_INIT_FN(name) \
47void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
48#endif
24be5ae3 49PPC_IRQ_INIT_FN(405);
e9df014c 50PPC_IRQ_INIT_FN(6xx);
d0dfae6e 51PPC_IRQ_INIT_FN(970);
e9df014c 52
3fc6c082
FB		 53/* Generic callbacks:
54 * do nothing but store/retrieve spr value
55 */
04f20795 56#ifdef PPC_DUMP_SPR_ACCESSES
3fc6c082
FB		 57static void spr_read_generic (void *opaque, int sprn)
58{
04f20795 59 gen_op_load_dump_spr(sprn);
3fc6c082
FB		 60}
61
62static void spr_write_generic (void *opaque, int sprn)
63{
04f20795 64 gen_op_store_dump_spr(sprn);
3fc6c082 65}
04f20795
JM		 66#else
67static void spr_read_generic (void *opaque, int sprn)
a496775f 68{
04f20795 69 gen_op_load_spr(sprn);
a496775f
JM		 70}
71
04f20795 72static void spr_write_generic (void *opaque, int sprn)
a496775f 73{
04f20795 74 gen_op_store_spr(sprn);
a496775f 75}
04f20795 76#endif
a496775f
JM		 77
78#if !defined(CONFIG_USER_ONLY)
79static void spr_write_clear (void *opaque, int sprn)
80{
81 gen_op_mask_spr(sprn);
82}
83#endif
84
76a66253 85/* SPR common to all PowerPC */
3fc6c082
FB		 86/* XER */
87static void spr_read_xer (void *opaque, int sprn)
88{
89 gen_op_load_xer();
90}
91
92static void spr_write_xer (void *opaque, int sprn)
93{
94 gen_op_store_xer();
95}
96
97/* LR */
98static void spr_read_lr (void *opaque, int sprn)
99{
100 gen_op_load_lr();
101}
102
103static void spr_write_lr (void *opaque, int sprn)
104{
105 gen_op_store_lr();
106}
107
108/* CTR */
109static void spr_read_ctr (void *opaque, int sprn)
110{
111 gen_op_load_ctr();
112}
113
114static void spr_write_ctr (void *opaque, int sprn)
115{
116 gen_op_store_ctr();
117}
118
119/* User read access to SPR */
120/* USPRx */
121/* UMMCRx */
122/* UPMCx */
123/* USIA */
124/* UDECR */
125static void spr_read_ureg (void *opaque, int sprn)
126{
127 gen_op_load_spr(sprn + 0x10);
128}
129
76a66253 130/* SPR common to all non-embedded PowerPC */
3fc6c082 131/* DECR */
76a66253 132#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 133static void spr_read_decr (void *opaque, int sprn)
134{
135 gen_op_load_decr();
136}
137
138static void spr_write_decr (void *opaque, int sprn)
139{
140 gen_op_store_decr();
141}
76a66253 142#endif
3fc6c082 143
76a66253 144/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082
FB		 145/* Time base */
146static void spr_read_tbl (void *opaque, int sprn)
147{
148 gen_op_load_tbl();
149}
150
76a66253 151static void spr_read_tbu (void *opaque, int sprn)
3fc6c082 152{
76a66253 153 gen_op_load_tbu();
3fc6c082
FB		 154}
155
76a66253
JM		 156#if !defined(CONFIG_USER_ONLY)
157static void spr_write_tbl (void *opaque, int sprn)
3fc6c082 158{
76a66253 159 gen_op_store_tbl();
3fc6c082
FB		 160}
161
162static void spr_write_tbu (void *opaque, int sprn)
163{
164 gen_op_store_tbu();
165}
76a66253 166#endif
3fc6c082 167
76a66253 168#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 169/* IBAT0U...IBAT0U */
170/* IBAT0L...IBAT7L */
171static void spr_read_ibat (void *opaque, int sprn)
172{
173 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
174}
175
176static void spr_read_ibat_h (void *opaque, int sprn)
177{
178 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
179}
180
181static void spr_write_ibatu (void *opaque, int sprn)
182{
183 DisasContext *ctx = opaque;
184
185 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
186 RET_STOP(ctx);
187}
188
189static void spr_write_ibatu_h (void *opaque, int sprn)
190{
191 DisasContext *ctx = opaque;
192
193 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
194 RET_STOP(ctx);
195}
196
197static void spr_write_ibatl (void *opaque, int sprn)
198{
199 DisasContext *ctx = opaque;
200
201 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
202 RET_STOP(ctx);
203}
204
205static void spr_write_ibatl_h (void *opaque, int sprn)
206{
207 DisasContext *ctx = opaque;
208
209 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
210 RET_STOP(ctx);
211}
212
213/* DBAT0U...DBAT7U */
214/* DBAT0L...DBAT7L */
215static void spr_read_dbat (void *opaque, int sprn)
216{
217 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
218}
219
220static void spr_read_dbat_h (void *opaque, int sprn)
221{
222 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
223}
224
225static void spr_write_dbatu (void *opaque, int sprn)
226{
227 DisasContext *ctx = opaque;
228
229 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
230 RET_STOP(ctx);
231}
232
233static void spr_write_dbatu_h (void *opaque, int sprn)
234{
235 DisasContext *ctx = opaque;
236
237 gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
238 RET_STOP(ctx);
239}
240
241static void spr_write_dbatl (void *opaque, int sprn)
242{
243 DisasContext *ctx = opaque;
244
245 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
246 RET_STOP(ctx);
247}
248
249static void spr_write_dbatl_h (void *opaque, int sprn)
250{
251 DisasContext *ctx = opaque;
252
253 gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
254 RET_STOP(ctx);
255}
256
257/* SDR1 */
258static void spr_read_sdr1 (void *opaque, int sprn)
259{
260 gen_op_load_sdr1();
261}
262
263static void spr_write_sdr1 (void *opaque, int sprn)
264{
265 DisasContext *ctx = opaque;
266
267 gen_op_store_sdr1();
268 RET_STOP(ctx);
269}
270
76a66253
JM		 271/* 64 bits PowerPC specific SPRs */
272/* ASR */
273#if defined(TARGET_PPC64)
274static void spr_read_asr (void *opaque, int sprn)
275{
276 gen_op_load_asr();
277}
278
279static void spr_write_asr (void *opaque, int sprn)
280{
281 DisasContext *ctx = opaque;
282
283 gen_op_store_asr();
284 RET_STOP(ctx);
285}
286#endif
287#endif /* !defined(CONFIG_USER_ONLY) */
288
289/* PowerPC 601 specific registers */
290/* RTC */
291static void spr_read_601_rtcl (void *opaque, int sprn)
292{
293 gen_op_load_601_rtcl();
294}
295
296static void spr_read_601_rtcu (void *opaque, int sprn)
297{
298 gen_op_load_601_rtcu();
299}
300
301#if !defined(CONFIG_USER_ONLY)
302static void spr_write_601_rtcu (void *opaque, int sprn)
303{
304 gen_op_store_601_rtcu();
305}
306
307static void spr_write_601_rtcl (void *opaque, int sprn)
308{
309 gen_op_store_601_rtcl();
310}
311#endif
312
313/* Unified bats */
314#if !defined(CONFIG_USER_ONLY)
315static void spr_read_601_ubat (void *opaque, int sprn)
316{
317 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
318}
319
320static void spr_write_601_ubatu (void *opaque, int sprn)
321{
322 DisasContext *ctx = opaque;
323
324 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
325 RET_STOP(ctx);
326}
327
328static void spr_write_601_ubatl (void *opaque, int sprn)
329{
330 DisasContext *ctx = opaque;
331
332 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
333 RET_STOP(ctx);
334}
335#endif
336
337/* PowerPC 40x specific registers */
338#if !defined(CONFIG_USER_ONLY)
339static void spr_read_40x_pit (void *opaque, int sprn)
340{
341 gen_op_load_40x_pit();
342}
343
344static void spr_write_40x_pit (void *opaque, int sprn)
345{
346 gen_op_store_40x_pit();
347}
348
8ecc7913
JM		 349static void spr_write_40x_dbcr0 (void *opaque, int sprn)
350{
351 DisasContext *ctx = opaque;
352
353 gen_op_store_40x_dbcr0();
354 /* We must stop translation as we may have rebooted */
355 RET_STOP(ctx);
356}
357
c294fc58
JM		 358static void spr_write_40x_sler (void *opaque, int sprn)
359{
360 DisasContext *ctx = opaque;
361
362 gen_op_store_40x_sler();
363 /* We must stop the translation as we may have changed
364 * some regions endianness
365 */
366 RET_STOP(ctx);
367}
368
76a66253
JM		 369static void spr_write_booke_tcr (void *opaque, int sprn)
370{
371 gen_op_store_booke_tcr();
372}
373
374static void spr_write_booke_tsr (void *opaque, int sprn)
375{
376 gen_op_store_booke_tsr();
377}
378#endif
379
380/* PowerPC 403 specific registers */
381/* PBL1 / PBU1 / PBL2 / PBU2 */
382#if !defined(CONFIG_USER_ONLY)
383static void spr_read_403_pbr (void *opaque, int sprn)
384{
385 gen_op_load_403_pb(sprn - SPR_403_PBL1);
386}
387
388static void spr_write_403_pbr (void *opaque, int sprn)
389{
390 DisasContext *ctx = opaque;
391
392 gen_op_store_403_pb(sprn - SPR_403_PBL1);
393 RET_STOP(ctx);
394}
395
3fc6c082
FB		 396static void spr_write_pir (void *opaque, int sprn)
397{
398 gen_op_store_pir();
399}
76a66253 400#endif
3fc6c082 401
76a66253
JM		 402#if defined(CONFIG_USER_ONLY)
403#define spr_register(env, num, name, uea_read, uea_write, \
404 oea_read, oea_write, initial_value) \
405do { \
406 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
407} while (0)
408static inline void _spr_register (CPUPPCState *env, int num,
409 const unsigned char *name,
410 void (*uea_read)(void *opaque, int sprn),
411 void (*uea_write)(void *opaque, int sprn),
412 target_ulong initial_value)
413#else
3fc6c082
FB		 414static inline void spr_register (CPUPPCState *env, int num,
415 const unsigned char *name,
416 void (*uea_read)(void *opaque, int sprn),
417 void (*uea_write)(void *opaque, int sprn),
418 void (*oea_read)(void *opaque, int sprn),
419 void (*oea_write)(void *opaque, int sprn),
420 target_ulong initial_value)
76a66253 421#endif
3fc6c082
FB		 422{
423 ppc_spr_t *spr;
424
425 spr = &env->spr_cb[num];
426 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 427#if !defined(CONFIG_USER_ONLY)
428 spr->oea_read != NULL || spr->oea_write != NULL ||
429#endif
430 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 431 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
432 exit(1);
433 }
434#if defined(PPC_DEBUG_SPR)
1b9eb036 435 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
76a66253 436 initial_value);
3fc6c082
FB		 437#endif
438 spr->name = name;
439 spr->uea_read = uea_read;
440 spr->uea_write = uea_write;
76a66253 441#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 442 spr->oea_read = oea_read;
443 spr->oea_write = oea_write;
76a66253 444#endif
3fc6c082
FB		 445 env->spr[num] = initial_value;
446}
447
448/* Generic PowerPC SPRs */
449static void gen_spr_generic (CPUPPCState *env)
450{
451 /* Integer processing */
452 spr_register(env, SPR_XER, "XER",
453 &spr_read_xer, &spr_write_xer,
454 &spr_read_xer, &spr_write_xer,
455 0x00000000);
456 /* Branch contol */
457 spr_register(env, SPR_LR, "LR",
458 &spr_read_lr, &spr_write_lr,
459 &spr_read_lr, &spr_write_lr,
460 0x00000000);
461 spr_register(env, SPR_CTR, "CTR",
462 &spr_read_ctr, &spr_write_ctr,
463 &spr_read_ctr, &spr_write_ctr,
464 0x00000000);
465 /* Interrupt processing */
466 spr_register(env, SPR_SRR0, "SRR0",
467 SPR_NOACCESS, SPR_NOACCESS,
468 &spr_read_generic, &spr_write_generic,
469 0x00000000);
470 spr_register(env, SPR_SRR1, "SRR1",
471 SPR_NOACCESS, SPR_NOACCESS,
472 &spr_read_generic, &spr_write_generic,
473 0x00000000);
474 /* Processor control */
475 spr_register(env, SPR_SPRG0, "SPRG0",
476 SPR_NOACCESS, SPR_NOACCESS,
477 &spr_read_generic, &spr_write_generic,
478 0x00000000);
479 spr_register(env, SPR_SPRG1, "SPRG1",
480 SPR_NOACCESS, SPR_NOACCESS,
481 &spr_read_generic, &spr_write_generic,
482 0x00000000);
483 spr_register(env, SPR_SPRG2, "SPRG2",
484 SPR_NOACCESS, SPR_NOACCESS,
485 &spr_read_generic, &spr_write_generic,
486 0x00000000);
487 spr_register(env, SPR_SPRG3, "SPRG3",
488 SPR_NOACCESS, SPR_NOACCESS,
489 &spr_read_generic, &spr_write_generic,
490 0x00000000);
491}
492
493/* SPR common to all non-embedded PowerPC, including 601 */
494static void gen_spr_ne_601 (CPUPPCState *env)
495{
496 /* Exception processing */
497 spr_register(env, SPR_DSISR, "DSISR",
498 SPR_NOACCESS, SPR_NOACCESS,
499 &spr_read_generic, &spr_write_generic,
500 0x00000000);
501 spr_register(env, SPR_DAR, "DAR",
502 SPR_NOACCESS, SPR_NOACCESS,
503 &spr_read_generic, &spr_write_generic,
504 0x00000000);
505 /* Timer */
506 spr_register(env, SPR_DECR, "DECR",
507 SPR_NOACCESS, SPR_NOACCESS,
508 &spr_read_decr, &spr_write_decr,
509 0x00000000);
510 /* Memory management */
511 spr_register(env, SPR_SDR1, "SDR1",
512 SPR_NOACCESS, SPR_NOACCESS,
513 &spr_read_sdr1, &spr_write_sdr1,
514 0x00000000);
515}
516
517/* BATs 0-3 */
518static void gen_low_BATs (CPUPPCState *env)
519{
520 spr_register(env, SPR_IBAT0U, "IBAT0U",
521 SPR_NOACCESS, SPR_NOACCESS,
522 &spr_read_ibat, &spr_write_ibatu,
523 0x00000000);
524 spr_register(env, SPR_IBAT0L, "IBAT0L",
525 SPR_NOACCESS, SPR_NOACCESS,
526 &spr_read_ibat, &spr_write_ibatl,
527 0x00000000);
528 spr_register(env, SPR_IBAT1U, "IBAT1U",
529 SPR_NOACCESS, SPR_NOACCESS,
530 &spr_read_ibat, &spr_write_ibatu,
531 0x00000000);
532 spr_register(env, SPR_IBAT1L, "IBAT1L",
533 SPR_NOACCESS, SPR_NOACCESS,
534 &spr_read_ibat, &spr_write_ibatl,
535 0x00000000);
536 spr_register(env, SPR_IBAT2U, "IBAT2U",
537 SPR_NOACCESS, SPR_NOACCESS,
538 &spr_read_ibat, &spr_write_ibatu,
539 0x00000000);
540 spr_register(env, SPR_IBAT2L, "IBAT2L",
541 SPR_NOACCESS, SPR_NOACCESS,
542 &spr_read_ibat, &spr_write_ibatl,
543 0x00000000);
544 spr_register(env, SPR_IBAT3U, "IBAT3U",
545 SPR_NOACCESS, SPR_NOACCESS,
546 &spr_read_ibat, &spr_write_ibatu,
547 0x00000000);
548 spr_register(env, SPR_IBAT3L, "IBAT3L",
549 SPR_NOACCESS, SPR_NOACCESS,
550 &spr_read_ibat, &spr_write_ibatl,
551 0x00000000);
552 spr_register(env, SPR_DBAT0U, "DBAT0U",
553 SPR_NOACCESS, SPR_NOACCESS,
554 &spr_read_dbat, &spr_write_dbatu,
555 0x00000000);
556 spr_register(env, SPR_DBAT0L, "DBAT0L",
557 SPR_NOACCESS, SPR_NOACCESS,
558 &spr_read_dbat, &spr_write_dbatl,
559 0x00000000);
560 spr_register(env, SPR_DBAT1U, "DBAT1U",
561 SPR_NOACCESS, SPR_NOACCESS,
562 &spr_read_dbat, &spr_write_dbatu,
563 0x00000000);
564 spr_register(env, SPR_DBAT1L, "DBAT1L",
565 SPR_NOACCESS, SPR_NOACCESS,
566 &spr_read_dbat, &spr_write_dbatl,
567 0x00000000);
568 spr_register(env, SPR_DBAT2U, "DBAT2U",
569 SPR_NOACCESS, SPR_NOACCESS,
570 &spr_read_dbat, &spr_write_dbatu,
571 0x00000000);
572 spr_register(env, SPR_DBAT2L, "DBAT2L",
573 SPR_NOACCESS, SPR_NOACCESS,
574 &spr_read_dbat, &spr_write_dbatl,
575 0x00000000);
576 spr_register(env, SPR_DBAT3U, "DBAT3U",
577 SPR_NOACCESS, SPR_NOACCESS,
578 &spr_read_dbat, &spr_write_dbatu,
579 0x00000000);
580 spr_register(env, SPR_DBAT3L, "DBAT3L",
581 SPR_NOACCESS, SPR_NOACCESS,
582 &spr_read_dbat, &spr_write_dbatl,
583 0x00000000);
584 env->nb_BATs = 4;
585}
586
587/* BATs 4-7 */
588static void gen_high_BATs (CPUPPCState *env)
589{
590 spr_register(env, SPR_IBAT4U, "IBAT4U",
591 SPR_NOACCESS, SPR_NOACCESS,
592 &spr_read_ibat_h, &spr_write_ibatu_h,
593 0x00000000);
594 spr_register(env, SPR_IBAT4L, "IBAT4L",
595 SPR_NOACCESS, SPR_NOACCESS,
596 &spr_read_ibat_h, &spr_write_ibatl_h,
597 0x00000000);
598 spr_register(env, SPR_IBAT5U, "IBAT5U",
599 SPR_NOACCESS, SPR_NOACCESS,
600 &spr_read_ibat_h, &spr_write_ibatu_h,
601 0x00000000);
602 spr_register(env, SPR_IBAT5L, "IBAT5L",
603 SPR_NOACCESS, SPR_NOACCESS,
604 &spr_read_ibat_h, &spr_write_ibatl_h,
605 0x00000000);
606 spr_register(env, SPR_IBAT6U, "IBAT6U",
607 SPR_NOACCESS, SPR_NOACCESS,
608 &spr_read_ibat_h, &spr_write_ibatu_h,
609 0x00000000);
610 spr_register(env, SPR_IBAT6L, "IBAT6L",
611 SPR_NOACCESS, SPR_NOACCESS,
612 &spr_read_ibat_h, &spr_write_ibatl_h,
613 0x00000000);
614 spr_register(env, SPR_IBAT7U, "IBAT7U",
615 SPR_NOACCESS, SPR_NOACCESS,
616 &spr_read_ibat_h, &spr_write_ibatu_h,
617 0x00000000);
618 spr_register(env, SPR_IBAT7L, "IBAT7L",
619 SPR_NOACCESS, SPR_NOACCESS,
620 &spr_read_ibat_h, &spr_write_ibatl_h,
621 0x00000000);
622 spr_register(env, SPR_DBAT4U, "DBAT4U",
623 SPR_NOACCESS, SPR_NOACCESS,
624 &spr_read_dbat_h, &spr_write_dbatu_h,
625 0x00000000);
626 spr_register(env, SPR_DBAT4L, "DBAT4L",
627 SPR_NOACCESS, SPR_NOACCESS,
628 &spr_read_dbat_h, &spr_write_dbatl_h,
629 0x00000000);
630 spr_register(env, SPR_DBAT5U, "DBAT5U",
631 SPR_NOACCESS, SPR_NOACCESS,
632 &spr_read_dbat_h, &spr_write_dbatu_h,
633 0x00000000);
634 spr_register(env, SPR_DBAT5L, "DBAT5L",
635 SPR_NOACCESS, SPR_NOACCESS,
636 &spr_read_dbat_h, &spr_write_dbatl_h,
637 0x00000000);
638 spr_register(env, SPR_DBAT6U, "DBAT6U",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_dbat_h, &spr_write_dbatu_h,
641 0x00000000);
642 spr_register(env, SPR_DBAT6L, "DBAT6L",
643 SPR_NOACCESS, SPR_NOACCESS,
644 &spr_read_dbat_h, &spr_write_dbatl_h,
645 0x00000000);
646 spr_register(env, SPR_DBAT7U, "DBAT7U",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_dbat_h, &spr_write_dbatu_h,
649 0x00000000);
650 spr_register(env, SPR_DBAT7L, "DBAT7L",
651 SPR_NOACCESS, SPR_NOACCESS,
652 &spr_read_dbat_h, &spr_write_dbatl_h,
653 0x00000000);
654 env->nb_BATs = 8;
655}
656
657/* Generic PowerPC time base */
658static void gen_tbl (CPUPPCState *env)
659{
660 spr_register(env, SPR_VTBL, "TBL",
661 &spr_read_tbl, SPR_NOACCESS,
662 &spr_read_tbl, SPR_NOACCESS,
663 0x00000000);
664 spr_register(env, SPR_TBL, "TBL",
665 SPR_NOACCESS, SPR_NOACCESS,
666 SPR_NOACCESS, &spr_write_tbl,
667 0x00000000);
668 spr_register(env, SPR_VTBU, "TBU",
669 &spr_read_tbu, SPR_NOACCESS,
670 &spr_read_tbu, SPR_NOACCESS,
671 0x00000000);
672 spr_register(env, SPR_TBU, "TBU",
673 SPR_NOACCESS, SPR_NOACCESS,
674 SPR_NOACCESS, &spr_write_tbu,
675 0x00000000);
676}
677
76a66253
JM		 678/* Softare table search registers */
679static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
680{
681 env->nb_tlb = nb_tlbs;
682 env->nb_ways = nb_ways;
683 env->id_tlbs = 1;
684 spr_register(env, SPR_DMISS, "DMISS",
685 SPR_NOACCESS, SPR_NOACCESS,
686 &spr_read_generic, SPR_NOACCESS,
687 0x00000000);
688 spr_register(env, SPR_DCMP, "DCMP",
689 SPR_NOACCESS, SPR_NOACCESS,
690 &spr_read_generic, SPR_NOACCESS,
691 0x00000000);
692 spr_register(env, SPR_HASH1, "HASH1",
693 SPR_NOACCESS, SPR_NOACCESS,
694 &spr_read_generic, SPR_NOACCESS,
695 0x00000000);
696 spr_register(env, SPR_HASH2, "HASH2",
697 SPR_NOACCESS, SPR_NOACCESS,
698 &spr_read_generic, SPR_NOACCESS,
699 0x00000000);
700 spr_register(env, SPR_IMISS, "IMISS",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_generic, SPR_NOACCESS,
703 0x00000000);
704 spr_register(env, SPR_ICMP, "ICMP",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_generic, SPR_NOACCESS,
707 0x00000000);
708 spr_register(env, SPR_RPA, "RPA",
709 SPR_NOACCESS, SPR_NOACCESS,
710 &spr_read_generic, &spr_write_generic,
711 0x00000000);
712}
713
714/* SPR common to MPC755 and G2 */
715static void gen_spr_G2_755 (CPUPPCState *env)
716{
717 /* SGPRs */
718 spr_register(env, SPR_SPRG4, "SPRG4",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_generic, &spr_write_generic,
721 0x00000000);
722 spr_register(env, SPR_SPRG5, "SPRG5",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_generic, &spr_write_generic,
725 0x00000000);
726 spr_register(env, SPR_SPRG6, "SPRG6",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_generic, &spr_write_generic,
729 0x00000000);
730 spr_register(env, SPR_SPRG7, "SPRG7",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_generic, &spr_write_generic,
733 0x00000000);
734 /* External access control */
735 /* XXX : not implemented */
736 spr_register(env, SPR_EAR, "EAR",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_generic, &spr_write_generic,
739 0x00000000);
740}
741
3fc6c082
FB		 742/* SPR common to all 7xx PowerPC implementations */
743static void gen_spr_7xx (CPUPPCState *env)
744{
745 /* Breakpoints */
746 /* XXX : not implemented */
747 spr_register(env, SPR_DABR, "DABR",
748 SPR_NOACCESS, SPR_NOACCESS,
749 &spr_read_generic, &spr_write_generic,
750 0x00000000);
751 /* XXX : not implemented */
752 spr_register(env, SPR_IABR, "IABR",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_generic, &spr_write_generic,
755 0x00000000);
756 /* Cache management */
757 /* XXX : not implemented */
758 spr_register(env, SPR_ICTC, "ICTC",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_generic, &spr_write_generic,
761 0x00000000);
76a66253
JM		 762 /* XXX : not implemented */
763 spr_register(env, SPR_L2CR, "L2CR",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_generic, &spr_write_generic,
766 0x00000000);
3fc6c082
FB		 767 /* Performance monitors */
768 /* XXX : not implemented */
769 spr_register(env, SPR_MMCR0, "MMCR0",
770 SPR_NOACCESS, SPR_NOACCESS,
771 &spr_read_generic, &spr_write_generic,
772 0x00000000);
773 /* XXX : not implemented */
774 spr_register(env, SPR_MMCR1, "MMCR1",
775 SPR_NOACCESS, SPR_NOACCESS,
776 &spr_read_generic, &spr_write_generic,
777 0x00000000);
778 /* XXX : not implemented */
779 spr_register(env, SPR_PMC1, "PMC1",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_generic, &spr_write_generic,
782 0x00000000);
783 /* XXX : not implemented */
784 spr_register(env, SPR_PMC2, "PMC2",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_generic, &spr_write_generic,
787 0x00000000);
788 /* XXX : not implemented */
789 spr_register(env, SPR_PMC3, "PMC3",
790 SPR_NOACCESS, SPR_NOACCESS,
791 &spr_read_generic, &spr_write_generic,
792 0x00000000);
793 /* XXX : not implemented */
794 spr_register(env, SPR_PMC4, "PMC4",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_generic, &spr_write_generic,
797 0x00000000);
798 /* XXX : not implemented */
799 spr_register(env, SPR_SIA, "SIA",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_generic, SPR_NOACCESS,
802 0x00000000);
803 spr_register(env, SPR_UMMCR0, "UMMCR0",
804 &spr_read_ureg, SPR_NOACCESS,
805 &spr_read_ureg, SPR_NOACCESS,
806 0x00000000);
807 spr_register(env, SPR_UMMCR1, "UMMCR1",
808 &spr_read_ureg, SPR_NOACCESS,
809 &spr_read_ureg, SPR_NOACCESS,
810 0x00000000);
811 spr_register(env, SPR_UPMC1, "UPMC1",
812 &spr_read_ureg, SPR_NOACCESS,
813 &spr_read_ureg, SPR_NOACCESS,
814 0x00000000);
815 spr_register(env, SPR_UPMC2, "UPMC2",
816 &spr_read_ureg, SPR_NOACCESS,
817 &spr_read_ureg, SPR_NOACCESS,
818 0x00000000);
819 spr_register(env, SPR_UPMC3, "UPMC3",
820 &spr_read_ureg, SPR_NOACCESS,
821 &spr_read_ureg, SPR_NOACCESS,
822 0x00000000);
823 spr_register(env, SPR_UPMC4, "UPMC4",
824 &spr_read_ureg, SPR_NOACCESS,
825 &spr_read_ureg, SPR_NOACCESS,
826 0x00000000);
827 spr_register(env, SPR_USIA, "USIA",
828 &spr_read_ureg, SPR_NOACCESS,
829 &spr_read_ureg, SPR_NOACCESS,
830 0x00000000);
831 /* Thermal management */
832 /* XXX : not implemented */
833 spr_register(env, SPR_THRM1, "THRM1",
834 SPR_NOACCESS, SPR_NOACCESS,
835 &spr_read_generic, &spr_write_generic,
836 0x00000000);
837 /* XXX : not implemented */
838 spr_register(env, SPR_THRM2, "THRM2",
839 SPR_NOACCESS, SPR_NOACCESS,
840 &spr_read_generic, &spr_write_generic,
841 0x00000000);
842 /* XXX : not implemented */
843 spr_register(env, SPR_THRM3, "THRM3",
844 SPR_NOACCESS, SPR_NOACCESS,
845 &spr_read_generic, &spr_write_generic,
846 0x00000000);
847 /* External access control */
848 /* XXX : not implemented */
849 spr_register(env, SPR_EAR, "EAR",
850 SPR_NOACCESS, SPR_NOACCESS,
851 &spr_read_generic, &spr_write_generic,
852 0x00000000);
853}
854
855/* SPR specific to PowerPC 604 implementation */
856static void gen_spr_604 (CPUPPCState *env)
857{
858 /* Processor identification */
859 spr_register(env, SPR_PIR, "PIR",
860 SPR_NOACCESS, SPR_NOACCESS,
861 &spr_read_generic, &spr_write_pir,
862 0x00000000);
863 /* Breakpoints */
864 /* XXX : not implemented */
865 spr_register(env, SPR_IABR, "IABR",
866 SPR_NOACCESS, SPR_NOACCESS,
867 &spr_read_generic, &spr_write_generic,
868 0x00000000);
869 /* XXX : not implemented */
870 spr_register(env, SPR_DABR, "DABR",
871 SPR_NOACCESS, SPR_NOACCESS,
872 &spr_read_generic, &spr_write_generic,
873 0x00000000);
874 /* Performance counters */
875 /* XXX : not implemented */
876 spr_register(env, SPR_MMCR0, "MMCR0",
877 SPR_NOACCESS, SPR_NOACCESS,
878 &spr_read_generic, &spr_write_generic,
879 0x00000000);
880 /* XXX : not implemented */
881 spr_register(env, SPR_MMCR1, "MMCR1",
882 SPR_NOACCESS, SPR_NOACCESS,
883 &spr_read_generic, &spr_write_generic,
884 0x00000000);
885 /* XXX : not implemented */
886 spr_register(env, SPR_PMC1, "PMC1",
887 SPR_NOACCESS, SPR_NOACCESS,
888 &spr_read_generic, &spr_write_generic,
889 0x00000000);
890 /* XXX : not implemented */
891 spr_register(env, SPR_PMC2, "PMC2",
892 SPR_NOACCESS, SPR_NOACCESS,
893 &spr_read_generic, &spr_write_generic,
894 0x00000000);
895 /* XXX : not implemented */
896 spr_register(env, SPR_PMC3, "PMC3",
897 SPR_NOACCESS, SPR_NOACCESS,
898 &spr_read_generic, &spr_write_generic,
899 0x00000000);
900 /* XXX : not implemented */
901 spr_register(env, SPR_PMC4, "PMC4",
902 SPR_NOACCESS, SPR_NOACCESS,
903 &spr_read_generic, &spr_write_generic,
904 0x00000000);
905 /* XXX : not implemented */
906 spr_register(env, SPR_SIA, "SIA",
907 SPR_NOACCESS, SPR_NOACCESS,
908 &spr_read_generic, SPR_NOACCESS,
909 0x00000000);
910 /* XXX : not implemented */
911 spr_register(env, SPR_SDA, "SDA",
912 SPR_NOACCESS, SPR_NOACCESS,
913 &spr_read_generic, SPR_NOACCESS,
914 0x00000000);
915 /* External access control */
916 /* XXX : not implemented */
917 spr_register(env, SPR_EAR, "EAR",
918 SPR_NOACCESS, SPR_NOACCESS,
919 &spr_read_generic, &spr_write_generic,
920 0x00000000);
921}
922
76a66253
JM		 923/* SPR specific to PowerPC 603 implementation */
924static void gen_spr_603 (CPUPPCState *env)
3fc6c082 925{
76a66253
JM		 926 /* External access control */
927 /* XXX : not implemented */
928 spr_register(env, SPR_EAR, "EAR",
3fc6c082 929 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 930 &spr_read_generic, &spr_write_generic,
931 0x00000000);
3fc6c082
FB		 932}
933
76a66253
JM		 934/* SPR specific to PowerPC G2 implementation */
935static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 936{
76a66253
JM		 937 /* Memory base address */
938 /* MBAR */
939 spr_register(env, SPR_MBAR, "MBAR",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 /* System version register */
944 /* SVR */
945 spr_register(env, SPR_SVR, "SVR",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, SPR_NOACCESS,
948 0x00000000);
949 /* Exception processing */
363be49c 950 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
363be49c 954 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, &spr_write_generic,
957 0x00000000);
958 /* Breakpoints */
959 /* XXX : not implemented */
960 spr_register(env, SPR_DABR, "DABR",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_generic,
963 0x00000000);
964 /* XXX : not implemented */
965 spr_register(env, SPR_DABR2, "DABR2",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969 /* XXX : not implemented */
970 spr_register(env, SPR_IABR, "IABR",
971 SPR_NOACCESS, SPR_NOACCESS,
972 &spr_read_generic, &spr_write_generic,
973 0x00000000);
974 /* XXX : not implemented */
975 spr_register(env, SPR_IABR2, "IABR2",
976 SPR_NOACCESS, SPR_NOACCESS,
977 &spr_read_generic, &spr_write_generic,
978 0x00000000);
979 /* XXX : not implemented */
980 spr_register(env, SPR_IBCR, "IBCR",
981 SPR_NOACCESS, SPR_NOACCESS,
982 &spr_read_generic, &spr_write_generic,
983 0x00000000);
984 /* XXX : not implemented */
985 spr_register(env, SPR_DBCR, "DBCR",
986 SPR_NOACCESS, SPR_NOACCESS,
987 &spr_read_generic, &spr_write_generic,
988 0x00000000);
989}
990
991/* SPR specific to PowerPC 602 implementation */
992static void gen_spr_602 (CPUPPCState *env)
993{
994 /* ESA registers */
995 /* XXX : not implemented */
996 spr_register(env, SPR_SER, "SER",
997 SPR_NOACCESS, SPR_NOACCESS,
998 &spr_read_generic, &spr_write_generic,
999 0x00000000);
1000 /* XXX : not implemented */
1001 spr_register(env, SPR_SEBR, "SEBR",
1002 SPR_NOACCESS, SPR_NOACCESS,
1003 &spr_read_generic, &spr_write_generic,
1004 0x00000000);
1005 /* XXX : not implemented */
1006 spr_register(env, SPR_ESASR, "ESASR",
1007 SPR_NOACCESS, SPR_NOACCESS,
1008 &spr_read_generic, &spr_write_generic,
1009 0x00000000);
1010 /* Floating point status */
1011 /* XXX : not implemented */
1012 spr_register(env, SPR_SP, "SP",
1013 SPR_NOACCESS, SPR_NOACCESS,
1014 &spr_read_generic, &spr_write_generic,
1015 0x00000000);
1016 /* XXX : not implemented */
1017 spr_register(env, SPR_LT, "LT",
1018 SPR_NOACCESS, SPR_NOACCESS,
1019 &spr_read_generic, &spr_write_generic,
1020 0x00000000);
1021 /* Watchdog timer */
1022 /* XXX : not implemented */
1023 spr_register(env, SPR_TCR, "TCR",
1024 SPR_NOACCESS, SPR_NOACCESS,
1025 &spr_read_generic, &spr_write_generic,
1026 0x00000000);
1027 /* Interrupt base */
1028 spr_register(env, SPR_IBR, "IBR",
1029 SPR_NOACCESS, SPR_NOACCESS,
1030 &spr_read_generic, &spr_write_generic,
1031 0x00000000);
1032}
1033
1034/* SPR specific to PowerPC 601 implementation */
1035static void gen_spr_601 (CPUPPCState *env)
1036{
1037 /* Multiplication/division register */
1038 /* MQ */
1039 spr_register(env, SPR_MQ, "MQ",
1040 &spr_read_generic, &spr_write_generic,
1041 &spr_read_generic, &spr_write_generic,
1042 0x00000000);
1043 /* RTC registers */
1044 spr_register(env, SPR_601_RTCU, "RTCU",
1045 SPR_NOACCESS, SPR_NOACCESS,
1046 SPR_NOACCESS, &spr_write_601_rtcu,
1047 0x00000000);
1048 spr_register(env, SPR_601_VRTCU, "RTCU",
1049 &spr_read_601_rtcu, SPR_NOACCESS,
1050 &spr_read_601_rtcu, SPR_NOACCESS,
1051 0x00000000);
1052 spr_register(env, SPR_601_RTCL, "RTCL",
1053 SPR_NOACCESS, SPR_NOACCESS,
1054 SPR_NOACCESS, &spr_write_601_rtcl,
1055 0x00000000);
1056 spr_register(env, SPR_601_VRTCL, "RTCL",
1057 &spr_read_601_rtcl, SPR_NOACCESS,
1058 &spr_read_601_rtcl, SPR_NOACCESS,
1059 0x00000000);
1060 /* Timer */
1061#if 0 /* ? */
1062 spr_register(env, SPR_601_UDECR, "UDECR",
1063 &spr_read_decr, SPR_NOACCESS,
1064 &spr_read_decr, SPR_NOACCESS,
1065 0x00000000);
1066#endif
1067 /* External access control */
1068 /* XXX : not implemented */
1069 spr_register(env, SPR_EAR, "EAR",
1070 SPR_NOACCESS, SPR_NOACCESS,
1071 &spr_read_generic, &spr_write_generic,
1072 0x00000000);
1073 /* Memory management */
1074 spr_register(env, SPR_IBAT0U, "IBAT0U",
1075 SPR_NOACCESS, SPR_NOACCESS,
1076 &spr_read_601_ubat, &spr_write_601_ubatu,
1077 0x00000000);
1078 spr_register(env, SPR_IBAT0L, "IBAT0L",
1079 SPR_NOACCESS, SPR_NOACCESS,
1080 &spr_read_601_ubat, &spr_write_601_ubatl,
1081 0x00000000);
1082 spr_register(env, SPR_IBAT1U, "IBAT1U",
1083 SPR_NOACCESS, SPR_NOACCESS,
1084 &spr_read_601_ubat, &spr_write_601_ubatu,
1085 0x00000000);
1086 spr_register(env, SPR_IBAT1L, "IBAT1L",
1087 SPR_NOACCESS, SPR_NOACCESS,
1088 &spr_read_601_ubat, &spr_write_601_ubatl,
1089 0x00000000);
1090 spr_register(env, SPR_IBAT2U, "IBAT2U",
1091 SPR_NOACCESS, SPR_NOACCESS,
1092 &spr_read_601_ubat, &spr_write_601_ubatu,
1093 0x00000000);
1094 spr_register(env, SPR_IBAT2L, "IBAT2L",
1095 SPR_NOACCESS, SPR_NOACCESS,
1096 &spr_read_601_ubat, &spr_write_601_ubatl,
1097 0x00000000);
1098 spr_register(env, SPR_IBAT3U, "IBAT3U",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 &spr_read_601_ubat, &spr_write_601_ubatu,
1101 0x00000000);
1102 spr_register(env, SPR_IBAT3L, "IBAT3L",
1103 SPR_NOACCESS, SPR_NOACCESS,
1104 &spr_read_601_ubat, &spr_write_601_ubatl,
1105 0x00000000);
1106}
1107
1108/* PowerPC BookE SPR */
1109static void gen_spr_BookE (CPUPPCState *env)
1110{
1111 /* Processor identification */
1112 spr_register(env, SPR_BOOKE_PIR, "PIR",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_generic, &spr_write_pir,
1115 0x00000000);
1116 /* Interrupt processing */
363be49c 1117 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1118 SPR_NOACCESS, SPR_NOACCESS,
1119 &spr_read_generic, &spr_write_generic,
1120 0x00000000);
363be49c
JM		 1121 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1122 SPR_NOACCESS, SPR_NOACCESS,
1123 &spr_read_generic, &spr_write_generic,
1124 0x00000000);
1125 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1126 SPR_NOACCESS, SPR_NOACCESS,
1127 &spr_read_generic, &spr_write_generic,
1128 0x00000000);
1129 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1130 SPR_NOACCESS, SPR_NOACCESS,
1131 &spr_read_generic, &spr_write_generic,
1132 0x00000000);
1133 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
1134 SPR_NOACCESS, SPR_NOACCESS,
1135 &spr_read_generic, &spr_write_generic,
1136 0x00000000);
1137 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
76a66253
JM		 1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_generic, &spr_write_generic,
1140 0x00000000);
1141 /* Debug */
1142 /* XXX : not implemented */
1143 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1144 SPR_NOACCESS, SPR_NOACCESS,
1145 &spr_read_generic, &spr_write_generic,
1146 0x00000000);
1147 /* XXX : not implemented */
1148 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1149 SPR_NOACCESS, SPR_NOACCESS,
1150 &spr_read_generic, &spr_write_generic,
1151 0x00000000);
1152 /* XXX : not implemented */
1153 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1154 SPR_NOACCESS, SPR_NOACCESS,
1155 &spr_read_generic, &spr_write_generic,
1156 0x00000000);
1157 /* XXX : not implemented */
1158 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1159 SPR_NOACCESS, SPR_NOACCESS,
1160 &spr_read_generic, &spr_write_generic,
1161 0x00000000);
1162 /* XXX : not implemented */
1163 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167 /* XXX : not implemented */
1168 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1169 SPR_NOACCESS, SPR_NOACCESS,
1170 &spr_read_generic, &spr_write_generic,
1171 0x00000000);
1172 /* XXX : not implemented */
1173 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1174 SPR_NOACCESS, SPR_NOACCESS,
1175 &spr_read_generic, &spr_write_generic,
1176 0x00000000);
1177 /* XXX : not implemented */
1178 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1179 SPR_NOACCESS, SPR_NOACCESS,
1180 &spr_read_generic, &spr_write_generic,
1181 0x00000000);
1182 /* XXX : not implemented */
1183 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1184 SPR_NOACCESS, SPR_NOACCESS,
1185 &spr_read_generic, &spr_write_generic,
1186 0x00000000);
1187 /* XXX : not implemented */
1188 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1189 SPR_NOACCESS, SPR_NOACCESS,
1190 &spr_read_generic, &spr_write_generic,
1191 0x00000000);
1192 /* XXX : not implemented */
1193 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1194 SPR_NOACCESS, SPR_NOACCESS,
1195 &spr_read_generic, &spr_write_generic,
1196 0x00000000);
1197 /* XXX : not implemented */
1198 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1199 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1200 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1201 0x00000000);
1202 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1203 SPR_NOACCESS, SPR_NOACCESS,
1204 &spr_read_generic, &spr_write_generic,
1205 0x00000000);
1206 spr_register(env, SPR_BOOKE_ESR, "ESR",
1207 SPR_NOACCESS, SPR_NOACCESS,
1208 &spr_read_generic, &spr_write_generic,
1209 0x00000000);
363be49c
JM		 1210 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1211 SPR_NOACCESS, SPR_NOACCESS,
1212 &spr_read_generic, &spr_write_generic,
1213 0x00000000);
1214 /* Exception vectors */
76a66253
JM		 1215 spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1216 SPR_NOACCESS, SPR_NOACCESS,
1217 &spr_read_generic, &spr_write_generic,
1218 0x00000000);
1219 spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1220 SPR_NOACCESS, SPR_NOACCESS,
1221 &spr_read_generic, &spr_write_generic,
1222 0x00000000);
1223 spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1224 SPR_NOACCESS, SPR_NOACCESS,
1225 &spr_read_generic, &spr_write_generic,
1226 0x00000000);
1227 spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1228 SPR_NOACCESS, SPR_NOACCESS,
1229 &spr_read_generic, &spr_write_generic,
1230 0x00000000);
1231 spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1232 SPR_NOACCESS, SPR_NOACCESS,
1233 &spr_read_generic, &spr_write_generic,
1234 0x00000000);
1235 spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1236 SPR_NOACCESS, SPR_NOACCESS,
1237 &spr_read_generic, &spr_write_generic,
1238 0x00000000);
1239 spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1240 SPR_NOACCESS, SPR_NOACCESS,
1241 &spr_read_generic, &spr_write_generic,
1242 0x00000000);
1243 spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1244 SPR_NOACCESS, SPR_NOACCESS,
1245 &spr_read_generic, &spr_write_generic,
1246 0x00000000);
1247 spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1248 SPR_NOACCESS, SPR_NOACCESS,
1249 &spr_read_generic, &spr_write_generic,
1250 0x00000000);
1251 spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1252 SPR_NOACCESS, SPR_NOACCESS,
1253 &spr_read_generic, &spr_write_generic,
1254 0x00000000);
1255 spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1256 SPR_NOACCESS, SPR_NOACCESS,
1257 &spr_read_generic, &spr_write_generic,
1258 0x00000000);
1259 spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1260 SPR_NOACCESS, SPR_NOACCESS,
1261 &spr_read_generic, &spr_write_generic,
1262 0x00000000);
1263 spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1264 SPR_NOACCESS, SPR_NOACCESS,
1265 &spr_read_generic, &spr_write_generic,
1266 0x00000000);
1267 spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1268 SPR_NOACCESS, SPR_NOACCESS,
1269 &spr_read_generic, &spr_write_generic,
1270 0x00000000);
1271 spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1272 SPR_NOACCESS, SPR_NOACCESS,
1273 &spr_read_generic, &spr_write_generic,
1274 0x00000000);
1275 spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1276 SPR_NOACCESS, SPR_NOACCESS,
1277 &spr_read_generic, &spr_write_generic,
1278 0x00000000);
363be49c
JM		 1279 spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 &spr_read_generic, &spr_write_generic,
1282 0x00000000);
1283 spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1284 SPR_NOACCESS, SPR_NOACCESS,
1285 &spr_read_generic, &spr_write_generic,
1286 0x00000000);
1287 spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1288 SPR_NOACCESS, SPR_NOACCESS,
1289 &spr_read_generic, &spr_write_generic,
1290 0x00000000);
1291 spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1292 SPR_NOACCESS, SPR_NOACCESS,
1293 &spr_read_generic, &spr_write_generic,
1294 0x00000000);
1295 spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_generic,
1298 0x00000000);
1299 spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_generic, &spr_write_generic,
1302 0x00000000);
76a66253
JM		 1303 spr_register(env, SPR_BOOKE_PID, "PID",
1304 SPR_NOACCESS, SPR_NOACCESS,
1305 &spr_read_generic, &spr_write_generic,
1306 0x00000000);
1307 spr_register(env, SPR_BOOKE_TCR, "TCR",
1308 SPR_NOACCESS, SPR_NOACCESS,
1309 &spr_read_generic, &spr_write_booke_tcr,
1310 0x00000000);
1311 spr_register(env, SPR_BOOKE_TSR, "TSR",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_generic, &spr_write_booke_tsr,
1314 0x00000000);
1315 /* Timer */
1316 spr_register(env, SPR_DECR, "DECR",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_decr, &spr_write_decr,
1319 0x00000000);
1320 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1321 SPR_NOACCESS, SPR_NOACCESS,
1322 SPR_NOACCESS, &spr_write_generic,
1323 0x00000000);
1324 /* SPRGs */
1325 spr_register(env, SPR_USPRG0, "USPRG0",
1326 &spr_read_generic, &spr_write_generic,
1327 &spr_read_generic, &spr_write_generic,
1328 0x00000000);
1329 spr_register(env, SPR_SPRG4, "SPRG4",
1330 SPR_NOACCESS, SPR_NOACCESS,
1331 &spr_read_generic, &spr_write_generic,
1332 0x00000000);
1333 spr_register(env, SPR_USPRG4, "USPRG4",
1334 &spr_read_ureg, SPR_NOACCESS,
1335 &spr_read_ureg, SPR_NOACCESS,
1336 0x00000000);
1337 spr_register(env, SPR_SPRG5, "SPRG5",
1338 SPR_NOACCESS, SPR_NOACCESS,
1339 &spr_read_generic, &spr_write_generic,
1340 0x00000000);
1341 spr_register(env, SPR_USPRG5, "USPRG5",
1342 &spr_read_ureg, SPR_NOACCESS,
1343 &spr_read_ureg, SPR_NOACCESS,
1344 0x00000000);
1345 spr_register(env, SPR_SPRG6, "SPRG6",
1346 SPR_NOACCESS, SPR_NOACCESS,
1347 &spr_read_generic, &spr_write_generic,
1348 0x00000000);
1349 spr_register(env, SPR_USPRG6, "USPRG6",
1350 &spr_read_ureg, SPR_NOACCESS,
1351 &spr_read_ureg, SPR_NOACCESS,
1352 0x00000000);
1353 spr_register(env, SPR_SPRG7, "SPRG7",
1354 SPR_NOACCESS, SPR_NOACCESS,
1355 &spr_read_generic, &spr_write_generic,
1356 0x00000000);
1357 spr_register(env, SPR_USPRG7, "USPRG7",
1358 &spr_read_ureg, SPR_NOACCESS,
1359 &spr_read_ureg, SPR_NOACCESS,
1360 0x00000000);
1361}
1362
363be49c
JM		 1363/* FSL storage control registers */
1364static void gen_spr_BookE_FSL (CPUPPCState *env)
1365{
1366 /* TLB assist registers */
1367 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1368 SPR_NOACCESS, SPR_NOACCESS,
1369 &spr_read_generic, &spr_write_generic,
1370 0x00000000);
1371 spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1372 SPR_NOACCESS, SPR_NOACCESS,
1373 &spr_read_generic, &spr_write_generic,
1374 0x00000000);
1375 spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1376 SPR_NOACCESS, SPR_NOACCESS,
1377 &spr_read_generic, &spr_write_generic,
1378 0x00000000);
1379 spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1380 SPR_NOACCESS, SPR_NOACCESS,
1381 &spr_read_generic, &spr_write_generic,
1382 0x00000000);
1383 spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1384 SPR_NOACCESS, SPR_NOACCESS,
1385 &spr_read_generic, &spr_write_generic,
1386 0x00000000);
1387 spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1388 SPR_NOACCESS, SPR_NOACCESS,
1389 &spr_read_generic, &spr_write_generic,
1390 0x00000000);
1391 spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1392 SPR_NOACCESS, SPR_NOACCESS,
1393 &spr_read_generic, &spr_write_generic,
1394 0x00000000);
1395 if (env->nb_pids > 1) {
1396 spr_register(env, SPR_BOOKE_PID1, "PID1",
1397 SPR_NOACCESS, SPR_NOACCESS,
1398 &spr_read_generic, &spr_write_generic,
1399 0x00000000);
1400 }
1401 if (env->nb_pids > 2) {
1402 spr_register(env, SPR_BOOKE_PID2, "PID2",
1403 SPR_NOACCESS, SPR_NOACCESS,
1404 &spr_read_generic, &spr_write_generic,
1405 0x00000000);
1406 }
1407 spr_register(env, SPR_BOOKE_MMUCFG, "MMUCFG",
1408 SPR_NOACCESS, SPR_NOACCESS,
1409 &spr_read_generic, SPR_NOACCESS,
1410 0x00000000); /* TOFIX */
1411 spr_register(env, SPR_BOOKE_MMUCSR0, "MMUCSR0",
1412 SPR_NOACCESS, SPR_NOACCESS,
1413 &spr_read_generic, &spr_write_generic,
1414 0x00000000); /* TOFIX */
1415 switch (env->nb_ways) {
1416 case 4:
1417 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1418 SPR_NOACCESS, SPR_NOACCESS,
1419 &spr_read_generic, SPR_NOACCESS,
1420 0x00000000); /* TOFIX */
1421 /* Fallthru */
1422 case 3:
1423 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1424 SPR_NOACCESS, SPR_NOACCESS,
1425 &spr_read_generic, SPR_NOACCESS,
1426 0x00000000); /* TOFIX */
1427 /* Fallthru */
1428 case 2:
1429 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1430 SPR_NOACCESS, SPR_NOACCESS,
1431 &spr_read_generic, SPR_NOACCESS,
1432 0x00000000); /* TOFIX */
1433 /* Fallthru */
1434 case 1:
1435 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1436 SPR_NOACCESS, SPR_NOACCESS,
1437 &spr_read_generic, SPR_NOACCESS,
1438 0x00000000); /* TOFIX */
1439 /* Fallthru */
1440 case 0:
1441 default:
1442 break;
1443 }
1444}
1445
76a66253
JM		 1446/* SPR specific to PowerPC 440 implementation */
1447static void gen_spr_440 (CPUPPCState *env)
1448{
1449 /* Cache control */
1450 /* XXX : not implemented */
1451 spr_register(env, SPR_440_DNV0, "DNV0",
1452 SPR_NOACCESS, SPR_NOACCESS,
1453 &spr_read_generic, &spr_write_generic,
1454 0x00000000);
1455 /* XXX : not implemented */
1456 spr_register(env, SPR_440_DNV1, "DNV1",
1457 SPR_NOACCESS, SPR_NOACCESS,
1458 &spr_read_generic, &spr_write_generic,
1459 0x00000000);
1460 /* XXX : not implemented */
1461 spr_register(env, SPR_440_DNV2, "DNV2",
1462 SPR_NOACCESS, SPR_NOACCESS,
1463 &spr_read_generic, &spr_write_generic,
1464 0x00000000);
1465 /* XXX : not implemented */
1466 spr_register(env, SPR_440_DNV3, "DNV3",
1467 SPR_NOACCESS, SPR_NOACCESS,
1468 &spr_read_generic, &spr_write_generic,
1469 0x00000000);
1470 /* XXX : not implemented */
1471 spr_register(env, SPR_440_DVT0, "DVT0",
1472 SPR_NOACCESS, SPR_NOACCESS,
1473 &spr_read_generic, &spr_write_generic,
1474 0x00000000);
1475 /* XXX : not implemented */
1476 spr_register(env, SPR_440_DVT1, "DVT1",
1477 SPR_NOACCESS, SPR_NOACCESS,
1478 &spr_read_generic, &spr_write_generic,
1479 0x00000000);
1480 /* XXX : not implemented */
1481 spr_register(env, SPR_440_DVT2, "DVT2",
1482 SPR_NOACCESS, SPR_NOACCESS,
1483 &spr_read_generic, &spr_write_generic,
1484 0x00000000);
1485 /* XXX : not implemented */
1486 spr_register(env, SPR_440_DVT3, "DVT3",
1487 SPR_NOACCESS, SPR_NOACCESS,
1488 &spr_read_generic, &spr_write_generic,
1489 0x00000000);
1490 /* XXX : not implemented */
1491 spr_register(env, SPR_440_DVLIM, "DVLIM",
1492 SPR_NOACCESS, SPR_NOACCESS,
1493 &spr_read_generic, &spr_write_generic,
1494 0x00000000);
1495 /* XXX : not implemented */
1496 spr_register(env, SPR_440_INV0, "INV0",
1497 SPR_NOACCESS, SPR_NOACCESS,
1498 &spr_read_generic, &spr_write_generic,
1499 0x00000000);
1500 /* XXX : not implemented */
1501 spr_register(env, SPR_440_INV1, "INV1",
1502 SPR_NOACCESS, SPR_NOACCESS,
1503 &spr_read_generic, &spr_write_generic,
1504 0x00000000);
1505 /* XXX : not implemented */
1506 spr_register(env, SPR_440_INV2, "INV2",
1507 SPR_NOACCESS, SPR_NOACCESS,
1508 &spr_read_generic, &spr_write_generic,
1509 0x00000000);
1510 /* XXX : not implemented */
1511 spr_register(env, SPR_440_INV3, "INV3",
1512 SPR_NOACCESS, SPR_NOACCESS,
1513 &spr_read_generic, &spr_write_generic,
1514 0x00000000);
1515 /* XXX : not implemented */
1516 spr_register(env, SPR_440_IVT0, "IVT0",
1517 SPR_NOACCESS, SPR_NOACCESS,
1518 &spr_read_generic, &spr_write_generic,
1519 0x00000000);
1520 /* XXX : not implemented */
1521 spr_register(env, SPR_440_IVT1, "IVT1",
1522 SPR_NOACCESS, SPR_NOACCESS,
1523 &spr_read_generic, &spr_write_generic,
1524 0x00000000);
1525 /* XXX : not implemented */
1526 spr_register(env, SPR_440_IVT2, "IVT2",
1527 SPR_NOACCESS, SPR_NOACCESS,
1528 &spr_read_generic, &spr_write_generic,
1529 0x00000000);
1530 /* XXX : not implemented */
1531 spr_register(env, SPR_440_IVT3, "IVT3",
1532 SPR_NOACCESS, SPR_NOACCESS,
1533 &spr_read_generic, &spr_write_generic,
1534 0x00000000);
1535 /* XXX : not implemented */
1536 spr_register(env, SPR_440_IVLIM, "IVLIM",
1537 SPR_NOACCESS, SPR_NOACCESS,
1538 &spr_read_generic, &spr_write_generic,
1539 0x00000000);
1540 /* Cache debug */
1541 /* XXX : not implemented */
363be49c 1542 spr_register(env, SPR_BOOKE_DCBTRH, "DCBTRH",
76a66253
JM		 1543 SPR_NOACCESS, SPR_NOACCESS,
1544 &spr_read_generic, SPR_NOACCESS,
1545 0x00000000);
1546 /* XXX : not implemented */
363be49c 1547 spr_register(env, SPR_BOOKE_DCBTRL, "DCBTRL",
76a66253
JM		 1548 SPR_NOACCESS, SPR_NOACCESS,
1549 &spr_read_generic, SPR_NOACCESS,
1550 0x00000000);
1551 /* XXX : not implemented */
363be49c 1552 spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
76a66253
JM		 1553 SPR_NOACCESS, SPR_NOACCESS,
1554 &spr_read_generic, SPR_NOACCESS,
1555 0x00000000);
1556 /* XXX : not implemented */
363be49c 1557 spr_register(env, SPR_BOOKE_ICBTRH, "ICBTRH",
76a66253
JM		 1558 SPR_NOACCESS, SPR_NOACCESS,
1559 &spr_read_generic, SPR_NOACCESS,
1560 0x00000000);
1561 /* XXX : not implemented */
363be49c 1562 spr_register(env, SPR_BOOKE_ICBTRL, "ICBTRL",
76a66253
JM		 1563 SPR_NOACCESS, SPR_NOACCESS,
1564 &spr_read_generic, SPR_NOACCESS,
1565 0x00000000);
1566 /* XXX : not implemented */
1567 spr_register(env, SPR_440_DBDR, "DBDR",
1568 SPR_NOACCESS, SPR_NOACCESS,
1569 &spr_read_generic, &spr_write_generic,
1570 0x00000000);
1571 /* Processor control */
1572 spr_register(env, SPR_4xx_CCR0, "CCR0",
1573 SPR_NOACCESS, SPR_NOACCESS,
1574 &spr_read_generic, &spr_write_generic,
1575 0x00000000);
1576 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1577 SPR_NOACCESS, SPR_NOACCESS,
1578 &spr_read_generic, SPR_NOACCESS,
1579 0x00000000);
1580 /* Storage control */
1581 spr_register(env, SPR_440_MMUCR, "MMUCR",
1582 SPR_NOACCESS, SPR_NOACCESS,
1583 &spr_read_generic, &spr_write_generic,
1584 0x00000000);
1585}
1586
1587/* SPR shared between PowerPC 40x implementations */
1588static void gen_spr_40x (CPUPPCState *env)
1589{
1590 /* Cache */
1591 /* XXX : not implemented */
1592 spr_register(env, SPR_40x_DCCR, "DCCR",
1593 SPR_NOACCESS, SPR_NOACCESS,
1594 &spr_read_generic, &spr_write_generic,
1595 0x00000000);
1596 /* XXX : not implemented */
1597 spr_register(env, SPR_40x_DCWR, "DCWR",
1598 SPR_NOACCESS, SPR_NOACCESS,
1599 &spr_read_generic, &spr_write_generic,
1600 0x00000000);
1601 /* XXX : not implemented */
1602 spr_register(env, SPR_40x_ICCR, "ICCR",
1603 SPR_NOACCESS, SPR_NOACCESS,
1604 &spr_read_generic, &spr_write_generic,
1605 0x00000000);
1606 /* XXX : not implemented */
363be49c 1607 spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
76a66253
JM		 1608 SPR_NOACCESS, SPR_NOACCESS,
1609 &spr_read_generic, SPR_NOACCESS,
1610 0x00000000);
1611 /* Bus access control */
1612 spr_register(env, SPR_40x_SGR, "SGR",
1613 SPR_NOACCESS, SPR_NOACCESS,
1614 &spr_read_generic, &spr_write_generic,
1615 0xFFFFFFFF);
1616 spr_register(env, SPR_40x_ZPR, "ZPR",
1617 SPR_NOACCESS, SPR_NOACCESS,
1618 &spr_read_generic, &spr_write_generic,
1619 0x00000000);
1620 /* MMU */
1621 spr_register(env, SPR_40x_PID, "PID",
1622 SPR_NOACCESS, SPR_NOACCESS,
1623 &spr_read_generic, &spr_write_generic,
1624 0x00000000);
1625 /* Exception */
1626 spr_register(env, SPR_40x_DEAR, "DEAR",
1627 SPR_NOACCESS, SPR_NOACCESS,
1628 &spr_read_generic, &spr_write_generic,
1629 0x00000000);
1630 spr_register(env, SPR_40x_ESR, "ESR",
1631 SPR_NOACCESS, SPR_NOACCESS,
1632 &spr_read_generic, &spr_write_generic,
1633 0x00000000);
1634 spr_register(env, SPR_40x_EVPR, "EVPR",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, &spr_write_generic,
1637 0x00000000);
1638 spr_register(env, SPR_40x_SRR2, "SRR2",
1639 &spr_read_generic, &spr_write_generic,
1640 &spr_read_generic, &spr_write_generic,
1641 0x00000000);
1642 spr_register(env, SPR_40x_SRR3, "SRR3",
1643 &spr_read_generic, &spr_write_generic,
1644 &spr_read_generic, &spr_write_generic,
1645 0x00000000);
1646 /* Timers */
1647 spr_register(env, SPR_40x_PIT, "PIT",
1648 SPR_NOACCESS, SPR_NOACCESS,
1649 &spr_read_40x_pit, &spr_write_40x_pit,
1650 0x00000000);
1651 spr_register(env, SPR_40x_TCR, "TCR",
1652 SPR_NOACCESS, SPR_NOACCESS,
1653 &spr_read_generic, &spr_write_booke_tcr,
1654 0x00000000);
1655 spr_register(env, SPR_40x_TSR, "TSR",
1656 SPR_NOACCESS, SPR_NOACCESS,
1657 &spr_read_generic, &spr_write_booke_tsr,
1658 0x00000000);
1659 /* Debug interface */
1660 /* XXX : not implemented */
1661 spr_register(env, SPR_40x_DAC1, "DAC1",
1662 SPR_NOACCESS, SPR_NOACCESS,
1663 &spr_read_generic, &spr_write_generic,
1664 0x00000000);
1665 spr_register(env, SPR_40x_DAC2, "DAC2",
1666 SPR_NOACCESS, SPR_NOACCESS,
1667 &spr_read_generic, &spr_write_generic,
1668 0x00000000);
1669 /* XXX : not implemented */
1670 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1671 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1672 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1673 0x00000000);
1674 /* XXX : not implemented */
1675 spr_register(env, SPR_40x_DBSR, "DBSR",
1676 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1677 &spr_read_generic, &spr_write_clear,
1678 /* Last reset was system reset */
76a66253
JM		 1679 0x00000300);
1680 /* XXX : not implemented */
1681 spr_register(env, SPR_40x_IAC1, "IAC1",
1682 SPR_NOACCESS, SPR_NOACCESS,
1683 &spr_read_generic, &spr_write_generic,
1684 0x00000000);
1685 spr_register(env, SPR_40x_IAC2, "IAC2",
1686 SPR_NOACCESS, SPR_NOACCESS,
1687 &spr_read_generic, &spr_write_generic,
1688 0x00000000);
1689}
1690
1691/* SPR specific to PowerPC 405 implementation */
1692static void gen_spr_405 (CPUPPCState *env)
1693{
1694 spr_register(env, SPR_4xx_CCR0, "CCR0",
1695 SPR_NOACCESS, SPR_NOACCESS,
1696 &spr_read_generic, &spr_write_generic,
1697 0x00700000);
1698 /* Debug */
1699 /* XXX : not implemented */
1700 spr_register(env, SPR_405_DBCR1, "DBCR1",
1701 SPR_NOACCESS, SPR_NOACCESS,
1702 &spr_read_generic, &spr_write_generic,
1703 0x00000000);
1704 /* XXX : not implemented */
1705 spr_register(env, SPR_405_DVC1, "DVC1",
1706 SPR_NOACCESS, SPR_NOACCESS,
1707 &spr_read_generic, &spr_write_generic,
1708 0x00000000);
1709 /* XXX : not implemented */
1710 spr_register(env, SPR_405_DVC2, "DVC2",
1711 SPR_NOACCESS, SPR_NOACCESS,
1712 &spr_read_generic, &spr_write_generic,
1713 0x00000000);
1714 /* XXX : not implemented */
1715 spr_register(env, SPR_405_IAC3, "IAC3",
1716 SPR_NOACCESS, SPR_NOACCESS,
1717 &spr_read_generic, &spr_write_generic,
1718 0x00000000);
1719 /* XXX : not implemented */
1720 spr_register(env, SPR_405_IAC4, "IAC4",
1721 SPR_NOACCESS, SPR_NOACCESS,
1722 &spr_read_generic, &spr_write_generic,
1723 0x00000000);
1724 /* Storage control */
76a66253
JM		 1725 spr_register(env, SPR_405_SLER, "SLER",
1726 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1727 &spr_read_generic, &spr_write_40x_sler,
76a66253
JM		 1728 0x00000000);
1729 /* XXX : not implemented */
1730 spr_register(env, SPR_405_SU0R, "SU0R",
1731 SPR_NOACCESS, SPR_NOACCESS,
1732 &spr_read_generic, &spr_write_generic,
1733 0x00000000);
1734 /* SPRG */
1735 spr_register(env, SPR_USPRG0, "USPRG0",
1736 &spr_read_ureg, SPR_NOACCESS,
1737 &spr_read_ureg, SPR_NOACCESS,
1738 0x00000000);
1739 spr_register(env, SPR_SPRG4, "SPRG4",
1740 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1741 &spr_read_generic, &spr_write_generic,
76a66253
JM		 1742 0x00000000);
1743 spr_register(env, SPR_USPRG4, "USPRG4",
1744 &spr_read_ureg, SPR_NOACCESS,
1745 &spr_read_ureg, SPR_NOACCESS,
1746 0x00000000);
1747 spr_register(env, SPR_SPRG5, "SPRG5",
1748 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1749 spr_read_generic, &spr_write_generic,
76a66253
JM		 1750 0x00000000);
1751 spr_register(env, SPR_USPRG5, "USPRG5",
1752 &spr_read_ureg, SPR_NOACCESS,
1753 &spr_read_ureg, SPR_NOACCESS,
1754 0x00000000);
1755 spr_register(env, SPR_SPRG6, "SPRG6",
1756 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1757 spr_read_generic, &spr_write_generic,
76a66253
JM		 1758 0x00000000);
1759 spr_register(env, SPR_USPRG6, "USPRG6",
1760 &spr_read_ureg, SPR_NOACCESS,
1761 &spr_read_ureg, SPR_NOACCESS,
1762 0x00000000);
1763 spr_register(env, SPR_SPRG7, "SPRG7",
1764 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1765 spr_read_generic, &spr_write_generic,
76a66253
JM		 1766 0x00000000);
1767 spr_register(env, SPR_USPRG7, "USPRG7",
1768 &spr_read_ureg, SPR_NOACCESS,
1769 &spr_read_ureg, SPR_NOACCESS,
1770 0x00000000);
76a66253
JM		 1771}
1772
1773/* SPR shared between PowerPC 401 & 403 implementations */
1774static void gen_spr_401_403 (CPUPPCState *env)
1775{
1776 /* Time base */
1777 spr_register(env, SPR_403_VTBL, "TBL",
1778 &spr_read_tbl, SPR_NOACCESS,
1779 &spr_read_tbl, SPR_NOACCESS,
1780 0x00000000);
1781 spr_register(env, SPR_403_TBL, "TBL",
1782 SPR_NOACCESS, SPR_NOACCESS,
1783 SPR_NOACCESS, &spr_write_tbl,
1784 0x00000000);
1785 spr_register(env, SPR_403_VTBU, "TBU",
1786 &spr_read_tbu, SPR_NOACCESS,
1787 &spr_read_tbu, SPR_NOACCESS,
1788 0x00000000);
1789 spr_register(env, SPR_403_TBU, "TBU",
1790 SPR_NOACCESS, SPR_NOACCESS,
1791 SPR_NOACCESS, &spr_write_tbu,
1792 0x00000000);
1793 /* Debug */
1794 /* XXX: not implemented */
1795 spr_register(env, SPR_403_CDBCR, "CDBCR",
1796 SPR_NOACCESS, SPR_NOACCESS,
1797 &spr_read_generic, &spr_write_generic,
1798 0x00000000);
1799}
1800
1801/* SPR specific to PowerPC 403 implementation */
1802static void gen_spr_403 (CPUPPCState *env)
1803{
1804 /* MMU */
1805 spr_register(env, SPR_403_PBL1, "PBL1",
1806 SPR_NOACCESS, SPR_NOACCESS,
1807 &spr_read_403_pbr, &spr_write_403_pbr,
1808 0x00000000);
1809 spr_register(env, SPR_403_PBU1, "PBU1",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_403_pbr, &spr_write_403_pbr,
1812 0x00000000);
1813 spr_register(env, SPR_403_PBL2, "PBL2",
1814 SPR_NOACCESS, SPR_NOACCESS,
1815 &spr_read_403_pbr, &spr_write_403_pbr,
1816 0x00000000);
1817 spr_register(env, SPR_403_PBU2, "PBU2",
1818 SPR_NOACCESS, SPR_NOACCESS,
1819 &spr_read_403_pbr, &spr_write_403_pbr,
1820 0x00000000);
1821 /* Debug */
1822 /* XXX : not implemented */
1823 spr_register(env, SPR_40x_DAC2, "DAC2",
1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, &spr_write_generic,
1826 0x00000000);
1827 /* XXX : not implemented */
1828 spr_register(env, SPR_40x_IAC2, "IAC2",
1829 SPR_NOACCESS, SPR_NOACCESS,
1830 &spr_read_generic, &spr_write_generic,
1831 0x00000000);
1832}
1833
1834/* SPR specific to PowerPC compression coprocessor extension */
1835#if defined (TODO)
1836static void gen_spr_compress (CPUPPCState *env)
1837{
1838 spr_register(env, SPR_401_SKR, "SKR",
1839 SPR_NOACCESS, SPR_NOACCESS,
1840 &spr_read_generic, &spr_write_generic,
1841 0x00000000);
1842}
1843#endif
1844
1845// XXX: TODO (64 bits PowerPC SPRs)
1846/*
1847 * ASR => SPR 280 (64 bits)
1848 * FPECR => SPR 1022 (?)
1849 * VRSAVE => SPR 256 (Altivec)
1850 * SCOMC => SPR 276 (64 bits ?)
1851 * SCOMD => SPR 277 (64 bits ?)
1852 * HSPRG0 => SPR 304 (hypervisor)
1853 * HSPRG1 => SPR 305 (hypervisor)
1854 * HDEC => SPR 310 (hypervisor)
1855 * HIOR => SPR 311 (hypervisor)
1856 * RMOR => SPR 312 (970)
1857 * HRMOR => SPR 313 (hypervisor)
1858 * HSRR0 => SPR 314 (hypervisor)
1859 * HSRR1 => SPR 315 (hypervisor)
1860 * LPCR => SPR 316 (970)
1861 * LPIDR => SPR 317 (970)
1862 * ... and more (thermal management, performance counters, ...)
1863 */
1864
1865static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
1866{
1867 env->reserve = -1;
1868 /* Default MMU definitions */
1869 env->nb_BATs = -1;
1870 env->nb_tlb = 0;
1871 env->nb_ways = 0;
1872 /* XXX: missing:
1873 * 32 bits PowerPC:
1874 * - MPC5xx(x)
1875 * - MPC8xx(x)
1876 * - RCPU (same as MPC5xx ?)
1877 */
1878 spr_register(env, SPR_PVR, "PVR",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, SPR_NOACCESS,
1881 def->pvr);
1882 printf("%s: PVR %08x mask %08x => %08x\n", __func__,
1883 def->pvr, def->pvr_mask, def->pvr & def->pvr_mask);
3a607854 1884 switch (def->pvr) {
426613db 1885 /* Embedded PowerPC from IBM */
76a66253
JM		 1886 case CPU_PPC_401A1: /* 401 A1 family */
1887 case CPU_PPC_401B2: /* 401 B2 family */
1888 case CPU_PPC_401C2: /* 401 C2 family */
1889 case CPU_PPC_401D2: /* 401 D2 family */
1890 case CPU_PPC_401E2: /* 401 E2 family */
1891 case CPU_PPC_401F2: /* 401 F2 family */
1892 case CPU_PPC_401G2: /* 401 G2 family */
1893 case CPU_PPC_IOP480: /* IOP 480 family */
1894 case CPU_PPC_COBRA: /* IBM Processor for Network Resources */
1895 gen_spr_generic(env);
1896 gen_spr_40x(env);
1897 gen_spr_401_403(env);
1898#if defined (TODO)
1899 /* XXX: optional ? */
1900 gen_spr_compress(env);
1901#endif
1902 env->nb_BATs = 0;
1903 env->nb_tlb = 64;
1904 env->nb_ways = 1;
1905 env->id_tlbs = 0;
e9df014c 1906 /* XXX: TODO: allocate internal IRQ controller */
76a66253
JM		 1907 break;
1908
1909 case CPU_PPC_403GA: /* 403 GA family */
1910 case CPU_PPC_403GB: /* 403 GB family */
1911 case CPU_PPC_403GC: /* 403 GC family */
1912 case CPU_PPC_403GCX: /* 403 GCX family */
1913 gen_spr_generic(env);
1914 gen_spr_40x(env);
1915 gen_spr_401_403(env);
1916 gen_spr_403(env);
1917 env->nb_BATs = 0;
1918 env->nb_tlb = 64;
1919 env->nb_ways = 1;
1920 env->id_tlbs = 0;
e9df014c 1921 /* XXX: TODO: allocate internal IRQ controller */
76a66253
JM		 1922 break;
1923
1924 case CPU_PPC_405CR: /* 405 GP/CR family */
1925 case CPU_PPC_405EP: /* 405 EP family */
1926 case CPU_PPC_405GPR: /* 405 GPR family */
1927 case CPU_PPC_405D2: /* 405 D2 family */
1928 case CPU_PPC_405D4: /* 405 D4 family */
1929 gen_spr_generic(env);
1930 /* Time base */
1931 gen_tbl(env);
1932 gen_spr_40x(env);
1933 gen_spr_405(env);
1934 env->nb_BATs = 0;
1935 env->nb_tlb = 64;
1936 env->nb_ways = 1;
1937 env->id_tlbs = 0;
24be5ae3
JM		 1938 /* Allocate hardware IRQ controller */
1939 ppc405_irq_init(env);
76a66253
JM		 1940 break;
1941
1942 case CPU_PPC_NPE405H: /* NPe405 H family */
1943 case CPU_PPC_NPE405H2:
1944 case CPU_PPC_NPE405L: /* Npe405 L family */
1945 gen_spr_generic(env);
1946 /* Time base */
1947 gen_tbl(env);
1948 gen_spr_40x(env);
1949 gen_spr_405(env);
1950 env->nb_BATs = 0;
1951 env->nb_tlb = 64;
1952 env->nb_ways = 1;
1953 env->id_tlbs = 0;
24be5ae3
JM		 1954 /* Allocate hardware IRQ controller */
1955 ppc405_irq_init(env);
76a66253
JM		 1956 break;
1957
1958#if defined (TODO)
1959 case CPU_PPC_STB01000:
1960#endif
1961#if defined (TODO)
1962 case CPU_PPC_STB01010:
1963#endif
1964#if defined (TODO)
1965 case CPU_PPC_STB0210:
1966#endif
1967 case CPU_PPC_STB03: /* STB03 family */
1968#if defined (TODO)
1969 case CPU_PPC_STB043: /* STB043 family */
1970#endif
1971#if defined (TODO)
1972 case CPU_PPC_STB045: /* STB045 family */
1973#endif
1974 case CPU_PPC_STB25: /* STB25 family */
1975#if defined (TODO)
1976 case CPU_PPC_STB130: /* STB130 family */
1977#endif
1978 gen_spr_generic(env);
1979 /* Time base */
1980 gen_tbl(env);
1981 gen_spr_40x(env);
1982 gen_spr_405(env);
1983 env->nb_BATs = 0;
1984 env->nb_tlb = 64;
1985 env->nb_ways = 1;
1986 env->id_tlbs = 0;
24be5ae3
JM		 1987 /* Allocate hardware IRQ controller */
1988 ppc405_irq_init(env);
76a66253
JM		 1989 break;
1990
1991 case CPU_PPC_440EP: /* 440 EP family */
1992 case CPU_PPC_440GP: /* 440 GP family */
1993 case CPU_PPC_440GX: /* 440 GX family */
1994 case CPU_PPC_440GXc: /* 440 GXc family */
1995 case CPU_PPC_440GXf: /* 440 GXf family */
1996 case CPU_PPC_440SP: /* 440 SP family */
1997 case CPU_PPC_440SP2:
1998 case CPU_PPC_440SPE: /* 440 SPE family */
1999 gen_spr_generic(env);
2000 /* Time base */
2001 gen_tbl(env);
2002 gen_spr_BookE(env);
2003 gen_spr_440(env);
2004 env->nb_BATs = 0;
2005 env->nb_tlb = 64;
2006 env->nb_ways = 1;
2007 env->id_tlbs = 0;
e9df014c 2008 /* XXX: TODO: allocate internal IRQ controller */
76a66253
JM		 2009 break;
2010
426613db 2011 /* Embedded PowerPC from Freescale */
76a66253
JM		 2012#if defined (TODO)
2013 case CPU_PPC_5xx:
2014 break;
2015#endif
2016#if defined (TODO)
2017 case CPU_PPC_8xx: /* MPC821 / 823 / 850 / 860 */
2018 break;
2019#endif
2020#if defined (TODO)
2021 case CPU_PPC_82xx_HIP3: /* MPC8240 / 8260 */
2022 case CPU_PPC_82xx_HIP4: /* MPC8240 / 8260 */
2023 break;
2024#endif
2025#if defined (TODO)
2026 case CPU_PPC_827x: /* MPC 827x / 828x */
2027 break;
2028#endif
2029
426613db 2030 /* XXX: Use MPC8540 PVR to implement a test PowerPC BookE target */
76a66253
JM		 2031 case CPU_PPC_e500v110:
2032 case CPU_PPC_e500v120:
2033 case CPU_PPC_e500v210:
2034 case CPU_PPC_e500v220:
2035 gen_spr_generic(env);
2036 /* Time base */
2037 gen_tbl(env);
2038 gen_spr_BookE(env);
363be49c 2039 gen_spr_BookE_FSL(env);
76a66253
JM		 2040 env->nb_BATs = 0;
2041 env->nb_tlb = 64;
2042 env->nb_ways = 1;
2043 env->id_tlbs = 0;
e9df014c 2044 /* XXX: TODO: allocate internal IRQ controller */
76a66253
JM		 2045 break;
2046
2047#if defined (TODO)
2048 case CPU_PPC_e600:
2049 break;
2050#endif
2051
426613db 2052 /* 32 bits PowerPC */
76a66253
JM		 2053 case CPU_PPC_601: /* PowerPC 601 */
2054 gen_spr_generic(env);
2055 gen_spr_ne_601(env);
2056 gen_spr_601(env);
2057 /* Hardware implementation registers */
2058 /* XXX : not implemented */
2059 spr_register(env, SPR_HID0, "HID0",
2060 SPR_NOACCESS, SPR_NOACCESS,
2061 &spr_read_generic, &spr_write_generic,
2062 0x00000000);
2063 /* XXX : not implemented */
2064 spr_register(env, SPR_HID1, "HID1",
2065 SPR_NOACCESS, SPR_NOACCESS,
2066 &spr_read_generic, &spr_write_generic,
2067 0x00000000);
2068 /* XXX : not implemented */
2069 spr_register(env, SPR_601_HID2, "HID2",
2070 SPR_NOACCESS, SPR_NOACCESS,
2071 &spr_read_generic, &spr_write_generic,
2072 0x00000000);
2073 /* XXX : not implemented */
2074 spr_register(env, SPR_601_HID5, "HID5",
2075 SPR_NOACCESS, SPR_NOACCESS,
2076 &spr_read_generic, &spr_write_generic,
2077 0x00000000);
2078 /* XXX : not implemented */
2079#if 0 /* ? */
2080 spr_register(env, SPR_601_HID15, "HID15",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 &spr_read_generic, &spr_write_generic,
2083 0x00000000);
2084#endif
2085 env->nb_tlb = 64;
2086 env->nb_ways = 2;
2087 env->id_tlbs = 0;
2088 env->id_tlbs = 0;
e9df014c 2089 /* XXX: TODO: allocate internal IRQ controller */
76a66253
JM		 2090 break;
2091
2092 case CPU_PPC_602: /* PowerPC 602 */
2093 gen_spr_generic(env);
2094 gen_spr_ne_601(env);
2095 /* Memory management */
2096 gen_low_BATs(env);
2097 /* Time base */
2098 gen_tbl(env);
2099 gen_6xx_7xx_soft_tlb(env, 64, 2);
2100 gen_spr_602(env);
2101 /* hardware implementation registers */
2102 /* XXX : not implemented */
2103 spr_register(env, SPR_HID0, "HID0",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_generic, &spr_write_generic,
2106 0x00000000);
2107 /* XXX : not implemented */
2108 spr_register(env, SPR_HID1, "HID1",
2109 SPR_NOACCESS, SPR_NOACCESS,
2110 &spr_read_generic, &spr_write_generic,
2111 0x00000000);
e9df014c
JM		 2112 /* Allocate hardware IRQ controller */
2113 ppc6xx_irq_init(env);
76a66253
JM		 2114 break;
2115
2116 case CPU_PPC_603: /* PowerPC 603 */
2117 case CPU_PPC_603E: /* PowerPC 603e */
2118 case CPU_PPC_603E7v:
2119 case CPU_PPC_603E7v2:
2120 case CPU_PPC_603P: /* PowerPC 603p */
2121 case CPU_PPC_603R: /* PowerPC 603r */
2122 gen_spr_generic(env);
2123 gen_spr_ne_601(env);
2124 /* Memory management */
2125 gen_low_BATs(env);
2126 /* Time base */
2127 gen_tbl(env);
2128 gen_6xx_7xx_soft_tlb(env, 64, 2);
2129 gen_spr_603(env);
2130 /* hardware implementation registers */
2131 /* XXX : not implemented */
2132 spr_register(env, SPR_HID0, "HID0",
2133 SPR_NOACCESS, SPR_NOACCESS,
2134 &spr_read_generic, &spr_write_generic,
2135 0x00000000);
2136 /* XXX : not implemented */
2137 spr_register(env, SPR_HID1, "HID1",
2138 SPR_NOACCESS, SPR_NOACCESS,
2139 &spr_read_generic, &spr_write_generic,
2140 0x00000000);
e9df014c
JM		 2141 /* Allocate hardware IRQ controller */
2142 ppc6xx_irq_init(env);
76a66253
JM		 2143 break;
2144
2145 case CPU_PPC_G2: /* PowerPC G2 family */
2146 case CPU_PPC_G2H4:
2147 case CPU_PPC_G2gp:
2148 case CPU_PPC_G2ls:
2149 case CPU_PPC_G2LE: /* PowerPC G2LE family */
2150 case CPU_PPC_G2LEgp:
2151 case CPU_PPC_G2LEls:
2152 gen_spr_generic(env);
2153 gen_spr_ne_601(env);
2154 /* Memory management */
2155 gen_low_BATs(env);
2156 /* Time base */
2157 gen_tbl(env);
2158 /* Memory management */
2159 gen_high_BATs(env);
2160 gen_6xx_7xx_soft_tlb(env, 64, 2);
2161 gen_spr_G2_755(env);
2162 gen_spr_G2(env);
2163 /* Hardware implementation register */
2164 /* XXX : not implemented */
2165 spr_register(env, SPR_HID0, "HID0",
2166 SPR_NOACCESS, SPR_NOACCESS,
2167 &spr_read_generic, &spr_write_generic,
2168 0x00000000);
2169 /* XXX : not implemented */
2170 spr_register(env, SPR_HID1, "HID1",
2171 SPR_NOACCESS, SPR_NOACCESS,
2172 &spr_read_generic, &spr_write_generic,
2173 0x00000000);
2174 /* XXX : not implemented */
2175 spr_register(env, SPR_HID2, "HID2",
2176 SPR_NOACCESS, SPR_NOACCESS,
2177 &spr_read_generic, &spr_write_generic,
2178 0x00000000);
e9df014c
JM		 2179 /* Allocate hardware IRQ controller */
2180 ppc6xx_irq_init(env);
76a66253
JM		 2181 break;
2182
2183 case CPU_PPC_604: /* PowerPC 604 */
2184 case CPU_PPC_604E: /* PowerPC 604e */
2185 case CPU_PPC_604R: /* PowerPC 604r */
2186 gen_spr_generic(env);
2187 gen_spr_ne_601(env);
2188 /* Memory management */
2189 gen_low_BATs(env);
2190 /* Time base */
2191 gen_tbl(env);
2192 gen_spr_604(env);
2193 /* Hardware implementation registers */
2194 /* XXX : not implemented */
2195 spr_register(env, SPR_HID0, "HID0",
2196 SPR_NOACCESS, SPR_NOACCESS,
2197 &spr_read_generic, &spr_write_generic,
2198 0x00000000);
2199 /* XXX : not implemented */
2200 spr_register(env, SPR_HID1, "HID1",
2201 SPR_NOACCESS, SPR_NOACCESS,
2202 &spr_read_generic, &spr_write_generic,
2203 0x00000000);
e9df014c
JM		 2204 /* Allocate hardware IRQ controller */
2205 ppc6xx_irq_init(env);
76a66253
JM		 2206 break;
2207
2208 case CPU_PPC_74x: /* PowerPC 740 / 750 */
2209 case CPU_PPC_740E:
2210 case CPU_PPC_750E:
2211 case CPU_PPC_74xP: /* PowerPC 740P / 750P */
2212 case CPU_PPC_750CXE21: /* IBM PowerPC 750cxe */
2213 case CPU_PPC_750CXE22:
2214 case CPU_PPC_750CXE23:
2215 case CPU_PPC_750CXE24:
2216 case CPU_PPC_750CXE24b:
2217 case CPU_PPC_750CXE31:
2218 case CPU_PPC_750CXE31b:
2219 case CPU_PPC_750CXR:
2220 gen_spr_generic(env);
2221 gen_spr_ne_601(env);
2222 /* Memory management */
2223 gen_low_BATs(env);
2224 /* Time base */
2225 gen_tbl(env);
2226 gen_spr_7xx(env);
2227 /* Hardware implementation registers */
2228 /* XXX : not implemented */
2229 spr_register(env, SPR_HID0, "HID0",
2230 SPR_NOACCESS, SPR_NOACCESS,
2231 &spr_read_generic, &spr_write_generic,
2232 0x00000000);
2233 /* XXX : not implemented */
2234 spr_register(env, SPR_HID1, "HID1",
2235 SPR_NOACCESS, SPR_NOACCESS,
2236 &spr_read_generic, &spr_write_generic,
2237 0x00000000);
e9df014c
JM		 2238 /* Allocate hardware IRQ controller */
2239 ppc6xx_irq_init(env);
76a66253
JM		 2240 break;
2241
2242 case CPU_PPC_750FX10: /* IBM PowerPC 750 FX */
2243 case CPU_PPC_750FX20:
2244 case CPU_PPC_750FX21:
2245 case CPU_PPC_750FX22:
2246 case CPU_PPC_750FX23:
2247 case CPU_PPC_750GX10: /* IBM PowerPC 750 GX */
2248 case CPU_PPC_750GX11:
2249 case CPU_PPC_750GX12:
2250 gen_spr_generic(env);
2251 gen_spr_ne_601(env);
2252 /* Memory management */
2253 gen_low_BATs(env);
2254 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
2255 gen_high_BATs(env);
2256 /* Time base */
2257 gen_tbl(env);
2258 gen_spr_7xx(env);
2259 /* Hardware implementation registers */
2260 /* XXX : not implemented */
2261 spr_register(env, SPR_HID0, "HID0",
2262 SPR_NOACCESS, SPR_NOACCESS,
2263 &spr_read_generic, &spr_write_generic,
2264 0x00000000);
2265 /* XXX : not implemented */
2266 spr_register(env, SPR_HID1, "HID1",
2267 SPR_NOACCESS, SPR_NOACCESS,
2268 &spr_read_generic, &spr_write_generic,
2269 0x00000000);
2270 /* XXX : not implemented */
2271 spr_register(env, SPR_750_HID2, "HID2",
2272 SPR_NOACCESS, SPR_NOACCESS,
2273 &spr_read_generic, &spr_write_generic,
2274 0x00000000);
e9df014c
JM		 2275 /* Allocate hardware IRQ controller */
2276 ppc6xx_irq_init(env);
76a66253
JM		 2277 break;
2278
2279 case CPU_PPC_755_10: /* PowerPC 755 */
2280 case CPU_PPC_755_11:
2281 case CPU_PPC_755_20:
2282 case CPU_PPC_755D:
2283 case CPU_PPC_755E:
2284 gen_spr_generic(env);
2285 gen_spr_ne_601(env);
2286 /* Memory management */
2287 gen_low_BATs(env);
2288 /* Time base */
2289 gen_tbl(env);
2290 /* Memory management */
2291 gen_high_BATs(env);
2292 gen_6xx_7xx_soft_tlb(env, 64, 2);
2293 gen_spr_G2_755(env);
2294 /* L2 cache control */
2295 /* XXX : not implemented */
2296 spr_register(env, SPR_ICTC, "ICTC",
2297 SPR_NOACCESS, SPR_NOACCESS,
2298 &spr_read_generic, &spr_write_generic,
2299 0x00000000);
2300 /* XXX : not implemented */
2301 spr_register(env, SPR_L2PM, "L2PM",
2302 SPR_NOACCESS, SPR_NOACCESS,
2303 &spr_read_generic, &spr_write_generic,
2304 0x00000000);
2305 /* Hardware implementation registers */
2306 /* XXX : not implemented */
2307 spr_register(env, SPR_HID0, "HID0",
2308 SPR_NOACCESS, SPR_NOACCESS,
2309 &spr_read_generic, &spr_write_generic,
2310 0x00000000);
2311 /* XXX : not implemented */
2312 spr_register(env, SPR_HID1, "HID1",
2313 SPR_NOACCESS, SPR_NOACCESS,
2314 &spr_read_generic, &spr_write_generic,
2315 0x00000000);
2316 /* XXX : not implemented */
2317 spr_register(env, SPR_HID2, "HID2",
2318 SPR_NOACCESS, SPR_NOACCESS,
2319 &spr_read_generic, &spr_write_generic,
2320 0x00000000);
e9df014c
JM		 2321 /* Allocate hardware IRQ controller */
2322 ppc6xx_irq_init(env);
76a66253
JM		 2323 break;
2324
2325#if defined (TODO)
426613db 2326 /* G4 family */
76a66253
JM		 2327 case CPU_PPC_7400: /* PowerPC 7400 */
2328 case CPU_PPC_7410C: /* PowerPC 7410 */
2329 case CPU_PPC_7410D:
2330 case CPU_PPC_7410E:
2331 case CPU_PPC_7441: /* PowerPC 7441 */
2332 case CPU_PPC_7445: /* PowerPC 7445 */
2333 case CPU_PPC_7447: /* PowerPC 7447 */
2334 case CPU_PPC_7447A: /* PowerPC 7447A */
2335 case CPU_PPC_7448: /* PowerPC 7448 */
2336 case CPU_PPC_7450: /* PowerPC 7450 */
2337 case CPU_PPC_7450b:
2338 case CPU_PPC_7451: /* PowerPC 7451 */
2339 case CPU_PPC_7451G:
2340 case CPU_PPC_7455: /* PowerPC 7455 */
2341 case CPU_PPC_7455F:
2342 case CPU_PPC_7455G:
2343 case CPU_PPC_7457: /* PowerPC 7457 */
2344 case CPU_PPC_7457C:
2345 case CPU_PPC_7457A: /* PowerPC 7457A */
2346 break;
2347#endif
2348
426613db
JM		 2349 /* 64 bits PowerPC */
2350#if defined (TARGET_PPC64)
76a66253 2351#if defined (TODO)
76a66253
JM		 2352 case CPU_PPC_620: /* PowerPC 620 */
2353 case CPU_PPC_630: /* PowerPC 630 (Power 3) */
2354 case CPU_PPC_631: /* PowerPC 631 (Power 3+) */
2355 case CPU_PPC_POWER4: /* Power 4 */
2356 case CPU_PPC_POWER4P: /* Power 4+ */
2357 case CPU_PPC_POWER5: /* Power 5 */
2358 case CPU_PPC_POWER5P: /* Power 5+ */
426613db 2359#endif
d0dfae6e
JM		 2360 break;
2361
76a66253
JM		 2362 case CPU_PPC_970: /* PowerPC 970 */
2363 case CPU_PPC_970FX10: /* PowerPC 970 FX */
2364 case CPU_PPC_970FX20:
2365 case CPU_PPC_970FX21:
2366 case CPU_PPC_970FX30:
2367 case CPU_PPC_970FX31:
2368 case CPU_PPC_970MP10: /* PowerPC 970 MP */
2369 case CPU_PPC_970MP11:
d0dfae6e
JM		 2370 gen_spr_generic(env);
2371 gen_spr_ne_601(env);
2372 /* XXX: not correct */
2373 gen_low_BATs(env);
2374 /* Time base */
2375 gen_tbl(env);
2376 gen_spr_7xx(env);
2377 /* Hardware implementation registers */
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_HID0, "HID0",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* XXX : not implemented */
2384 spr_register(env, SPR_HID1, "HID1",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 /* XXX : not implemented */
2389 spr_register(env, SPR_750_HID2, "HID2",
2390 SPR_NOACCESS, SPR_NOACCESS,
2391 &spr_read_generic, &spr_write_generic,
2392 0x00000000);
2393 /* Allocate hardware IRQ controller */
2394 ppc970_irq_init(env);
2395 break;
2396
426613db 2397#if defined (TODO)
76a66253
JM		 2398 case CPU_PPC_CELL10: /* Cell family */
2399 case CPU_PPC_CELL20:
2400 case CPU_PPC_CELL30:
2401 case CPU_PPC_CELL31:
426613db 2402#endif
d0dfae6e
JM		 2403 break;
2404
426613db 2405#if defined (TODO)
76a66253
JM		 2406 case CPU_PPC_RS64: /* Apache (RS64/A35) */
2407 case CPU_PPC_RS64II: /* NorthStar (RS64-II/A50) */
2408 case CPU_PPC_RS64III: /* Pulsar (RS64-III) */
2409 case CPU_PPC_RS64IV: /* IceStar/IStar/SStar (RS64-IV) */
76a66253 2410#endif
426613db
JM		 2411 break;
2412#endif /* defined (TARGET_PPC64) */
76a66253
JM		 2413
2414#if defined (TODO)
2415 /* POWER */
2416 case CPU_POWER: /* POWER */
2417 case CPU_POWER2: /* POWER2 */
2418 break;
2419#endif
2420
2421 default:
2422 gen_spr_generic(env);
e9df014c 2423 /* XXX: TODO: allocate internal IRQ controller */
76a66253
JM		 2424 break;
2425 }
2426 if (env->nb_BATs == -1)
2427 env->nb_BATs = 4;
2428 /* Allocate TLBs buffer when needed */
2429 if (env->nb_tlb != 0) {
2430 int nb_tlb = env->nb_tlb;
2431 if (env->id_tlbs != 0)
2432 nb_tlb *= 2;
2433 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
2434 /* Pre-compute some useful values */
2435 env->tlb_per_way = env->nb_tlb / env->nb_ways;
2436 }
2437}
2438
2439#if defined(PPC_DUMP_CPU)
2440static void dump_sprs (CPUPPCState *env)
2441{
2442 ppc_spr_t *spr;
2443 uint32_t pvr = env->spr[SPR_PVR];
2444 uint32_t sr, sw, ur, uw;
2445 int i, j, n;
2446
2447 printf("* SPRs for PVR=%08x\n", pvr);
2448 for (i = 0; i < 32; i++) {
2449 for (j = 0; j < 32; j++) {
2450 n = (i << 5) | j;
2451 spr = &env->spr_cb[n];
2452#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 2453 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
2454 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
76a66253
JM		 2455#else
2456 sw = 0;
2457 sr = 0;
2458#endif
3fc6c082
FB		 2459 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
2460 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
2461 if (sw || sr || uw || ur) {
2462 printf("%4d (%03x) %8s s%c%c u%c%c\n",
2463 (i << 5) | j, (i << 5) | j, spr->name,
2464 sw ? 'w' : '-', sr ? 'r' : '-',
2465 uw ? 'w' : '-', ur ? 'r' : '-');
2466 }
2467 }
2468 }
2469 fflush(stdout);
2470 fflush(stderr);
2471}
2472#endif
2473
2474/*****************************************************************************/
2475#include <stdlib.h>
2476#include <string.h>
2477
2478int fflush (FILE *stream);
2479
2480/* Opcode types */
2481enum {
2482 PPC_DIRECT = 0, /* Opcode routine */
2483 PPC_INDIRECT = 1, /* Indirect opcode table */
2484};
2485
2486static inline int is_indirect_opcode (void *handler)
2487{
2488 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2489}
2490
2491static inline opc_handler_t **ind_table(void *handler)
2492{
2493 return (opc_handler_t **)((unsigned long)handler & ~3);
2494}
2495
2496/* Instruction table creation */
2497/* Opcodes tables creation */
2498static void fill_new_table (opc_handler_t **table, int len)
2499{
2500 int i;
2501
2502 for (i = 0; i < len; i++)
2503 table[i] = &invalid_handler;
2504}
2505
2506static int create_new_table (opc_handler_t **table, unsigned char idx)
2507{
2508 opc_handler_t **tmp;
2509
2510 tmp = malloc(0x20 * sizeof(opc_handler_t));
2511 if (tmp == NULL)
2512 return -1;
2513 fill_new_table(tmp, 0x20);
2514 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2515
2516 return 0;
2517}
2518
2519static int insert_in_table (opc_handler_t **table, unsigned char idx,
2520 opc_handler_t *handler)
2521{
2522 if (table[idx] != &invalid_handler)
2523 return -1;
2524 table[idx] = handler;
2525
2526 return 0;
2527}
2528
2529static int register_direct_insn (opc_handler_t **ppc_opcodes,
2530 unsigned char idx, opc_handler_t *handler)
2531{
2532 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
2533 printf("*** ERROR: opcode %02x already assigned in main "
76a66253 2534 "opcode table\n", idx);
3fc6c082
FB		 2535 return -1;
2536 }
2537
2538 return 0;
2539}
2540
2541static int register_ind_in_table (opc_handler_t **table,
2542 unsigned char idx1, unsigned char idx2,
2543 opc_handler_t *handler)
2544{
2545 if (table[idx1] == &invalid_handler) {
2546 if (create_new_table(table, idx1) < 0) {
2547 printf("*** ERROR: unable to create indirect table "
76a66253 2548 "idx=%02x\n", idx1);
3fc6c082
FB		 2549 return -1;
2550 }
2551 } else {
2552 if (!is_indirect_opcode(table[idx1])) {
2553 printf("*** ERROR: idx %02x already assigned to a direct "
76a66253 2554 "opcode\n", idx1);
3fc6c082
FB		 2555 return -1;
2556 }
2557 }
2558 if (handler != NULL &&
2559 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
2560 printf("*** ERROR: opcode %02x already assigned in "
76a66253 2561 "opcode table %02x\n", idx2, idx1);
3fc6c082
FB		 2562 return -1;
2563 }
2564
2565 return 0;
2566}
2567
2568static int register_ind_insn (opc_handler_t **ppc_opcodes,
2569 unsigned char idx1, unsigned char idx2,
76a66253 2570 opc_handler_t *handler)
3fc6c082
FB		 2571{
2572 int ret;
2573
2574 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2575
2576 return ret;
2577}
2578
2579static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2580 unsigned char idx1, unsigned char idx2,
76a66253 2581 unsigned char idx3, opc_handler_t *handler)
3fc6c082
FB		 2582{
2583 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
2584 printf("*** ERROR: unable to join indirect table idx "
76a66253 2585 "[%02x-%02x]\n", idx1, idx2);
3fc6c082
FB		 2586 return -1;
2587 }
2588 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2589 handler) < 0) {
2590 printf("*** ERROR: unable to insert opcode "
76a66253 2591 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
3fc6c082
FB		 2592 return -1;
2593 }
2594
2595 return 0;
2596}
2597
2598static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
2599{
2600 if (insn->opc2 != 0xFF) {
2601 if (insn->opc3 != 0xFF) {
2602 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2603 insn->opc3, &insn->handler) < 0)
2604 return -1;
2605 } else {
2606 if (register_ind_insn(ppc_opcodes, insn->opc1,
2607 insn->opc2, &insn->handler) < 0)
2608 return -1;
2609 }
2610 } else {
2611 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
2612 return -1;
2613 }
2614
2615 return 0;
2616}
2617
2618static int test_opcode_table (opc_handler_t **table, int len)
2619{
2620 int i, count, tmp;
2621
2622 for (i = 0, count = 0; i < len; i++) {
2623 /* Consistency fixup */
2624 if (table[i] == NULL)
2625 table[i] = &invalid_handler;
2626 if (table[i] != &invalid_handler) {
2627 if (is_indirect_opcode(table[i])) {
2628 tmp = test_opcode_table(ind_table(table[i]), 0x20);
2629 if (tmp == 0) {
2630 free(table[i]);
2631 table[i] = &invalid_handler;
2632 } else {
2633 count++;
2634 }
2635 } else {
2636 count++;
2637 }
2638 }
2639 }
2640
2641 return count;
2642}
2643
2644static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
2645{
2646 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
2647 printf("*** WARNING: no opcode defined !\n");
2648}
2649
2650/*****************************************************************************/
2651static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
2652{
2653 opcode_t *opc, *start, *end;
2654
2655 fill_new_table(env->opcodes, 0x40);
2656#if defined(PPC_DUMP_CPU)
1b9eb036 2657 printf("* PowerPC instructions for PVR %08x: %s flags %016" PRIx64
0487d6a8 2658 " %08x\n",
76a66253 2659 def->pvr, def->name, def->insns_flags, def->flags);
3fc6c082
FB		 2660#endif
2661 if (&opc_start < &opc_end) {
76a66253
JM		 2662 start = &opc_start;
2663 end = &opc_end;
3fc6c082 2664 } else {
76a66253
JM		 2665 start = &opc_end;
2666 end = &opc_start;
3fc6c082
FB		 2667 }
2668 for (opc = start + 1; opc != end; opc++) {
2669 if ((opc->handler.type & def->insns_flags) != 0) {
2670 if (register_insn(env->opcodes, opc) < 0) {
76a66253
JM		 2671 printf("*** ERROR initializing PowerPC instruction "
2672 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2673 opc->opc3);
3fc6c082
FB		 2674 return -1;
2675 }
2676#if defined(PPC_DUMP_CPU)
2677 if (opc1 != 0x00) {
2678 if (opc->opc3 == 0xFF) {
2679 if (opc->opc2 == 0xFF) {
2680 printf(" %02x -- -- (%2d ----) : %s\n",
2681 opc->opc1, opc->opc1, opc->oname);
2682 } else {
2683 printf(" %02x %02x -- (%2d %4d) : %s\n",
2684 opc->opc1, opc->opc2, opc->opc1, opc->opc2,
76a66253 2685 opc->oname);
3fc6c082
FB		 2686 }
2687 } else {
2688 printf(" %02x %02x %02x (%2d %4d) : %s\n",
2689 opc->opc1, opc->opc2, opc->opc3,
2690 opc->opc1, (opc->opc3 << 5) | opc->opc2,
2691 opc->oname);
2692 }
2693 }
2694#endif
2695 }
2696 }
2697 fix_opcode_tables(env->opcodes);
2698 fflush(stdout);
2699 fflush(stderr);
2700
2701 return 0;
2702}
2703
2704int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
2705{
2706 env->msr_mask = def->msr_mask;
2707 env->flags = def->flags;
76a66253 2708 if (create_ppc_opcodes(env, def) < 0)
3fc6c082 2709 return -1;
3fc6c082
FB		 2710 init_ppc_proc(env, def);
2711#if defined(PPC_DUMP_CPU)
2712 dump_sprs(env);
76a66253
JM		 2713 if (env->tlb != NULL) {
2714 printf("%d %s TLB in %d ways\n", env->nb_tlb,
2715 env->id_tlbs ? "splitted" : "merged", env->nb_ways);
2716 }
3fc6c082 2717#endif
3fc6c082
FB		 2718
2719 return 0;
2720}
2721
3fc6c082
FB		 2722/*****************************************************************************/
2723/* PowerPC CPU definitions */
3a607854
JM		 2724static ppc_def_t ppc_defs[] = {
2725 /* Embedded PowerPC */
2726#if defined (TODO)
2727 /* PowerPC 401 */
2728 {
2729 .name = "401",
2730 .pvr = CPU_PPC_401,
2731 .pvr_mask = 0xFFFF0000,
2732 .insns_flags = PPC_INSNS_401,
2733 .flags = PPC_FLAGS_401,
2734 .msr_mask = xxx,
2735 },
3fc6c082
FB		 2736#endif
2737#if defined (TODO)
3a607854
JM		 2738 /* IOP480 (401 microcontroler) */
2739 {
2740 .name = "iop480",
2741 .pvr = CPU_PPC_IOP480,
2742 .pvr_mask = 0xFFFF0000,
2743 .insns_flags = PPC_INSNS_401,
2744 .flags = PPC_FLAGS_401,
2745 .msr_mask = xxx,
2746 },
3fc6c082
FB		 2747#endif
2748#if defined (TODO)
3a607854
JM		 2749 /* IBM Processor for Network Resources */
2750 {
2751 .name = "Cobra",
2752 .pvr = CPU_PPC_COBRA,
2753 .pvr_mask = 0xFFFF0000,
2754 .insns_flags = PPC_INSNS_401,
2755 .flags = PPC_FLAGS_401,
2756 .msr_mask = xxx,
2757 },
3fc6c082
FB		 2758#endif
2759#if defined (TODO)
3a607854
JM		 2760 /* Generic PowerPC 403 */
2761 {
2762 .name = "403",
2763 .pvr = CPU_PPC_403,
2764 .pvr_mask = 0xFFFFFF00,
2765 .insns_flags = PPC_INSNS_403,
2766 .flags = PPC_FLAGS_403,
04f20795 2767 .msr_mask = 0x000000000007D23DULL,
3a607854 2768 },
3fc6c082
FB		 2769#endif
2770#if defined (TODO)
3a607854
JM		 2771 /* PowerPC 403 GA */
2772 {
2773 .name = "403ga",
2774 .pvr = CPU_PPC_403GA,
2775 .pvr_mask = 0xFFFFFF00,
2776 .insns_flags = PPC_INSNS_403,
2777 .flags = PPC_FLAGS_403,
04f20795 2778 .msr_mask = 0x000000000007D23DULL,
3a607854 2779 },
3fc6c082
FB		 2780#endif
2781#if defined (TODO)
3a607854
JM		 2782 /* PowerPC 403 GB */
2783 {
2784 .name = "403gb",
2785 .pvr = CPU_PPC_403GB,
2786 .pvr_mask = 0xFFFFFF00,
2787 .insns_flags = PPC_INSNS_403,
2788 .flags = PPC_FLAGS_403,
04f20795 2789 .msr_mask = 0x000000000007D23DULL,
3a607854 2790 },
3fc6c082
FB		 2791#endif
2792#if defined (TODO)
3a607854
JM		 2793 /* PowerPC 403 GC */
2794 {
2795 .name = "403gc",
2796 .pvr = CPU_PPC_403GC,
2797 .pvr_mask = 0xFFFFFF00,
2798 .insns_flags = PPC_INSNS_403,
2799 .flags = PPC_FLAGS_403,
04f20795 2800 .msr_mask = 0x000000000007D23DULL,
3a607854 2801 },
3fc6c082
FB		 2802#endif
2803#if defined (TODO)
3a607854
JM		 2804 /* PowerPC 403 GCX */
2805 {
2806 .name = "403gcx",
2807 .pvr = CPU_PPC_403GCX,
2808 .pvr_mask = 0xFFFFFF00,
2809 .insns_flags = PPC_INSNS_403,
2810 .flags = PPC_FLAGS_403,
04f20795 2811 .msr_mask = 0x000000000007D23DULL,
3a607854
JM		 2812 },
2813#endif
2814 /* Generic PowerPC 405 */
2815 {
2816 .name = "405",
2817 .pvr = CPU_PPC_405,
2818 .pvr_mask = 0xFFFF0000,
2819 .insns_flags = PPC_INSNS_405,
2820 .flags = PPC_FLAGS_405,
04f20795 2821 .msr_mask = 0x00000000020EFF30ULL,
3a607854
JM		 2822 },
2823 /* PowerPC 405 CR */
2824 {
2825 .name = "405cr",
2826 .pvr = CPU_PPC_405,
2827 .pvr_mask = 0xFFFFFFFF,
2828 .insns_flags = PPC_INSNS_405,
2829 .flags = PPC_FLAGS_405,
04f20795 2830 .msr_mask = 0x00000000020EFF30ULL,
3a607854
JM		 2831 },
2832#if defined (TODO)
2833 /* PowerPC 405 GP */
2834 {
2835 .name = "405gp",
2836 .pvr = CPU_PPC_405,
2837 .pvr_mask = 0xFFFFFFFF,
2838 .insns_flags = PPC_INSNS_405,
2839 .flags = PPC_FLAGS_405,
04f20795 2840 .msr_mask = 0x00000000020EFF30ULL,
3a607854
JM		 2841 },
2842#endif
2843 /* PowerPC 405 EP */
2844 {
2845 .name = "405ep",
2846 .pvr = CPU_PPC_405EP,
2847 .pvr_mask = 0xFFFFFFFF,
2848 .insns_flags = PPC_INSNS_405,
2849 .flags = PPC_FLAGS_405,
c294fc58 2850 .msr_mask = 0x00000000000ED630ULL,
3a607854
JM		 2851 },
2852#if defined (TODO)
2853 /* PowerPC 405 EZ */
2854 {
2855 .name = "405ez",
2856 .pvr = CPU_PPC_405EZ,
2857 .pvr_mask = 0xFFFFFFFF,
2858 .insns_flags = PPC_INSNS_405,
2859 .flags = PPC_FLAGS_405,
04f20795 2860 .msr_mask = 0x00000000020EFF30ULL,
3a607854 2861 },
3fc6c082
FB		 2862#endif
2863#if defined (TODO)
3a607854
JM		 2864 /* PowerPC 405 GPR */
2865 {
2866 .name = "405gpr",
2867 .pvr = CPU_PPC_405GPR,
2868 .pvr_mask = 0xFFFFFFFF,
2869 .insns_flags = PPC_INSNS_405,
2870 .flags = PPC_FLAGS_405,
04f20795 2871 .msr_mask = 0x00000000020EFF30ULL,
3a607854 2872 },
3fc6c082 2873#endif
3a607854
JM		 2874 /* PowerPC 405 D2 */
2875 {
2876 .name = "405d2",
2877 .pvr = CPU_PPC_405D2,
2878 .pvr_mask = 0xFFFFFFFF,
2879 .insns_flags = PPC_INSNS_405,
2880 .flags = PPC_FLAGS_405,
04f20795 2881 .msr_mask = 0x00000000020EFF30ULL,
3a607854 2882 },
3a607854
JM		 2883 /* PowerPC 405 D4 */
2884 {
2885 .name = "405d4",
2886 .pvr = CPU_PPC_405D4,
2887 .pvr_mask = 0xFFFFFFFF,
2888 .insns_flags = PPC_INSNS_405,
2889 .flags = PPC_FLAGS_405,
04f20795 2890 .msr_mask = 0x00000000020EFF30ULL,
3a607854 2891 },
3fc6c082 2892#if defined (TODO)
3a607854
JM		 2893 /* Npe405 H */
2894 {
2895 .name = "Npe405H",
2896 .pvr = CPU_PPC_NPE405H,
2897 .pvr_mask = 0xFFFFFFFF,
76a66253 2898 .insns_flags = PPC_INSNS_405,
3a607854 2899 .flags = PPC_FLAGS_405,
04f20795 2900 .msr_mask = 0x00000000020EFF30ULL,
3a607854 2901 },
3fc6c082 2902#endif
3fc6c082 2903#if defined (TODO)
3a607854
JM		 2904 /* Npe405 L */
2905 {
2906 .name = "Npe405L",
2907 .pvr = CPU_PPC_NPE405L,
2908 .pvr_mask = 0xFFFFFFFF,
2909 .insns_flags = PPC_INSNS_405,
2910 .flags = PPC_FLAGS_405,
04f20795 2911 .msr_mask = 0x00000000020EFF30ULL,
3a607854 2912 },
3fc6c082
FB		 2913#endif
2914#if defined (TODO)
3a607854
JM		 2915 /* STB010000 */
2916 {
2917 .name = "STB01000",
2918 .pvr = CPU_PPC_STB01000,
2919 .pvr_mask = 0xFFFFFFFF,
2920 .insns_flags = PPC_INSNS_405,
2921 .flags = PPC_FLAGS_405,
04f20795 2922 .msr_mask = 0x00000000020EFF30ULL,
3a607854 2923 },
3fc6c082
FB		 2924#endif
2925#if defined (TODO)
3a607854
JM		 2926 /* STB01010 */
2927 {
2928 .name = "STB01010",
2929 .pvr = CPU_PPC_STB01010,
2930 .pvr_mask = 0xFFFFFFFF,
2931 .insns_flags = PPC_INSNS_405,
2932 .flags = PPC_FLAGS_405,
04f20795 2933 .msr_mask = 0x00000000020EFF30ULL,
3a607854 2934 },
3fc6c082
FB		 2935#endif
2936#if defined (TODO)
3a607854
JM		 2937 /* STB0210 */
2938 {
2939 .name = "STB0210",
2940 .pvr = CPU_PPC_STB0210,
2941 .pvr_mask = 0xFFFFFFFF,
2942 .insns_flags = PPC_INSNS_405,
2943 .flags = PPC_FLAGS_405,
04f20795 2944 .msr_mask = 0x00000000020EFF30ULL,
3a607854
JM		 2945 },
2946#endif
04f20795 2947#if defined (TODO)
3a607854
JM		 2948 /* STB03xx */
2949 {
2950 .name = "STB03",
2951 .pvr = CPU_PPC_STB03,
2952 .pvr_mask = 0xFFFFFFFF,
2953 .insns_flags = PPC_INSNS_405,
2954 .flags = PPC_FLAGS_405,
04f20795 2955 .msr_mask = 0x00000000020EFF30ULL,
3a607854 2956 },
3fc6c082
FB		 2957#endif
2958#if defined (TODO)
3a607854
JM		 2959 /* STB043x */
2960 {
2961 .name = "STB043",
2962 .pvr = CPU_PPC_STB043,
2963 .pvr_mask = 0xFFFFFFFF,
2964 .insns_flags = PPC_INSNS_405,
2965 .flags = PPC_FLAGS_405,
04f20795 2966 .msr_mask = 0x00000000020EFF30ULL,
3a607854
JM		 2967 },
2968#endif
2969#if defined (TODO)
2970 /* STB045x */
2971 {
2972 .name = "STB045",
2973 .pvr = CPU_PPC_STB045,
2974 .pvr_mask = 0xFFFFFFFF,
2975 .insns_flags = PPC_INSNS_405,
2976 .flags = PPC_FLAGS_405,
04f20795 2977 .msr_mask = 0x00000000020EFF30ULL,
3a607854
JM		 2978 },
2979#endif
04f20795 2980#if defined (TODO)
3a607854
JM		 2981 /* STB25xx */
2982 {
2983 .name = "STB25",
2984 .pvr = CPU_PPC_STB25,
2985 .pvr_mask = 0xFFFFFFFF,
2986 .insns_flags = PPC_INSNS_405,
2987 .flags = PPC_FLAGS_405,
04f20795 2988 .msr_mask = 0x00000000020EFF30ULL,
3a607854
JM		 2989 },
2990#endif
2991#if defined (TODO)
2992 /* STB130 */
2993 {
2994 .name = "STB130",
2995 .pvr = CPU_PPC_STB130,
2996 .pvr_mask = 0xFFFFFFFF,
2997 .insns_flags = PPC_INSNS_405,
2998 .flags = PPC_FLAGS_405,
04f20795 2999 .msr_mask = 0x00000000020EFF30ULL,
3a607854 3000 },
3fc6c082 3001#endif
76a66253 3002 /* Xilinx PowerPC 405 cores */
3fc6c082 3003#if defined (TODO)
3a607854
JM		 3004 {
3005 .name = "x2vp4",
3006 .pvr = CPU_PPC_X2VP4,
3007 .pvr_mask = 0xFFFFFFFF,
3008 .insns_flags = PPC_INSNS_405,
3009 .flags = PPC_FLAGS_405,
04f20795 3010 .msr_mask = 0x00000000020EFF30ULL,
3a607854
JM		 3011 },
3012 {
3013 .name = "x2vp7",
3014 .pvr = CPU_PPC_X2VP7,
3015 .pvr_mask = 0xFFFFFFFF,
3016 .insns_flags = PPC_INSNS_405,
3017 .flags = PPC_FLAGS_405,
04f20795 3018 .msr_mask = 0x00000000020EFF30ULL,
3a607854
JM		 3019 },
3020 {
3021 .name = "x2vp20",
3022 .pvr = CPU_PPC_X2VP20,
3023 .pvr_mask = 0xFFFFFFFF,
3024 .insns_flags = PPC_INSNS_405,
3025 .flags = PPC_FLAGS_405,
04f20795 3026 .msr_mask = 0x00000000020EFF30ULL,
3a607854
JM		 3027 },
3028 {
3029 .name = "x2vp50",
3030 .pvr = CPU_PPC_X2VP50,
3031 .pvr_mask = 0xFFFFFFFF,
3032 .insns_flags = PPC_INSNS_405,
3033 .flags = PPC_FLAGS_405,
04f20795 3034 .msr_mask = 0x00000000020EFF30ULL,
3a607854 3035 },
3fc6c082
FB		 3036#endif
3037#if defined (TODO)
3a607854
JM		 3038 /* PowerPC 440 EP */
3039 {
3040 .name = "440ep",
3041 .pvr = CPU_PPC_440EP,
3042 .pvr_mask = 0xFFFF0000,
3043 .insns_flags = PPC_INSNS_440,
3044 .flags = PPC_FLAGS_440,
04f20795 3045 .msr_mask = 0x000000000006D630ULL,
3a607854 3046 },
3fc6c082
FB		 3047#endif
3048#if defined (TODO)
3a607854
JM		 3049 /* PowerPC 440 GR */
3050 {
3051 .name = "440gr",
3052 .pvr = CPU_PPC_440GR,
3053 .pvr_mask = 0xFFFF0000,
3054 .insns_flags = PPC_INSNS_440,
3055 .flags = PPC_FLAGS_440,
04f20795 3056 .msr_mask = 0x000000000006D630ULL,
3a607854 3057 },
3fc6c082 3058#endif
3fc6c082 3059#if defined (TODO)
3a607854
JM		 3060 /* PowerPC 440 GP */
3061 {
3062 .name = "440gp",
3063 .pvr = CPU_PPC_440GP,
3064 .pvr_mask = 0xFFFFFF00,
3065 .insns_flags = PPC_INSNS_440,
3066 .flags = PPC_FLAGS_440,
04f20795 3067 .msr_mask = 0x000000000006D630ULL,
3a607854 3068 },
3fc6c082
FB		 3069#endif
3070#if defined (TODO)
3a607854
JM		 3071 /* PowerPC 440 GX */
3072 {
3073 .name = "440gx",
3074 .pvr = CPU_PPC_440GX,
3075 .pvr_mask = 0xFFFF0000,
3076 .insns_flags = PPC_INSNS_405,
3077 .flags = PPC_FLAGS_440,
04f20795 3078 .msr_mask = 0x000000000006D630ULL,
3a607854 3079 },
3fc6c082
FB		 3080#endif
3081#if defined (TODO)
3a607854
JM		 3082 /* PowerPC 440 GXc */
3083 {
3084 .name = "440gxc",
3085 .pvr = CPU_PPC_440GXC,
3086 .pvr_mask = 0xFFFF0000,
3087 .insns_flags = PPC_INSNS_405,
3088 .flags = PPC_FLAGS_440,
04f20795 3089 .msr_mask = 0x000000000006D630ULL,
3a607854
JM		 3090 },
3091#endif
3092#if defined (TODO)
3093 /* PowerPC 440 GXf */
3094 {
3095 .name = "440gxf",
3096 .pvr = CPU_PPC_440GXF,
3097 .pvr_mask = 0xFFFF0000,
3098 .insns_flags = PPC_INSNS_405,
3099 .flags = PPC_FLAGS_440,
04f20795 3100 .msr_mask = 0x000000000006D630ULL,
3a607854
JM		 3101 },
3102#endif
3103#if defined (TODO)
3104 /* PowerPC 440 SP */
3105 {
3106 .name = "440sp",
3107 .pvr = CPU_PPC_440SP,
3108 .pvr_mask = 0xFFFF0000,
3109 .insns_flags = PPC_INSNS_405,
3110 .flags = PPC_FLAGS_440,
04f20795 3111 .msr_mask = 0x000000000006D630ULL,
3a607854
JM		 3112 },
3113#endif
3114#if defined (TODO)
3115 /* PowerPC 440 SP2 */
3116 {
3117 .name = "440sp2",
3118 .pvr = CPU_PPC_440SP2,
3119 .pvr_mask = 0xFFFF0000,
3120 .insns_flags = PPC_INSNS_405,
3121 .flags = PPC_FLAGS_440,
04f20795 3122 .msr_mask = 0x000000000006D630ULL,
3a607854
JM		 3123 },
3124#endif
3125#if defined (TODO)
3126 /* PowerPC 440 SPE */
3127 {
3128 .name = "440spe",
3129 .pvr = CPU_PPC_440SPE,
3130 .pvr_mask = 0xFFFF0000,
3131 .insns_flags = PPC_INSNS_405,
3132 .flags = PPC_FLAGS_440,
04f20795 3133 .msr_mask = 0x000000000006D630ULL,
3a607854
JM		 3134 },
3135#endif
3136 /* Fake generic BookE PowerPC */
3137 {
3138 .name = "BookE",
3139 .pvr = CPU_PPC_e500,
3140 .pvr_mask = 0xFFFFFFFF,
3141 .insns_flags = PPC_INSNS_BOOKE,
3142 .flags = PPC_FLAGS_BOOKE,
04f20795 3143 .msr_mask = 0x000000000006D630ULL,
3a607854
JM		 3144 },
3145 /* PowerPC 460 cores - TODO */
3146 /* PowerPC MPC 5xx cores - TODO */
3147 /* PowerPC MPC 8xx cores - TODO */
3148 /* PowerPC MPC 8xxx cores - TODO */
3149 /* e200 cores - TODO */
3150 /* e500 cores - TODO */
3151 /* e600 cores - TODO */
3152
3153 /* 32 bits "classic" PowerPC */
3154#if defined (TODO)
3155 /* PowerPC 601 */
3156 {
3157 .name = "601",
3158 .pvr = CPU_PPC_601,
3159 .pvr_mask = 0xFFFF0000,
3160 .insns_flags = PPC_INSNS_601,
3161 .flags = PPC_FLAGS_601,
04f20795 3162 .msr_mask = 0x000000000000FD70ULL,
3a607854
JM		 3163 },
3164#endif
3165#if defined (TODO)
3166 /* PowerPC 602 */
3167 {
3168 .name = "602",
3169 .pvr = CPU_PPC_602,
3170 .pvr_mask = 0xFFFF0000,
3171 .insns_flags = PPC_INSNS_602,
3172 .flags = PPC_FLAGS_602,
04f20795 3173 .msr_mask = 0x0000000000C7FF73ULL,
3a607854
JM		 3174 },
3175#endif
3176 /* PowerPC 603 */
3177 {
3178 .name = "603",
3179 .pvr = CPU_PPC_603,
3180 .pvr_mask = 0xFFFFFFFF,
3181 .insns_flags = PPC_INSNS_603,
3182 .flags = PPC_FLAGS_603,
04f20795 3183 .msr_mask = 0x000000000007FF73ULL,
3a607854
JM		 3184 },
3185 /* PowerPC 603e */
3186 {
3187 .name = "603e",
3188 .pvr = CPU_PPC_603E,
3189 .pvr_mask = 0xFFFFFFFF,
3190 .insns_flags = PPC_INSNS_603,
3191 .flags = PPC_FLAGS_603,
04f20795 3192 .msr_mask = 0x000000000007FF73ULL,
3a607854
JM		 3193 },
3194 {
3195 .name = "Stretch",
3196 .pvr = CPU_PPC_603E,
3197 .pvr_mask = 0xFFFFFFFF,
3198 .insns_flags = PPC_INSNS_603,
3199 .flags = PPC_FLAGS_603,
04f20795 3200 .msr_mask = 0x000000000007FF73ULL,
3a607854
JM		 3201 },
3202 /* PowerPC 603p */
3203 {
3204 .name = "603p",
3205 .pvr = CPU_PPC_603P,
3206 .pvr_mask = 0xFFFFFFFF,
3207 .insns_flags = PPC_INSNS_603,
3208 .flags = PPC_FLAGS_603,
04f20795 3209 .msr_mask = 0x000000000007FF73ULL,
3a607854
JM		 3210 },
3211 /* PowerPC 603e7 */
3212 {
3213 .name = "603e7",
3214 .pvr = CPU_PPC_603E7,
3215 .pvr_mask = 0xFFFFFFFF,
3216 .insns_flags = PPC_INSNS_603,
3217 .flags = PPC_FLAGS_603,
04f20795 3218 .msr_mask = 0x000000000007FF73ULL,
3a607854
JM		 3219 },
3220 /* PowerPC 603e7v */
3221 {
3222 .name = "603e7v",
3223 .pvr = CPU_PPC_603E7v,
3224 .pvr_mask = 0xFFFFFFFF,
3225 .insns_flags = PPC_INSNS_603,
3226 .flags = PPC_FLAGS_603,
04f20795 3227 .msr_mask = 0x000000000007FF73ULL,
3a607854
JM		 3228 },
3229 /* PowerPC 603e7v2 */
3230 {
3231 .name = "603e7v2",
3232 .pvr = CPU_PPC_603E7v2,
3233 .pvr_mask = 0xFFFFFFFF,
3234 .insns_flags = PPC_INSNS_603,
3235 .flags = PPC_FLAGS_603,
04f20795 3236 .msr_mask = 0x000000000007FF73ULL,
3a607854
JM		 3237 },
3238 /* PowerPC 603r */
3239 {
3240 .name = "603r",
3241 .pvr = CPU_PPC_603R,
3242 .pvr_mask = 0xFFFFFFFF,
3243 .insns_flags = PPC_INSNS_603,
3244 .flags = PPC_FLAGS_603,
04f20795 3245 .msr_mask = 0x000000000007FF73ULL,
3a607854
JM		 3246 },
3247 {
3248 .name = "Goldeneye",
3249 .pvr = CPU_PPC_603R,
3250 .pvr_mask = 0xFFFFFFFF,
3251 .insns_flags = PPC_INSNS_603,
3252 .flags = PPC_FLAGS_603,
04f20795 3253 .msr_mask = 0x000000000007FF73ULL,
3a607854
JM		 3254 },
3255#if defined (TODO)
3256 /* XXX: TODO: according to Motorola UM, this is a derivative to 603e */
3257 {
3258 .name = "G2",
3259 .pvr = CPU_PPC_G2,
3260 .pvr_mask = 0xFFFF0000,
3261 .insns_flags = PPC_INSNS_G2,
3262 .flags = PPC_FLAGS_G2,
04f20795 3263 .msr_mask = 0x000000000006FFF2ULL,
3a607854
JM		 3264 },
3265 {
3266 .name = "G2h4",
3267 .pvr = CPU_PPC_G2H4,
3268 .pvr_mask = 0xFFFF0000,
3269 .insns_flags = PPC_INSNS_G2,
3270 .flags = PPC_FLAGS_G2,
04f20795 3271 .msr_mask = 0x000000000006FFF2ULL,
3a607854
JM		 3272 },
3273 {
3274 .name = "G2gp",
3275 .pvr = CPU_PPC_G2gp,
3276 .pvr_mask = 0xFFFF0000,
3277 .insns_flags = PPC_INSNS_G2,
3278 .flags = PPC_FLAGS_G2,
04f20795 3279 .msr_mask = 0x000000000006FFF2ULL,
3a607854
JM		 3280 },
3281 {
3282 .name = "G2ls",
3283 .pvr = CPU_PPC_G2ls,
3284 .pvr_mask = 0xFFFF0000,
3285 .insns_flags = PPC_INSNS_G2,
3286 .flags = PPC_FLAGS_G2,
04f20795 3287 .msr_mask = 0x000000000006FFF2ULL,
3a607854
JM		 3288 },
3289 { /* Same as G2, with LE mode support */
3290 .name = "G2le",
3291 .pvr = CPU_PPC_G2LE,
3292 .pvr_mask = 0xFFFF0000,
3293 .insns_flags = PPC_INSNS_G2,
3294 .flags = PPC_FLAGS_G2,
04f20795 3295 .msr_mask = 0x000000000007FFF3ULL,
3a607854
JM		 3296 },
3297 {
3298 .name = "G2legp",
3299 .pvr = CPU_PPC_G2LEgp,
3300 .pvr_mask = 0xFFFF0000,
3301 .insns_flags = PPC_INSNS_G2,
3302 .flags = PPC_FLAGS_G2,
04f20795 3303 .msr_mask = 0x000000000007FFF3ULL,
3a607854
JM		 3304 },
3305 {
3306 .name = "G2lels",
3307 .pvr = CPU_PPC_G2LEls,
3308 .pvr_mask = 0xFFFF0000,
3309 .insns_flags = PPC_INSNS_G2,
3310 .flags = PPC_FLAGS_G2,
04f20795 3311 .msr_mask = 0x000000000007FFF3ULL,
3a607854
JM		 3312 },
3313#endif
3314 /* PowerPC 604 */
3315 {
3316 .name = "604",
3317 .pvr = CPU_PPC_604,
3318 .pvr_mask = 0xFFFFFFFF,
3319 .insns_flags = PPC_INSNS_604,
3320 .flags = PPC_FLAGS_604,
04f20795 3321 .msr_mask = 0x000000000005FF77ULL,
3a607854
JM		 3322 },
3323 /* PowerPC 604e */
3324 {
3325 .name = "604e",
3326 .pvr = CPU_PPC_604E,
3327 .pvr_mask = 0xFFFFFFFF,
3328 .insns_flags = PPC_INSNS_604,
3329 .flags = PPC_FLAGS_604,
04f20795 3330 .msr_mask = 0x000000000005FF77ULL,
3a607854
JM		 3331 },
3332 /* PowerPC 604r */
3333 {
3334 .name = "604r",
3335 .pvr = CPU_PPC_604R,
3336 .pvr_mask = 0xFFFFFFFF,
3337 .insns_flags = PPC_INSNS_604,
3338 .flags = PPC_FLAGS_604,
04f20795 3339 .msr_mask = 0x000000000005FF77ULL,
3a607854
JM		 3340 },
3341 /* generic G3 */
3342 {
3343 .name = "G3",
3344 .pvr = CPU_PPC_74x,
3345 .pvr_mask = 0xFFFFFFFF,
3346 .insns_flags = PPC_INSNS_7x0,
3347 .flags = PPC_FLAGS_7x0,
04f20795 3348 .msr_mask = 0x000000000007FF77ULL,
3a607854
JM		 3349 },
3350 /* MPC740 (G3) */
3351 {
3352 .name = "740",
3353 .pvr = CPU_PPC_74x,
3354 .pvr_mask = 0xFFFFFFFF,
3355 .insns_flags = PPC_INSNS_7x0,
3356 .flags = PPC_FLAGS_7x0,
04f20795 3357 .msr_mask = 0x000000000007FF77ULL,
3a607854
JM		 3358 },
3359 {
3360 .name = "Arthur",
3361 .pvr = CPU_PPC_74x,
3362 .pvr_mask = 0xFFFFFFFF,
3363 .insns_flags = PPC_INSNS_7x0,
3364 .flags = PPC_FLAGS_7x0,
04f20795 3365 .msr_mask = 0x000000000007FF77ULL,
3a607854
JM		 3366 },
3367#if defined (TODO)
3368 /* MPC745 (G3) */
3369 {
3370 .name = "745",
3371 .pvr = CPU_PPC_74x,
3372 .pvr_mask = 0xFFFFF000,
3373 .insns_flags = PPC_INSNS_7x5,
3374 .flags = PPC_FLAGS_7x5,
04f20795 3375 .msr_mask = 0x000000000007FF77ULL,
3a607854
JM		 3376 },
3377 {
3378 .name = "Goldfinger",
3379 .pvr = CPU_PPC_74x,
3380 .pvr_mask = 0xFFFFF000,
3381 .insns_flags = PPC_INSNS_7x5,
3382 .flags = PPC_FLAGS_7x5,
04f20795 3383 .msr_mask = 0x000000000007FF77ULL,
3a607854
JM		 3384 },
3385#endif
3386 /* MPC750 (G3) */
3387 {
3388 .name = "750",
3389 .pvr = CPU_PPC_74x,
3390 .pvr_mask = 0xFFFFFFFF,
3391 .insns_flags = PPC_INSNS_7x0,
3392 .flags = PPC_FLAGS_7x0,
04f20795 3393 .msr_mask = 0x000000000007FF77ULL,
3a607854
JM		 3394 },
3395#if defined (TODO)
3396 /* MPC755 (G3) */
3397 {
3398 .name = "755",
3399 .pvr = CPU_PPC_755,
3400 .pvr_mask = 0xFFFFF000,
3401 .insns_flags = PPC_INSNS_7x5,
3402 .flags = PPC_FLAGS_7x5,
04f20795 3403 .msr_mask = 0x000000000007FF77ULL,
3a607854
JM		 3404 },
3405#endif
3406 /* MPC740P (G3) */
3407 {
3408 .name = "740p",
3409 .pvr = CPU_PPC_74xP,
3410 .pvr_mask = 0xFFFFFFFF,
3411 .insns_flags = PPC_INSNS_7x0,
3412 .flags = PPC_FLAGS_7x0,
04f20795 3413 .msr_mask = 0x000000000007FF77ULL,
3a607854
JM		 3414 },
3415 {
3416 .name = "Conan/Doyle",
3417 .pvr = CPU_PPC_74xP,
3418 .pvr_mask = 0xFFFFFFFF,
3419 .insns_flags = PPC_INSNS_7x0,
3420 .flags = PPC_FLAGS_7x0,
04f20795 3421 .msr_mask = 0x000000000007FF77ULL,
3a607854
JM		 3422 },
3423#if defined (TODO)
3424 /* MPC745P (G3) */
3425 {
3426 .name = "745p",
3427 .pvr = CPU_PPC_74xP,
3428 .pvr_mask = 0xFFFFF000,
3429 .insns_flags = PPC_INSNS_7x5,
3430 .flags = PPC_FLAGS_7x5,
04f20795 3431 .msr_mask = 0x000000000007FF77ULL,
3a607854
JM		 3432 },
3433#endif
3434 /* MPC750P (G3) */
3435 {
3436 .name = "750p",
3437 .pvr = CPU_PPC_74xP,
3438 .pvr_mask = 0xFFFFFFFF,
3439 .insns_flags = PPC_INSNS_7x0,
3440 .flags = PPC_FLAGS_7x0,
04f20795 3441 .msr_mask = 0x000000000007FF77ULL,
3a607854
JM		 3442 },
3443#if defined (TODO)
3444 /* MPC755P (G3) */
3445 {
3446 .name = "755p",
3447 .pvr = CPU_PPC_74xP,
3448 .pvr_mask = 0xFFFFF000,
3449 .insns_flags = PPC_INSNS_7x5,
3450 .flags = PPC_FLAGS_7x5,
04f20795 3451 .msr_mask = 0x000000000007FF77ULL,
3a607854
JM		 3452 },
3453#endif
3454 /* IBM 750CXe (G3 embedded) */
3455 {
3456 .name = "750cxe",
3457 .pvr = CPU_PPC_750CXE,
3458 .pvr_mask = 0xFFFFFFFF,
3459 .insns_flags = PPC_INSNS_7x0,
3460 .flags = PPC_FLAGS_7x0,
04f20795 3461 .msr_mask = 0x000000000007FF77ULL,
3a607854
JM		 3462 },
3463 /* IBM 750FX (G3 embedded) */
3464 {
3465 .name = "750fx",
3466 .pvr = CPU_PPC_750FX,
3467 .pvr_mask = 0xFFFFFFFF,
3468 .insns_flags = PPC_INSNS_7x0,
3469 .flags = PPC_FLAGS_7x0,
04f20795 3470 .msr_mask = 0x000000000007FF77ULL,
3a607854
JM		 3471 },
3472 /* IBM 750GX (G3 embedded) */
3473 {
3474 .name = "750gx",
3475 .pvr = CPU_PPC_750GX,
3476 .pvr_mask = 0xFFFFFFFF,
3477 .insns_flags = PPC_INSNS_7x0,
3478 .flags = PPC_FLAGS_7x0,
04f20795 3479 .msr_mask = 0x000000000007FF77ULL,
3a607854
JM		 3480 },
3481#if defined (TODO)
3482 /* generic G4 */
3483 {
3484 .name = "G4",
3485 .pvr = CPU_PPC_7400,
3486 .pvr_mask = 0xFFFF0000,
3487 .insns_flags = PPC_INSNS_74xx,
3488 .flags = PPC_FLAGS_74xx,
04f20795 3489 .msr_mask = 0x000000000205FF77ULL,
3a607854
JM		 3490 },
3491#endif
3492#if defined (TODO)
3493 /* PowerPC 7400 (G4) */
3494 {
3495 .name = "7400",
3496 .pvr = CPU_PPC_7400,
3497 .pvr_mask = 0xFFFF0000,
3498 .insns_flags = PPC_INSNS_74xx,
3499 .flags = PPC_FLAGS_74xx,
04f20795 3500 .msr_mask = 0x000000000205FF77ULL,
3a607854
JM		 3501 },
3502 {
3503 .name = "Max",
3504 .pvr = CPU_PPC_7400,
3505 .pvr_mask = 0xFFFF0000,
3506 .insns_flags = PPC_INSNS_74xx,
3507 .flags = PPC_FLAGS_74xx,
04f20795 3508 .msr_mask = 0x000000000205FF77ULL,
3a607854
JM		 3509 },
3510#endif
3511#if defined (TODO)
3512 /* PowerPC 7410 (G4) */
3513 {
3514 .name = "7410",
3515 .pvr = CPU_PPC_7410,
3516 .pvr_mask = 0xFFFF0000,
3517 .insns_flags = PPC_INSNS_74xx,
3518 .flags = PPC_FLAGS_74xx,
04f20795 3519 .msr_mask = 0x000000000205FF77ULL,
3a607854
JM		 3520 },
3521 {
3522 .name = "Nitro",
3523 .pvr = CPU_PPC_7410,
3524 .pvr_mask = 0xFFFF0000,
3525 .insns_flags = PPC_INSNS_74xx,
3526 .flags = PPC_FLAGS_74xx,
04f20795 3527 .msr_mask = 0x000000000205FF77ULL,
3a607854
JM		 3528 },
3529#endif
3530 /* XXX: 7441 */
3531 /* XXX: 7445 */
3532 /* XXX: 7447 */
3533 /* XXX: 7447A */
3534#if defined (TODO)
3535 /* PowerPC 7450 (G4) */
3536 {
3537 .name = "7450",
3538 .pvr = CPU_PPC_7450,
3539 .pvr_mask = 0xFFFF0000,
3540 .insns_flags = PPC_INSNS_74xx,
3541 .flags = PPC_FLAGS_74xx,
04f20795 3542 .msr_mask = 0x000000000205FF77ULL,
3a607854
JM		 3543 },
3544 {
3545 .name = "Vger",
3546 .pvr = CPU_PPC_7450,
3547 .pvr_mask = 0xFFFF0000,
3548 .insns_flags = PPC_INSNS_74xx,
3549 .flags = PPC_FLAGS_74xx,
04f20795 3550 .msr_mask = 0x000000000205FF77ULL,
3a607854
JM		 3551 },
3552#endif
3553 /* XXX: 7451 */
3554#if defined (TODO)
3555 /* PowerPC 7455 (G4) */
3556 {
3557 .name = "7455",
3558 .pvr = CPU_PPC_7455,
3559 .pvr_mask = 0xFFFF0000,
3560 .insns_flags = PPC_INSNS_74xx,
3561 .flags = PPC_FLAGS_74xx,
04f20795 3562 .msr_mask = 0x000000000205FF77ULL,
3a607854
JM		 3563 },
3564 {
3565 .name = "Apollo 6",
3566 .pvr = CPU_PPC_7455,
3567 .pvr_mask = 0xFFFF0000,
3568 .insns_flags = PPC_INSNS_74xx,
3569 .flags = PPC_FLAGS_74xx,
04f20795 3570 .msr_mask = 0x000000000205FF77ULL,
3a607854
JM		 3571 },
3572#endif
3573#if defined (TODO)
3574 /* PowerPC 7457 (G4) */
3575 {
3576 .name = "7457",
3577 .pvr = CPU_PPC_7457,
3578 .pvr_mask = 0xFFFF0000,
3579 .insns_flags = PPC_INSNS_74xx,
3580 .flags = PPC_FLAGS_74xx,
04f20795 3581 .msr_mask = 0x000000000205FF77ULL,
3a607854
JM		 3582 },
3583 {
3584 .name = "Apollo 7",
3585 .pvr = CPU_PPC_7457,
3586 .pvr_mask = 0xFFFF0000,
3587 .insns_flags = PPC_INSNS_74xx,
3588 .flags = PPC_FLAGS_74xx,
04f20795 3589 .msr_mask = 0x000000000205FF77ULL,
3a607854
JM		 3590 },
3591#endif
3592#if defined (TODO)
3593 /* PowerPC 7457A (G4) */
3594 {
3595 .name = "7457A",
3596 .pvr = CPU_PPC_7457A,
3597 .pvr_mask = 0xFFFF0000,
3598 .insns_flags = PPC_INSNS_74xx,
3599 .flags = PPC_FLAGS_74xx,
04f20795 3600 .msr_mask = 0x000000000205FF77ULL,
3a607854
JM		 3601 },
3602 {
3603 .name = "Apollo 7 PM",
3604 .pvr = CPU_PPC_7457A,
3605 .pvr_mask = 0xFFFF0000,
3606 .insns_flags = PPC_INSNS_74xx,
3607 .flags = PPC_FLAGS_74xx,
04f20795 3608 .msr_mask = 0x000000000205FF77ULL,
3a607854
JM		 3609 },
3610#endif
3611 /* 64 bits PowerPC */
426613db 3612#if defined (TARGET_PPC64)
3fc6c082 3613#if defined (TODO)
3a607854
JM		 3614 /* PowerPC 620 */
3615 {
3616 .name = "620",
3617 .pvr = CPU_PPC_620,
3618 .pvr_mask = 0xFFFF0000,
3619 .insns_flags = PPC_INSNS_620,
3620 .flags = PPC_FLAGS_620,
04f20795 3621 .msr_mask = 0x800000000005FF73ULL,
3a607854 3622 },
76a66253
JM		 3623#endif
3624#if defined (TODO)
3a607854
JM		 3625 /* PowerPC 630 (POWER3) */
3626 {
3627 .name = "630",
3628 .pvr = CPU_PPC_630,
3629 .pvr_mask = 0xFFFF0000,
3630 .insns_flags = PPC_INSNS_630,
3631 .flags = PPC_FLAGS_630,
3632 .msr_mask = xxx,
3633 }
3634 {
3635 .name = "POWER3",
3636 .pvr = CPU_PPC_630,
3637 .pvr_mask = 0xFFFF0000,
3638 .insns_flags = PPC_INSNS_630,
3639 .flags = PPC_FLAGS_630,
3640 .msr_mask = xxx,
3641 }
3642#endif
3643#if defined (TODO)
3644 /* PowerPC 631 (Power 3+)*/
3645 {
3646 .name = "631",
3647 .pvr = CPU_PPC_631,
3648 .pvr_mask = 0xFFFF0000,
3649 .insns_flags = PPC_INSNS_631,
3650 .flags = PPC_FLAGS_631,
3651 .msr_mask = xxx,
3652 },
3653 {
3654 .name = "POWER3+",
3655 .pvr = CPU_PPC_631,
3656 .pvr_mask = 0xFFFF0000,
3657 .insns_flags = PPC_INSNS_631,
3658 .flags = PPC_FLAGS_631,
3659 .msr_mask = xxx,
3660 },
3661#endif
3662#if defined (TODO)
3663 /* POWER4 */
3664 {
3665 .name = "POWER4",
3666 .pvr = CPU_PPC_POWER4,
3667 .pvr_mask = 0xFFFF0000,
3668 .insns_flags = PPC_INSNS_POWER4,
3669 .flags = PPC_FLAGS_POWER4,
3670 .msr_mask = xxx,
3671 },
3672#endif
3673#if defined (TODO)
3674 /* POWER4p */
3675 {
3676 .name = "POWER4+",
3677 .pvr = CPU_PPC_POWER4P,
3678 .pvr_mask = 0xFFFF0000,
3679 .insns_flags = PPC_INSNS_POWER4,
3680 .flags = PPC_FLAGS_POWER4,
3681 .msr_mask = xxx,
3682 },
3683#endif
3684#if defined (TODO)
3685 /* POWER5 */
3686 {
3687 .name = "POWER5",
3688 .pvr = CPU_PPC_POWER5,
3689 .pvr_mask = 0xFFFF0000,
3690 .insns_flags = PPC_INSNS_POWER5,
3691 .flags = PPC_FLAGS_POWER5,
3692 .msr_mask = xxx,
3693 },
3694#endif
3695#if defined (TODO)
3696 /* POWER5+ */
3697 {
3698 .name = "POWER5+",
3699 .pvr = CPU_PPC_POWER5P,
3700 .pvr_mask = 0xFFFF0000,
3701 .insns_flags = PPC_INSNS_POWER5,
3702 .flags = PPC_FLAGS_POWER5,
3703 .msr_mask = xxx,
3704 },
3705#endif
04f20795 3706#if defined (TODO)
3a607854
JM		 3707 /* PowerPC 970 */
3708 {
3709 .name = "970",
3710 .pvr = CPU_PPC_970,
3711 .pvr_mask = 0xFFFF0000,
3712 .insns_flags = PPC_INSNS_970,
3713 .flags = PPC_FLAGS_970,
04f20795 3714 .msr_mask = 0x900000000204FF36ULL,
3a607854
JM		 3715 },
3716#endif
3717#if defined (TODO)
3718 /* PowerPC 970FX (G5) */
3719 {
3720 .name = "970fx",
3721 .pvr = CPU_PPC_970FX,
3722 .pvr_mask = 0xFFFF0000,
3723 .insns_flags = PPC_INSNS_970FX,
3724 .flags = PPC_FLAGS_970FX,
04f20795 3725 .msr_mask = 0x800000000204FF36ULL,
3a607854
JM		 3726 },
3727#endif
3728#if defined (TODO)
3729 /* RS64 (Apache/A35) */
3730 /* This one seems to support the whole POWER2 instruction set
3731 * and the PowerPC 64 one.
3732 */
3733 {
3734 .name = "RS64",
3735 .pvr = CPU_PPC_RS64,
3736 .pvr_mask = 0xFFFF0000,
3737 .insns_flags = PPC_INSNS_RS64,
3738 .flags = PPC_FLAGS_RS64,
3739 .msr_mask = xxx,
3740 },
3741 {
3742 .name = "Apache",
3743 .pvr = CPU_PPC_RS64,
3744 .pvr_mask = 0xFFFF0000,
3745 .insns_flags = PPC_INSNS_RS64,
3746 .flags = PPC_FLAGS_RS64,
3747 .msr_mask = xxx,
3748 },
3749 {
3750 .name = "A35",
3751 .pvr = CPU_PPC_RS64,
3752 .pvr_mask = 0xFFFF0000,
3753 .insns_flags = PPC_INSNS_RS64,
3754 .flags = PPC_FLAGS_RS64,
3755 .msr_mask = xxx,
3756 },
3757#endif
3758#if defined (TODO)
3759 /* RS64-II (NorthStar/A50) */
3760 {
3761 .name = "RS64-II",
3762 .pvr = CPU_PPC_RS64II,
3763 .pvr_mask = 0xFFFF0000,
3764 .insns_flags = PPC_INSNS_RS64,
3765 .flags = PPC_FLAGS_RS64,
3766 .msr_mask = xxx,
3767 },
3768 {
3769 .name = "NortStar",
3770 .pvr = CPU_PPC_RS64II,
3771 .pvr_mask = 0xFFFF0000,
3772 .insns_flags = PPC_INSNS_RS64,
3773 .flags = PPC_FLAGS_RS64,
3774 .msr_mask = xxx,
3775 },
3776 {
3777 .name = "A50",
3778 .pvr = CPU_PPC_RS64II,
3779 .pvr_mask = 0xFFFF0000,
3780 .insns_flags = PPC_INSNS_RS64,
3781 .flags = PPC_FLAGS_RS64,
3782 .msr_mask = xxx,
3783 },
3784#endif
3785#if defined (TODO)
3786 /* RS64-III (Pulsar) */
3787 {
3788 .name = "RS64-III",
3789 .pvr = CPU_PPC_RS64III,
3790 .pvr_mask = 0xFFFF0000,
3791 .insns_flags = PPC_INSNS_RS64,
3792 .flags = PPC_FLAGS_RS64,
3793 .msr_mask = xxx,
3794 },
3795 {
3796 .name = "Pulsar",
3797 .pvr = CPU_PPC_RS64III,
3798 .pvr_mask = 0xFFFF0000,
3799 .insns_flags = PPC_INSNS_RS64,
3800 .flags = PPC_FLAGS_RS64,
3801 .msr_mask = xxx,
3802 },
3803#endif
3804#if defined (TODO)
3805 /* RS64-IV (IceStar/IStar/SStar) */
3806 {
3807 .name = "RS64-IV",
3808 .pvr = CPU_PPC_RS64IV,
3809 .pvr_mask = 0xFFFF0000,
3810 .insns_flags = PPC_INSNS_RS64,
3811 .flags = PPC_FLAGS_RS64,
3812 .msr_mask = xxx,
3813 },
3814 {
3815 .name = "IceStar",
3816 .pvr = CPU_PPC_RS64IV,
3817 .pvr_mask = 0xFFFF0000,
3818 .insns_flags = PPC_INSNS_RS64,
3819 .flags = PPC_FLAGS_RS64,
3820 .msr_mask = xxx,
3821 },
3822 {
3823 .name = "IStar",
3824 .pvr = CPU_PPC_RS64IV,
3825 .pvr_mask = 0xFFFF0000,
3826 .insns_flags = PPC_INSNS_RS64,
3827 .flags = PPC_FLAGS_RS64,
3828 .msr_mask = xxx,
3829 },
3830 {
3831 .name = "SStar",
3832 .pvr = CPU_PPC_RS64IV,
3833 .pvr_mask = 0xFFFF0000,
3834 .insns_flags = PPC_INSNS_RS64,
3835 .flags = PPC_FLAGS_RS64,
3836 .msr_mask = xxx,
3837 },
3838#endif
3839 /* POWER */
3840#if defined (TODO)
3841 /* Original POWER */
3842 {
3843 .name = "POWER",
3844 .pvr = CPU_POWER,
3845 .pvr_mask = 0xFFFF0000,
3846 .insns_flags = PPC_INSNS_POWER,
3847 .flags = PPC_FLAGS_POWER,
3848 .msr_mask = xxx,
3849 },
76a66253 3850#endif
426613db 3851#endif /* defined (TARGET_PPC64) */
76a66253 3852#if defined (TODO)
3a607854
JM		 3853 /* POWER2 */
3854 {
3855 .name = "POWER2",
3856 .pvr = CPU_POWER2,
3857 .pvr_mask = 0xFFFF0000,
3858 .insns_flags = PPC_INSNS_POWER,
3859 .flags = PPC_FLAGS_POWER,
3860 .msr_mask = xxx,
3861 },
3862#endif
3863 /* Generic PowerPCs */
04f20795 3864#if defined (TODO)
3a607854
JM		 3865 {
3866 .name = "ppc64",
3867 .pvr = CPU_PPC_970,
3868 .pvr_mask = 0xFFFF0000,
3869 .insns_flags = PPC_INSNS_PPC64,
3870 .flags = PPC_FLAGS_PPC64,
04f20795 3871 .msr_mask = 0xA00000000204FF36ULL,
3a607854
JM		 3872 },
3873#endif
3874 {
3875 .name = "ppc32",
3876 .pvr = CPU_PPC_604,
3877 .pvr_mask = 0xFFFFFFFF,
3878 .insns_flags = PPC_INSNS_PPC32,
3879 .flags = PPC_FLAGS_PPC32,
04f20795 3880 .msr_mask = 0x000000000005FF77ULL,
3a607854
JM		 3881 },
3882 /* Fallback */
3883 {
3884 .name = "ppc",
3885 .pvr = CPU_PPC_604,
3886 .pvr_mask = 0xFFFFFFFF,
3887 .insns_flags = PPC_INSNS_PPC32,
3888 .flags = PPC_FLAGS_PPC32,
04f20795 3889 .msr_mask = 0x000000000005FF77ULL,
3a607854
JM		 3890 },
3891};
3fc6c082
FB		 3892
3893int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
3894{
3895 int i, ret;
3896
3897 ret = -1;
3898 *def = NULL;
3899 for (i = 0; strcmp(ppc_defs[i].name, "ppc") != 0; i++) {
3900 if (strcasecmp(name, ppc_defs[i].name) == 0) {
3901 *def = &ppc_defs[i];
3902 ret = 0;
3903 break;
3904 }
3905 }
3906
3907 return ret;
3908}
3909
3910int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
3911{
3912 int i, ret;
3913
3914 ret = -1;
3915 *def = NULL;
3916 for (i = 0; ppc_defs[i].name != NULL; i++) {
3917 if ((pvr & ppc_defs[i].pvr_mask) ==
3918 (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
3919 *def = &ppc_defs[i];
3920 ret = 0;
3921 break;
3922 }
3923 }
3924
3925 return ret;
3926}
3927
3928void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3929{
3930 int i;
3931
3932 for (i = 0; ; i++) {
76a66253 3933 (*cpu_fprintf)(f, "PowerPC %16s PVR %08x mask %08x\n",
3fc6c082
FB		 3934 ppc_defs[i].name,
3935 ppc_defs[i].pvr, ppc_defs[i].pvr_mask);
3936 if (strcmp(ppc_defs[i].name, "ppc") == 0)
3937 break;
3938 }
3939}
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