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b00052e4 AZ |
1 | /* |
2 | * PXA270-based Clamshell PDA platforms. | |
3 | * | |
4 | * Copyright (c) 2006 Openedhand Ltd. | |
5 | * Written by Andrzej Zaborowski <[email protected]> | |
6 | * | |
7 | * This code is licensed under the GNU GPL v2. | |
8 | */ | |
9 | ||
87ecb68b PB |
10 | #include "hw.h" |
11 | #include "pxa.h" | |
12 | #include "arm-misc.h" | |
13 | #include "sysemu.h" | |
14 | #include "pcmcia.h" | |
15 | #include "i2c.h" | |
a984a69e | 16 | #include "ssi.h" |
87ecb68b PB |
17 | #include "flash.h" |
18 | #include "qemu-timer.h" | |
19 | #include "devices.h" | |
e33d8cdb | 20 | #include "sharpsl.h" |
87ecb68b PB |
21 | #include "console.h" |
22 | #include "block.h" | |
23 | #include "audio/audio.h" | |
24 | #include "boards.h" | |
b00052e4 | 25 | |
b00052e4 AZ |
26 | #undef REG_FMT |
27 | #define REG_FMT "0x%02lx" | |
28 | ||
29 | /* Spitz Flash */ | |
30 | #define FLASH_BASE 0x0c000000 | |
31 | #define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */ | |
32 | #define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */ | |
33 | #define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */ | |
34 | #define FLASH_ECCCNTR 0x0c /* ECC byte counter */ | |
35 | #define FLASH_ECCCLRR 0x10 /* Clear ECC */ | |
36 | #define FLASH_FLASHIO 0x14 /* Flash I/O */ | |
37 | #define FLASH_FLASHCTL 0x18 /* Flash Control */ | |
38 | ||
39 | #define FLASHCTL_CE0 (1 << 0) | |
40 | #define FLASHCTL_CLE (1 << 1) | |
41 | #define FLASHCTL_ALE (1 << 2) | |
42 | #define FLASHCTL_WP (1 << 3) | |
43 | #define FLASHCTL_CE1 (1 << 4) | |
44 | #define FLASHCTL_RYBY (1 << 5) | |
45 | #define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1) | |
46 | ||
bc24a225 PB |
47 | typedef struct { |
48 | NANDFlashState *nand; | |
b00052e4 | 49 | uint8_t ctl; |
bc24a225 PB |
50 | ECCState ecc; |
51 | } SLNANDState; | |
b00052e4 | 52 | |
c227f099 | 53 | static uint32_t sl_readb(void *opaque, target_phys_addr_t addr) |
b00052e4 | 54 | { |
bc24a225 | 55 | SLNANDState *s = (SLNANDState *) opaque; |
b00052e4 | 56 | int ryby; |
b00052e4 AZ |
57 | |
58 | switch (addr) { | |
59 | #define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to)) | |
60 | case FLASH_ECCLPLB: | |
61 | return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) | | |
62 | BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7); | |
63 | ||
64 | #define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to)) | |
65 | case FLASH_ECCLPUB: | |
66 | return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) | | |
67 | BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7); | |
68 | ||
69 | case FLASH_ECCCP: | |
70 | return s->ecc.cp; | |
71 | ||
72 | case FLASH_ECCCNTR: | |
73 | return s->ecc.count & 0xff; | |
74 | ||
75 | case FLASH_FLASHCTL: | |
76 | nand_getpins(s->nand, &ryby); | |
77 | if (ryby) | |
78 | return s->ctl | FLASHCTL_RYBY; | |
79 | else | |
80 | return s->ctl; | |
81 | ||
82 | case FLASH_FLASHIO: | |
83 | return ecc_digest(&s->ecc, nand_getio(s->nand)); | |
84 | ||
85 | default: | |
a8b7063b | 86 | zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); |
b00052e4 AZ |
87 | } |
88 | return 0; | |
89 | } | |
90 | ||
c227f099 | 91 | static uint32_t sl_readl(void *opaque, target_phys_addr_t addr) |
a5236105 | 92 | { |
bc24a225 | 93 | SLNANDState *s = (SLNANDState *) opaque; |
a5236105 AZ |
94 | |
95 | if (addr == FLASH_FLASHIO) | |
96 | return ecc_digest(&s->ecc, nand_getio(s->nand)) | | |
97 | (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16); | |
98 | ||
99 | return sl_readb(opaque, addr); | |
100 | } | |
101 | ||
c227f099 | 102 | static void sl_writeb(void *opaque, target_phys_addr_t addr, |
b00052e4 AZ |
103 | uint32_t value) |
104 | { | |
bc24a225 | 105 | SLNANDState *s = (SLNANDState *) opaque; |
b00052e4 AZ |
106 | |
107 | switch (addr) { | |
108 | case FLASH_ECCCLRR: | |
109 | /* Value is ignored. */ | |
110 | ecc_reset(&s->ecc); | |
111 | break; | |
112 | ||
113 | case FLASH_FLASHCTL: | |
114 | s->ctl = value & 0xff & ~FLASHCTL_RYBY; | |
115 | nand_setpins(s->nand, | |
116 | s->ctl & FLASHCTL_CLE, | |
117 | s->ctl & FLASHCTL_ALE, | |
118 | s->ctl & FLASHCTL_NCE, | |
119 | s->ctl & FLASHCTL_WP, | |
120 | 0); | |
121 | break; | |
122 | ||
123 | case FLASH_FLASHIO: | |
124 | nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff)); | |
125 | break; | |
126 | ||
127 | default: | |
a8b7063b | 128 | zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); |
b00052e4 AZ |
129 | } |
130 | } | |
131 | ||
aa941b94 AZ |
132 | static void sl_save(QEMUFile *f, void *opaque) |
133 | { | |
bc24a225 | 134 | SLNANDState *s = (SLNANDState *) opaque; |
aa941b94 AZ |
135 | |
136 | qemu_put_8s(f, &s->ctl); | |
137 | ecc_put(f, &s->ecc); | |
138 | } | |
139 | ||
140 | static int sl_load(QEMUFile *f, void *opaque, int version_id) | |
141 | { | |
bc24a225 | 142 | SLNANDState *s = (SLNANDState *) opaque; |
aa941b94 AZ |
143 | |
144 | qemu_get_8s(f, &s->ctl); | |
145 | ecc_get(f, &s->ecc); | |
146 | ||
147 | return 0; | |
148 | } | |
149 | ||
b00052e4 AZ |
150 | enum { |
151 | FLASH_128M, | |
152 | FLASH_1024M, | |
153 | }; | |
154 | ||
bc24a225 | 155 | static void sl_flash_register(PXA2xxState *cpu, int size) |
b00052e4 AZ |
156 | { |
157 | int iomemtype; | |
bc24a225 | 158 | SLNANDState *s; |
d60efc6b | 159 | CPUReadMemoryFunc * const sl_readfn[] = { |
b00052e4 AZ |
160 | sl_readb, |
161 | sl_readb, | |
a5236105 | 162 | sl_readl, |
b00052e4 | 163 | }; |
d60efc6b | 164 | CPUWriteMemoryFunc * const sl_writefn[] = { |
b00052e4 AZ |
165 | sl_writeb, |
166 | sl_writeb, | |
167 | sl_writeb, | |
168 | }; | |
169 | ||
bc24a225 | 170 | s = (SLNANDState *) qemu_mallocz(sizeof(SLNANDState)); |
b00052e4 AZ |
171 | s->ctl = 0; |
172 | if (size == FLASH_128M) | |
173 | s->nand = nand_init(NAND_MFR_SAMSUNG, 0x73); | |
174 | else if (size == FLASH_1024M) | |
175 | s->nand = nand_init(NAND_MFR_SAMSUNG, 0xf1); | |
176 | ||
1eed09cb | 177 | iomemtype = cpu_register_io_memory(sl_readfn, |
b00052e4 | 178 | sl_writefn, s); |
8da3ff18 | 179 | cpu_register_physical_memory(FLASH_BASE, 0x40, iomemtype); |
aa941b94 AZ |
180 | |
181 | register_savevm("sl_flash", 0, 0, sl_save, sl_load, s); | |
b00052e4 AZ |
182 | } |
183 | ||
184 | /* Spitz Keyboard */ | |
185 | ||
186 | #define SPITZ_KEY_STROBE_NUM 11 | |
187 | #define SPITZ_KEY_SENSE_NUM 7 | |
188 | ||
189 | static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = { | |
190 | 12, 17, 91, 34, 36, 38, 39 | |
191 | }; | |
192 | ||
193 | static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = { | |
194 | 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114 | |
195 | }; | |
196 | ||
197 | /* Eighth additional row maps the special keys */ | |
198 | static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = { | |
199 | { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 }, | |
200 | { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 }, | |
201 | { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 }, | |
202 | { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 }, | |
203 | { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 }, | |
2b76bdc9 AZ |
204 | { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 }, |
205 | { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 }, | |
b00052e4 AZ |
206 | { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 }, |
207 | }; | |
208 | ||
209 | #define SPITZ_GPIO_AK_INT 13 /* Remote control */ | |
210 | #define SPITZ_GPIO_SYNC 16 /* Sync button */ | |
211 | #define SPITZ_GPIO_ON_KEY 95 /* Power button */ | |
212 | #define SPITZ_GPIO_SWA 97 /* Lid */ | |
213 | #define SPITZ_GPIO_SWB 96 /* Tablet mode */ | |
214 | ||
215 | /* The special buttons are mapped to unused keys */ | |
216 | static const int spitz_gpiomap[5] = { | |
217 | SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY, | |
218 | SPITZ_GPIO_SWA, SPITZ_GPIO_SWB, | |
219 | }; | |
220 | static int spitz_gpio_invert[5] = { 0, 0, 0, 0, 0, }; | |
221 | ||
bc24a225 | 222 | typedef struct { |
38641a52 AZ |
223 | qemu_irq sense[SPITZ_KEY_SENSE_NUM]; |
224 | qemu_irq *strobe; | |
225 | qemu_irq gpiomap[5]; | |
b00052e4 AZ |
226 | int keymap[0x80]; |
227 | uint16_t keyrow[SPITZ_KEY_SENSE_NUM]; | |
228 | uint16_t strobe_state; | |
229 | uint16_t sense_state; | |
230 | ||
231 | uint16_t pre_map[0x100]; | |
232 | uint16_t modifiers; | |
233 | uint16_t imodifiers; | |
234 | uint8_t fifo[16]; | |
235 | int fifopos, fifolen; | |
236 | QEMUTimer *kbdtimer; | |
bc24a225 | 237 | } SpitzKeyboardState; |
b00052e4 | 238 | |
bc24a225 | 239 | static void spitz_keyboard_sense_update(SpitzKeyboardState *s) |
b00052e4 AZ |
240 | { |
241 | int i; | |
242 | uint16_t strobe, sense = 0; | |
243 | for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) { | |
244 | strobe = s->keyrow[i] & s->strobe_state; | |
245 | if (strobe) { | |
246 | sense |= 1 << i; | |
247 | if (!(s->sense_state & (1 << i))) | |
38641a52 | 248 | qemu_irq_raise(s->sense[i]); |
b00052e4 | 249 | } else if (s->sense_state & (1 << i)) |
38641a52 | 250 | qemu_irq_lower(s->sense[i]); |
b00052e4 AZ |
251 | } |
252 | ||
253 | s->sense_state = sense; | |
254 | } | |
255 | ||
38641a52 | 256 | static void spitz_keyboard_strobe(void *opaque, int line, int level) |
b00052e4 | 257 | { |
bc24a225 | 258 | SpitzKeyboardState *s = (SpitzKeyboardState *) opaque; |
38641a52 AZ |
259 | |
260 | if (level) | |
261 | s->strobe_state |= 1 << line; | |
262 | else | |
263 | s->strobe_state &= ~(1 << line); | |
264 | spitz_keyboard_sense_update(s); | |
b00052e4 AZ |
265 | } |
266 | ||
bc24a225 | 267 | static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode) |
b00052e4 AZ |
268 | { |
269 | int spitz_keycode = s->keymap[keycode & 0x7f]; | |
270 | if (spitz_keycode == -1) | |
271 | return; | |
272 | ||
273 | /* Handle the additional keys */ | |
274 | if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) { | |
38641a52 | 275 | qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80) ^ |
b00052e4 AZ |
276 | spitz_gpio_invert[spitz_keycode & 0xf]); |
277 | return; | |
278 | } | |
279 | ||
280 | if (keycode & 0x80) | |
281 | s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf)); | |
282 | else | |
283 | s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf); | |
284 | ||
285 | spitz_keyboard_sense_update(s); | |
286 | } | |
287 | ||
288 | #define SHIFT (1 << 7) | |
289 | #define CTRL (1 << 8) | |
290 | #define FN (1 << 9) | |
291 | ||
292 | #define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c | |
293 | ||
bc24a225 | 294 | static void spitz_keyboard_handler(SpitzKeyboardState *s, int keycode) |
b00052e4 AZ |
295 | { |
296 | uint16_t code; | |
297 | int mapcode; | |
298 | switch (keycode) { | |
299 | case 0x2a: /* Left Shift */ | |
300 | s->modifiers |= 1; | |
301 | break; | |
302 | case 0xaa: | |
303 | s->modifiers &= ~1; | |
304 | break; | |
305 | case 0x36: /* Right Shift */ | |
306 | s->modifiers |= 2; | |
307 | break; | |
308 | case 0xb6: | |
309 | s->modifiers &= ~2; | |
310 | break; | |
311 | case 0x1d: /* Control */ | |
312 | s->modifiers |= 4; | |
313 | break; | |
314 | case 0x9d: | |
315 | s->modifiers &= ~4; | |
316 | break; | |
317 | case 0x38: /* Alt */ | |
318 | s->modifiers |= 8; | |
319 | break; | |
320 | case 0xb8: | |
321 | s->modifiers &= ~8; | |
322 | break; | |
323 | } | |
324 | ||
325 | code = s->pre_map[mapcode = ((s->modifiers & 3) ? | |
326 | (keycode | SHIFT) : | |
327 | (keycode & ~SHIFT))]; | |
328 | ||
329 | if (code != mapcode) { | |
330 | #if 0 | |
331 | if ((code & SHIFT) && !(s->modifiers & 1)) | |
332 | QUEUE_KEY(0x2a | (keycode & 0x80)); | |
333 | if ((code & CTRL ) && !(s->modifiers & 4)) | |
334 | QUEUE_KEY(0x1d | (keycode & 0x80)); | |
335 | if ((code & FN ) && !(s->modifiers & 8)) | |
336 | QUEUE_KEY(0x38 | (keycode & 0x80)); | |
337 | if ((code & FN ) && (s->modifiers & 1)) | |
338 | QUEUE_KEY(0x2a | (~keycode & 0x80)); | |
339 | if ((code & FN ) && (s->modifiers & 2)) | |
340 | QUEUE_KEY(0x36 | (~keycode & 0x80)); | |
341 | #else | |
342 | if (keycode & 0x80) { | |
343 | if ((s->imodifiers & 1 ) && !(s->modifiers & 1)) | |
344 | QUEUE_KEY(0x2a | 0x80); | |
345 | if ((s->imodifiers & 4 ) && !(s->modifiers & 4)) | |
346 | QUEUE_KEY(0x1d | 0x80); | |
347 | if ((s->imodifiers & 8 ) && !(s->modifiers & 8)) | |
348 | QUEUE_KEY(0x38 | 0x80); | |
349 | if ((s->imodifiers & 0x10) && (s->modifiers & 1)) | |
350 | QUEUE_KEY(0x2a); | |
351 | if ((s->imodifiers & 0x20) && (s->modifiers & 2)) | |
352 | QUEUE_KEY(0x36); | |
353 | s->imodifiers = 0; | |
354 | } else { | |
355 | if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) { | |
356 | QUEUE_KEY(0x2a); | |
357 | s->imodifiers |= 1; | |
358 | } | |
359 | if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) { | |
360 | QUEUE_KEY(0x1d); | |
361 | s->imodifiers |= 4; | |
362 | } | |
363 | if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) { | |
364 | QUEUE_KEY(0x38); | |
365 | s->imodifiers |= 8; | |
366 | } | |
367 | if ((code & FN ) && (s->modifiers & 1) && | |
368 | !(s->imodifiers & 0x10)) { | |
369 | QUEUE_KEY(0x2a | 0x80); | |
370 | s->imodifiers |= 0x10; | |
371 | } | |
372 | if ((code & FN ) && (s->modifiers & 2) && | |
373 | !(s->imodifiers & 0x20)) { | |
374 | QUEUE_KEY(0x36 | 0x80); | |
375 | s->imodifiers |= 0x20; | |
376 | } | |
377 | } | |
378 | #endif | |
379 | } | |
380 | ||
381 | QUEUE_KEY((code & 0x7f) | (keycode & 0x80)); | |
382 | } | |
383 | ||
384 | static void spitz_keyboard_tick(void *opaque) | |
385 | { | |
bc24a225 | 386 | SpitzKeyboardState *s = (SpitzKeyboardState *) opaque; |
b00052e4 AZ |
387 | |
388 | if (s->fifolen) { | |
389 | spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]); | |
390 | s->fifolen --; | |
391 | if (s->fifopos >= 16) | |
392 | s->fifopos = 0; | |
393 | } | |
394 | ||
6ee093c9 JQ |
395 | qemu_mod_timer(s->kbdtimer, qemu_get_clock(vm_clock) + |
396 | get_ticks_per_sec() / 32); | |
b00052e4 AZ |
397 | } |
398 | ||
bc24a225 | 399 | static void spitz_keyboard_pre_map(SpitzKeyboardState *s) |
b00052e4 AZ |
400 | { |
401 | int i; | |
402 | for (i = 0; i < 0x100; i ++) | |
403 | s->pre_map[i] = i; | |
404 | s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT; /* exclam */ | |
405 | s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT; /* quotedbl */ | |
406 | s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT; /* numbersign */ | |
407 | s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT; /* dollar */ | |
408 | s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT; /* percent */ | |
409 | s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT; /* ampersand */ | |
410 | s->pre_map[0x28 ] = 0x08 | SHIFT; /* apostrophe */ | |
411 | s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT; /* parenleft */ | |
412 | s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT; /* parenright */ | |
413 | s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT; /* asciitilde */ | |
414 | s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT; /* at */ | |
415 | s->pre_map[0xd3 ] = 0x0e | FN; /* Delete */ | |
416 | s->pre_map[0x3a ] = 0x0f | FN; /* Caps_Lock */ | |
417 | s->pre_map[0x07 | SHIFT ] = 0x11 | FN; /* asciicircum */ | |
418 | s->pre_map[0x0d ] = 0x12 | FN; /* equal */ | |
419 | s->pre_map[0x0d | SHIFT ] = 0x13 | FN; /* plus */ | |
420 | s->pre_map[0x1a ] = 0x14 | FN; /* bracketleft */ | |
421 | s->pre_map[0x1b ] = 0x15 | FN; /* bracketright */ | |
2b76bdc9 AZ |
422 | s->pre_map[0x1a | SHIFT ] = 0x16 | FN; /* braceleft */ |
423 | s->pre_map[0x1b | SHIFT ] = 0x17 | FN; /* braceright */ | |
b00052e4 AZ |
424 | s->pre_map[0x27 ] = 0x22 | FN; /* semicolon */ |
425 | s->pre_map[0x27 | SHIFT ] = 0x23 | FN; /* colon */ | |
426 | s->pre_map[0x09 | SHIFT ] = 0x24 | FN; /* asterisk */ | |
427 | s->pre_map[0x2b ] = 0x25 | FN; /* backslash */ | |
428 | s->pre_map[0x2b | SHIFT ] = 0x26 | FN; /* bar */ | |
429 | s->pre_map[0x0c | SHIFT ] = 0x30 | FN; /* underscore */ | |
2b76bdc9 | 430 | s->pre_map[0x33 | SHIFT ] = 0x33 | FN; /* less */ |
b00052e4 | 431 | s->pre_map[0x35 ] = 0x33 | SHIFT; /* slash */ |
2b76bdc9 | 432 | s->pre_map[0x34 | SHIFT ] = 0x34 | FN; /* greater */ |
b00052e4 AZ |
433 | s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT; /* question */ |
434 | s->pre_map[0x49 ] = 0x48 | FN; /* Page_Up */ | |
435 | s->pre_map[0x51 ] = 0x50 | FN; /* Page_Down */ | |
436 | ||
437 | s->modifiers = 0; | |
438 | s->imodifiers = 0; | |
439 | s->fifopos = 0; | |
440 | s->fifolen = 0; | |
441 | s->kbdtimer = qemu_new_timer(vm_clock, spitz_keyboard_tick, s); | |
442 | spitz_keyboard_tick(s); | |
443 | } | |
444 | ||
445 | #undef SHIFT | |
446 | #undef CTRL | |
447 | #undef FN | |
448 | ||
aa941b94 AZ |
449 | static void spitz_keyboard_save(QEMUFile *f, void *opaque) |
450 | { | |
bc24a225 | 451 | SpitzKeyboardState *s = (SpitzKeyboardState *) opaque; |
aa941b94 AZ |
452 | int i; |
453 | ||
454 | qemu_put_be16s(f, &s->sense_state); | |
455 | qemu_put_be16s(f, &s->strobe_state); | |
456 | for (i = 0; i < 5; i ++) | |
457 | qemu_put_byte(f, spitz_gpio_invert[i]); | |
458 | } | |
459 | ||
460 | static int spitz_keyboard_load(QEMUFile *f, void *opaque, int version_id) | |
461 | { | |
bc24a225 | 462 | SpitzKeyboardState *s = (SpitzKeyboardState *) opaque; |
aa941b94 AZ |
463 | int i; |
464 | ||
465 | qemu_get_be16s(f, &s->sense_state); | |
466 | qemu_get_be16s(f, &s->strobe_state); | |
467 | for (i = 0; i < 5; i ++) | |
468 | spitz_gpio_invert[i] = qemu_get_byte(f); | |
469 | ||
470 | /* Release all pressed keys */ | |
471 | memset(s->keyrow, 0, sizeof(s->keyrow)); | |
472 | spitz_keyboard_sense_update(s); | |
473 | s->modifiers = 0; | |
474 | s->imodifiers = 0; | |
475 | s->fifopos = 0; | |
476 | s->fifolen = 0; | |
477 | ||
478 | return 0; | |
479 | } | |
480 | ||
bc24a225 | 481 | static void spitz_keyboard_register(PXA2xxState *cpu) |
b00052e4 AZ |
482 | { |
483 | int i, j; | |
bc24a225 | 484 | SpitzKeyboardState *s; |
b00052e4 | 485 | |
bc24a225 PB |
486 | s = (SpitzKeyboardState *) |
487 | qemu_mallocz(sizeof(SpitzKeyboardState)); | |
488 | memset(s, 0, sizeof(SpitzKeyboardState)); | |
b00052e4 AZ |
489 | |
490 | for (i = 0; i < 0x80; i ++) | |
491 | s->keymap[i] = -1; | |
492 | for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++) | |
493 | for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++) | |
494 | if (spitz_keymap[i][j] != -1) | |
495 | s->keymap[spitz_keymap[i][j]] = (i << 4) | j; | |
496 | ||
38641a52 AZ |
497 | for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) |
498 | s->sense[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpio_key_sense[i]]; | |
499 | ||
500 | for (i = 0; i < 5; i ++) | |
501 | s->gpiomap[i] = pxa2xx_gpio_in_get(cpu->gpio)[spitz_gpiomap[i]]; | |
502 | ||
503 | s->strobe = qemu_allocate_irqs(spitz_keyboard_strobe, s, | |
504 | SPITZ_KEY_STROBE_NUM); | |
b00052e4 | 505 | for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++) |
38641a52 | 506 | pxa2xx_gpio_out_set(cpu->gpio, spitz_gpio_key_strobe[i], s->strobe[i]); |
b00052e4 AZ |
507 | |
508 | spitz_keyboard_pre_map(s); | |
509 | qemu_add_kbd_event_handler((QEMUPutKBDEvent *) spitz_keyboard_handler, s); | |
aa941b94 AZ |
510 | |
511 | register_savevm("spitz_keyboard", 0, 0, | |
512 | spitz_keyboard_save, spitz_keyboard_load, s); | |
b00052e4 AZ |
513 | } |
514 | ||
b00052e4 AZ |
515 | /* LCD backlight controller */ |
516 | ||
517 | #define LCDTG_RESCTL 0x00 | |
518 | #define LCDTG_PHACTRL 0x01 | |
519 | #define LCDTG_DUTYCTRL 0x02 | |
520 | #define LCDTG_POWERREG0 0x03 | |
521 | #define LCDTG_POWERREG1 0x04 | |
522 | #define LCDTG_GPOR3 0x05 | |
523 | #define LCDTG_PICTRL 0x06 | |
524 | #define LCDTG_POLCTRL 0x07 | |
525 | ||
a984a69e PB |
526 | typedef struct { |
527 | SSISlave ssidev; | |
528 | int bl_intensity; | |
529 | int bl_power; | |
530 | } SpitzLCDTG; | |
b00052e4 | 531 | |
a984a69e | 532 | static void spitz_bl_update(SpitzLCDTG *s) |
b00052e4 | 533 | { |
a984a69e PB |
534 | if (s->bl_power && s->bl_intensity) |
535 | zaurus_printf("LCD Backlight now at %i/63\n", s->bl_intensity); | |
b00052e4 | 536 | else |
89cdb6af | 537 | zaurus_printf("LCD Backlight now off\n"); |
b00052e4 AZ |
538 | } |
539 | ||
a984a69e PB |
540 | /* FIXME: Implement GPIO properly and remove this hack. */ |
541 | static SpitzLCDTG *spitz_lcdtg; | |
542 | ||
38641a52 | 543 | static inline void spitz_bl_bit5(void *opaque, int line, int level) |
b00052e4 | 544 | { |
a984a69e PB |
545 | SpitzLCDTG *s = spitz_lcdtg; |
546 | int prev = s->bl_intensity; | |
b00052e4 AZ |
547 | |
548 | if (level) | |
a984a69e | 549 | s->bl_intensity &= ~0x20; |
b00052e4 | 550 | else |
a984a69e | 551 | s->bl_intensity |= 0x20; |
b00052e4 | 552 | |
a984a69e PB |
553 | if (s->bl_power && prev != s->bl_intensity) |
554 | spitz_bl_update(s); | |
b00052e4 AZ |
555 | } |
556 | ||
38641a52 | 557 | static inline void spitz_bl_power(void *opaque, int line, int level) |
b00052e4 | 558 | { |
a984a69e PB |
559 | SpitzLCDTG *s = spitz_lcdtg; |
560 | s->bl_power = !!level; | |
561 | spitz_bl_update(s); | |
b00052e4 AZ |
562 | } |
563 | ||
a984a69e | 564 | static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value) |
b00052e4 | 565 | { |
a984a69e PB |
566 | SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev); |
567 | int addr; | |
568 | addr = value >> 5; | |
569 | value &= 0x1f; | |
b00052e4 AZ |
570 | |
571 | switch (addr) { | |
572 | case LCDTG_RESCTL: | |
573 | if (value) | |
89cdb6af | 574 | zaurus_printf("LCD in QVGA mode\n"); |
b00052e4 | 575 | else |
89cdb6af | 576 | zaurus_printf("LCD in VGA mode\n"); |
b00052e4 AZ |
577 | break; |
578 | ||
579 | case LCDTG_DUTYCTRL: | |
a984a69e PB |
580 | s->bl_intensity &= ~0x1f; |
581 | s->bl_intensity |= value; | |
582 | if (s->bl_power) | |
583 | spitz_bl_update(s); | |
b00052e4 AZ |
584 | break; |
585 | ||
586 | case LCDTG_POWERREG0: | |
587 | /* Set common voltage to M62332FP */ | |
588 | break; | |
589 | } | |
a984a69e PB |
590 | return 0; |
591 | } | |
592 | ||
593 | static void spitz_lcdtg_save(QEMUFile *f, void *opaque) | |
594 | { | |
595 | SpitzLCDTG *s = (SpitzLCDTG *)opaque; | |
596 | qemu_put_be32(f, s->bl_intensity); | |
597 | qemu_put_be32(f, s->bl_power); | |
598 | } | |
599 | ||
600 | static int spitz_lcdtg_load(QEMUFile *f, void *opaque, int version_id) | |
601 | { | |
602 | SpitzLCDTG *s = (SpitzLCDTG *)opaque; | |
603 | s->bl_intensity = qemu_get_be32(f); | |
604 | s->bl_power = qemu_get_be32(f); | |
605 | return 0; | |
606 | } | |
607 | ||
81a322d4 | 608 | static int spitz_lcdtg_init(SSISlave *dev) |
a984a69e PB |
609 | { |
610 | SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev); | |
611 | ||
612 | spitz_lcdtg = s; | |
613 | s->bl_power = 0; | |
614 | s->bl_intensity = 0x20; | |
615 | ||
616 | register_savevm("spitz-lcdtg", -1, 1, | |
617 | spitz_lcdtg_save, spitz_lcdtg_load, s); | |
81a322d4 | 618 | return 0; |
b00052e4 AZ |
619 | } |
620 | ||
621 | /* SSP devices */ | |
622 | ||
623 | #define CORGI_SSP_PORT 2 | |
624 | ||
625 | #define SPITZ_GPIO_LCDCON_CS 53 | |
626 | #define SPITZ_GPIO_ADS7846_CS 14 | |
627 | #define SPITZ_GPIO_MAX1111_CS 20 | |
628 | #define SPITZ_GPIO_TP_INT 11 | |
629 | ||
a984a69e | 630 | static DeviceState *max1111; |
b00052e4 AZ |
631 | |
632 | /* "Demux" the signal based on current chipselect */ | |
a984a69e PB |
633 | typedef struct { |
634 | SSISlave ssidev; | |
635 | SSIBus *bus[3]; | |
636 | int enable[3]; | |
637 | } CorgiSSPState; | |
b00052e4 | 638 | |
a984a69e | 639 | static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value) |
b00052e4 | 640 | { |
a984a69e PB |
641 | CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev); |
642 | int i; | |
643 | ||
644 | for (i = 0; i < 3; i++) { | |
645 | if (s->enable[i]) { | |
646 | return ssi_transfer(s->bus[i], value); | |
647 | } | |
648 | } | |
649 | return 0; | |
b00052e4 AZ |
650 | } |
651 | ||
38641a52 | 652 | static void corgi_ssp_gpio_cs(void *opaque, int line, int level) |
b00052e4 | 653 | { |
a984a69e PB |
654 | CorgiSSPState *s = (CorgiSSPState *)opaque; |
655 | assert(line >= 0 && line < 3); | |
656 | s->enable[line] = !level; | |
b00052e4 AZ |
657 | } |
658 | ||
659 | #define MAX1111_BATT_VOLT 1 | |
660 | #define MAX1111_BATT_TEMP 2 | |
661 | #define MAX1111_ACIN_VOLT 3 | |
662 | ||
663 | #define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */ | |
664 | #define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */ | |
665 | #define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */ | |
666 | ||
38641a52 | 667 | static void spitz_adc_temp_on(void *opaque, int line, int level) |
b00052e4 AZ |
668 | { |
669 | if (!max1111) | |
670 | return; | |
671 | ||
672 | if (level) | |
673 | max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP); | |
674 | else | |
675 | max111x_set_input(max1111, MAX1111_BATT_TEMP, 0); | |
676 | } | |
677 | ||
aa941b94 AZ |
678 | static void spitz_ssp_save(QEMUFile *f, void *opaque) |
679 | { | |
a984a69e PB |
680 | CorgiSSPState *s = (CorgiSSPState *)opaque; |
681 | int i; | |
682 | ||
683 | for (i = 0; i < 3; i++) { | |
684 | qemu_put_be32(f, s->enable[i]); | |
685 | } | |
aa941b94 AZ |
686 | } |
687 | ||
688 | static int spitz_ssp_load(QEMUFile *f, void *opaque, int version_id) | |
689 | { | |
a984a69e PB |
690 | CorgiSSPState *s = (CorgiSSPState *)opaque; |
691 | int i; | |
aa941b94 | 692 | |
a984a69e PB |
693 | if (version_id != 1) { |
694 | return -EINVAL; | |
695 | } | |
696 | for (i = 0; i < 3; i++) { | |
697 | s->enable[i] = qemu_get_be32(f); | |
698 | } | |
aa941b94 AZ |
699 | return 0; |
700 | } | |
701 | ||
81a322d4 | 702 | static int corgi_ssp_init(SSISlave *dev) |
a984a69e PB |
703 | { |
704 | CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev); | |
705 | ||
706 | qdev_init_gpio_in(&dev->qdev, corgi_ssp_gpio_cs, 3); | |
02e2da45 PB |
707 | s->bus[0] = ssi_create_bus(&dev->qdev, "ssi0"); |
708 | s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1"); | |
709 | s->bus[2] = ssi_create_bus(&dev->qdev, "ssi2"); | |
a984a69e PB |
710 | |
711 | register_savevm("spitz_ssp", -1, 1, spitz_ssp_save, spitz_ssp_load, s); | |
81a322d4 | 712 | return 0; |
a984a69e PB |
713 | } |
714 | ||
bc24a225 | 715 | static void spitz_ssp_attach(PXA2xxState *cpu) |
b00052e4 | 716 | { |
a984a69e PB |
717 | DeviceState *mux; |
718 | DeviceState *dev; | |
719 | void *bus; | |
720 | ||
721 | mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp"); | |
38641a52 | 722 | |
a984a69e PB |
723 | bus = qdev_get_child_bus(mux, "ssi0"); |
724 | dev = ssi_create_slave(bus, "spitz-lcdtg"); | |
b00052e4 | 725 | |
a984a69e PB |
726 | bus = qdev_get_child_bus(mux, "ssi1"); |
727 | dev = ssi_create_slave(bus, "ads7846"); | |
728 | qdev_connect_gpio_out(dev, 0, | |
729 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_TP_INT]); | |
b00052e4 | 730 | |
a984a69e PB |
731 | bus = qdev_get_child_bus(mux, "ssi2"); |
732 | max1111 = ssi_create_slave(bus, "max1111"); | |
b00052e4 AZ |
733 | max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT); |
734 | max111x_set_input(max1111, MAX1111_BATT_TEMP, 0); | |
735 | max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN); | |
736 | ||
a984a69e PB |
737 | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_LCDCON_CS, |
738 | qdev_get_gpio_in(mux, 0)); | |
739 | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ADS7846_CS, | |
740 | qdev_get_gpio_in(mux, 1)); | |
741 | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_MAX1111_CS, | |
742 | qdev_get_gpio_in(mux, 2)); | |
b00052e4 AZ |
743 | } |
744 | ||
745 | /* CF Microdrive */ | |
746 | ||
bc24a225 | 747 | static void spitz_microdrive_attach(PXA2xxState *cpu, int slot) |
b00052e4 | 748 | { |
bc24a225 | 749 | PCMCIACardState *md; |
e4bcb14c | 750 | BlockDriverState *bs; |
751c6a17 | 751 | DriveInfo *dinfo; |
b00052e4 | 752 | |
751c6a17 GH |
753 | dinfo = drive_get(IF_IDE, 0, 0); |
754 | if (!dinfo) | |
e4bcb14c | 755 | return; |
751c6a17 | 756 | bs = dinfo->bdrv; |
e4bcb14c | 757 | if (bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) { |
f455e98c | 758 | md = dscm1xxxx_init(dinfo); |
15b18ec2 | 759 | pxa2xx_pcmcia_attach(cpu->pcmcia[slot], md); |
b00052e4 AZ |
760 | } |
761 | } | |
762 | ||
adb86c37 AZ |
763 | /* Wm8750 and Max7310 on I2C */ |
764 | ||
765 | #define AKITA_MAX_ADDR 0x18 | |
611d7189 AZ |
766 | #define SPITZ_WM_ADDRL 0x1b |
767 | #define SPITZ_WM_ADDRH 0x1a | |
adb86c37 AZ |
768 | |
769 | #define SPITZ_GPIO_WM 5 | |
770 | ||
771 | #ifdef HAS_AUDIO | |
38641a52 | 772 | static void spitz_wm8750_addr(void *opaque, int line, int level) |
adb86c37 AZ |
773 | { |
774 | i2c_slave *wm = (i2c_slave *) opaque; | |
775 | if (level) | |
776 | i2c_set_slave_address(wm, SPITZ_WM_ADDRH); | |
777 | else | |
778 | i2c_set_slave_address(wm, SPITZ_WM_ADDRL); | |
779 | } | |
780 | #endif | |
781 | ||
bc24a225 | 782 | static void spitz_i2c_setup(PXA2xxState *cpu) |
adb86c37 AZ |
783 | { |
784 | /* Attach the CPU on one end of our I2C bus. */ | |
785 | i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]); | |
786 | ||
787 | #ifdef HAS_AUDIO | |
cdbe40ca | 788 | DeviceState *wm; |
adb86c37 | 789 | |
adb86c37 | 790 | /* Attach a WM8750 to the bus */ |
cdbe40ca | 791 | wm = i2c_create_slave(bus, "wm8750", 0); |
adb86c37 | 792 | |
38641a52 AZ |
793 | spitz_wm8750_addr(wm, 0, 0); |
794 | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_WM, | |
795 | qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]); | |
adb86c37 AZ |
796 | /* .. and to the sound interface. */ |
797 | cpu->i2s->opaque = wm; | |
798 | cpu->i2s->codec_out = wm8750_dac_dat; | |
799 | cpu->i2s->codec_in = wm8750_adc_dat; | |
800 | wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s); | |
801 | #endif | |
802 | } | |
803 | ||
bc24a225 | 804 | static void spitz_akita_i2c_setup(PXA2xxState *cpu) |
adb86c37 AZ |
805 | { |
806 | /* Attach a Max7310 to Akita I2C bus. */ | |
6c0bd6bd PB |
807 | i2c_create_slave(pxa2xx_i2c_bus(cpu->i2c[0]), "max7310", |
808 | AKITA_MAX_ADDR); | |
adb86c37 AZ |
809 | } |
810 | ||
b00052e4 AZ |
811 | /* Other peripherals */ |
812 | ||
38641a52 | 813 | static void spitz_out_switch(void *opaque, int line, int level) |
b00052e4 | 814 | { |
38641a52 AZ |
815 | switch (line) { |
816 | case 0: | |
89cdb6af | 817 | zaurus_printf("Charging %s.\n", level ? "off" : "on"); |
38641a52 AZ |
818 | break; |
819 | case 1: | |
89cdb6af | 820 | zaurus_printf("Discharging %s.\n", level ? "on" : "off"); |
38641a52 AZ |
821 | break; |
822 | case 2: | |
89cdb6af | 823 | zaurus_printf("Green LED %s.\n", level ? "on" : "off"); |
38641a52 AZ |
824 | break; |
825 | case 3: | |
89cdb6af | 826 | zaurus_printf("Orange LED %s.\n", level ? "on" : "off"); |
38641a52 AZ |
827 | break; |
828 | case 4: | |
829 | spitz_bl_bit5(opaque, line, level); | |
830 | break; | |
831 | case 5: | |
832 | spitz_bl_power(opaque, line, level); | |
833 | break; | |
834 | case 6: | |
835 | spitz_adc_temp_on(opaque, line, level); | |
836 | break; | |
837 | } | |
b00052e4 AZ |
838 | } |
839 | ||
840 | #define SPITZ_SCP_LED_GREEN 1 | |
841 | #define SPITZ_SCP_JK_B 2 | |
842 | #define SPITZ_SCP_CHRG_ON 3 | |
843 | #define SPITZ_SCP_MUTE_L 4 | |
844 | #define SPITZ_SCP_MUTE_R 5 | |
845 | #define SPITZ_SCP_CF_POWER 6 | |
846 | #define SPITZ_SCP_LED_ORANGE 7 | |
847 | #define SPITZ_SCP_JK_A 8 | |
848 | #define SPITZ_SCP_ADC_TEMP_ON 9 | |
849 | #define SPITZ_SCP2_IR_ON 1 | |
850 | #define SPITZ_SCP2_AKIN_PULLUP 2 | |
851 | #define SPITZ_SCP2_BACKLIGHT_CONT 7 | |
852 | #define SPITZ_SCP2_BACKLIGHT_ON 8 | |
853 | #define SPITZ_SCP2_MIC_BIAS 9 | |
854 | ||
bc24a225 PB |
855 | static void spitz_scoop_gpio_setup(PXA2xxState *cpu, |
856 | ScoopInfo *scp0, ScoopInfo *scp1) | |
b00052e4 | 857 | { |
38641a52 AZ |
858 | qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8); |
859 | ||
e33d8cdb AZ |
860 | scoop_gpio_out_set(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]); |
861 | scoop_gpio_out_set(scp0, SPITZ_SCP_JK_B, outsignals[1]); | |
862 | scoop_gpio_out_set(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]); | |
863 | scoop_gpio_out_set(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]); | |
b00052e4 | 864 | |
e33d8cdb AZ |
865 | if (scp1) { |
866 | scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]); | |
867 | scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]); | |
b00052e4 AZ |
868 | } |
869 | ||
e33d8cdb | 870 | scoop_gpio_out_set(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); |
b00052e4 AZ |
871 | } |
872 | ||
873 | #define SPITZ_GPIO_HSYNC 22 | |
874 | #define SPITZ_GPIO_SD_DETECT 9 | |
875 | #define SPITZ_GPIO_SD_WP 81 | |
876 | #define SPITZ_GPIO_ON_RESET 89 | |
877 | #define SPITZ_GPIO_BAT_COVER 90 | |
878 | #define SPITZ_GPIO_CF1_IRQ 105 | |
879 | #define SPITZ_GPIO_CF1_CD 94 | |
880 | #define SPITZ_GPIO_CF2_IRQ 106 | |
881 | #define SPITZ_GPIO_CF2_CD 93 | |
882 | ||
38641a52 | 883 | static int spitz_hsync; |
b00052e4 | 884 | |
38641a52 | 885 | static void spitz_lcd_hsync_handler(void *opaque, int line, int level) |
b00052e4 | 886 | { |
bc24a225 | 887 | PXA2xxState *cpu = (PXA2xxState *) opaque; |
38641a52 | 888 | qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_HSYNC], spitz_hsync); |
b00052e4 AZ |
889 | spitz_hsync ^= 1; |
890 | } | |
891 | ||
bc24a225 | 892 | static void spitz_gpio_setup(PXA2xxState *cpu, int slots) |
b00052e4 | 893 | { |
38641a52 | 894 | qemu_irq lcd_hsync; |
b00052e4 AZ |
895 | /* |
896 | * Bad hack: We toggle the LCD hsync GPIO on every GPIO status | |
897 | * read to satisfy broken guests that poll-wait for hsync. | |
898 | * Simulating a real hsync event would be less practical and | |
899 | * wouldn't guarantee that a guest ever exits the loop. | |
900 | */ | |
901 | spitz_hsync = 0; | |
38641a52 AZ |
902 | lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0]; |
903 | pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync); | |
904 | pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync); | |
b00052e4 AZ |
905 | |
906 | /* MMC/SD host */ | |
02ce600c AZ |
907 | pxa2xx_mmci_handlers(cpu->mmc, |
908 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_WP], | |
909 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SD_DETECT]); | |
b00052e4 AZ |
910 | |
911 | /* Battery lock always closed */ | |
38641a52 | 912 | qemu_irq_raise(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_BAT_COVER]); |
b00052e4 AZ |
913 | |
914 | /* Handle reset */ | |
38641a52 | 915 | pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset); |
b00052e4 AZ |
916 | |
917 | /* PCMCIA signals: card's IRQ and Card-Detect */ | |
b00052e4 | 918 | if (slots >= 1) |
38641a52 AZ |
919 | pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0], |
920 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_IRQ], | |
921 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF1_CD]); | |
b00052e4 | 922 | if (slots >= 2) |
38641a52 AZ |
923 | pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1], |
924 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_IRQ], | |
925 | pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_CF2_CD]); | |
b00052e4 AZ |
926 | |
927 | /* Initialise the screen rotation related signals */ | |
928 | spitz_gpio_invert[3] = 0; /* Always open */ | |
929 | if (graphic_rotate) { /* Tablet mode */ | |
930 | spitz_gpio_invert[4] = 0; | |
931 | } else { /* Portrait mode */ | |
932 | spitz_gpio_invert[4] = 1; | |
933 | } | |
38641a52 AZ |
934 | qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWA], |
935 | spitz_gpio_invert[3]); | |
936 | qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_SWB], | |
937 | spitz_gpio_invert[4]); | |
b00052e4 AZ |
938 | } |
939 | ||
b00052e4 AZ |
940 | /* Board init. */ |
941 | enum spitz_model_e { spitz, akita, borzoi, terrier }; | |
942 | ||
7fb4fdcf AZ |
943 | #define SPITZ_RAM 0x04000000 |
944 | #define SPITZ_ROM 0x00800000 | |
945 | ||
f93eb9ff AZ |
946 | static struct arm_boot_info spitz_binfo = { |
947 | .loader_start = PXA2XX_SDRAM_BASE, | |
948 | .ram_size = 0x04000000, | |
949 | }; | |
950 | ||
c227f099 | 951 | static void spitz_common_init(ram_addr_t ram_size, |
3023f332 | 952 | const char *kernel_filename, |
b00052e4 | 953 | const char *kernel_cmdline, const char *initrd_filename, |
4207117c | 954 | const char *cpu_model, enum spitz_model_e model, int arm_id) |
b00052e4 | 955 | { |
bc24a225 PB |
956 | PXA2xxState *cpu; |
957 | ScoopInfo *scp0, *scp1 = NULL; | |
b00052e4 | 958 | |
4207117c AZ |
959 | if (!cpu_model) |
960 | cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0"; | |
b00052e4 | 961 | |
d95b2f8d | 962 | /* Setup CPU & memory */ |
3023f332 | 963 | cpu = pxa270_init(spitz_binfo.ram_size, cpu_model); |
b00052e4 AZ |
964 | |
965 | sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M); | |
966 | ||
7fb4fdcf AZ |
967 | cpu_register_physical_memory(0, SPITZ_ROM, |
968 | qemu_ram_alloc(SPITZ_ROM) | IO_MEM_ROM); | |
b00052e4 AZ |
969 | |
970 | /* Setup peripherals */ | |
971 | spitz_keyboard_register(cpu); | |
972 | ||
973 | spitz_ssp_attach(cpu); | |
974 | ||
e33d8cdb AZ |
975 | scp0 = scoop_init(cpu, 0, 0x10800000); |
976 | if (model != akita) { | |
977 | scp1 = scoop_init(cpu, 1, 0x08800040); | |
978 | } | |
b00052e4 | 979 | |
e33d8cdb | 980 | spitz_scoop_gpio_setup(cpu, scp0, scp1); |
b00052e4 AZ |
981 | |
982 | spitz_gpio_setup(cpu, (model == akita) ? 1 : 2); | |
983 | ||
adb86c37 AZ |
984 | spitz_i2c_setup(cpu); |
985 | ||
986 | if (model == akita) | |
987 | spitz_akita_i2c_setup(cpu); | |
988 | ||
b00052e4 | 989 | if (model == terrier) |
bf5ee248 | 990 | /* A 6.0 GB microdrive is permanently sitting in CF slot 1. */ |
15b18ec2 | 991 | spitz_microdrive_attach(cpu, 1); |
b00052e4 | 992 | else if (model != akita) |
15b18ec2 AZ |
993 | /* A 4.0 GB microdrive is permanently sitting in CF slot 0. */ |
994 | spitz_microdrive_attach(cpu, 0); | |
b00052e4 AZ |
995 | |
996 | /* Setup initial (reset) machine state */ | |
f93eb9ff | 997 | cpu->env->regs[15] = spitz_binfo.loader_start; |
b00052e4 | 998 | |
f93eb9ff AZ |
999 | spitz_binfo.kernel_filename = kernel_filename; |
1000 | spitz_binfo.kernel_cmdline = kernel_cmdline; | |
1001 | spitz_binfo.initrd_filename = initrd_filename; | |
1002 | spitz_binfo.board_id = arm_id; | |
1003 | arm_load_kernel(cpu->env, &spitz_binfo); | |
f78630ab | 1004 | sl_bootparam_write(SL_PXA_PARAM_BASE); |
b00052e4 AZ |
1005 | } |
1006 | ||
c227f099 | 1007 | static void spitz_init(ram_addr_t ram_size, |
3023f332 | 1008 | const char *boot_device, |
b00052e4 AZ |
1009 | const char *kernel_filename, const char *kernel_cmdline, |
1010 | const char *initrd_filename, const char *cpu_model) | |
1011 | { | |
fbe1b595 | 1012 | spitz_common_init(ram_size, kernel_filename, |
4207117c | 1013 | kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9); |
b00052e4 AZ |
1014 | } |
1015 | ||
c227f099 | 1016 | static void borzoi_init(ram_addr_t ram_size, |
3023f332 | 1017 | const char *boot_device, |
b00052e4 AZ |
1018 | const char *kernel_filename, const char *kernel_cmdline, |
1019 | const char *initrd_filename, const char *cpu_model) | |
1020 | { | |
fbe1b595 | 1021 | spitz_common_init(ram_size, kernel_filename, |
4207117c | 1022 | kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f); |
b00052e4 AZ |
1023 | } |
1024 | ||
c227f099 | 1025 | static void akita_init(ram_addr_t ram_size, |
3023f332 | 1026 | const char *boot_device, |
b00052e4 AZ |
1027 | const char *kernel_filename, const char *kernel_cmdline, |
1028 | const char *initrd_filename, const char *cpu_model) | |
1029 | { | |
fbe1b595 | 1030 | spitz_common_init(ram_size, kernel_filename, |
4207117c | 1031 | kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8); |
b00052e4 AZ |
1032 | } |
1033 | ||
c227f099 | 1034 | static void terrier_init(ram_addr_t ram_size, |
3023f332 | 1035 | const char *boot_device, |
b00052e4 AZ |
1036 | const char *kernel_filename, const char *kernel_cmdline, |
1037 | const char *initrd_filename, const char *cpu_model) | |
1038 | { | |
fbe1b595 | 1039 | spitz_common_init(ram_size, kernel_filename, |
4207117c | 1040 | kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f); |
b00052e4 AZ |
1041 | } |
1042 | ||
11be4b3e | 1043 | static QEMUMachine akitapda_machine = { |
4b32e168 AL |
1044 | .name = "akita", |
1045 | .desc = "Akita PDA (PXA270)", | |
1046 | .init = akita_init, | |
b00052e4 AZ |
1047 | }; |
1048 | ||
f80f9ec9 | 1049 | static QEMUMachine spitzpda_machine = { |
4b32e168 AL |
1050 | .name = "spitz", |
1051 | .desc = "Spitz PDA (PXA270)", | |
1052 | .init = spitz_init, | |
b00052e4 AZ |
1053 | }; |
1054 | ||
f80f9ec9 | 1055 | static QEMUMachine borzoipda_machine = { |
4b32e168 AL |
1056 | .name = "borzoi", |
1057 | .desc = "Borzoi PDA (PXA270)", | |
1058 | .init = borzoi_init, | |
b00052e4 AZ |
1059 | }; |
1060 | ||
f80f9ec9 | 1061 | static QEMUMachine terrierpda_machine = { |
4b32e168 AL |
1062 | .name = "terrier", |
1063 | .desc = "Terrier PDA (PXA270)", | |
1064 | .init = terrier_init, | |
b00052e4 | 1065 | }; |
a984a69e | 1066 | |
f80f9ec9 AL |
1067 | static void spitz_machine_init(void) |
1068 | { | |
1069 | qemu_register_machine(&akitapda_machine); | |
1070 | qemu_register_machine(&spitzpda_machine); | |
1071 | qemu_register_machine(&borzoipda_machine); | |
1072 | qemu_register_machine(&terrierpda_machine); | |
1073 | } | |
1074 | ||
1075 | machine_init(spitz_machine_init); | |
1076 | ||
a984a69e | 1077 | static SSISlaveInfo corgi_ssp_info = { |
074f2fff GH |
1078 | .qdev.name = "corgi-ssp", |
1079 | .qdev.size = sizeof(CorgiSSPState), | |
a984a69e PB |
1080 | .init = corgi_ssp_init, |
1081 | .transfer = corgi_ssp_transfer | |
1082 | }; | |
1083 | ||
1084 | static SSISlaveInfo spitz_lcdtg_info = { | |
074f2fff GH |
1085 | .qdev.name = "spitz-lcdtg", |
1086 | .qdev.size = sizeof(SpitzLCDTG), | |
a984a69e PB |
1087 | .init = spitz_lcdtg_init, |
1088 | .transfer = spitz_lcdtg_transfer | |
1089 | }; | |
1090 | ||
1091 | static void spitz_register_devices(void) | |
1092 | { | |
074f2fff GH |
1093 | ssi_register_slave(&corgi_ssp_info); |
1094 | ssi_register_slave(&spitz_lcdtg_info); | |
a984a69e PB |
1095 | } |
1096 | ||
1097 | device_init(spitz_register_devices) |