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2c50e26e EI |
1 | /* |
2 | * Model of Xilinx Virtex5 ML507 PPC-440 refdesign. | |
3 | * | |
4 | * Copyright (c) 2010 Edgar E. Iglesias. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
83c9f4ca PB |
25 | #include "hw/sysbus.h" |
26 | #include "hw/hw.h" | |
0d09e41a PB |
27 | #include "hw/char/serial.h" |
28 | #include "hw/block/flash.h" | |
9c17d615 | 29 | #include "sysemu/sysemu.h" |
bd2be150 | 30 | #include "hw/devices.h" |
83c9f4ca | 31 | #include "hw/boards.h" |
9c17d615 | 32 | #include "sysemu/device_tree.h" |
83c9f4ca | 33 | #include "hw/loader.h" |
2c50e26e | 34 | #include "elf.h" |
1de7afc9 | 35 | #include "qemu/log.h" |
022c62cb | 36 | #include "exec/address-spaces.h" |
2c50e26e | 37 | |
0d09e41a PB |
38 | #include "hw/ppc/ppc.h" |
39 | #include "hw/ppc/ppc4xx.h" | |
47b43a1f | 40 | #include "ppc405.h" |
2c50e26e | 41 | |
9c17d615 | 42 | #include "sysemu/blockdev.h" |
83c9f4ca | 43 | #include "hw/xilinx.h" |
2c50e26e EI |
44 | |
45 | #define EPAPR_MAGIC (0x45504150) | |
46 | #define FLASH_SIZE (16 * 1024 * 1024) | |
47 | ||
48 | static struct boot_info | |
49 | { | |
50 | uint32_t bootstrap_pc; | |
51 | uint32_t cmdline; | |
52 | uint32_t fdt; | |
53 | uint32_t ima_size; | |
54 | void *vfdt; | |
55 | } boot_info; | |
56 | ||
57 | /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ | |
e2684c0b | 58 | static void mmubooke_create_initial_mapping(CPUPPCState *env, |
2c50e26e | 59 | target_ulong va, |
a8170e5e | 60 | hwaddr pa) |
2c50e26e | 61 | { |
1c53accc | 62 | ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; |
2c50e26e EI |
63 | |
64 | tlb->attr = 0; | |
65 | tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); | |
66 | tlb->size = 1 << 31; /* up to 0x80000000 */ | |
67 | tlb->EPN = va & TARGET_PAGE_MASK; | |
68 | tlb->RPN = pa & TARGET_PAGE_MASK; | |
69 | tlb->PID = 0; | |
70 | ||
1c53accc | 71 | tlb = &env->tlb.tlbe[1]; |
2c50e26e EI |
72 | tlb->attr = 0; |
73 | tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); | |
74 | tlb->size = 1 << 31; /* up to 0xffffffff */ | |
75 | tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; | |
76 | tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; | |
77 | tlb->PID = 0; | |
78 | } | |
79 | ||
68281699 AF |
80 | static PowerPCCPU *ppc440_init_xilinx(ram_addr_t *ram_size, |
81 | int do_init, | |
82 | const char *cpu_model, | |
83 | uint32_t sysclk) | |
2c50e26e | 84 | { |
d1d4938b | 85 | PowerPCCPU *cpu; |
e2684c0b | 86 | CPUPPCState *env; |
2c50e26e EI |
87 | qemu_irq *irqs; |
88 | ||
d1d4938b AF |
89 | cpu = cpu_ppc_init(cpu_model); |
90 | if (cpu == NULL) { | |
2c50e26e EI |
91 | fprintf(stderr, "Unable to initialize CPU!\n"); |
92 | exit(1); | |
93 | } | |
d1d4938b | 94 | env = &cpu->env; |
2c50e26e | 95 | |
a34a92b9 | 96 | ppc_booke_timers_init(cpu, sysclk, 0/* no flags */); |
2c50e26e EI |
97 | |
98 | ppc_dcr_init(env, NULL, NULL); | |
99 | ||
100 | /* interrupt controller */ | |
7267c094 | 101 | irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); |
2c50e26e EI |
102 | irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
103 | irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; | |
49a2942d | 104 | ppcuic_init(env, irqs, 0x0C0, 0, 1); |
68281699 | 105 | return cpu; |
2c50e26e EI |
106 | } |
107 | ||
108 | static void main_cpu_reset(void *opaque) | |
109 | { | |
f8031482 AF |
110 | PowerPCCPU *cpu = opaque; |
111 | CPUPPCState *env = &cpu->env; | |
2c50e26e EI |
112 | struct boot_info *bi = env->load_info; |
113 | ||
f8031482 | 114 | cpu_reset(CPU(cpu)); |
2c50e26e EI |
115 | /* Linux Kernel Parameters (passing device tree): |
116 | * r3: pointer to the fdt | |
117 | * r4: 0 | |
118 | * r5: 0 | |
119 | * r6: epapr magic | |
120 | * r7: size of IMA in bytes | |
121 | * r8: 0 | |
122 | * r9: 0 | |
123 | */ | |
124 | env->gpr[1] = (16<<20) - 8; | |
125 | /* Provide a device-tree. */ | |
126 | env->gpr[3] = bi->fdt; | |
127 | env->nip = bi->bootstrap_pc; | |
128 | ||
129 | /* Create a mapping for the kernel. */ | |
130 | mmubooke_create_initial_mapping(env, 0, 0); | |
131 | env->gpr[6] = tswap32(EPAPR_MAGIC); | |
132 | env->gpr[7] = bi->ima_size; | |
133 | } | |
134 | ||
135 | #define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb" | |
a8170e5e | 136 | static int xilinx_load_device_tree(hwaddr addr, |
2c50e26e | 137 | uint32_t ramsize, |
a8170e5e AK |
138 | hwaddr initrd_base, |
139 | hwaddr initrd_size, | |
2c50e26e EI |
140 | const char *kernel_cmdline) |
141 | { | |
142 | char *path; | |
143 | int fdt_size; | |
2c50e26e EI |
144 | void *fdt; |
145 | int r; | |
146 | ||
147 | /* Try the local "ppc.dtb" override. */ | |
148 | fdt = load_device_tree("ppc.dtb", &fdt_size); | |
149 | if (!fdt) { | |
150 | path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); | |
151 | if (path) { | |
152 | fdt = load_device_tree(path, &fdt_size); | |
7267c094 | 153 | g_free(path); |
2c50e26e | 154 | } |
3b2e3dc9 | 155 | if (!fdt) { |
2c50e26e | 156 | return 0; |
3b2e3dc9 | 157 | } |
2c50e26e EI |
158 | } |
159 | ||
160 | r = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline); | |
161 | if (r < 0) | |
162 | fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
e1fe50dc | 163 | cpu_physical_memory_write(addr, fdt, fdt_size); |
2c50e26e EI |
164 | return fdt_size; |
165 | } | |
166 | ||
5f072e1f | 167 | static void virtex_init(QEMUMachineInitArgs *args) |
2c50e26e | 168 | { |
5f072e1f EH |
169 | ram_addr_t ram_size = args->ram_size; |
170 | const char *cpu_model = args->cpu_model; | |
171 | const char *kernel_filename = args->kernel_filename; | |
172 | const char *kernel_cmdline = args->kernel_cmdline; | |
39186d8a | 173 | MemoryRegion *address_space_mem = get_system_memory(); |
2c50e26e | 174 | DeviceState *dev; |
68281699 | 175 | PowerPCCPU *cpu; |
e2684c0b | 176 | CPUPPCState *env; |
a8170e5e | 177 | hwaddr ram_base = 0; |
2c50e26e | 178 | DriveInfo *dinfo; |
333b13fc | 179 | MemoryRegion *phys_ram = g_new(MemoryRegion, 1); |
2c50e26e | 180 | qemu_irq irq[32], *cpu_irq; |
2c50e26e EI |
181 | int kernel_size; |
182 | int i; | |
183 | ||
184 | /* init CPUs */ | |
185 | if (cpu_model == NULL) { | |
186 | cpu_model = "440-Xilinx"; | |
187 | } | |
188 | ||
68281699 AF |
189 | cpu = ppc440_init_xilinx(&ram_size, 1, cpu_model, 400000000); |
190 | env = &cpu->env; | |
f8031482 | 191 | qemu_register_reset(main_cpu_reset, cpu); |
2c50e26e | 192 | |
2c9b15ca | 193 | memory_region_init_ram(phys_ram, NULL, "ram", ram_size); |
c5705a77 | 194 | vmstate_register_ram_global(phys_ram); |
333b13fc | 195 | memory_region_add_subregion(address_space_mem, ram_base, phys_ram); |
2c50e26e | 196 | |
2c50e26e | 197 | dinfo = drive_get(IF_PFLASH, 0, 0); |
cfe5f011 | 198 | pflash_cfi01_register(0xfc000000, NULL, "virtex.flash", FLASH_SIZE, |
2c50e26e EI |
199 | dinfo ? dinfo->bdrv : NULL, (64 * 1024), |
200 | FLASH_SIZE >> 16, | |
01e0451a | 201 | 1, 0x89, 0x18, 0x0000, 0x0, 1); |
2c50e26e EI |
202 | |
203 | cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT]; | |
204 | dev = xilinx_intc_create(0x81800000, cpu_irq[0], 0); | |
205 | for (i = 0; i < 32; i++) { | |
206 | irq[i] = qdev_get_gpio_in(dev, i); | |
207 | } | |
208 | ||
39186d8a RH |
209 | serial_mm_init(address_space_mem, 0x83e01003ULL, 2, irq[9], 115200, |
210 | serial_hds[0], DEVICE_LITTLE_ENDIAN); | |
2c50e26e EI |
211 | |
212 | /* 2 timers at irq 2 @ 62 Mhz. */ | |
abe098e4 | 213 | xilinx_timer_create(0x83c00000, irq[3], 0, 62 * 1000000); |
2c50e26e EI |
214 | |
215 | if (kernel_filename) { | |
216 | uint64_t entry, low, high; | |
a8170e5e | 217 | hwaddr boot_offset; |
2c50e26e EI |
218 | |
219 | /* Boots a kernel elf binary. */ | |
220 | kernel_size = load_elf(kernel_filename, NULL, NULL, | |
221 | &entry, &low, &high, 1, ELF_MACHINE, 0); | |
2c50e26e EI |
222 | boot_info.bootstrap_pc = entry & 0x00ffffff; |
223 | ||
224 | if (kernel_size < 0) { | |
225 | boot_offset = 0x1200000; | |
226 | /* If we failed loading ELF's try a raw image. */ | |
227 | kernel_size = load_image_targphys(kernel_filename, | |
228 | boot_offset, | |
229 | ram_size); | |
230 | boot_info.bootstrap_pc = boot_offset; | |
231 | high = boot_info.bootstrap_pc + kernel_size + 8192; | |
232 | } | |
233 | ||
234 | boot_info.ima_size = kernel_size; | |
235 | ||
236 | /* Provide a device-tree. */ | |
237 | boot_info.fdt = high + (8192 * 2); | |
238 | boot_info.fdt &= ~8191; | |
239 | xilinx_load_device_tree(boot_info.fdt, ram_size, 0, 0, kernel_cmdline); | |
240 | } | |
241 | env->load_info = &boot_info; | |
242 | } | |
243 | ||
244 | static QEMUMachine virtex_machine = { | |
245 | .name = "virtex-ml507", | |
246 | .desc = "Xilinx Virtex ML507 reference design", | |
247 | .init = virtex_init, | |
248 | }; | |
249 | ||
250 | static void virtex_machine_init(void) | |
251 | { | |
252 | qemu_register_machine(&virtex_machine); | |
253 | } | |
254 | ||
255 | machine_init(virtex_machine_init); |