[qemu.git] / target-mips / op_helper.c

/*
 *  MIPS emulation helpers for qemu.
 * 
 *  Copyright (c) 2004-2005 Jocelyn Mayer
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <stdlib.h>
#include "exec.h"

#define GETPC() (__builtin_return_address(0))

/*****************************************************************************/
/* Exceptions processing helpers */
void cpu_loop_exit(void)
{
    longjmp(env->jmp_env, 1);
}

void do_raise_exception_err (uint32_t exception, int error_code)
{
#if 1
    if (logfile && exception < 0x100)
        fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
#endif
    env->exception_index = exception;
    env->error_code = error_code;
    T0 = 0;
    cpu_loop_exit();
}

void do_raise_exception (uint32_t exception)
{
    do_raise_exception_err(exception, 0);
}

void do_restore_state (void *pc_ptr)
{
  TranslationBlock *tb;
  unsigned long pc = (unsigned long) pc_ptr;

  tb = tb_find_pc (pc);
  cpu_restore_state (tb, env, pc, NULL);
}

void do_raise_exception_direct_err (uint32_t exception, int error_code)
{
    do_restore_state (GETPC ());
    do_raise_exception_err (exception, error_code);
}

void do_raise_exception_direct (uint32_t exception)
{
    do_raise_exception_direct_err (exception, 0);
}

#define MEMSUFFIX _raw
#include "op_helper_mem.c"
#undef MEMSUFFIX
#if !defined(CONFIG_USER_ONLY)
#define MEMSUFFIX _user
#include "op_helper_mem.c"
#undef MEMSUFFIX
#define MEMSUFFIX _kernel
#include "op_helper_mem.c"
#undef MEMSUFFIX
#endif

#ifdef TARGET_MIPS64
#if TARGET_LONG_BITS > HOST_LONG_BITS
/* Those might call libgcc functions.  */
void do_dsll (void)
{
    T0 = T0 << T1;
}

void do_dsll32 (void)
{
    T0 = T0 << (T1 + 32);
}

void do_dsra (void)
{
    T0 = (int64_t)T0 >> T1;
}

void do_dsra32 (void)
{
    T0 = (int64_t)T0 >> (T1 + 32);
}

void do_dsrl (void)
{
    T0 = T0 >> T1;
}

void do_dsrl32 (void)
{
    T0 = T0 >> (T1 + 32);
}

void do_drotr (void)
{
    target_ulong tmp;

    if (T1) {
       tmp = T0 << (0x40 - T1);
       T0 = (T0 >> T1) | tmp;
    }
}

void do_drotr32 (void)
{
    target_ulong tmp;

    if (T1) {
       tmp = T0 << (0x40 - (32 + T1));
       T0 = (T0 >> (32 + T1)) | tmp;
    }
}

void do_dsllv (void)
{
    T0 = T1 << (T0 & 0x3F);
}

void do_dsrav (void)
{
    T0 = (int64_t)T1 >> (T0 & 0x3F);
}

void do_dsrlv (void)
{
    T0 = T1 >> (T0 & 0x3F);
}

void do_drotrv (void)
{
    target_ulong tmp;

    T0 &= 0x3F;
    if (T0) {
       tmp = T1 << (0x40 - T0);
       T0 = (T1 >> T0) | tmp;
    } else
       T0 = T1;
}
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
#endif /* TARGET_MIPS64 */

/* 64 bits arithmetic for 32 bits hosts */
#if TARGET_LONG_BITS > HOST_LONG_BITS
static inline uint64_t get_HILO (void)
{
    return (env->HI << 32) | (uint32_t)env->LO;
}

static inline void set_HILO (uint64_t HILO)
{
    env->LO = (int32_t)HILO;
    env->HI = (int32_t)(HILO >> 32);
}

void do_mult (void)
{
    set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
}

void do_multu (void)
{
    set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
}

void do_madd (void)
{
    int64_t tmp;

    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
    set_HILO((int64_t)get_HILO() + tmp);
}

void do_maddu (void)
{
    uint64_t tmp;

    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
    set_HILO(get_HILO() + tmp);
}

void do_msub (void)
{
    int64_t tmp;

    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
    set_HILO((int64_t)get_HILO() - tmp);
}

void do_msubu (void)
{
    uint64_t tmp;

    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
    set_HILO(get_HILO() - tmp);
}
#endif

#if HOST_LONG_BITS < 64
void do_div (void)
{
    /* 64bit datatypes because we may see overflow/underflow. */
    if (T1 != 0) {
        env->LO = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
        env->HI = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
    }
}
#endif

#ifdef TARGET_MIPS64
void do_dmult (void)
{
    env->LO = (int64_t)T0 * (int64_t)T1;
    /* XXX */
    env->HI = (env->LO | (1ULL << 63)) ? ~0ULL : 0ULL;
}

void do_dmultu (void)
{
    env->LO = T0 * T1;
    /* XXX */
    env->HI = 0;
}

void do_ddiv (void)
{
    if (T1 != 0) {
        lldiv_t res = lldiv((int64_t)T0, (int64_t)T1);
        env->LO = res.quot;
        env->HI = res.rem;
    }
}

void do_ddivu (void)
{
    if (T1 != 0) {
        /* XXX: lldivu? */
        lldiv_t res = lldiv(T0, T1);
        env->LO = (uint64_t)res.quot;
        env->HI = (uint64_t)res.rem;
    }
}
#endif

#if defined(CONFIG_USER_ONLY) 
void do_mfc0_random (void)
{
    cpu_abort(env, "mfc0 random\n");
}

void do_mfc0_count (void)
{
    cpu_abort(env, "mfc0 count\n");
}

void cpu_mips_store_count(CPUState *env, uint32_t value)
{
    cpu_abort(env, "mtc0 count\n");
}

void cpu_mips_store_compare(CPUState *env, uint32_t value)
{
    cpu_abort(env, "mtc0 compare\n");
}

void cpu_mips_update_irq(CPUState *env)
{
    cpu_abort(env, "mtc0 status / mtc0 cause\n");
}

void do_mtc0_status_debug(uint32_t old, uint32_t val)
{
    cpu_abort(env, "mtc0 status debug\n");
}

void do_mtc0_status_irqraise_debug (void)
{
    cpu_abort(env, "mtc0 status irqraise debug\n");
}

void do_tlbwi (void)
{
    cpu_abort(env, "tlbwi\n");
}

void do_tlbwr (void)
{
    cpu_abort(env, "tlbwr\n");
}

void do_tlbp (void)
{
    cpu_abort(env, "tlbp\n");
}

void do_tlbr (void)
{
    cpu_abort(env, "tlbr\n");
}

void cpu_mips_tlb_flush (CPUState *env, int flush_global)
{
    cpu_abort(env, "mips_tlb_flush\n");
}

#else

/* CP0 helpers */
void do_mfc0_random (void)
{
    T0 = (int32_t)cpu_mips_get_random(env);
}

void do_mfc0_count (void)
{
    T0 = (int32_t)cpu_mips_get_count(env);
}

void do_mtc0_status_debug(uint32_t old, uint32_t val)
{
    fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
            old, old & env->CP0_Cause & CP0Ca_IP_mask,
            val, val & env->CP0_Cause & CP0Ca_IP_mask,
            env->CP0_Cause);
    (env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
                                  : fputs("\n", logfile);
}

void do_mtc0_status_irqraise_debug(void)
{
    fprintf(logfile, "Raise pending IRQs\n");
}

void fpu_handle_exception(void)
{
#ifdef CONFIG_SOFTFLOAT
    int flags = get_float_exception_flags(&env->fp_status);
    unsigned int cpuflags = 0, enable, cause = 0;

    enable = GET_FP_ENABLE(env->fcr31);

    /* determine current flags */   
    if (flags & float_flag_invalid) {
        cpuflags |= FP_INVALID;
        cause |= FP_INVALID & enable;
    }
    if (flags & float_flag_divbyzero) {
        cpuflags |= FP_DIV0;    
        cause |= FP_DIV0 & enable;
    }
    if (flags & float_flag_overflow) {
        cpuflags |= FP_OVERFLOW;    
        cause |= FP_OVERFLOW & enable;
    }
    if (flags & float_flag_underflow) {
        cpuflags |= FP_UNDERFLOW;   
        cause |= FP_UNDERFLOW & enable;
    }
    if (flags & float_flag_inexact) {
        cpuflags |= FP_INEXACT; 
        cause |= FP_INEXACT & enable;
    }
    SET_FP_FLAGS(env->fcr31, cpuflags);
    SET_FP_CAUSE(env->fcr31, cause);
#else
    SET_FP_FLAGS(env->fcr31, 0);
    SET_FP_CAUSE(env->fcr31, 0);
#endif
}

/* TLB management */
#if defined(MIPS_USES_R4K_TLB)
void cpu_mips_tlb_flush (CPUState *env, int flush_global)
{
    /* Flush qemu's TLB and discard all shadowed entries.  */
    tlb_flush (env, flush_global);
    env->tlb_in_use = env->nb_tlb;
}

static void mips_tlb_flush_extra (CPUState *env, int first)
{
    /* Discard entries from env->tlb[first] onwards.  */
    while (env->tlb_in_use > first) {
        invalidate_tlb(env, --env->tlb_in_use, 0);
    }
}

static void fill_tlb (int idx)
{
    tlb_t *tlb;

    /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
    tlb = &env->tlb[idx];
    tlb->VPN = env->CP0_EntryHi & ~(target_ulong)0x1FFF;
    tlb->ASID = env->CP0_EntryHi & 0xFF;
    tlb->PageMask = env->CP0_PageMask;
    tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
    tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
    tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
    tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
    tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
    tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
    tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
    tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
    tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
}

void do_tlbwi (void)
{
    /* Discard cached TLB entries.  We could avoid doing this if the
       tlbwi is just upgrading access permissions on the current entry;
       that might be a further win.  */
    mips_tlb_flush_extra (env, env->nb_tlb);

    invalidate_tlb(env, env->CP0_Index % env->nb_tlb, 0);
    fill_tlb(env->CP0_Index % env->nb_tlb);
}

void do_tlbwr (void)
{
    int r = cpu_mips_get_random(env);

    invalidate_tlb(env, r, 1);
    fill_tlb(r);
}

void do_tlbp (void)
{
    tlb_t *tlb;
    target_ulong tag;
    uint8_t ASID;
    int i;

    tag = env->CP0_EntryHi & (int32_t)0xFFFFE000;
    ASID = env->CP0_EntryHi & 0xFF;
    for (i = 0; i < env->nb_tlb; i++) {
        tlb = &env->tlb[i];
        /* Check ASID, virtual page number & size */
        if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
            /* TLB match */
            env->CP0_Index = i;
            break;
        }
    }
    if (i == env->nb_tlb) {
        /* No match.  Discard any shadow entries, if any of them match.  */
        for (i = env->nb_tlb; i < env->tlb_in_use; i++) {
	    tlb = &env->tlb[i];

	    /* Check ASID, virtual page number & size */
	    if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
                mips_tlb_flush_extra (env, i);
	        break;
	    }
	}

        env->CP0_Index |= 0x80000000;
    }
}

void do_tlbr (void)
{
    tlb_t *tlb;
    uint8_t ASID;

    ASID = env->CP0_EntryHi & 0xFF;
    tlb = &env->tlb[env->CP0_Index % env->nb_tlb];

    /* If this will change the current ASID, flush qemu's TLB.  */
    if (ASID != tlb->ASID)
        cpu_mips_tlb_flush (env, 1);

    mips_tlb_flush_extra(env, env->nb_tlb);

    env->CP0_EntryHi = tlb->VPN | tlb->ASID;
    env->CP0_PageMask = tlb->PageMask;
    env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
                        (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
    env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
                        (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
}
#endif

#endif /* !CONFIG_USER_ONLY */

void dump_ldst (const unsigned char *func)
{
    if (loglevel)
        fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
}

void dump_sc (void)
{
    if (loglevel) {
        fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
                T1, T0, env->CP0_LLAddr);
    }
}

void debug_pre_eret (void)
{
    fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
            env->PC, env->CP0_EPC);
    if (env->CP0_Status & (1 << CP0St_ERL))
        fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
    if (env->hflags & MIPS_HFLAG_DM)
        fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
    fputs("\n", logfile);
}

void debug_post_eret (void)
{
    fprintf(logfile, "  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
            env->PC, env->CP0_EPC);
    if (env->CP0_Status & (1 << CP0St_ERL))
        fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
    if (env->hflags & MIPS_HFLAG_DM)
        fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
    if (env->hflags & MIPS_HFLAG_UM)
        fputs(", UM\n", logfile);
    else
        fputs("\n", logfile);
}

void do_pmon (int function)
{
    function /= 2;
    switch (function) {
    case 2: /* TODO: char inbyte(int waitflag); */
        if (env->gpr[4] == 0)
            env->gpr[2] = -1;
        /* Fall through */
    case 11: /* TODO: char inbyte (void); */
        env->gpr[2] = -1;
        break;
    case 3:
    case 12:
        printf("%c", (char)(env->gpr[4] & 0xFF));
        break;
    case 17:
        break;
    case 158:
        {
            unsigned char *fmt = (void *)(unsigned long)env->gpr[4];
            printf("%s", fmt);
        }
        break;
    }
}

#if !defined(CONFIG_USER_ONLY) 

static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);

#define MMUSUFFIX _mmu
#define ALIGNED_ONLY

#define SHIFT 0
#include "softmmu_template.h"

#define SHIFT 1
#include "softmmu_template.h"

#define SHIFT 2
#include "softmmu_template.h"

#define SHIFT 3
#include "softmmu_template.h"

static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
{
    env->CP0_BadVAddr = addr;
    do_restore_state (retaddr);
    do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
}

void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
{
    TranslationBlock *tb;
    CPUState *saved_env;
    unsigned long pc;
    int ret;

    /* XXX: hack to restore env in all cases, even if not called from
       generated code */
    saved_env = env;
    env = cpu_single_env;
    ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
    if (ret) {
        if (retaddr) {
            /* now we have a real cpu fault */
            pc = (unsigned long)retaddr;
            tb = tb_find_pc(pc);
            if (tb) {
                /* the PC is inside the translated code. It means that we have
                   a virtual CPU fault */
                cpu_restore_state(tb, env, pc, NULL);
            }
        }
        do_raise_exception_err(env->exception_index, env->error_code);
    }
    env = saved_env;
}

#endif
Commit	Line	Data
6af0bf9c FB	1	/*
	2	* MIPS emulation helpers for qemu.
	3	*
	4	* Copyright (c) 2004-2005 Jocelyn Mayer
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
2d0e944d	20	#include <stdlib.h>
6af0bf9c FB	21	#include "exec.h"
6af0bf9c FB	22
4ad40f36 FB	23	#define GETPC() (__builtin_return_address(0))
4ad40f36 FB	24
6af0bf9c FB	25	/*****************************************************************************/
	26	/* Exceptions processing helpers */
	27	void cpu_loop_exit(void)
	28	{
	29	longjmp(env->jmp_env, 1);
	30	}
	31
6af0bf9c FB	32	void do_raise_exception_err (uint32_t exception, int error_code)
	33	{
	34	#if 1
	35	if (logfile && exception < 0x100)
	36	fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
	37	#endif
	38	env->exception_index = exception;
	39	env->error_code = error_code;
	40	T0 = 0;
	41	cpu_loop_exit();
	42	}
	43
6af0bf9c FB	44	void do_raise_exception (uint32_t exception)
	45	{
	46	do_raise_exception_err(exception, 0);
	47	}
	48
4ad40f36 FB	49	void do_restore_state (void *pc_ptr)
	50	{
	51	TranslationBlock *tb;
	52	unsigned long pc = (unsigned long) pc_ptr;
	53
	54	tb = tb_find_pc (pc);
	55	cpu_restore_state (tb, env, pc, NULL);
	56	}
	57
e397ee33	58	void do_raise_exception_direct_err (uint32_t exception, int error_code)
4ad40f36 FB	59	{
4ad40f36 FB	60	do_restore_state (GETPC ());
e397ee33 TS	61	do_raise_exception_err (exception, error_code);
	62	}
	63
	64	void do_raise_exception_direct (uint32_t exception)
	65	{
	66	do_raise_exception_direct_err (exception, 0);
4ad40f36 FB	67	}
4ad40f36 FB	68
6af0bf9c FB	69	#define MEMSUFFIX _raw
	70	#include "op_helper_mem.c"
	71	#undef MEMSUFFIX
	72	#if !defined(CONFIG_USER_ONLY)
	73	#define MEMSUFFIX _user
	74	#include "op_helper_mem.c"
	75	#undef MEMSUFFIX
	76	#define MEMSUFFIX _kernel
	77	#include "op_helper_mem.c"
	78	#undef MEMSUFFIX
	79	#endif
	80
60aa19ab	81	#ifdef TARGET_MIPS64
c570fd16 TS	82	#if TARGET_LONG_BITS > HOST_LONG_BITS
	83	/* Those might call libgcc functions. */
	84	void do_dsll (void)
	85	{
	86	T0 = T0 << T1;
	87	}
	88
	89	void do_dsll32 (void)
	90	{
	91	T0 = T0 << (T1 + 32);
	92	}
	93
	94	void do_dsra (void)
	95	{
	96	T0 = (int64_t)T0 >> T1;
	97	}
	98
	99	void do_dsra32 (void)
	100	{
	101	T0 = (int64_t)T0 >> (T1 + 32);
	102	}
	103
	104	void do_dsrl (void)
	105	{
	106	T0 = T0 >> T1;
	107	}
	108
	109	void do_dsrl32 (void)
	110	{
	111	T0 = T0 >> (T1 + 32);
	112	}
	113
	114	void do_drotr (void)
	115	{
	116	target_ulong tmp;
	117
	118	if (T1) {
	119	tmp = T0 << (0x40 - T1);
	120	T0 = (T0 >> T1) \| tmp;
5a63bcb2	121	}
c570fd16 TS	122	}
	123
	124	void do_drotr32 (void)
	125	{
	126	target_ulong tmp;
	127
	128	if (T1) {
	129	tmp = T0 << (0x40 - (32 + T1));
	130	T0 = (T0 >> (32 + T1)) \| tmp;
5a63bcb2	131	}
c570fd16 TS	132	}
	133
	134	void do_dsllv (void)
	135	{
	136	T0 = T1 << (T0 & 0x3F);
	137	}
	138
	139	void do_dsrav (void)
	140	{
	141	T0 = (int64_t)T1 >> (T0 & 0x3F);
	142	}
	143
	144	void do_dsrlv (void)
	145	{
	146	T0 = T1 >> (T0 & 0x3F);
	147	}
	148
	149	void do_drotrv (void)
	150	{
	151	target_ulong tmp;
	152
	153	T0 &= 0x3F;
	154	if (T0) {
	155	tmp = T1 << (0x40 - T0);
	156	T0 = (T1 >> T0) \| tmp;
	157	} else
	158	T0 = T1;
	159	}
	160	#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
60aa19ab	161	#endif /* TARGET_MIPS64 */
c570fd16	162
6af0bf9c	163	/* 64 bits arithmetic for 32 bits hosts */
c570fd16	164	#if TARGET_LONG_BITS > HOST_LONG_BITS
6af0bf9c FB	165	static inline uint64_t get_HILO (void)
6af0bf9c FB	166	{
7495fd0f	167	return (env->HI << 32) \| (uint32_t)env->LO;
6af0bf9c FB	168	}
	169
	170	static inline void set_HILO (uint64_t HILO)
	171	{
7495fd0f	172	env->LO = (int32_t)HILO;
5dc4b744	173	env->HI = (int32_t)(HILO >> 32);
6af0bf9c FB	174	}
	175
	176	void do_mult (void)
	177	{
4ad40f36	178	set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c FB	179	}
	180
	181	void do_multu (void)
	182	{
c570fd16	183	set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c FB	184	}
	185
	186	void do_madd (void)
	187	{
	188	int64_t tmp;
	189
4ad40f36	190	tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c FB	191	set_HILO((int64_t)get_HILO() + tmp);
	192	}
	193
	194	void do_maddu (void)
	195	{
	196	uint64_t tmp;
	197
c570fd16	198	tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c FB	199	set_HILO(get_HILO() + tmp);
	200	}
	201
	202	void do_msub (void)
	203	{
	204	int64_t tmp;
	205
4ad40f36	206	tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c FB	207	set_HILO((int64_t)get_HILO() - tmp);
	208	}
	209
	210	void do_msubu (void)
	211	{
	212	uint64_t tmp;
	213
c570fd16	214	tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c FB	215	set_HILO(get_HILO() - tmp);
	216	}
	217	#endif
	218
80c27194 TS	219	#if HOST_LONG_BITS < 64
	220	void do_div (void)
	221	{
	222	/* 64bit datatypes because we may see overflow/underflow. */
	223	if (T1 != 0) {
	224	env->LO = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
	225	env->HI = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
	226	}
	227	}
	228	#endif
	229
60aa19ab	230	#ifdef TARGET_MIPS64
c570fd16 TS	231	void do_dmult (void)
c570fd16 TS	232	{
2d0e944d	233	env->LO = (int64_t)T0 * (int64_t)T1;
c570fd16	234	/* XXX */
2d0e944d	235	env->HI = (env->LO \| (1ULL << 63)) ? ~0ULL : 0ULL;
c570fd16 TS	236	}
	237
	238	void do_dmultu (void)
	239	{
2d0e944d	240	env->LO = T0 * T1;
c570fd16	241	/* XXX */
2d0e944d	242	env->HI = 0;
c570fd16 TS	243	}
	244
	245	void do_ddiv (void)
	246	{
	247	if (T1 != 0) {
2d0e944d TS	248	lldiv_t res = lldiv((int64_t)T0, (int64_t)T1);
	249	env->LO = res.quot;
	250	env->HI = res.rem;
c570fd16 TS	251	}
	252	}
	253
	254	void do_ddivu (void)
	255	{
	256	if (T1 != 0) {
2d0e944d TS	257	/* XXX: lldivu? */
	258	lldiv_t res = lldiv(T0, T1);
	259	env->LO = (uint64_t)res.quot;
	260	env->HI = (uint64_t)res.rem;
c570fd16 TS	261	}
	262	}
	263	#endif
	264
048f6b4d	265	#if defined(CONFIG_USER_ONLY)
873eb012	266	void do_mfc0_random (void)
048f6b4d	267	{
873eb012	268	cpu_abort(env, "mfc0 random\n");
048f6b4d	269	}
873eb012 TS	270
	271	void do_mfc0_count (void)
	272	{
	273	cpu_abort(env, "mfc0 count\n");
	274	}
	275
8c0fdd85	276	void cpu_mips_store_count(CPUState *env, uint32_t value)
048f6b4d	277	{
8c0fdd85 TS	278	cpu_abort(env, "mtc0 count\n");
	279	}
	280
	281	void cpu_mips_store_compare(CPUState *env, uint32_t value)
	282	{
	283	cpu_abort(env, "mtc0 compare\n");
	284	}
	285
4de9b249 TS	286	void cpu_mips_update_irq(CPUState *env)
	287	{
	288	cpu_abort(env, "mtc0 status / mtc0 cause\n");
	289	}
	290
8c0fdd85 TS	291	void do_mtc0_status_debug(uint32_t old, uint32_t val)
8c0fdd85 TS	292	{
7a387fff	293	cpu_abort(env, "mtc0 status debug\n");
8c0fdd85 TS	294	}
8c0fdd85 TS	295
7a387fff	296	void do_mtc0_status_irqraise_debug (void)
8c0fdd85	297	{
7a387fff	298	cpu_abort(env, "mtc0 status irqraise debug\n");
048f6b4d FB	299	}
	300
	301	void do_tlbwi (void)
	302	{
	303	cpu_abort(env, "tlbwi\n");
	304	}
	305
	306	void do_tlbwr (void)
	307	{
	308	cpu_abort(env, "tlbwr\n");
	309	}
	310
	311	void do_tlbp (void)
	312	{
	313	cpu_abort(env, "tlbp\n");
	314	}
	315
	316	void do_tlbr (void)
	317	{
	318	cpu_abort(env, "tlbr\n");
	319	}
873eb012	320
8c0fdd85 TS	321	void cpu_mips_tlb_flush (CPUState *env, int flush_global)
	322	{
	323	cpu_abort(env, "mips_tlb_flush\n");
	324	}
	325
048f6b4d FB	326	#else
048f6b4d FB	327
6af0bf9c	328	/* CP0 helpers */
873eb012	329	void do_mfc0_random (void)
6af0bf9c	330	{
5dc4b744	331	T0 = (int32_t)cpu_mips_get_random(env);
873eb012	332	}
6af0bf9c	333
873eb012 TS	334	void do_mfc0_count (void)
873eb012 TS	335	{
5dc4b744	336	T0 = (int32_t)cpu_mips_get_count(env);
6af0bf9c FB	337	}
6af0bf9c FB	338
8c0fdd85	339	void do_mtc0_status_debug(uint32_t old, uint32_t val)
6af0bf9c	340	{
f41c52f1 TS	341	fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
	342	old, old & env->CP0_Cause & CP0Ca_IP_mask,
	343	val, val & env->CP0_Cause & CP0Ca_IP_mask,
	344	env->CP0_Cause);
	345	(env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
	346	: fputs("\n", logfile);
8c0fdd85 TS	347	}
	348
	349	void do_mtc0_status_irqraise_debug(void)
	350	{
	351	fprintf(logfile, "Raise pending IRQs\n");
6af0bf9c FB	352	}
6af0bf9c FB	353
6ea83fed FB	354	void fpu_handle_exception(void)
	355	{
	356	#ifdef CONFIG_SOFTFLOAT
	357	int flags = get_float_exception_flags(&env->fp_status);
	358	unsigned int cpuflags = 0, enable, cause = 0;
	359
	360	enable = GET_FP_ENABLE(env->fcr31);
	361
	362	/* determine current flags */
	363	if (flags & float_flag_invalid) {
	364	cpuflags \|= FP_INVALID;
	365	cause \|= FP_INVALID & enable;
	366	}
	367	if (flags & float_flag_divbyzero) {
	368	cpuflags \|= FP_DIV0;
	369	cause \|= FP_DIV0 & enable;
	370	}
	371	if (flags & float_flag_overflow) {
	372	cpuflags \|= FP_OVERFLOW;
	373	cause \|= FP_OVERFLOW & enable;
	374	}
	375	if (flags & float_flag_underflow) {
	376	cpuflags \|= FP_UNDERFLOW;
	377	cause \|= FP_UNDERFLOW & enable;
	378	}
	379	if (flags & float_flag_inexact) {
	380	cpuflags \|= FP_INEXACT;
	381	cause \|= FP_INEXACT & enable;
	382	}
	383	SET_FP_FLAGS(env->fcr31, cpuflags);
	384	SET_FP_CAUSE(env->fcr31, cause);
	385	#else
	386	SET_FP_FLAGS(env->fcr31, 0);
	387	SET_FP_CAUSE(env->fcr31, 0);
	388	#endif
	389	}
6ea83fed	390
6af0bf9c FB	391	/* TLB management */
6af0bf9c FB	392	#if defined(MIPS_USES_R4K_TLB)
814b9a47 TS	393	void cpu_mips_tlb_flush (CPUState *env, int flush_global)
	394	{
	395	/* Flush qemu's TLB and discard all shadowed entries. */
	396	tlb_flush (env, flush_global);
fcb4a419	397	env->tlb_in_use = env->nb_tlb;
814b9a47 TS	398	}
814b9a47 TS	399
814b9a47 TS	400	static void mips_tlb_flush_extra (CPUState *env, int first)
	401	{
	402	/* Discard entries from env->tlb[first] onwards. */
	403	while (env->tlb_in_use > first) {
2ee4aed8	404	invalidate_tlb(env, --env->tlb_in_use, 0);
814b9a47 TS	405	}
	406	}
	407
98c1b82b	408	static void fill_tlb (int idx)
6af0bf9c FB	409	{
6af0bf9c FB	410	tlb_t *tlb;
6af0bf9c FB	411
	412	/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
	413	tlb = &env->tlb[idx];
925fd0f2	414	tlb->VPN = env->CP0_EntryHi & ~(target_ulong)0x1FFF;
98c1b82b	415	tlb->ASID = env->CP0_EntryHi & 0xFF;
3b1c8be4	416	tlb->PageMask = env->CP0_PageMask;
6af0bf9c	417	tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
98c1b82b PB	418	tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
	419	tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
	420	tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
6af0bf9c	421	tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
98c1b82b PB	422	tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
	423	tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
	424	tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
6af0bf9c FB	425	tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
	426	}
	427
	428	void do_tlbwi (void)
	429	{
814b9a47 TS	430	/* Discard cached TLB entries. We could avoid doing this if the
	431	tlbwi is just upgrading access permissions on the current entry;
	432	that might be a further win. */
fcb4a419	433	mips_tlb_flush_extra (env, env->nb_tlb);
814b9a47	434
fcb4a419 TS	435	invalidate_tlb(env, env->CP0_Index % env->nb_tlb, 0);
fcb4a419 TS	436	fill_tlb(env->CP0_Index % env->nb_tlb);
6af0bf9c FB	437	}
	438
	439	void do_tlbwr (void)
	440	{
	441	int r = cpu_mips_get_random(env);
	442
2ee4aed8	443	invalidate_tlb(env, r, 1);
98c1b82b	444	fill_tlb(r);
6af0bf9c FB	445	}
	446
	447	void do_tlbp (void)
	448	{
	449	tlb_t *tlb;
	450	target_ulong tag;
	451	uint8_t ASID;
	452	int i;
	453
5dc4b744	454	tag = env->CP0_EntryHi & (int32_t)0xFFFFE000;
3d9fb9fe	455	ASID = env->CP0_EntryHi & 0xFF;
fcb4a419	456	for (i = 0; i < env->nb_tlb; i++) {
6af0bf9c FB	457	tlb = &env->tlb[i];
	458	/* Check ASID, virtual page number & size */
	459	if ((tlb->G == 1 \|\| tlb->ASID == ASID) && tlb->VPN == tag) {
	460	/* TLB match */
9c2149c8	461	env->CP0_Index = i;
6af0bf9c FB	462	break;
	463	}
	464	}
fcb4a419	465	if (i == env->nb_tlb) {
814b9a47	466	/* No match. Discard any shadow entries, if any of them match. */
fcb4a419	467	for (i = env->nb_tlb; i < env->tlb_in_use; i++) {
814b9a47 TS	468	tlb = &env->tlb[i];
	469
	470	/* Check ASID, virtual page number & size */
	471	if ((tlb->G == 1 \|\| tlb->ASID == ASID) && tlb->VPN == tag) {
	472	mips_tlb_flush_extra (env, i);
	473	break;
	474	}
	475	}
	476
9c2149c8	477	env->CP0_Index \|= 0x80000000;
6af0bf9c FB	478	}
	479	}
	480
	481	void do_tlbr (void)
	482	{
	483	tlb_t *tlb;
09c56b84	484	uint8_t ASID;
6af0bf9c	485
09c56b84	486	ASID = env->CP0_EntryHi & 0xFF;
fcb4a419	487	tlb = &env->tlb[env->CP0_Index % env->nb_tlb];
4ad40f36 FB	488
4ad40f36 FB	489	/* If this will change the current ASID, flush qemu's TLB. */
814b9a47 TS	490	if (ASID != tlb->ASID)
	491	cpu_mips_tlb_flush (env, 1);
	492
fcb4a419	493	mips_tlb_flush_extra(env, env->nb_tlb);
4ad40f36	494
6af0bf9c	495	env->CP0_EntryHi = tlb->VPN \| tlb->ASID;
3b1c8be4	496	env->CP0_PageMask = tlb->PageMask;
7495fd0f TS	497	env->CP0_EntryLo0 = tlb->G \| (tlb->V0 << 1) \| (tlb->D0 << 2) \|
	498	(tlb->C0 << 3) \| (tlb->PFN[0] >> 6);
	499	env->CP0_EntryLo1 = tlb->G \| (tlb->V1 << 1) \| (tlb->D1 << 2) \|
	500	(tlb->C1 << 3) \| (tlb->PFN[1] >> 6);
6af0bf9c FB	501	}
	502	#endif
	503
048f6b4d FB	504	#endif /* !CONFIG_USER_ONLY */
048f6b4d FB	505
c570fd16	506	void dump_ldst (const unsigned char *func)
6af0bf9c FB	507	{
6af0bf9c FB	508	if (loglevel)
3594c774	509	fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
6af0bf9c FB	510	}
	511
	512	void dump_sc (void)
	513	{
	514	if (loglevel) {
3594c774	515	fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
6af0bf9c FB	516	T1, T0, env->CP0_LLAddr);
	517	}
	518	}
	519
f41c52f1	520	void debug_pre_eret (void)
6af0bf9c	521	{
f41c52f1 TS	522	fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
	523	env->PC, env->CP0_EPC);
	524	if (env->CP0_Status & (1 << CP0St_ERL))
	525	fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
	526	if (env->hflags & MIPS_HFLAG_DM)
	527	fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
	528	fputs("\n", logfile);
	529	}
	530
	531	void debug_post_eret (void)
	532	{
744e0915	533	fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
f41c52f1 TS	534	env->PC, env->CP0_EPC);
	535	if (env->CP0_Status & (1 << CP0St_ERL))
	536	fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
	537	if (env->hflags & MIPS_HFLAG_DM)
	538	fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
	539	if (env->hflags & MIPS_HFLAG_UM)
	540	fputs(", UM\n", logfile);
	541	else
24c7b0e3	542	fputs("\n", logfile);
6af0bf9c FB	543	}
6af0bf9c FB	544
6af0bf9c FB	545	void do_pmon (int function)
	546	{
	547	function /= 2;
	548	switch (function) {
	549	case 2: /* TODO: char inbyte(int waitflag); */
	550	if (env->gpr[4] == 0)
	551	env->gpr[2] = -1;
	552	/* Fall through */
	553	case 11: /* TODO: char inbyte (void); */
	554	env->gpr[2] = -1;
	555	break;
	556	case 3:
	557	case 12:
c570fd16	558	printf("%c", (char)(env->gpr[4] & 0xFF));
6af0bf9c FB	559	break;
	560	case 17:
	561	break;
	562	case 158:
	563	{
c570fd16	564	unsigned char fmt = (void )(unsigned long)env->gpr[4];
6af0bf9c FB	565	printf("%s", fmt);
	566	}
	567	break;
	568	}
	569	}
e37e863f FB	570
	571	#if !defined(CONFIG_USER_ONLY)
	572
4ad40f36 FB	573	static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
4ad40f36 FB	574
e37e863f	575	#define MMUSUFFIX _mmu
4ad40f36	576	#define ALIGNED_ONLY
e37e863f FB	577
	578	#define SHIFT 0
	579	#include "softmmu_template.h"
	580
	581	#define SHIFT 1
	582	#include "softmmu_template.h"
	583
	584	#define SHIFT 2
	585	#include "softmmu_template.h"
	586
	587	#define SHIFT 3
	588	#include "softmmu_template.h"
	589
4ad40f36 FB	590	static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
	591	{
	592	env->CP0_BadVAddr = addr;
	593	do_restore_state (retaddr);
	594	do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
	595	}
	596
e37e863f FB	597	void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
	598	{
	599	TranslationBlock *tb;
	600	CPUState *saved_env;
	601	unsigned long pc;
	602	int ret;
	603
	604	/* XXX: hack to restore env in all cases, even if not called from
	605	generated code */
	606	saved_env = env;
	607	env = cpu_single_env;
	608	ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
	609	if (ret) {
	610	if (retaddr) {
	611	/* now we have a real cpu fault */
	612	pc = (unsigned long)retaddr;
	613	tb = tb_find_pc(pc);
	614	if (tb) {
	615	/* the PC is inside the translated code. It means that we have
	616	a virtual CPU fault */
	617	cpu_restore_state(tb, env, pc, NULL);
	618	}
	619	}
	620	do_raise_exception_err(env->exception_index, env->error_code);
	621	}
	622	env = saved_env;
	623	}
	624
	625	#endif