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Commit | Line | Data |
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1fc3d392 AJ |
1 | /* |
2 | * QEMU G364 framebuffer Emulator. | |
3 | * | |
97a3f6ff | 4 | * Copyright (c) 2007-2011 Herve Poussineau |
1fc3d392 AJ |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of | |
9 | * the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
fad6cb1a | 16 | * You should have received a copy of the GNU General Public License along |
8167ee88 | 17 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
1fc3d392 AJ |
18 | */ |
19 | ||
47df5154 | 20 | #include "qemu/osdep.h" |
f0353b0d | 21 | #include "qemu/units.h" |
83c9f4ca | 22 | #include "hw/hw.h" |
d49b6836 | 23 | #include "qemu/error-report.h" |
0b8fa32f | 24 | #include "qemu/module.h" |
28ecbaee PB |
25 | #include "ui/console.h" |
26 | #include "ui/pixel_ops.h" | |
b213b370 | 27 | #include "trace.h" |
83c9f4ca | 28 | #include "hw/sysbus.h" |
0add30cf | 29 | |
1fc3d392 | 30 | typedef struct G364State { |
0add30cf AJ |
31 | /* hardware */ |
32 | uint8_t *vram; | |
97a3f6ff | 33 | uint32_t vram_size; |
0add30cf | 34 | qemu_irq irq; |
97a3f6ff HP |
35 | MemoryRegion mem_vram; |
36 | MemoryRegion mem_ctrl; | |
0add30cf AJ |
37 | /* registers */ |
38 | uint8_t color_palette[256][3]; | |
39 | uint8_t cursor_palette[3][3]; | |
40 | uint16_t cursor[512]; | |
41 | uint32_t cursor_position; | |
1fc3d392 | 42 | uint32_t ctla; |
0add30cf AJ |
43 | uint32_t top_of_screen; |
44 | uint32_t width, height; /* in pixels */ | |
1fc3d392 | 45 | /* display refresh support */ |
c78f7137 | 46 | QemuConsole *con; |
0add30cf AJ |
47 | int depth; |
48 | int blanked; | |
1fc3d392 AJ |
49 | } G364State; |
50 | ||
97a3f6ff HP |
51 | #define REG_BOOT 0x000000 |
52 | #define REG_DISPLAY 0x000118 | |
53 | #define REG_VDISPLAY 0x000150 | |
54 | #define REG_CTLA 0x000300 | |
55 | #define REG_TOP 0x000400 | |
56 | #define REG_CURS_PAL 0x000508 | |
57 | #define REG_CURS_POS 0x000638 | |
58 | #define REG_CLR_PAL 0x000800 | |
59 | #define REG_CURS_PAT 0x001000 | |
60 | #define REG_RESET 0x100000 | |
0add30cf AJ |
61 | |
62 | #define CTLA_FORCE_BLANK 0x00000400 | |
63 | #define CTLA_NO_CURSOR 0x00800000 | |
64 | ||
1213406b BS |
65 | #define G364_PAGE_SIZE 4096 |
66 | ||
f7189ac8 | 67 | static inline int check_dirty(G364State *s, DirtyBitmapSnapshot *snap, ram_addr_t page) |
0add30cf | 68 | { |
f7189ac8 | 69 | return memory_region_snapshot_get_dirty(&s->mem_vram, snap, page, G364_PAGE_SIZE); |
0add30cf AJ |
70 | } |
71 | ||
72 | static void g364fb_draw_graphic8(G364State *s) | |
1fc3d392 | 73 | { |
c78f7137 | 74 | DisplaySurface *surface = qemu_console_surface(s->con); |
f7189ac8 | 75 | DirtyBitmapSnapshot *snap; |
0add30cf AJ |
76 | int i, w; |
77 | uint8_t *vram; | |
78 | uint8_t *data_display, *dd; | |
7fcf0c24 | 79 | ram_addr_t page; |
0add30cf AJ |
80 | int x, y; |
81 | int xmin, xmax; | |
82 | int ymin, ymax; | |
83 | int xcursor, ycursor; | |
84 | unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b); | |
85 | ||
c78f7137 | 86 | switch (surface_bits_per_pixel(surface)) { |
1fc3d392 | 87 | case 8: |
0add30cf AJ |
88 | rgb_to_pixel = rgb_to_pixel8; |
89 | w = 1; | |
1fc3d392 AJ |
90 | break; |
91 | case 15: | |
0add30cf AJ |
92 | rgb_to_pixel = rgb_to_pixel15; |
93 | w = 2; | |
1fc3d392 AJ |
94 | break; |
95 | case 16: | |
0add30cf AJ |
96 | rgb_to_pixel = rgb_to_pixel16; |
97 | w = 2; | |
1fc3d392 AJ |
98 | break; |
99 | case 32: | |
0add30cf AJ |
100 | rgb_to_pixel = rgb_to_pixel32; |
101 | w = 4; | |
1fc3d392 AJ |
102 | break; |
103 | default: | |
b213b370 | 104 | hw_error("g364: unknown host depth %d", |
c78f7137 | 105 | surface_bits_per_pixel(surface)); |
1fc3d392 AJ |
106 | return; |
107 | } | |
108 | ||
97a3f6ff | 109 | page = 0; |
0add30cf AJ |
110 | |
111 | x = y = 0; | |
112 | xmin = s->width; | |
113 | xmax = 0; | |
114 | ymin = s->height; | |
115 | ymax = 0; | |
116 | ||
117 | if (!(s->ctla & CTLA_NO_CURSOR)) { | |
118 | xcursor = s->cursor_position >> 12; | |
119 | ycursor = s->cursor_position & 0xfff; | |
120 | } else { | |
121 | xcursor = ycursor = -65; | |
122 | } | |
123 | ||
124 | vram = s->vram + s->top_of_screen; | |
125 | /* XXX: out of range in vram? */ | |
c78f7137 | 126 | data_display = dd = surface_data(surface); |
f7189ac8 PB |
127 | snap = memory_region_snapshot_and_clear_dirty(&s->mem_vram, 0, s->vram_size, |
128 | DIRTY_MEMORY_VGA); | |
0add30cf | 129 | while (y < s->height) { |
f7189ac8 | 130 | if (check_dirty(s, snap, page)) { |
0add30cf AJ |
131 | if (y < ymin) |
132 | ymin = ymax = y; | |
0add30cf AJ |
133 | if (x < xmin) |
134 | xmin = x; | |
1213406b | 135 | for (i = 0; i < G364_PAGE_SIZE; i++) { |
0add30cf AJ |
136 | uint8_t index; |
137 | unsigned int color; | |
138 | if (unlikely((y >= ycursor && y < ycursor + 64) && | |
139 | (x >= xcursor && x < xcursor + 64))) { | |
140 | /* pointer area */ | |
141 | int xdiff = x - xcursor; | |
142 | uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8]; | |
143 | int op = (curs >> ((xdiff & 7) * 2)) & 3; | |
144 | if (likely(op == 0)) { | |
145 | /* transparent */ | |
146 | index = *vram; | |
147 | color = (*rgb_to_pixel)( | |
148 | s->color_palette[index][0], | |
149 | s->color_palette[index][1], | |
150 | s->color_palette[index][2]); | |
151 | } else { | |
152 | /* get cursor color */ | |
153 | index = op - 1; | |
154 | color = (*rgb_to_pixel)( | |
155 | s->cursor_palette[index][0], | |
156 | s->cursor_palette[index][1], | |
157 | s->cursor_palette[index][2]); | |
158 | } | |
159 | } else { | |
160 | /* normal area */ | |
161 | index = *vram; | |
162 | color = (*rgb_to_pixel)( | |
163 | s->color_palette[index][0], | |
164 | s->color_palette[index][1], | |
165 | s->color_palette[index][2]); | |
166 | } | |
167 | memcpy(dd, &color, w); | |
168 | dd += w; | |
169 | x++; | |
170 | vram++; | |
171 | if (x == s->width) { | |
172 | xmax = s->width - 1; | |
173 | y++; | |
174 | if (y == s->height) { | |
175 | ymax = s->height - 1; | |
176 | goto done; | |
177 | } | |
c78f7137 | 178 | data_display = dd = data_display + surface_stride(surface); |
0add30cf AJ |
179 | xmin = 0; |
180 | x = 0; | |
181 | } | |
182 | } | |
183 | if (x > xmax) | |
184 | xmax = x; | |
185 | if (y > ymax) | |
186 | ymax = y; | |
187 | } else { | |
188 | int dy; | |
7fcf0c24 | 189 | if (xmax || ymax) { |
c78f7137 | 190 | dpy_gfx_update(s->con, xmin, ymin, |
a93a4a22 | 191 | xmax - xmin + 1, ymax - ymin + 1); |
0add30cf AJ |
192 | xmin = s->width; |
193 | xmax = 0; | |
194 | ymin = s->height; | |
195 | ymax = 0; | |
196 | } | |
1213406b | 197 | x += G364_PAGE_SIZE; |
0add30cf AJ |
198 | dy = x / s->width; |
199 | x = x % s->width; | |
200 | y += dy; | |
1213406b | 201 | vram += G364_PAGE_SIZE; |
c78f7137 | 202 | data_display += dy * surface_stride(surface); |
0add30cf AJ |
203 | dd = data_display + x * w; |
204 | } | |
1213406b | 205 | page += G364_PAGE_SIZE; |
0add30cf AJ |
206 | } |
207 | ||
208 | done: | |
7fcf0c24 | 209 | if (xmax || ymax) { |
c78f7137 | 210 | dpy_gfx_update(s->con, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); |
0add30cf | 211 | } |
723250d6 | 212 | g_free(snap); |
1fc3d392 AJ |
213 | } |
214 | ||
0add30cf | 215 | static void g364fb_draw_blank(G364State *s) |
1fc3d392 | 216 | { |
c78f7137 | 217 | DisplaySurface *surface = qemu_console_surface(s->con); |
1fc3d392 AJ |
218 | int i, w; |
219 | uint8_t *d; | |
220 | ||
0add30cf AJ |
221 | if (s->blanked) { |
222 | /* Screen is already blank. No need to redraw it */ | |
1fc3d392 | 223 | return; |
0add30cf | 224 | } |
1fc3d392 | 225 | |
c78f7137 GH |
226 | w = s->width * surface_bytes_per_pixel(surface); |
227 | d = surface_data(surface); | |
0add30cf | 228 | for (i = 0; i < s->height; i++) { |
1fc3d392 | 229 | memset(d, 0, w); |
c78f7137 | 230 | d += surface_stride(surface); |
1fc3d392 | 231 | } |
221bb2d5 | 232 | |
91155f8b | 233 | dpy_gfx_update_full(s->con); |
0add30cf | 234 | s->blanked = 1; |
1fc3d392 AJ |
235 | } |
236 | ||
1fc3d392 AJ |
237 | static void g364fb_update_display(void *opaque) |
238 | { | |
239 | G364State *s = opaque; | |
c78f7137 | 240 | DisplaySurface *surface = qemu_console_surface(s->con); |
1fc3d392 | 241 | |
e9a07334 JK |
242 | qemu_flush_coalesced_mmio_buffer(); |
243 | ||
0add30cf | 244 | if (s->width == 0 || s->height == 0) |
221bb2d5 AJ |
245 | return; |
246 | ||
c78f7137 GH |
247 | if (s->width != surface_width(surface) || |
248 | s->height != surface_height(surface)) { | |
249 | qemu_console_resize(s->con, s->width, s->height); | |
221bb2d5 | 250 | } |
0add30cf AJ |
251 | |
252 | if (s->ctla & CTLA_FORCE_BLANK) { | |
253 | g364fb_draw_blank(s); | |
254 | } else if (s->depth == 8) { | |
255 | g364fb_draw_graphic8(s); | |
256 | } else { | |
b213b370 | 257 | error_report("g364: unknown guest depth %d", s->depth); |
1fc3d392 | 258 | } |
0add30cf AJ |
259 | |
260 | qemu_irq_raise(s->irq); | |
1fc3d392 AJ |
261 | } |
262 | ||
86178a57 | 263 | static inline void g364fb_invalidate_display(void *opaque) |
1fc3d392 AJ |
264 | { |
265 | G364State *s = opaque; | |
0add30cf AJ |
266 | |
267 | s->blanked = 0; | |
fd4aa979 | 268 | memory_region_set_dirty(&s->mem_vram, 0, s->vram_size); |
1fc3d392 AJ |
269 | } |
270 | ||
97a3f6ff | 271 | static void g364fb_reset(G364State *s) |
1fc3d392 | 272 | { |
0add30cf AJ |
273 | qemu_irq_lower(s->irq); |
274 | ||
275 | memset(s->color_palette, 0, sizeof(s->color_palette)); | |
276 | memset(s->cursor_palette, 0, sizeof(s->cursor_palette)); | |
277 | memset(s->cursor, 0, sizeof(s->cursor)); | |
278 | s->cursor_position = 0; | |
279 | s->ctla = 0; | |
280 | s->top_of_screen = 0; | |
281 | s->width = s->height = 0; | |
282 | memset(s->vram, 0, s->vram_size); | |
97a3f6ff | 283 | g364fb_invalidate_display(s); |
1fc3d392 AJ |
284 | } |
285 | ||
1fc3d392 | 286 | /* called for accesses to io ports */ |
97a3f6ff | 287 | static uint64_t g364fb_ctrl_read(void *opaque, |
a8170e5e | 288 | hwaddr addr, |
97a3f6ff | 289 | unsigned int size) |
1fc3d392 | 290 | { |
0add30cf | 291 | G364State *s = opaque; |
1fc3d392 AJ |
292 | uint32_t val; |
293 | ||
0add30cf AJ |
294 | if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { |
295 | /* cursor pattern */ | |
296 | int idx = (addr - REG_CURS_PAT) >> 3; | |
297 | val = s->cursor[idx]; | |
298 | } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { | |
299 | /* cursor palette */ | |
300 | int idx = (addr - REG_CURS_PAL) >> 3; | |
301 | val = ((uint32_t)s->cursor_palette[idx][0] << 16); | |
302 | val |= ((uint32_t)s->cursor_palette[idx][1] << 8); | |
303 | val |= ((uint32_t)s->cursor_palette[idx][2] << 0); | |
304 | } else { | |
305 | switch (addr) { | |
0add30cf AJ |
306 | case REG_DISPLAY: |
307 | val = s->width / 4; | |
308 | break; | |
309 | case REG_VDISPLAY: | |
310 | val = s->height * 2; | |
311 | break; | |
312 | case REG_CTLA: | |
313 | val = s->ctla; | |
314 | break; | |
315 | default: | |
316 | { | |
b213b370 HP |
317 | error_report("g364: invalid read at [" TARGET_FMT_plx "]", |
318 | addr); | |
0add30cf AJ |
319 | val = 0; |
320 | break; | |
321 | } | |
322 | } | |
1fc3d392 AJ |
323 | } |
324 | ||
b213b370 | 325 | trace_g364fb_read(addr, val); |
1fc3d392 AJ |
326 | |
327 | return val; | |
328 | } | |
329 | ||
0add30cf | 330 | static void g364fb_update_depth(G364State *s) |
1fc3d392 | 331 | { |
38972938 | 332 | static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 }; |
0add30cf AJ |
333 | s->depth = depths[(s->ctla & 0x00700000) >> 20]; |
334 | } | |
1fc3d392 | 335 | |
0add30cf AJ |
336 | static void g364_invalidate_cursor_position(G364State *s) |
337 | { | |
c78f7137 | 338 | DisplaySurface *surface = qemu_console_surface(s->con); |
fd4aa979 | 339 | int ymin, ymax, start, end; |
1fc3d392 | 340 | |
0add30cf AJ |
341 | /* invalidate only near the cursor */ |
342 | ymin = s->cursor_position & 0xfff; | |
343 | ymax = MIN(s->height, ymin + 64); | |
c78f7137 GH |
344 | start = ymin * surface_stride(surface); |
345 | end = (ymax + 1) * surface_stride(surface); | |
1fc3d392 | 346 | |
fd4aa979 | 347 | memory_region_set_dirty(&s->mem_vram, start, end - start); |
0add30cf AJ |
348 | } |
349 | ||
97a3f6ff | 350 | static void g364fb_ctrl_write(void *opaque, |
a8170e5e | 351 | hwaddr addr, |
97a3f6ff HP |
352 | uint64_t val, |
353 | unsigned int size) | |
0add30cf AJ |
354 | { |
355 | G364State *s = opaque; | |
356 | ||
b213b370 | 357 | trace_g364fb_write(addr, val); |
0add30cf AJ |
358 | |
359 | if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) { | |
1fc3d392 | 360 | /* color palette */ |
0add30cf AJ |
361 | int idx = (addr - REG_CLR_PAL) >> 3; |
362 | s->color_palette[idx][0] = (val >> 16) & 0xff; | |
363 | s->color_palette[idx][1] = (val >> 8) & 0xff; | |
364 | s->color_palette[idx][2] = val & 0xff; | |
365 | g364fb_invalidate_display(s); | |
366 | } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { | |
367 | /* cursor pattern */ | |
368 | int idx = (addr - REG_CURS_PAT) >> 3; | |
369 | s->cursor[idx] = val; | |
370 | g364fb_invalidate_display(s); | |
371 | } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { | |
372 | /* cursor palette */ | |
373 | int idx = (addr - REG_CURS_PAL) >> 3; | |
374 | s->cursor_palette[idx][0] = (val >> 16) & 0xff; | |
375 | s->cursor_palette[idx][1] = (val >> 8) & 0xff; | |
376 | s->cursor_palette[idx][2] = val & 0xff; | |
377 | g364fb_invalidate_display(s); | |
1fc3d392 AJ |
378 | } else { |
379 | switch (addr) { | |
97a3f6ff HP |
380 | case REG_BOOT: /* Boot timing */ |
381 | case 0x00108: /* Line timing: half sync */ | |
382 | case 0x00110: /* Line timing: back porch */ | |
383 | case 0x00120: /* Line timing: short display */ | |
384 | case 0x00128: /* Frame timing: broad pulse */ | |
385 | case 0x00130: /* Frame timing: v sync */ | |
386 | case 0x00138: /* Frame timing: v preequalise */ | |
387 | case 0x00140: /* Frame timing: v postequalise */ | |
388 | case 0x00148: /* Frame timing: v blank */ | |
389 | case 0x00158: /* Line timing: line time */ | |
390 | case 0x00160: /* Frame store: line start */ | |
391 | case 0x00168: /* vram cycle: mem init */ | |
392 | case 0x00170: /* vram cycle: transfer delay */ | |
393 | case 0x00200: /* vram cycle: mask register */ | |
394 | /* ignore */ | |
395 | break; | |
396 | case REG_TOP: | |
397 | s->top_of_screen = val; | |
398 | g364fb_invalidate_display(s); | |
399 | break; | |
400 | case REG_DISPLAY: | |
401 | s->width = val * 4; | |
402 | break; | |
403 | case REG_VDISPLAY: | |
404 | s->height = val / 2; | |
405 | break; | |
406 | case REG_CTLA: | |
407 | s->ctla = val; | |
408 | g364fb_update_depth(s); | |
409 | g364fb_invalidate_display(s); | |
410 | break; | |
411 | case REG_CURS_POS: | |
412 | g364_invalidate_cursor_position(s); | |
413 | s->cursor_position = val; | |
414 | g364_invalidate_cursor_position(s); | |
415 | break; | |
416 | case REG_RESET: | |
417 | g364fb_reset(s); | |
418 | break; | |
419 | default: | |
420 | error_report("g364: invalid write of 0x%" PRIx64 | |
421 | " at [" TARGET_FMT_plx "]", val, addr); | |
422 | break; | |
1fc3d392 AJ |
423 | } |
424 | } | |
0add30cf | 425 | qemu_irq_lower(s->irq); |
1fc3d392 AJ |
426 | } |
427 | ||
97a3f6ff HP |
428 | static const MemoryRegionOps g364fb_ctrl_ops = { |
429 | .read = g364fb_ctrl_read, | |
430 | .write = g364fb_ctrl_write, | |
431 | .endianness = DEVICE_LITTLE_ENDIAN, | |
432 | .impl.min_access_size = 4, | |
433 | .impl.max_access_size = 4, | |
1fc3d392 AJ |
434 | }; |
435 | ||
97a3f6ff | 436 | static int g364fb_post_load(void *opaque, int version_id) |
1fc3d392 AJ |
437 | { |
438 | G364State *s = opaque; | |
0add30cf AJ |
439 | |
440 | /* force refresh */ | |
441 | g364fb_update_depth(s); | |
442 | g364fb_invalidate_display(s); | |
1fc3d392 | 443 | |
0add30cf | 444 | return 0; |
1fc3d392 AJ |
445 | } |
446 | ||
97a3f6ff HP |
447 | static const VMStateDescription vmstate_g364fb = { |
448 | .name = "g364fb", | |
449 | .version_id = 1, | |
450 | .minimum_version_id = 1, | |
97a3f6ff HP |
451 | .post_load = g364fb_post_load, |
452 | .fields = (VMStateField[]) { | |
59046ec2 | 453 | VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, vram_size), |
97a3f6ff HP |
454 | VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3), |
455 | VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9), | |
456 | VMSTATE_UINT16_ARRAY(cursor, G364State, 512), | |
457 | VMSTATE_UINT32(cursor_position, G364State), | |
458 | VMSTATE_UINT32(ctla, G364State), | |
459 | VMSTATE_UINT32(top_of_screen, G364State), | |
460 | VMSTATE_UINT32(width, G364State), | |
461 | VMSTATE_UINT32(height, G364State), | |
462 | VMSTATE_END_OF_LIST() | |
463 | } | |
464 | }; | |
1fc3d392 | 465 | |
380cd056 GH |
466 | static const GraphicHwOps g364fb_ops = { |
467 | .invalidate = g364fb_invalidate_display, | |
468 | .gfx_update = g364fb_update_display, | |
469 | }; | |
470 | ||
97a3f6ff | 471 | static void g364fb_init(DeviceState *dev, G364State *s) |
1fc3d392 | 472 | { |
97a3f6ff | 473 | s->vram = g_malloc0(s->vram_size); |
1fc3d392 | 474 | |
5643706a | 475 | s->con = graphic_console_init(dev, 0, &g364fb_ops, s); |
1fc3d392 | 476 | |
2c9b15ca PB |
477 | memory_region_init_io(&s->mem_ctrl, NULL, &g364fb_ctrl_ops, s, "ctrl", 0x180000); |
478 | memory_region_init_ram_ptr(&s->mem_vram, NULL, "vram", | |
97a3f6ff | 479 | s->vram_size, s->vram); |
c5705a77 | 480 | vmstate_register_ram(&s->mem_vram, dev); |
74259ae5 | 481 | memory_region_set_log(&s->mem_vram, true, DIRTY_MEMORY_VGA); |
97a3f6ff HP |
482 | } |
483 | ||
0f31aa86 AF |
484 | #define TYPE_G364 "sysbus-g364" |
485 | #define G364(obj) OBJECT_CHECK(G364SysBusState, (obj), TYPE_G364) | |
486 | ||
97a3f6ff | 487 | typedef struct { |
0f31aa86 AF |
488 | SysBusDevice parent_obj; |
489 | ||
97a3f6ff HP |
490 | G364State g364; |
491 | } G364SysBusState; | |
1fc3d392 | 492 | |
0323ee43 | 493 | static void g364fb_sysbus_realize(DeviceState *dev, Error **errp) |
97a3f6ff | 494 | { |
0f31aa86 AF |
495 | G364SysBusState *sbs = G364(dev); |
496 | G364State *s = &sbs->g364; | |
0323ee43 | 497 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
97a3f6ff | 498 | |
0f31aa86 AF |
499 | g364fb_init(dev, s); |
500 | sysbus_init_irq(sbd, &s->irq); | |
501 | sysbus_init_mmio(sbd, &s->mem_ctrl); | |
502 | sysbus_init_mmio(sbd, &s->mem_vram); | |
1fc3d392 | 503 | } |
97a3f6ff HP |
504 | |
505 | static void g364fb_sysbus_reset(DeviceState *d) | |
506 | { | |
0f31aa86 AF |
507 | G364SysBusState *s = G364(d); |
508 | ||
97a3f6ff HP |
509 | g364fb_reset(&s->g364); |
510 | } | |
511 | ||
999e12bb | 512 | static Property g364fb_sysbus_properties[] = { |
f0353b0d | 513 | DEFINE_PROP_UINT32("vram_size", G364SysBusState, g364.vram_size, 8 * MiB), |
999e12bb AL |
514 | DEFINE_PROP_END_OF_LIST(), |
515 | }; | |
516 | ||
517 | static void g364fb_sysbus_class_init(ObjectClass *klass, void *data) | |
518 | { | |
39bffca2 | 519 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 520 | |
0323ee43 | 521 | dc->realize = g364fb_sysbus_realize; |
125ee0ed | 522 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); |
39bffca2 AL |
523 | dc->desc = "G364 framebuffer"; |
524 | dc->reset = g364fb_sysbus_reset; | |
525 | dc->vmsd = &vmstate_g364fb; | |
526 | dc->props = g364fb_sysbus_properties; | |
999e12bb AL |
527 | } |
528 | ||
8c43a6f0 | 529 | static const TypeInfo g364fb_sysbus_info = { |
0f31aa86 | 530 | .name = TYPE_G364, |
39bffca2 AL |
531 | .parent = TYPE_SYS_BUS_DEVICE, |
532 | .instance_size = sizeof(G364SysBusState), | |
533 | .class_init = g364fb_sysbus_class_init, | |
97a3f6ff HP |
534 | }; |
535 | ||
83f7d43a | 536 | static void g364fb_register_types(void) |
97a3f6ff | 537 | { |
39bffca2 | 538 | type_register_static(&g364fb_sysbus_info); |
97a3f6ff HP |
539 | } |
540 | ||
83f7d43a | 541 | type_init(g364fb_register_types) |