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87ecb68b PB |
1 | /* |
2 | * Misc ARM declarations | |
3 | * | |
4 | * Copyright (c) 2006 CodeSourcery. | |
5 | * Written by Paul Brook | |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the LGPL. |
87ecb68b PB |
8 | * |
9 | */ | |
10 | ||
11 | #ifndef ARM_MISC_H | |
12 | #define ARM_MISC_H 1 | |
13 | ||
7d6f78cf AK |
14 | #include "memory.h" |
15 | ||
87ecb68b PB |
16 | /* The CPU is also modeled as an interrupt controller. */ |
17 | #define ARM_PIC_CPU_IRQ 0 | |
18 | #define ARM_PIC_CPU_FIQ 1 | |
4bd74661 | 19 | qemu_irq *arm_pic_init_cpu(ARMCPU *cpu); |
87ecb68b PB |
20 | |
21 | /* armv7m.c */ | |
7d6f78cf AK |
22 | qemu_irq *armv7m_init(MemoryRegion *address_space_mem, |
23 | int flash_size, int sram_size, | |
87ecb68b PB |
24 | const char *kernel_filename, const char *cpu_model); |
25 | ||
26 | /* arm_boot.c */ | |
f93eb9ff | 27 | struct arm_boot_info { |
de841dea | 28 | uint64_t ram_size; |
f93eb9ff AZ |
29 | const char *kernel_filename; |
30 | const char *kernel_cmdline; | |
31 | const char *initrd_filename; | |
412beee6 | 32 | const char *dtb_filename; |
a8170e5e | 33 | hwaddr loader_start; |
9d5ba9bf ML |
34 | /* multicore boards that use the default secondary core boot functions |
35 | * need to put the address of the secondary boot code, the boot reg, | |
36 | * and the GIC address in the next 3 values, respectively. boards that | |
37 | * have their own boot functions can use these values as they want. | |
38 | */ | |
a8170e5e AK |
39 | hwaddr smp_loader_start; |
40 | hwaddr smp_bootreg_addr; | |
41 | hwaddr gic_cpu_if_addr; | |
f93eb9ff AZ |
42 | int nb_cpus; |
43 | int board_id; | |
462a8bc6 | 44 | int (*atag_board)(const struct arm_boot_info *info, void *p); |
9d5ba9bf ML |
45 | /* multicore boards that use the default secondary core boot functions |
46 | * can ignore these two function calls. If the default functions won't | |
47 | * work, then write_secondary_boot() should write a suitable blob of | |
9b574c29 | 48 | * code mimicking the secondary CPU startup process used by the board's |
9d5ba9bf | 49 | * boot loader/boot ROM code, and secondary_cpu_reset_hook() should |
9b574c29 | 50 | * perform any necessary CPU reset handling and set the PC for the |
9d5ba9bf ML |
51 | * secondary CPUs to point at this boot blob. |
52 | */ | |
9543b0cd | 53 | void (*write_secondary_boot)(ARMCPU *cpu, |
9d5ba9bf | 54 | const struct arm_boot_info *info); |
5d309320 | 55 | void (*secondary_cpu_reset_hook)(ARMCPU *cpu, |
9d5ba9bf | 56 | const struct arm_boot_info *info); |
f2d74978 PB |
57 | /* Used internally by arm_boot.c */ |
58 | int is_linux; | |
fc53b7d4 | 59 | hwaddr initrd_start; |
a8170e5e AK |
60 | hwaddr initrd_size; |
61 | hwaddr entry; | |
f93eb9ff | 62 | }; |
3aaa8dfa | 63 | void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info); |
87ecb68b | 64 | |
79383c9c BS |
65 | /* Multiplication factor to convert from system clock ticks to qemu timer |
66 | ticks. */ | |
7ee930d0 | 67 | extern int system_clock_scale; |
87ecb68b PB |
68 | |
69 | #endif /* !ARM_MISC_H */ |