[qemu.git] / softmmu_header.h

/*
 *  Software MMU support
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#define DATA_STYPE int16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#define DATA_STYPE int8_t
#else
#error unsupported data size
#endif

#if ACCESS_TYPE < (NB_MMU_MODES)

#define CPU_MMU_INDEX ACCESS_TYPE
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == (NB_MMU_MODES)

#define CPU_MMU_INDEX (cpu_mmu_index(env))
#define MMUSUFFIX _mmu

#elif ACCESS_TYPE == (NB_MMU_MODES + 1)

#define CPU_MMU_INDEX (cpu_mmu_index(env))
#define MMUSUFFIX _cmmu

#else
#error invalid ACCESS_TYPE
#endif

#if DATA_SIZE == 8
#define RES_TYPE uint64_t
#else
#define RES_TYPE int
#endif

#if ACCESS_TYPE == (NB_MMU_MODES + 1)
#define ADDR_READ addr_code
#else
#define ADDR_READ addr_read
#endif

#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
    (ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU)

static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res;

    asm volatile ("movl %1, %%edx\n"
                  "movl %1, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %1, %%eax\n"
                  "je 1f\n"
                  "movl %6, %%edx\n"
                  "call %7\n"
                  "movl %%eax, %0\n"
                  "jmp 2f\n"
                  "1:\n"
                  "addl 12(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movzbl (%%eax), %0\n"
#elif DATA_SIZE == 2
                  "movzwl (%%eax), %0\n"
#elif DATA_SIZE == 4
                  "movl (%%eax), %0\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : "=r" (res)
                  : "r" (ptr),
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
                  "i" (CPU_MMU_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
    return res;
}

#if DATA_SIZE <= 2
static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res;

    asm volatile ("movl %1, %%edx\n"
                  "movl %1, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %1, %%eax\n"
                  "je 1f\n"
                  "movl %6, %%edx\n"
                  "call %7\n"
#if DATA_SIZE == 1
                  "movsbl %%al, %0\n"
#elif DATA_SIZE == 2
                  "movswl %%ax, %0\n"
#else
#error unsupported size
#endif
                  "jmp 2f\n"
                  "1:\n"
                  "addl 12(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movsbl (%%eax), %0\n"
#elif DATA_SIZE == 2
                  "movswl (%%eax), %0\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  : "=r" (res)
                  : "r" (ptr),
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
                  "i" (CPU_MMU_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
    return res;
}
#endif

static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
{
    asm volatile ("movl %0, %%edx\n"
                  "movl %0, %%eax\n"
                  "shrl %3, %%edx\n"
                  "andl %4, %%eax\n"
                  "andl %2, %%edx\n"
                  "leal %5(%%edx, %%ebp), %%edx\n"
                  "cmpl (%%edx), %%eax\n"
                  "movl %0, %%eax\n"
                  "je 1f\n"
#if DATA_SIZE == 1
                  "movzbl %b1, %%edx\n"
#elif DATA_SIZE == 2
                  "movzwl %w1, %%edx\n"
#elif DATA_SIZE == 4
                  "movl %1, %%edx\n"
#else
#error unsupported size
#endif
                  "movl %6, %%ecx\n"
                  "call %7\n"
                  "jmp 2f\n"
                  "1:\n"
                  "addl 8(%%edx), %%eax\n"
#if DATA_SIZE == 1
                  "movb %b1, (%%eax)\n"
#elif DATA_SIZE == 2
                  "movw %w1, (%%eax)\n"
#elif DATA_SIZE == 4
                  "movl %1, (%%eax)\n"
#else
#error unsupported size
#endif
                  "2:\n"
                  :
                  : "r" (ptr),
#if DATA_SIZE == 1
                  "q" (v),
#else
                  "r" (v),
#endif
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_write)),
                  "i" (CPU_MMU_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
                  : "%eax", "%ecx", "%edx", "memory", "cc");
}

#else

/* generic load/store macros */

static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int page_index;
    RES_TYPE res;
    target_ulong addr;
    unsigned long physaddr;
    int mmu_idx;

    addr = ptr;
    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    mmu_idx = CPU_MMU_INDEX;
    if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
                 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
        res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
    } else {
        physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
        res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
    }
    return res;
}

#if DATA_SIZE <= 2
static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
{
    int res, page_index;
    target_ulong addr;
    unsigned long physaddr;
    int mmu_idx;

    addr = ptr;
    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    mmu_idx = CPU_MMU_INDEX;
    if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
                 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
        res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
    } else {
        physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
        res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
    }
    return res;
}
#endif

#if ACCESS_TYPE != (NB_MMU_MODES + 1)

/* generic store macro */

static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
{
    int page_index;
    target_ulong addr;
    unsigned long physaddr;
    int mmu_idx;

    addr = ptr;
    page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
    mmu_idx = CPU_MMU_INDEX;
    if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=
                 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) {
        glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx);
    } else {
        physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
        glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
    }
}

#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */

#endif /* !asm */

#if ACCESS_TYPE != (NB_MMU_MODES + 1)

#if DATA_SIZE == 8
static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
{
    union {
        float64 d;
        uint64_t i;
    } u;
    u.i = glue(ldq, MEMSUFFIX)(ptr);
    return u.d;
}

static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
{
    union {
        float64 d;
        uint64_t i;
    } u;
    u.d = v;
    glue(stq, MEMSUFFIX)(ptr, u.i);
}
#endif /* DATA_SIZE == 8 */

#if DATA_SIZE == 4
static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
{
    union {
        float32 f;
        uint32_t i;
    } u;
    u.i = glue(ldl, MEMSUFFIX)(ptr);
    return u.f;
}

static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
{
    union {
        float32 f;
        uint32_t i;
    } u;
    u.f = v;
    glue(stl, MEMSUFFIX)(ptr, u.i);
}
#endif /* DATA_SIZE == 4 */

#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */

#undef RES_TYPE
#undef DATA_TYPE
#undef DATA_STYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
#undef CPU_MMU_INDEX
#undef MMUSUFFIX
#undef ADDR_READ
Commit	Line	Data
b92e5a22 FB	1	/*
b92e5a22 FB	2	* Software MMU support
5fafdf24	3	*
b92e5a22 FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#if DATA_SIZE == 8
	21	#define SUFFIX q
61382a50	22	#define USUFFIX q
b92e5a22 FB	23	#define DATA_TYPE uint64_t
	24	#elif DATA_SIZE == 4
	25	#define SUFFIX l
61382a50	26	#define USUFFIX l
b92e5a22 FB	27	#define DATA_TYPE uint32_t
	28	#elif DATA_SIZE == 2
	29	#define SUFFIX w
61382a50	30	#define USUFFIX uw
b92e5a22 FB	31	#define DATA_TYPE uint16_t
	32	#define DATA_STYPE int16_t
	33	#elif DATA_SIZE == 1
	34	#define SUFFIX b
61382a50	35	#define USUFFIX ub
b92e5a22 FB	36	#define DATA_TYPE uint8_t
	37	#define DATA_STYPE int8_t
	38	#else
	39	#error unsupported data size
	40	#endif
	41
6ebbf390	42	#if ACCESS_TYPE < (NB_MMU_MODES)
61382a50	43
6ebbf390	44	#define CPU_MMU_INDEX ACCESS_TYPE
61382a50 FB	45	#define MMUSUFFIX _mmu
61382a50 FB	46
6ebbf390	47	#elif ACCESS_TYPE == (NB_MMU_MODES)
61382a50	48
6ebbf390	49	#define CPU_MMU_INDEX (cpu_mmu_index(env))
61382a50 FB	50	#define MMUSUFFIX _mmu
61382a50 FB	51
6ebbf390	52	#elif ACCESS_TYPE == (NB_MMU_MODES + 1)
61382a50	53
6ebbf390	54	#define CPU_MMU_INDEX (cpu_mmu_index(env))
61382a50 FB	55	#define MMUSUFFIX _cmmu
61382a50 FB	56
b92e5a22	57	#else
61382a50	58	#error invalid ACCESS_TYPE
b92e5a22 FB	59	#endif
	60
	61	#if DATA_SIZE == 8
	62	#define RES_TYPE uint64_t
	63	#else
	64	#define RES_TYPE int
	65	#endif
	66
6ebbf390	67	#if ACCESS_TYPE == (NB_MMU_MODES + 1)
84b7b8e7 FB	68	#define ADDR_READ addr_code
	69	#else
	70	#define ADDR_READ addr_read
	71	#endif
b92e5a22	72
c27004ec	73	#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
6ebbf390	74	(ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU)
e16c53fa	75
c27004ec	76	static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
e16c53fa FB	77	{
	78	int res;
	79
	80	asm volatile ("movl %1, %%edx\n"
	81	"movl %1, %%eax\n"
	82	"shrl %3, %%edx\n"
	83	"andl %4, %%eax\n"
	84	"andl %2, %%edx\n"
	85	"leal %5(%%edx, %%ebp), %%edx\n"
	86	"cmpl (%%edx), %%eax\n"
	87	"movl %1, %%eax\n"
	88	"je 1f\n"
d656469f	89	"movl %6, %%edx\n"
e16c53fa	90	"call %7\n"
e16c53fa FB	91	"movl %%eax, %0\n"
	92	"jmp 2f\n"
	93	"1:\n"
84b7b8e7	94	"addl 12(%%edx), %%eax\n"
e16c53fa FB	95	#if DATA_SIZE == 1
	96	"movzbl (%%eax), %0\n"
	97	#elif DATA_SIZE == 2
	98	"movzwl (%%eax), %0\n"
	99	#elif DATA_SIZE == 4
	100	"movl (%%eax), %0\n"
	101	#else
	102	#error unsupported size
	103	#endif
	104	"2:\n"
	105	: "=r" (res)
5fafdf24 TS	106	: "r" (ptr),
	107	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
	108	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	109	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
6ebbf390 JM	110	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
6ebbf390 JM	111	"i" (CPU_MMU_INDEX),
e16c53fa FB	112	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))
	113	: "%eax", "%ecx", "%edx", "memory", "cc");
	114	return res;
	115	}
	116
	117	#if DATA_SIZE <= 2
c27004ec	118	static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
e16c53fa FB	119	{
	120	int res;
	121
	122	asm volatile ("movl %1, %%edx\n"
	123	"movl %1, %%eax\n"
	124	"shrl %3, %%edx\n"
	125	"andl %4, %%eax\n"
	126	"andl %2, %%edx\n"
	127	"leal %5(%%edx, %%ebp), %%edx\n"
	128	"cmpl (%%edx), %%eax\n"
	129	"movl %1, %%eax\n"
	130	"je 1f\n"
d656469f	131	"movl %6, %%edx\n"
e16c53fa	132	"call %7\n"
e16c53fa FB	133	#if DATA_SIZE == 1
	134	"movsbl %%al, %0\n"
	135	#elif DATA_SIZE == 2
	136	"movswl %%ax, %0\n"
	137	#else
	138	#error unsupported size
	139	#endif
	140	"jmp 2f\n"
	141	"1:\n"
84b7b8e7	142	"addl 12(%%edx), %%eax\n"
e16c53fa FB	143	#if DATA_SIZE == 1
	144	"movsbl (%%eax), %0\n"
	145	#elif DATA_SIZE == 2
	146	"movswl (%%eax), %0\n"
	147	#else
	148	#error unsupported size
	149	#endif
	150	"2:\n"
	151	: "=r" (res)
5fafdf24 TS	152	: "r" (ptr),
	153	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
	154	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	155	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
6ebbf390 JM	156	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
6ebbf390 JM	157	"i" (CPU_MMU_INDEX),
e16c53fa FB	158	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))
	159	: "%eax", "%ecx", "%edx", "memory", "cc");
	160	return res;
	161	}
	162	#endif
	163
c27004ec	164	static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
e16c53fa FB	165	{
	166	asm volatile ("movl %0, %%edx\n"
	167	"movl %0, %%eax\n"
	168	"shrl %3, %%edx\n"
	169	"andl %4, %%eax\n"
	170	"andl %2, %%edx\n"
	171	"leal %5(%%edx, %%ebp), %%edx\n"
	172	"cmpl (%%edx), %%eax\n"
	173	"movl %0, %%eax\n"
	174	"je 1f\n"
	175	#if DATA_SIZE == 1
	176	"movzbl %b1, %%edx\n"
	177	#elif DATA_SIZE == 2
	178	"movzwl %w1, %%edx\n"
	179	#elif DATA_SIZE == 4
	180	"movl %1, %%edx\n"
	181	#else
	182	#error unsupported size
	183	#endif
d656469f	184	"movl %6, %%ecx\n"
e16c53fa	185	"call %7\n"
e16c53fa FB	186	"jmp 2f\n"
e16c53fa FB	187	"1:\n"
84b7b8e7	188	"addl 8(%%edx), %%eax\n"
e16c53fa FB	189	#if DATA_SIZE == 1
	190	"movb %b1, (%%eax)\n"
	191	#elif DATA_SIZE == 2
	192	"movw %w1, (%%eax)\n"
	193	#elif DATA_SIZE == 4
	194	"movl %1, (%%eax)\n"
	195	#else
	196	#error unsupported size
	197	#endif
	198	"2:\n"
5fafdf24 TS	199	:
5fafdf24 TS	200	: "r" (ptr),
f220f4e3 FB	201	#if DATA_SIZE == 1
	202	"q" (v),
	203	#else
5fafdf24	204	"r" (v),
f220f4e3	205	#endif
5fafdf24 TS	206	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
5fafdf24 TS	207	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
e16c53fa	208	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
6ebbf390 JM	209	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_write)),
6ebbf390 JM	210	"i" (CPU_MMU_INDEX),
e16c53fa FB	211	"m" ((uint8_t )&glue(glue(__st, SUFFIX), MMUSUFFIX))
	212	: "%eax", "%ecx", "%edx", "memory", "cc");
	213	}
	214
	215	#else
	216
	217	/* generic load/store macros */
	218
c27004ec	219	static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
b92e5a22	220	{
4d7a0880	221	int page_index;
b92e5a22	222	RES_TYPE res;
c27004ec FB	223	target_ulong addr;
c27004ec FB	224	unsigned long physaddr;
6ebbf390	225	int mmu_idx;
61382a50	226
c27004ec	227	addr = ptr;
4d7a0880	228	page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
6ebbf390	229	mmu_idx = CPU_MMU_INDEX;
551bd27f TS	230	if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
551bd27f TS	231	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))))) {
6ebbf390	232	res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
b92e5a22	233	} else {
4d7a0880	234	physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
61382a50	235	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
b92e5a22 FB	236	}
	237	return res;
	238	}
	239
	240	#if DATA_SIZE <= 2
c27004ec	241	static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
b92e5a22	242	{
4d7a0880	243	int res, page_index;
c27004ec FB	244	target_ulong addr;
c27004ec FB	245	unsigned long physaddr;
6ebbf390	246	int mmu_idx;
61382a50	247
c27004ec	248	addr = ptr;
4d7a0880	249	page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
6ebbf390	250	mmu_idx = CPU_MMU_INDEX;
551bd27f TS	251	if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=
551bd27f TS	252	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))))) {
6ebbf390	253	res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, mmu_idx);
b92e5a22	254	} else {
4d7a0880	255	physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
b92e5a22 FB	256	res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
	257	}
	258	return res;
	259	}
	260	#endif
	261
6ebbf390	262	#if ACCESS_TYPE != (NB_MMU_MODES + 1)
84b7b8e7	263
e16c53fa FB	264	/* generic store macro */
e16c53fa FB	265
c27004ec	266	static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
b92e5a22	267	{
4d7a0880	268	int page_index;
c27004ec FB	269	target_ulong addr;
c27004ec FB	270	unsigned long physaddr;
6ebbf390	271	int mmu_idx;
61382a50	272
c27004ec	273	addr = ptr;
4d7a0880	274	page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
6ebbf390	275	mmu_idx = CPU_MMU_INDEX;
551bd27f TS	276	if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=
551bd27f TS	277	(addr & (TARGET_PAGE_MASK \| (DATA_SIZE - 1))))) {
6ebbf390	278	glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, mmu_idx);
b92e5a22	279	} else {
4d7a0880	280	physaddr = addr + env->tlb_table[mmu_idx][page_index].addend;
b92e5a22 FB	281	glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
	282	}
	283	}
	284
6ebbf390	285	#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
84b7b8e7 FB	286
	287	#endif /* !asm */
	288
6ebbf390	289	#if ACCESS_TYPE != (NB_MMU_MODES + 1)
e16c53fa	290
2d603d22	291	#if DATA_SIZE == 8
3f87bf69	292	static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
2d603d22 FB	293	{
2d603d22 FB	294	union {
3f87bf69	295	float64 d;
2d603d22 FB	296	uint64_t i;
	297	} u;
	298	u.i = glue(ldq, MEMSUFFIX)(ptr);
	299	return u.d;
	300	}
	301
3f87bf69	302	static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
2d603d22 FB	303	{
2d603d22 FB	304	union {
3f87bf69	305	float64 d;
2d603d22 FB	306	uint64_t i;
	307	} u;
	308	u.d = v;
	309	glue(stq, MEMSUFFIX)(ptr, u.i);
	310	}
	311	#endif /* DATA_SIZE == 8 */
	312
	313	#if DATA_SIZE == 4
3f87bf69	314	static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
2d603d22 FB	315	{
2d603d22 FB	316	union {
3f87bf69	317	float32 f;
2d603d22 FB	318	uint32_t i;
	319	} u;
	320	u.i = glue(ldl, MEMSUFFIX)(ptr);
	321	return u.f;
	322	}
	323
3f87bf69	324	static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
2d603d22 FB	325	{
2d603d22 FB	326	union {
3f87bf69	327	float32 f;
2d603d22 FB	328	uint32_t i;
	329	} u;
	330	u.f = v;
	331	glue(stl, MEMSUFFIX)(ptr, u.i);
	332	}
	333	#endif /* DATA_SIZE == 4 */
	334
6ebbf390	335	#endif /* ACCESS_TYPE != (NB_MMU_MODES + 1) */
84b7b8e7	336
b92e5a22 FB	337	#undef RES_TYPE
	338	#undef DATA_TYPE
	339	#undef DATA_STYPE
	340	#undef SUFFIX
61382a50	341	#undef USUFFIX
b92e5a22	342	#undef DATA_SIZE
6ebbf390	343	#undef CPU_MMU_INDEX
61382a50	344	#undef MMUSUFFIX
84b7b8e7	345	#undef ADDR_READ