[qemu.git] / hw / lm32 / lm32_boards.c

/*
 *  QEMU models for LatticeMico32 uclinux and evr32 boards.
 *
 *  Copyright (c) 2010 Michael Walle <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "hw/sysbus.h"
#include "hw/hw.h"
#include "hw/block/flash.h"
#include "hw/devices.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "sysemu/blockdev.h"
#include "elf.h"
#include "lm32_hwsetup.h"
#include "lm32.h"
#include "exec/address-spaces.h"

typedef struct {
    LM32CPU *cpu;
    hwaddr bootstrap_pc;
    hwaddr flash_base;
    hwaddr hwsetup_base;
    hwaddr initrd_base;
    size_t initrd_size;
    hwaddr cmdline_base;
} ResetInfo;

static void cpu_irq_handler(void *opaque, int irq, int level)
{
    LM32CPU *cpu = opaque;
    CPUState *cs = CPU(cpu);

    if (level) {
        cpu_interrupt(cs, CPU_INTERRUPT_HARD);
    } else {
        cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
    }
}

static void main_cpu_reset(void *opaque)
{
    ResetInfo *reset_info = opaque;
    CPULM32State *env = &reset_info->cpu->env;

    cpu_reset(CPU(reset_info->cpu));

    /* init defaults */
    env->pc = (uint32_t)reset_info->bootstrap_pc;
    env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
    env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
    env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
    env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
        reset_info->initrd_size);
    env->eba = reset_info->flash_base;
    env->deba = reset_info->flash_base;
}

static void lm32_evr_init(QEMUMachineInitArgs *args)
{
    const char *cpu_model = args->cpu_model;
    const char *kernel_filename = args->kernel_filename;
    LM32CPU *cpu;
    CPULM32State *env;
    DriveInfo *dinfo;
    MemoryRegion *address_space_mem =  get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq *cpu_irq, irq[32];
    ResetInfo *reset_info;
    int i;

    /* memory map */
    hwaddr flash_base  = 0x04000000;
    size_t flash_sector_size       = 256 * 1024;
    size_t flash_size              = 32 * 1024 * 1024;
    hwaddr ram_base    = 0x08000000;
    size_t ram_size                = 64 * 1024 * 1024;
    hwaddr timer0_base = 0x80002000;
    hwaddr uart0_base  = 0x80006000;
    hwaddr timer1_base = 0x8000a000;
    int uart0_irq                  = 0;
    int timer0_irq                 = 1;
    int timer1_irq                 = 3;

    reset_info = g_malloc0(sizeof(ResetInfo));

    if (cpu_model == NULL) {
        cpu_model = "lm32-full";
    }
    cpu = cpu_lm32_init(cpu_model);
    env = &cpu->env;
    reset_info->cpu = cpu;

    reset_info->flash_base = flash_base;

    memory_region_init_ram(phys_ram, "lm32_evr.sdram", ram_size);
    vmstate_register_ram_global(phys_ram);
    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
                          dinfo ? dinfo->bdrv : NULL, flash_sector_size,
                          flash_size / flash_sector_size, 1, 2,
                          0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    cpu_irq = qemu_allocate_irqs(cpu_irq_handler, cpu, 1);
    env->pic_state = lm32_pic_init(*cpu_irq);
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init();

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
                               1, ELF_MACHINE, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static void lm32_uclinux_init(QEMUMachineInitArgs *args)
{
    const char *cpu_model = args->cpu_model;
    const char *kernel_filename = args->kernel_filename;
    const char *kernel_cmdline = args->kernel_cmdline;
    const char *initrd_filename = args->initrd_filename;
    LM32CPU *cpu;
    CPULM32State *env;
    DriveInfo *dinfo;
    MemoryRegion *address_space_mem =  get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq *cpu_irq, irq[32];
    HWSetup *hw;
    ResetInfo *reset_info;
    int i;

    /* memory map */
    hwaddr flash_base   = 0x04000000;
    size_t flash_sector_size        = 256 * 1024;
    size_t flash_size               = 32 * 1024 * 1024;
    hwaddr ram_base     = 0x08000000;
    size_t ram_size                 = 64 * 1024 * 1024;
    hwaddr uart0_base   = 0x80000000;
    hwaddr timer0_base  = 0x80002000;
    hwaddr timer1_base  = 0x80010000;
    hwaddr timer2_base  = 0x80012000;
    int uart0_irq                   = 0;
    int timer0_irq                  = 1;
    int timer1_irq                  = 20;
    int timer2_irq                  = 21;
    hwaddr hwsetup_base = 0x0bffe000;
    hwaddr cmdline_base = 0x0bfff000;
    hwaddr initrd_base  = 0x08400000;
    size_t initrd_max               = 0x01000000;

    reset_info = g_malloc0(sizeof(ResetInfo));

    if (cpu_model == NULL) {
        cpu_model = "lm32-full";
    }
    cpu = cpu_lm32_init(cpu_model);
    env = &cpu->env;
    reset_info->cpu = cpu;

    reset_info->flash_base = flash_base;

    memory_region_init_ram(phys_ram, "lm32_uclinux.sdram", ram_size);
    vmstate_register_ram_global(phys_ram);
    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
                          dinfo ? dinfo->bdrv : NULL, flash_sector_size,
                          flash_size / flash_sector_size, 1, 2,
                          0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
    env->pic_state = lm32_pic_init(*cpu_irq);
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
    sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init();

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
                               1, ELF_MACHINE, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    }

    /* generate a rom with the hardware description */
    hw = hwsetup_init();
    hwsetup_add_cpu(hw, "LM32", 75000000);
    hwsetup_add_flash(hw, "flash", flash_base, flash_size);
    hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
    hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
    hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
    hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
    hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
    hwsetup_add_trailer(hw);
    hwsetup_create_rom(hw, hwsetup_base);
    hwsetup_free(hw);

    reset_info->hwsetup_base = hwsetup_base;

    if (kernel_cmdline && strlen(kernel_cmdline)) {
        pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
                kernel_cmdline);
        reset_info->cmdline_base = cmdline_base;
    }

    if (initrd_filename) {
        size_t initrd_size;
        initrd_size = load_image_targphys(initrd_filename, initrd_base,
                initrd_max);
        reset_info->initrd_base = initrd_base;
        reset_info->initrd_size = initrd_size;
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static QEMUMachine lm32_evr_machine = {
    .name = "lm32-evr",
    .desc = "LatticeMico32 EVR32 eval system",
    .init = lm32_evr_init,
    .is_default = 1,
    DEFAULT_MACHINE_OPTIONS,
};

static QEMUMachine lm32_uclinux_machine = {
    .name = "lm32-uclinux",
    .desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
    .init = lm32_uclinux_init,
    .is_default = 0,
    DEFAULT_MACHINE_OPTIONS,
};

static void lm32_machine_init(void)
{
    qemu_register_machine(&lm32_uclinux_machine);
    qemu_register_machine(&lm32_evr_machine);
}

machine_init(lm32_machine_init);
Commit	Line	Data
d821732a MW	1	/*
	2	* QEMU models for LatticeMico32 uclinux and evr32 boards.
	3	*
	4	* Copyright (c) 2010 Michael Walle <[email protected]>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
83c9f4ca PB	20	#include "hw/sysbus.h"
83c9f4ca PB	21	#include "hw/hw.h"
0d09e41a	22	#include "hw/block/flash.h"
bd2be150	23	#include "hw/devices.h"
83c9f4ca PB	24	#include "hw/boards.h"
83c9f4ca PB	25	#include "hw/loader.h"
9c17d615	26	#include "sysemu/blockdev.h"
d821732a	27	#include "elf.h"
47b43a1f PB	28	#include "lm32_hwsetup.h"
47b43a1f PB	29	#include "lm32.h"
022c62cb	30	#include "exec/address-spaces.h"
d821732a MW	31
d821732a MW	32	typedef struct {
b1435596	33	LM32CPU *cpu;
a8170e5e AK	34	hwaddr bootstrap_pc;
	35	hwaddr flash_base;
	36	hwaddr hwsetup_base;
	37	hwaddr initrd_base;
d821732a	38	size_t initrd_size;
a8170e5e	39	hwaddr cmdline_base;
d821732a MW	40	} ResetInfo;
	41
	42	static void cpu_irq_handler(void *opaque, int irq, int level)
	43	{
d8ed887b	44	LM32CPU *cpu = opaque;
d8ed887b	45	CPUState *cs = CPU(cpu);
d821732a MW	46
d821732a MW	47	if (level) {
c3affe56	48	cpu_interrupt(cs, CPU_INTERRUPT_HARD);
d821732a	49	} else {
d8ed887b	50	cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
d821732a MW	51	}
	52	}
	53
	54	static void main_cpu_reset(void *opaque)
	55	{
	56	ResetInfo *reset_info = opaque;
b1435596	57	CPULM32State *env = &reset_info->cpu->env;
d821732a	58
b1435596	59	cpu_reset(CPU(reset_info->cpu));
d821732a MW	60
	61	/* init defaults */
	62	env->pc = (uint32_t)reset_info->bootstrap_pc;
	63	env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
	64	env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
	65	env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
	66	env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
	67	reset_info->initrd_size);
	68	env->eba = reset_info->flash_base;
	69	env->deba = reset_info->flash_base;
	70	}
	71
5f072e1f	72	static void lm32_evr_init(QEMUMachineInitArgs *args)
d821732a	73	{
5f072e1f EH	74	const char *cpu_model = args->cpu_model;
5f072e1f EH	75	const char *kernel_filename = args->kernel_filename;
47dc4fa2	76	LM32CPU *cpu;
93a67402	77	CPULM32State *env;
d821732a	78	DriveInfo *dinfo;
88fa8031 AK	79	MemoryRegion *address_space_mem = get_system_memory();
88fa8031 AK	80	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
d821732a MW	81	qemu_irq *cpu_irq, irq[32];
	82	ResetInfo *reset_info;
	83	int i;
	84
	85	/* memory map */
a8170e5e	86	hwaddr flash_base = 0x04000000;
d821732a MW	87	size_t flash_sector_size = 256 * 1024;
d821732a MW	88	size_t flash_size = 32 * 1024 * 1024;
a8170e5e	89	hwaddr ram_base = 0x08000000;
d821732a	90	size_t ram_size = 64 * 1024 * 1024;
a8170e5e AK	91	hwaddr timer0_base = 0x80002000;
	92	hwaddr uart0_base = 0x80006000;
	93	hwaddr timer1_base = 0x8000a000;
d821732a MW	94	int uart0_irq = 0;
	95	int timer0_irq = 1;
	96	int timer1_irq = 3;
	97
7267c094	98	reset_info = g_malloc0(sizeof(ResetInfo));
d821732a MW	99
	100	if (cpu_model == NULL) {
	101	cpu_model = "lm32-full";
	102	}
47dc4fa2 AF	103	cpu = cpu_lm32_init(cpu_model);
47dc4fa2 AF	104	env = &cpu->env;
b1435596	105	reset_info->cpu = cpu;
d821732a MW	106
	107	reset_info->flash_base = flash_base;
	108
c5705a77 AK	109	memory_region_init_ram(phys_ram, "lm32_evr.sdram", ram_size);
c5705a77 AK	110	vmstate_register_ram_global(phys_ram);
88fa8031	111	memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
d821732a	112
d821732a MW	113	dinfo = drive_get(IF_PFLASH, 0, 0);
d821732a MW	114	/* Spansion S29NS128P */
cfe5f011	115	pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
d821732a MW	116	dinfo ? dinfo->bdrv : NULL, flash_sector_size,
d821732a MW	117	flash_size / flash_sector_size, 1, 2,
01e0451a	118	0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
d821732a MW	119
d821732a MW	120	/* create irq lines */
d8ed887b	121	cpu_irq = qemu_allocate_irqs(cpu_irq_handler, cpu, 1);
d821732a MW	122	env->pic_state = lm32_pic_init(*cpu_irq);
	123	for (i = 0; i < 32; i++) {
	124	irq[i] = qdev_get_gpio_in(env->pic_state, i);
	125	}
	126
	127	sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
	128	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
	129	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
	130
	131	/* make sure juart isn't the first chardev */
	132	env->juart_state = lm32_juart_init();
	133
	134	reset_info->bootstrap_pc = flash_base;
	135
	136	if (kernel_filename) {
	137	uint64_t entry;
	138	int kernel_size;
	139
	140	kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
	141	1, ELF_MACHINE, 0);
	142	reset_info->bootstrap_pc = entry;
	143
	144	if (kernel_size < 0) {
	145	kernel_size = load_image_targphys(kernel_filename, ram_base,
	146	ram_size);
	147	reset_info->bootstrap_pc = ram_base;
	148	}
	149
	150	if (kernel_size < 0) {
	151	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	152	kernel_filename);
	153	exit(1);
	154	}
	155	}
	156
	157	qemu_register_reset(main_cpu_reset, reset_info);
	158	}
	159
5f072e1f	160	static void lm32_uclinux_init(QEMUMachineInitArgs *args)
d821732a	161	{
5f072e1f EH	162	const char *cpu_model = args->cpu_model;
	163	const char *kernel_filename = args->kernel_filename;
	164	const char *kernel_cmdline = args->kernel_cmdline;
	165	const char *initrd_filename = args->initrd_filename;
47dc4fa2	166	LM32CPU *cpu;
93a67402	167	CPULM32State *env;
d821732a	168	DriveInfo *dinfo;
88fa8031 AK	169	MemoryRegion *address_space_mem = get_system_memory();
88fa8031 AK	170	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
d821732a MW	171	qemu_irq *cpu_irq, irq[32];
	172	HWSetup *hw;
	173	ResetInfo *reset_info;
	174	int i;
	175
	176	/* memory map */
a8170e5e	177	hwaddr flash_base = 0x04000000;
d821732a MW	178	size_t flash_sector_size = 256 * 1024;
d821732a MW	179	size_t flash_size = 32 * 1024 * 1024;
a8170e5e	180	hwaddr ram_base = 0x08000000;
d821732a	181	size_t ram_size = 64 * 1024 * 1024;
a8170e5e AK	182	hwaddr uart0_base = 0x80000000;
	183	hwaddr timer0_base = 0x80002000;
	184	hwaddr timer1_base = 0x80010000;
	185	hwaddr timer2_base = 0x80012000;
d821732a MW	186	int uart0_irq = 0;
	187	int timer0_irq = 1;
	188	int timer1_irq = 20;
	189	int timer2_irq = 21;
a8170e5e AK	190	hwaddr hwsetup_base = 0x0bffe000;
	191	hwaddr cmdline_base = 0x0bfff000;
	192	hwaddr initrd_base = 0x08400000;
d821732a MW	193	size_t initrd_max = 0x01000000;
d821732a MW	194
7267c094	195	reset_info = g_malloc0(sizeof(ResetInfo));
d821732a MW	196
	197	if (cpu_model == NULL) {
	198	cpu_model = "lm32-full";
	199	}
47dc4fa2 AF	200	cpu = cpu_lm32_init(cpu_model);
47dc4fa2 AF	201	env = &cpu->env;
b1435596	202	reset_info->cpu = cpu;
d821732a MW	203
	204	reset_info->flash_base = flash_base;
	205
c5705a77 AK	206	memory_region_init_ram(phys_ram, "lm32_uclinux.sdram", ram_size);
c5705a77 AK	207	vmstate_register_ram_global(phys_ram);
88fa8031	208	memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
d821732a	209
d821732a MW	210	dinfo = drive_get(IF_PFLASH, 0, 0);
d821732a MW	211	/* Spansion S29NS128P */
cfe5f011	212	pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
d821732a MW	213	dinfo ? dinfo->bdrv : NULL, flash_sector_size,
d821732a MW	214	flash_size / flash_sector_size, 1, 2,
01e0451a	215	0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
d821732a MW	216
	217	/* create irq lines */
	218	cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
	219	env->pic_state = lm32_pic_init(*cpu_irq);
	220	for (i = 0; i < 32; i++) {
	221	irq[i] = qdev_get_gpio_in(env->pic_state, i);
	222	}
	223
	224	sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
	225	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
	226	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
	227	sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
	228
	229	/* make sure juart isn't the first chardev */
	230	env->juart_state = lm32_juart_init();
	231
	232	reset_info->bootstrap_pc = flash_base;
	233
	234	if (kernel_filename) {
	235	uint64_t entry;
	236	int kernel_size;
	237
	238	kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
	239	1, ELF_MACHINE, 0);
	240	reset_info->bootstrap_pc = entry;
	241
	242	if (kernel_size < 0) {
	243	kernel_size = load_image_targphys(kernel_filename, ram_base,
	244	ram_size);
	245	reset_info->bootstrap_pc = ram_base;
	246	}
	247
	248	if (kernel_size < 0) {
	249	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	250	kernel_filename);
	251	exit(1);
	252	}
	253	}
	254
	255	/* generate a rom with the hardware description */
	256	hw = hwsetup_init();
	257	hwsetup_add_cpu(hw, "LM32", 75000000);
	258	hwsetup_add_flash(hw, "flash", flash_base, flash_size);
	259	hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
	260	hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
	261	hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
	262	hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
	263	hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
	264	hwsetup_add_trailer(hw);
	265	hwsetup_create_rom(hw, hwsetup_base);
	266	hwsetup_free(hw);
	267
	268	reset_info->hwsetup_base = hwsetup_base;
	269
	270	if (kernel_cmdline && strlen(kernel_cmdline)) {
	271	pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
	272	kernel_cmdline);
	273	reset_info->cmdline_base = cmdline_base;
	274	}
	275
	276	if (initrd_filename) {
	277	size_t initrd_size;
	278	initrd_size = load_image_targphys(initrd_filename, initrd_base,
	279	initrd_max);
280	reset_info->initrd_base = initrd_base;
281	reset_info->initrd_size = initrd_size;
282	}
283
284	qemu_register_reset(main_cpu_reset, reset_info);
285	}
286
287	static QEMUMachine lm32_evr_machine = {
288	.name = "lm32-evr",
289	.desc = "LatticeMico32 EVR32 eval system",
290	.init = lm32_evr_init,
e4ada29e AS	291	.is_default = 1,
e4ada29e AS	292	DEFAULT_MACHINE_OPTIONS,
d821732a MW	293	};
	294
	295	static QEMUMachine lm32_uclinux_machine = {
	296	.name = "lm32-uclinux",
	297	.desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
	298	.init = lm32_uclinux_init,
e4ada29e AS	299	.is_default = 0,
e4ada29e AS	300	DEFAULT_MACHINE_OPTIONS,
d821732a MW	301	};
	302
	303	static void lm32_machine_init(void)
	304	{
	305	qemu_register_machine(&lm32_uclinux_machine);
	306	qemu_register_machine(&lm32_evr_machine);
	307	}
	308
	309	machine_init(lm32_machine_init);