[qemu.git] / hw / intc / armv7m_nvic.c

/*
 * ARM Nested Vectored Interrupt Controller
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 *
 * The ARMv7M System controller is fairly tightly tied in with the
 * NVIC.  Much of that is also implemented here.
 */

#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "hw/arm/arm.h"
#include "exec/address-spaces.h"
#include "gic_internal.h"

typedef struct {
    GICState gic;
    struct {
        uint32_t control;
        uint32_t reload;
        int64_t tick;
        QEMUTimer *timer;
    } systick;
    MemoryRegion sysregmem;
    MemoryRegion gic_iomem_alias;
    MemoryRegion container;
    uint32_t num_irq;
} nvic_state;

#define TYPE_NVIC "armv7m_nvic"
/**
 * NVICClass:
 * @parent_reset: the parent class' reset handler.
 *
 * A model of the v7M NVIC and System Controller
 */
typedef struct NVICClass {
    /*< private >*/
    ARMGICClass parent_class;
    /*< public >*/
    DeviceRealize parent_realize;
    void (*parent_reset)(DeviceState *dev);
} NVICClass;

#define NVIC_CLASS(klass) \
    OBJECT_CLASS_CHECK(NVICClass, (klass), TYPE_NVIC)
#define NVIC_GET_CLASS(obj) \
    OBJECT_GET_CLASS(NVICClass, (obj), TYPE_NVIC)
#define NVIC(obj) \
    OBJECT_CHECK(nvic_state, (obj), TYPE_NVIC)

static const uint8_t nvic_id[] = {
    0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
};

/* qemu timers run at 1GHz.   We want something closer to 1MHz.  */
#define SYSTICK_SCALE 1000ULL

#define SYSTICK_ENABLE    (1 << 0)
#define SYSTICK_TICKINT   (1 << 1)
#define SYSTICK_CLKSOURCE (1 << 2)
#define SYSTICK_COUNTFLAG (1 << 16)

int system_clock_scale;

/* Conversion factor from qemu timer to SysTick frequencies.  */
static inline int64_t systick_scale(nvic_state *s)
{
    if (s->systick.control & SYSTICK_CLKSOURCE)
        return system_clock_scale;
    else
        return 1000;
}

static void systick_reload(nvic_state *s, int reset)
{
    if (reset)
        s->systick.tick = qemu_get_clock_ns(vm_clock);
    s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
    qemu_mod_timer(s->systick.timer, s->systick.tick);
}

static void systick_timer_tick(void * opaque)
{
    nvic_state *s = (nvic_state *)opaque;
    s->systick.control |= SYSTICK_COUNTFLAG;
    if (s->systick.control & SYSTICK_TICKINT) {
        /* Trigger the interrupt.  */
        armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
    }
    if (s->systick.reload == 0) {
        s->systick.control &= ~SYSTICK_ENABLE;
    } else {
        systick_reload(s, 0);
    }
}

static void systick_reset(nvic_state *s)
{
    s->systick.control = 0;
    s->systick.reload = 0;
    s->systick.tick = 0;
    qemu_del_timer(s->systick.timer);
}

/* The external routines use the hardware vector numbering, ie. the first
   IRQ is #16.  The internal GIC routines use #32 as the first IRQ.  */
void armv7m_nvic_set_pending(void *opaque, int irq)
{
    nvic_state *s = (nvic_state *)opaque;
    if (irq >= 16)
        irq += 16;
    gic_set_pending_private(&s->gic, 0, irq);
}

/* Make pending IRQ active.  */
int armv7m_nvic_acknowledge_irq(void *opaque)
{
    nvic_state *s = (nvic_state *)opaque;
    uint32_t irq;

    irq = gic_acknowledge_irq(&s->gic, 0);
    if (irq == 1023)
        hw_error("Interrupt but no vector\n");
    if (irq >= 32)
        irq -= 16;
    return irq;
}

void armv7m_nvic_complete_irq(void *opaque, int irq)
{
    nvic_state *s = (nvic_state *)opaque;
    if (irq >= 16)
        irq += 16;
    gic_complete_irq(&s->gic, 0, irq);
}

static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
{
    uint32_t val;
    int irq;

    switch (offset) {
    case 4: /* Interrupt Control Type.  */
        return (s->num_irq / 32) - 1;
    case 0x10: /* SysTick Control and Status.  */
        val = s->systick.control;
        s->systick.control &= ~SYSTICK_COUNTFLAG;
        return val;
    case 0x14: /* SysTick Reload Value.  */
        return s->systick.reload;
    case 0x18: /* SysTick Current Value.  */
        {
            int64_t t;
            if ((s->systick.control & SYSTICK_ENABLE) == 0)
                return 0;
            t = qemu_get_clock_ns(vm_clock);
            if (t >= s->systick.tick)
                return 0;
            val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
            /* The interrupt in triggered when the timer reaches zero.
               However the counter is not reloaded until the next clock
               tick.  This is a hack to return zero during the first tick.  */
            if (val > s->systick.reload)
                val = 0;
            return val;
        }
    case 0x1c: /* SysTick Calibration Value.  */
        return 10000;
    case 0xd00: /* CPUID Base.  */
        return cpu_single_env->cp15.c0_cpuid;
    case 0xd04: /* Interrupt Control State.  */
        /* VECTACTIVE */
        val = s->gic.running_irq[0];
        if (val == 1023) {
            val = 0;
        } else if (val >= 32) {
            val -= 16;
        }
        /* RETTOBASE */
        if (s->gic.running_irq[0] == 1023
                || s->gic.last_active[s->gic.running_irq[0]][0] == 1023) {
            val |= (1 << 11);
        }
        /* VECTPENDING */
        if (s->gic.current_pending[0] != 1023)
            val |= (s->gic.current_pending[0] << 12);
        /* ISRPENDING */
        for (irq = 32; irq < s->num_irq; irq++) {
            if (s->gic.irq_state[irq].pending) {
                val |= (1 << 22);
                break;
            }
        }
        /* PENDSTSET */
        if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending)
            val |= (1 << 26);
        /* PENDSVSET */
        if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending)
            val |= (1 << 28);
        /* NMIPENDSET */
        if (s->gic.irq_state[ARMV7M_EXCP_NMI].pending)
            val |= (1 << 31);
        return val;
    case 0xd08: /* Vector Table Offset.  */
        return cpu_single_env->v7m.vecbase;
    case 0xd0c: /* Application Interrupt/Reset Control.  */
        return 0xfa05000;
    case 0xd10: /* System Control.  */
        /* TODO: Implement SLEEPONEXIT.  */
        return 0;
    case 0xd14: /* Configuration Control.  */
        /* TODO: Implement Configuration Control bits.  */
        return 0;
    case 0xd24: /* System Handler Status.  */
        val = 0;
        if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
        if (s->gic.irq_state[ARMV7M_EXCP_BUS].active) val |= (1 << 1);
        if (s->gic.irq_state[ARMV7M_EXCP_USAGE].active) val |= (1 << 3);
        if (s->gic.irq_state[ARMV7M_EXCP_SVC].active) val |= (1 << 7);
        if (s->gic.irq_state[ARMV7M_EXCP_DEBUG].active) val |= (1 << 8);
        if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].active) val |= (1 << 10);
        if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].active) val |= (1 << 11);
        if (s->gic.irq_state[ARMV7M_EXCP_USAGE].pending) val |= (1 << 12);
        if (s->gic.irq_state[ARMV7M_EXCP_MEM].pending) val |= (1 << 13);
        if (s->gic.irq_state[ARMV7M_EXCP_BUS].pending) val |= (1 << 14);
        if (s->gic.irq_state[ARMV7M_EXCP_SVC].pending) val |= (1 << 15);
        if (s->gic.irq_state[ARMV7M_EXCP_MEM].enabled) val |= (1 << 16);
        if (s->gic.irq_state[ARMV7M_EXCP_BUS].enabled) val |= (1 << 17);
        if (s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled) val |= (1 << 18);
        return val;
    case 0xd28: /* Configurable Fault Status.  */
        /* TODO: Implement Fault Status.  */
        qemu_log_mask(LOG_UNIMP, "Configurable Fault Status unimplemented\n");
        return 0;
    case 0xd2c: /* Hard Fault Status.  */
    case 0xd30: /* Debug Fault Status.  */
    case 0xd34: /* Mem Manage Address.  */
    case 0xd38: /* Bus Fault Address.  */
    case 0xd3c: /* Aux Fault Status.  */
        /* TODO: Implement fault status registers.  */
        qemu_log_mask(LOG_UNIMP, "Fault status registers unimplemented\n");
        return 0;
    case 0xd40: /* PFR0.  */
        return 0x00000030;
    case 0xd44: /* PRF1.  */
        return 0x00000200;
    case 0xd48: /* DFR0.  */
        return 0x00100000;
    case 0xd4c: /* AFR0.  */
        return 0x00000000;
    case 0xd50: /* MMFR0.  */
        return 0x00000030;
    case 0xd54: /* MMFR1.  */
        return 0x00000000;
    case 0xd58: /* MMFR2.  */
        return 0x00000000;
    case 0xd5c: /* MMFR3.  */
        return 0x00000000;
    case 0xd60: /* ISAR0.  */
        return 0x01141110;
    case 0xd64: /* ISAR1.  */
        return 0x02111000;
    case 0xd68: /* ISAR2.  */
        return 0x21112231;
    case 0xd6c: /* ISAR3.  */
        return 0x01111110;
    case 0xd70: /* ISAR4.  */
        return 0x01310102;
    /* TODO: Implement debug registers.  */
    default:
        qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
        return 0;
    }
}

static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value)
{
    uint32_t oldval;
    switch (offset) {
    case 0x10: /* SysTick Control and Status.  */
        oldval = s->systick.control;
        s->systick.control &= 0xfffffff8;
        s->systick.control |= value & 7;
        if ((oldval ^ value) & SYSTICK_ENABLE) {
            int64_t now = qemu_get_clock_ns(vm_clock);
            if (value & SYSTICK_ENABLE) {
                if (s->systick.tick) {
                    s->systick.tick += now;
                    qemu_mod_timer(s->systick.timer, s->systick.tick);
                } else {
                    systick_reload(s, 1);
                }
            } else {
                qemu_del_timer(s->systick.timer);
                s->systick.tick -= now;
                if (s->systick.tick < 0)
                  s->systick.tick = 0;
            }
        } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
            /* This is a hack. Force the timer to be reloaded
               when the reference clock is changed.  */
            systick_reload(s, 1);
        }
        break;
    case 0x14: /* SysTick Reload Value.  */
        s->systick.reload = value;
        break;
    case 0x18: /* SysTick Current Value.  Writes reload the timer.  */
        systick_reload(s, 1);
        s->systick.control &= ~SYSTICK_COUNTFLAG;
        break;
    case 0xd04: /* Interrupt Control State.  */
        if (value & (1 << 31)) {
            armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
        }
        if (value & (1 << 28)) {
            armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
        } else if (value & (1 << 27)) {
            s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending = 0;
            gic_update(&s->gic);
        }
        if (value & (1 << 26)) {
            armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
        } else if (value & (1 << 25)) {
            s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending = 0;
            gic_update(&s->gic);
        }
        break;
    case 0xd08: /* Vector Table Offset.  */
        cpu_single_env->v7m.vecbase = value & 0xffffff80;
        break;
    case 0xd0c: /* Application Interrupt/Reset Control.  */
        if ((value >> 16) == 0x05fa) {
            if (value & 2) {
                qemu_log_mask(LOG_UNIMP, "VECTCLRACTIVE unimplemented\n");
            }
            if (value & 5) {
                qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n");
            }
        }
        break;
    case 0xd10: /* System Control.  */
    case 0xd14: /* Configuration Control.  */
        /* TODO: Implement control registers.  */
        qemu_log_mask(LOG_UNIMP, "NVIC: SCR and CCR unimplemented\n");
        break;
    case 0xd24: /* System Handler Control.  */
        /* TODO: Real hardware allows you to set/clear the active bits
           under some circumstances.  We don't implement this.  */
        s->gic.irq_state[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
        s->gic.irq_state[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
        s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
        break;
    case 0xd28: /* Configurable Fault Status.  */
    case 0xd2c: /* Hard Fault Status.  */
    case 0xd30: /* Debug Fault Status.  */
    case 0xd34: /* Mem Manage Address.  */
    case 0xd38: /* Bus Fault Address.  */
    case 0xd3c: /* Aux Fault Status.  */
        qemu_log_mask(LOG_UNIMP,
                      "NVIC: fault status registers unimplemented\n");
        break;
    case 0xf00: /* Software Triggered Interrupt Register */
        if ((value & 0x1ff) < s->num_irq) {
            gic_set_pending_private(&s->gic, 0, value & 0x1ff);
        }
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "NVIC: Bad write offset 0x%x\n", offset);
    }
}

static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
                                 unsigned size)
{
    nvic_state *s = (nvic_state *)opaque;
    uint32_t offset = addr;
    int i;
    uint32_t val;

    switch (offset) {
    case 0xd18 ... 0xd23: /* System Handler Priority.  */
        val = 0;
        for (i = 0; i < size; i++) {
            val |= s->gic.priority1[(offset - 0xd14) + i][0] << (i * 8);
        }
        return val;
    case 0xfe0 ... 0xfff: /* ID.  */
        if (offset & 3) {
            return 0;
        }
        return nvic_id[(offset - 0xfe0) >> 2];
    }
    if (size == 4) {
        return nvic_readl(s, offset);
    }
    qemu_log_mask(LOG_GUEST_ERROR,
                  "NVIC: Bad read of size %d at offset 0x%x\n", size, offset);
    return 0;
}

static void nvic_sysreg_write(void *opaque, hwaddr addr,
                              uint64_t value, unsigned size)
{
    nvic_state *s = (nvic_state *)opaque;
    uint32_t offset = addr;
    int i;

    switch (offset) {
    case 0xd18 ... 0xd23: /* System Handler Priority.  */
        for (i = 0; i < size; i++) {
            s->gic.priority1[(offset - 0xd14) + i][0] =
                (value >> (i * 8)) & 0xff;
        }
        gic_update(&s->gic);
        return;
    }
    if (size == 4) {
        nvic_writel(s, offset, value);
        return;
    }
    qemu_log_mask(LOG_GUEST_ERROR,
                  "NVIC: Bad write of size %d at offset 0x%x\n", size, offset);
}

static const MemoryRegionOps nvic_sysreg_ops = {
    .read = nvic_sysreg_read,
    .write = nvic_sysreg_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static const VMStateDescription vmstate_nvic = {
    .name = "armv7m_nvic",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(systick.control, nvic_state),
        VMSTATE_UINT32(systick.reload, nvic_state),
        VMSTATE_INT64(systick.tick, nvic_state),
        VMSTATE_TIMER(systick.timer, nvic_state),
        VMSTATE_END_OF_LIST()
    }
};

static void armv7m_nvic_reset(DeviceState *dev)
{
    nvic_state *s = NVIC(dev);
    NVICClass *nc = NVIC_GET_CLASS(s);
    nc->parent_reset(dev);
    /* Common GIC reset resets to disabled; the NVIC doesn't have
     * per-CPU interfaces so mark our non-existent CPU interface
     * as enabled by default, and with a priority mask which allows
     * all interrupts through.
     */
    s->gic.cpu_enabled[0] = true;
    s->gic.priority_mask[0] = 0x100;
    /* The NVIC as a whole is always enabled. */
    s->gic.enabled = true;
    systick_reset(s);
}

static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
{
    nvic_state *s = NVIC(dev);
    NVICClass *nc = NVIC_GET_CLASS(s);

    /* The NVIC always has only one CPU */
    s->gic.num_cpu = 1;
    /* Tell the common code we're an NVIC */
    s->gic.revision = 0xffffffff;
    s->num_irq = s->gic.num_irq;
    nc->parent_realize(dev, errp);
    if (error_is_set(errp)) {
        return;
    }
    gic_init_irqs_and_distributor(&s->gic, s->num_irq);
    /* The NVIC and system controller register area looks like this:
     *  0..0xff : system control registers, including systick
     *  0x100..0xcff : GIC-like registers
     *  0xd00..0xfff : system control registers
     * We use overlaying to put the GIC like registers
     * over the top of the system control register region.
     */
    memory_region_init(&s->container, "nvic", 0x1000);
    /* The system register region goes at the bottom of the priority
     * stack as it covers the whole page.
     */
    memory_region_init_io(&s->sysregmem, &nvic_sysreg_ops, s,
                          "nvic_sysregs", 0x1000);
    memory_region_add_subregion(&s->container, 0, &s->sysregmem);
    /* Alias the GIC region so we can get only the section of it
     * we need, and layer it on top of the system register region.
     */
    memory_region_init_alias(&s->gic_iomem_alias, "nvic-gic", &s->gic.iomem,
                             0x100, 0xc00);
    memory_region_add_subregion_overlap(&s->container, 0x100,
                                        &s->gic_iomem_alias, 1);
    /* Map the whole thing into system memory at the location required
     * by the v7M architecture.
     */
    memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->container);
    s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s);
}

static void armv7m_nvic_instance_init(Object *obj)
{
    /* We have a different default value for the num-irq property
     * than our superclass. This function runs after qdev init
     * has set the defaults from the Property array and before
     * any user-specified property setting, so just modify the
     * value in the GICState struct.
     */
    GICState *s = ARM_GIC_COMMON(obj);
    /* The ARM v7m may have anything from 0 to 496 external interrupt
     * IRQ lines. We default to 64. Other boards may differ and should
     * set the num-irq property appropriately.
     */
    s->num_irq = 64;
}

static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
{
    NVICClass *nc = NVIC_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    nc->parent_reset = dc->reset;
    nc->parent_realize = dc->realize;
    dc->vmsd  = &vmstate_nvic;
    dc->reset = armv7m_nvic_reset;
    dc->realize = armv7m_nvic_realize;
}

static const TypeInfo armv7m_nvic_info = {
    .name          = TYPE_NVIC,
    .parent        = TYPE_ARM_GIC_COMMON,
    .instance_init = armv7m_nvic_instance_init,
    .instance_size = sizeof(nvic_state),
    .class_init    = armv7m_nvic_class_init,
    .class_size    = sizeof(NVICClass),
};

static void armv7m_nvic_register_types(void)
{
    type_register_static(&armv7m_nvic_info);
}

type_init(armv7m_nvic_register_types)
Commit	Line	Data
9ee6e8bb PB	1	/*
	2	* ARM Nested Vectored Interrupt Controller
	3	*
	4	* Copyright (c) 2006-2007 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
9ee6e8bb PB	8	*
	9	* The ARMv7M System controller is fairly tightly tied in with the
	10	* NVIC. Much of that is also implemented here.
	11	*/
	12
83c9f4ca	13	#include "hw/sysbus.h"
1de7afc9	14	#include "qemu/timer.h"
bd2be150	15	#include "hw/arm/arm.h"
022c62cb	16	#include "exec/address-spaces.h"
47b43a1f	17	#include "gic_internal.h"
9ee6e8bb PB	18
9ee6e8bb PB	19	typedef struct {
fae15286	20	GICState gic;
9ee6e8bb PB	21	struct {
	22	uint32_t control;
	23	uint32_t reload;
	24	int64_t tick;
	25	QEMUTimer *timer;
	26	} systick;
2a29ddee PM	27	MemoryRegion sysregmem;
	28	MemoryRegion gic_iomem_alias;
	29	MemoryRegion container;
a32134aa	30	uint32_t num_irq;
9ee6e8bb PB	31	} nvic_state;
9ee6e8bb PB	32
1e8cae4d PM	33	#define TYPE_NVIC "armv7m_nvic"
	34	/**
	35	* NVICClass:
	36	* @parent_reset: the parent class' reset handler.
	37	*
	38	* A model of the v7M NVIC and System Controller
	39	*/
	40	typedef struct NVICClass {
	41	/< private >/
	42	ARMGICClass parent_class;
	43	/< public >/
53111180	44	DeviceRealize parent_realize;
1e8cae4d PM	45	void (parent_reset)(DeviceState dev);
	46	} NVICClass;
	47
	48	#define NVIC_CLASS(klass) \
	49	OBJECT_CLASS_CHECK(NVICClass, (klass), TYPE_NVIC)
	50	#define NVIC_GET_CLASS(obj) \
	51	OBJECT_GET_CLASS(NVICClass, (obj), TYPE_NVIC)
	52	#define NVIC(obj) \
	53	OBJECT_CHECK(nvic_state, (obj), TYPE_NVIC)
	54
2a29ddee PM	55	static const uint8_t nvic_id[] = {
	56	0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
	57	};
	58
9ee6e8bb PB	59	/* qemu timers run at 1GHz. We want something closer to 1MHz. */
	60	#define SYSTICK_SCALE 1000ULL
	61
	62	#define SYSTICK_ENABLE (1 << 0)
	63	#define SYSTICK_TICKINT (1 << 1)
	64	#define SYSTICK_CLKSOURCE (1 << 2)
	65	#define SYSTICK_COUNTFLAG (1 << 16)
	66
7ee930d0 BS	67	int system_clock_scale;
7ee930d0 BS	68
e57ec016	69	/* Conversion factor from qemu timer to SysTick frequencies. */
9ee6e8bb PB	70	static inline int64_t systick_scale(nvic_state *s)
	71	{
	72	if (s->systick.control & SYSTICK_CLKSOURCE)
e57ec016	73	return system_clock_scale;
9ee6e8bb PB	74	else
	75	return 1000;
	76	}
	77
	78	static void systick_reload(nvic_state *s, int reset)
	79	{
	80	if (reset)
74475455	81	s->systick.tick = qemu_get_clock_ns(vm_clock);
9ee6e8bb PB	82	s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
	83	qemu_mod_timer(s->systick.timer, s->systick.tick);
	84	}
	85
	86	static void systick_timer_tick(void * opaque)
	87	{
	88	nvic_state s = (nvic_state )opaque;
	89	s->systick.control \|= SYSTICK_COUNTFLAG;
	90	if (s->systick.control & SYSTICK_TICKINT) {
	91	/* Trigger the interrupt. */
	92	armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
	93	}
	94	if (s->systick.reload == 0) {
	95	s->systick.control &= ~SYSTICK_ENABLE;
	96	} else {
	97	systick_reload(s, 0);
	98	}
	99	}
	100
aecff692 PM	101	static void systick_reset(nvic_state *s)
	102	{
	103	s->systick.control = 0;
	104	s->systick.reload = 0;
	105	s->systick.tick = 0;
	106	qemu_del_timer(s->systick.timer);
	107	}
	108
9ee6e8bb PB	109	/* The external routines use the hardware vector numbering, ie. the first
	110	IRQ is #16. The internal GIC routines use #32 as the first IRQ. */
	111	void armv7m_nvic_set_pending(void *opaque, int irq)
	112	{
	113	nvic_state s = (nvic_state )opaque;
	114	if (irq >= 16)
	115	irq += 16;
fe7e8758	116	gic_set_pending_private(&s->gic, 0, irq);
9ee6e8bb PB	117	}
	118
	119	/* Make pending IRQ active. */
	120	int armv7m_nvic_acknowledge_irq(void *opaque)
	121	{
	122	nvic_state s = (nvic_state )opaque;
	123	uint32_t irq;
	124
fe7e8758	125	irq = gic_acknowledge_irq(&s->gic, 0);
9ee6e8bb	126	if (irq == 1023)
2ac71179	127	hw_error("Interrupt but no vector\n");
9ee6e8bb PB	128	if (irq >= 32)
	129	irq -= 16;
	130	return irq;
	131	}
	132
	133	void armv7m_nvic_complete_irq(void *opaque, int irq)
	134	{
	135	nvic_state s = (nvic_state )opaque;
	136	if (irq >= 16)
	137	irq += 16;
fe7e8758	138	gic_complete_irq(&s->gic, 0, irq);
9ee6e8bb PB	139	}
9ee6e8bb PB	140
0e8153dd	141	static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
9ee6e8bb	142	{
9ee6e8bb PB	143	uint32_t val;
	144	int irq;
	145
	146	switch (offset) {
	147	case 4: /* Interrupt Control Type. */
a32134aa	148	return (s->num_irq / 32) - 1;
9ee6e8bb PB	149	case 0x10: /* SysTick Control and Status. */
	150	val = s->systick.control;
	151	s->systick.control &= ~SYSTICK_COUNTFLAG;
	152	return val;
	153	case 0x14: /* SysTick Reload Value. */
	154	return s->systick.reload;
	155	case 0x18: /* SysTick Current Value. */
	156	{
	157	int64_t t;
	158	if ((s->systick.control & SYSTICK_ENABLE) == 0)
	159	return 0;
74475455	160	t = qemu_get_clock_ns(vm_clock);
9ee6e8bb PB	161	if (t >= s->systick.tick)
	162	return 0;
	163	val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
	164	/* The interrupt in triggered when the timer reaches zero.
	165	However the counter is not reloaded until the next clock
	166	tick. This is a hack to return zero during the first tick. */
	167	if (val > s->systick.reload)
	168	val = 0;
	169	return val;
	170	}
	171	case 0x1c: /* SysTick Calibration Value. */
	172	return 10000;
	173	case 0xd00: /* CPUID Base. */
	174	return cpu_single_env->cp15.c0_cpuid;
e03ba136	175	case 0xd04: /* Interrupt Control State. */
9ee6e8bb	176	/* VECTACTIVE */
fe7e8758	177	val = s->gic.running_irq[0];
9ee6e8bb PB	178	if (val == 1023) {
	179	val = 0;
	180	} else if (val >= 32) {
	181	val -= 16;
	182	}
	183	/* RETTOBASE */
fe7e8758 PB	184	if (s->gic.running_irq[0] == 1023
fe7e8758 PB	185	\|\| s->gic.last_active[s->gic.running_irq[0]][0] == 1023) {
9ee6e8bb PB	186	val \|= (1 << 11);
	187	}
	188	/* VECTPENDING */
fe7e8758 PB	189	if (s->gic.current_pending[0] != 1023)
fe7e8758 PB	190	val \|= (s->gic.current_pending[0] << 12);
9ee6e8bb	191	/* ISRPENDING */
a32134aa	192	for (irq = 32; irq < s->num_irq; irq++) {
fe7e8758	193	if (s->gic.irq_state[irq].pending) {
9ee6e8bb PB	194	val \|= (1 << 22);
	195	break;
	196	}
	197	}
	198	/* PENDSTSET */
fe7e8758	199	if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending)
9ee6e8bb PB	200	val \|= (1 << 26);
9ee6e8bb PB	201	/* PENDSVSET */
fe7e8758	202	if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending)
9ee6e8bb PB	203	val \|= (1 << 28);
9ee6e8bb PB	204	/* NMIPENDSET */
fe7e8758	205	if (s->gic.irq_state[ARMV7M_EXCP_NMI].pending)
9ee6e8bb PB	206	val \|= (1 << 31);
	207	return val;
	208	case 0xd08: /* Vector Table Offset. */
	209	return cpu_single_env->v7m.vecbase;
	210	case 0xd0c: /* Application Interrupt/Reset Control. */
	211	return 0xfa05000;
	212	case 0xd10: /* System Control. */
	213	/* TODO: Implement SLEEPONEXIT. */
	214	return 0;
	215	case 0xd14: /* Configuration Control. */
	216	/* TODO: Implement Configuration Control bits. */
	217	return 0;
9ee6e8bb PB	218	case 0xd24: /* System Handler Status. */
9ee6e8bb PB	219	val = 0;
fe7e8758 PB	220	if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val \|= (1 << 0);
	221	if (s->gic.irq_state[ARMV7M_EXCP_BUS].active) val \|= (1 << 1);
	222	if (s->gic.irq_state[ARMV7M_EXCP_USAGE].active) val \|= (1 << 3);
	223	if (s->gic.irq_state[ARMV7M_EXCP_SVC].active) val \|= (1 << 7);
	224	if (s->gic.irq_state[ARMV7M_EXCP_DEBUG].active) val \|= (1 << 8);
	225	if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].active) val \|= (1 << 10);
	226	if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].active) val \|= (1 << 11);
	227	if (s->gic.irq_state[ARMV7M_EXCP_USAGE].pending) val \|= (1 << 12);
	228	if (s->gic.irq_state[ARMV7M_EXCP_MEM].pending) val \|= (1 << 13);
	229	if (s->gic.irq_state[ARMV7M_EXCP_BUS].pending) val \|= (1 << 14);
	230	if (s->gic.irq_state[ARMV7M_EXCP_SVC].pending) val \|= (1 << 15);
	231	if (s->gic.irq_state[ARMV7M_EXCP_MEM].enabled) val \|= (1 << 16);
	232	if (s->gic.irq_state[ARMV7M_EXCP_BUS].enabled) val \|= (1 << 17);
	233	if (s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled) val \|= (1 << 18);
9ee6e8bb PB	234	return val;
	235	case 0xd28: /* Configurable Fault Status. */
	236	/* TODO: Implement Fault Status. */
e72e3ffc	237	qemu_log_mask(LOG_UNIMP, "Configurable Fault Status unimplemented\n");
9ee6e8bb PB	238	return 0;
	239	case 0xd2c: /* Hard Fault Status. */
	240	case 0xd30: /* Debug Fault Status. */
	241	case 0xd34: /* Mem Manage Address. */
	242	case 0xd38: /* Bus Fault Address. */
	243	case 0xd3c: /* Aux Fault Status. */
	244	/* TODO: Implement fault status registers. */
e72e3ffc PM	245	qemu_log_mask(LOG_UNIMP, "Fault status registers unimplemented\n");
e72e3ffc PM	246	return 0;
9ee6e8bb PB	247	case 0xd40: /* PFR0. */
	248	return 0x00000030;
	249	case 0xd44: /* PRF1. */
	250	return 0x00000200;
	251	case 0xd48: /* DFR0. */
	252	return 0x00100000;
	253	case 0xd4c: /* AFR0. */
	254	return 0x00000000;
	255	case 0xd50: /* MMFR0. */
	256	return 0x00000030;
	257	case 0xd54: /* MMFR1. */
	258	return 0x00000000;
	259	case 0xd58: /* MMFR2. */
	260	return 0x00000000;
	261	case 0xd5c: /* MMFR3. */
	262	return 0x00000000;
	263	case 0xd60: /* ISAR0. */
	264	return 0x01141110;
	265	case 0xd64: /* ISAR1. */
	266	return 0x02111000;
	267	case 0xd68: /* ISAR2. */
	268	return 0x21112231;
	269	case 0xd6c: /* ISAR3. */
	270	return 0x01111110;
	271	case 0xd70: /* ISAR4. */
	272	return 0x01310102;
	273	/* TODO: Implement debug registers. */
	274	default:
e72e3ffc PM	275	qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
e72e3ffc PM	276	return 0;
9ee6e8bb PB	277	}
	278	}
	279
0e8153dd	280	static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value)
9ee6e8bb	281	{
9ee6e8bb PB	282	uint32_t oldval;
	283	switch (offset) {
	284	case 0x10: /* SysTick Control and Status. */
	285	oldval = s->systick.control;
	286	s->systick.control &= 0xfffffff8;
	287	s->systick.control \|= value & 7;
	288	if ((oldval ^ value) & SYSTICK_ENABLE) {
74475455	289	int64_t now = qemu_get_clock_ns(vm_clock);
9ee6e8bb PB	290	if (value & SYSTICK_ENABLE) {
	291	if (s->systick.tick) {
	292	s->systick.tick += now;
	293	qemu_mod_timer(s->systick.timer, s->systick.tick);
	294	} else {
	295	systick_reload(s, 1);
	296	}
	297	} else {
	298	qemu_del_timer(s->systick.timer);
	299	s->systick.tick -= now;
	300	if (s->systick.tick < 0)
	301	s->systick.tick = 0;
	302	}
	303	} else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
	304	/* This is a hack. Force the timer to be reloaded
	305	when the reference clock is changed. */
	306	systick_reload(s, 1);
	307	}
	308	break;
	309	case 0x14: /* SysTick Reload Value. */
	310	s->systick.reload = value;
	311	break;
	312	case 0x18: /* SysTick Current Value. Writes reload the timer. */
	313	systick_reload(s, 1);
	314	s->systick.control &= ~SYSTICK_COUNTFLAG;
	315	break;
	316	case 0xd04: /* Interrupt Control State. */
	317	if (value & (1 << 31)) {
	318	armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
	319	}
	320	if (value & (1 << 28)) {
	321	armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
	322	} else if (value & (1 << 27)) {
fe7e8758 PB	323	s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending = 0;
fe7e8758 PB	324	gic_update(&s->gic);
9ee6e8bb PB	325	}
	326	if (value & (1 << 26)) {
	327	armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
	328	} else if (value & (1 << 25)) {
fe7e8758 PB	329	s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending = 0;
fe7e8758 PB	330	gic_update(&s->gic);
9ee6e8bb PB	331	}
	332	break;
	333	case 0xd08: /* Vector Table Offset. */
	334	cpu_single_env->v7m.vecbase = value & 0xffffff80;
	335	break;
	336	case 0xd0c: /* Application Interrupt/Reset Control. */
	337	if ((value >> 16) == 0x05fa) {
	338	if (value & 2) {
e72e3ffc	339	qemu_log_mask(LOG_UNIMP, "VECTCLRACTIVE unimplemented\n");
9ee6e8bb PB	340	}
9ee6e8bb PB	341	if (value & 5) {
e72e3ffc	342	qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n");
9ee6e8bb PB	343	}
	344	}
	345	break;
	346	case 0xd10: /* System Control. */
	347	case 0xd14: /* Configuration Control. */
	348	/* TODO: Implement control registers. */
e72e3ffc PM	349	qemu_log_mask(LOG_UNIMP, "NVIC: SCR and CCR unimplemented\n");
e72e3ffc PM	350	break;
9ee6e8bb PB	351	case 0xd24: /* System Handler Control. */
	352	/* TODO: Real hardware allows you to set/clear the active bits
	353	under some circumstances. We don't implement this. */
fe7e8758 PB	354	s->gic.irq_state[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
	355	s->gic.irq_state[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
	356	s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
9ee6e8bb PB	357	break;
	358	case 0xd28: /* Configurable Fault Status. */
	359	case 0xd2c: /* Hard Fault Status. */
	360	case 0xd30: /* Debug Fault Status. */
	361	case 0xd34: /* Mem Manage Address. */
	362	case 0xd38: /* Bus Fault Address. */
	363	case 0xd3c: /* Aux Fault Status. */
e72e3ffc PM	364	qemu_log_mask(LOG_UNIMP,
	365	"NVIC: fault status registers unimplemented\n");
	366	break;
2a29ddee PM	367	case 0xf00: /* Software Triggered Interrupt Register */
	368	if ((value & 0x1ff) < s->num_irq) {
	369	gic_set_pending_private(&s->gic, 0, value & 0x1ff);
	370	}
	371	break;
9ee6e8bb	372	default:
e72e3ffc PM	373	qemu_log_mask(LOG_GUEST_ERROR,
e72e3ffc PM	374	"NVIC: Bad write offset 0x%x\n", offset);
9ee6e8bb PB	375	}
	376	}
	377
a8170e5e	378	static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
2a29ddee PM	379	unsigned size)
2a29ddee PM	380	{
0e8153dd	381	nvic_state s = (nvic_state )opaque;
2a29ddee	382	uint32_t offset = addr;
0e8153dd AB	383	int i;
	384	uint32_t val;
	385
	386	switch (offset) {
	387	case 0xd18 ... 0xd23: /* System Handler Priority. */
	388	val = 0;
	389	for (i = 0; i < size; i++) {
	390	val \|= s->gic.priority1[(offset - 0xd14) + i][0] << (i * 8);
	391	}
	392	return val;
	393	case 0xfe0 ... 0xfff: /* ID. */
2a29ddee PM	394	if (offset & 3) {
	395	return 0;
	396	}
	397	return nvic_id[(offset - 0xfe0) >> 2];
	398	}
	399	if (size == 4) {
0e8153dd	400	return nvic_readl(s, offset);
2a29ddee	401	}
e72e3ffc PM	402	qemu_log_mask(LOG_GUEST_ERROR,
	403	"NVIC: Bad read of size %d at offset 0x%x\n", size, offset);
	404	return 0;
2a29ddee PM	405	}
2a29ddee PM	406
a8170e5e	407	static void nvic_sysreg_write(void *opaque, hwaddr addr,
2a29ddee PM	408	uint64_t value, unsigned size)
2a29ddee PM	409	{
0e8153dd	410	nvic_state s = (nvic_state )opaque;
2a29ddee	411	uint32_t offset = addr;
0e8153dd AB	412	int i;
	413
	414	switch (offset) {
	415	case 0xd18 ... 0xd23: /* System Handler Priority. */
	416	for (i = 0; i < size; i++) {
	417	s->gic.priority1[(offset - 0xd14) + i][0] =
	418	(value >> (i * 8)) & 0xff;
	419	}
	420	gic_update(&s->gic);
	421	return;
	422	}
2a29ddee	423	if (size == 4) {
0e8153dd	424	nvic_writel(s, offset, value);
2a29ddee PM	425	return;
2a29ddee PM	426	}
e72e3ffc PM	427	qemu_log_mask(LOG_GUEST_ERROR,
e72e3ffc PM	428	"NVIC: Bad write of size %d at offset 0x%x\n", size, offset);
2a29ddee PM	429	}
	430
	431	static const MemoryRegionOps nvic_sysreg_ops = {
	432	.read = nvic_sysreg_read,
	433	.write = nvic_sysreg_write,
	434	.endianness = DEVICE_NATIVE_ENDIAN,
	435	};
	436
0797226c JQ	437	static const VMStateDescription vmstate_nvic = {
	438	.name = "armv7m_nvic",
	439	.version_id = 1,
	440	.minimum_version_id = 1,
	441	.minimum_version_id_old = 1,
	442	.fields = (VMStateField[]) {
	443	VMSTATE_UINT32(systick.control, nvic_state),
	444	VMSTATE_UINT32(systick.reload, nvic_state),
	445	VMSTATE_INT64(systick.tick, nvic_state),
	446	VMSTATE_TIMER(systick.timer, nvic_state),
	447	VMSTATE_END_OF_LIST()
	448	}
	449	};
23e39294	450
aecff692 PM	451	static void armv7m_nvic_reset(DeviceState *dev)
aecff692 PM	452	{
1e8cae4d PM	453	nvic_state *s = NVIC(dev);
	454	NVICClass *nc = NVIC_GET_CLASS(s);
	455	nc->parent_reset(dev);
b3387ede PM	456	/* Common GIC reset resets to disabled; the NVIC doesn't have
b3387ede PM	457	* per-CPU interfaces so mark our non-existent CPU interface
ee3f0956 PM	458	* as enabled by default, and with a priority mask which allows
ee3f0956 PM	459	* all interrupts through.
b3387ede	460	*/
c3037774	461	s->gic.cpu_enabled[0] = true;
ee3f0956	462	s->gic.priority_mask[0] = 0x100;
b3387ede	463	/* The NVIC as a whole is always enabled. */
c3037774	464	s->gic.enabled = true;
aecff692 PM	465	systick_reset(s);
	466	}
	467
53111180	468	static void armv7m_nvic_realize(DeviceState dev, Error *errp)
9ee6e8bb	469	{
1e8cae4d PM	470	nvic_state *s = NVIC(dev);
1e8cae4d PM	471	NVICClass *nc = NVIC_GET_CLASS(s);
9ee6e8bb	472
c48c6522 PM	473	/* The NVIC always has only one CPU */
c48c6522 PM	474	s->gic.num_cpu = 1;
306a571a PM	475	/* Tell the common code we're an NVIC */
306a571a PM	476	s->gic.revision = 0xffffffff;
55e00a19	477	s->num_irq = s->gic.num_irq;
53111180 PM	478	nc->parent_realize(dev, errp);
	479	if (error_is_set(errp)) {
	480	return;
	481	}
2b518c56	482	gic_init_irqs_and_distributor(&s->gic, s->num_irq);
2a29ddee PM	483	/* The NVIC and system controller register area looks like this:
	484	* 0..0xff : system control registers, including systick
	485	* 0x100..0xcff : GIC-like registers
	486	* 0xd00..0xfff : system control registers
	487	* We use overlaying to put the GIC like registers
	488	* over the top of the system control register region.
	489	*/
	490	memory_region_init(&s->container, "nvic", 0x1000);
	491	/* The system register region goes at the bottom of the priority
	492	* stack as it covers the whole page.
	493	*/
	494	memory_region_init_io(&s->sysregmem, &nvic_sysreg_ops, s,
	495	"nvic_sysregs", 0x1000);
	496	memory_region_add_subregion(&s->container, 0, &s->sysregmem);
	497	/* Alias the GIC region so we can get only the section of it
	498	* we need, and layer it on top of the system register region.
	499	*/
	500	memory_region_init_alias(&s->gic_iomem_alias, "nvic-gic", &s->gic.iomem,
	501	0x100, 0xc00);
9892cae3 MI	502	memory_region_add_subregion_overlap(&s->container, 0x100,
9892cae3 MI	503	&s->gic_iomem_alias, 1);
2a29ddee PM	504	/* Map the whole thing into system memory at the location required
	505	* by the v7M architecture.
	506	*/
	507	memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->container);
74475455	508	s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s);
9ee6e8bb	509	}
fe7e8758	510
55e00a19 PM	511	static void armv7m_nvic_instance_init(Object *obj)
	512	{
	513	/* We have a different default value for the num-irq property
	514	* than our superclass. This function runs after qdev init
	515	* has set the defaults from the Property array and before
	516	* any user-specified property setting, so just modify the
fae15286	517	* value in the GICState struct.
55e00a19	518	*/
fae15286	519	GICState *s = ARM_GIC_COMMON(obj);
39bffca2 AL	520	/* The ARM v7m may have anything from 0 to 496 external interrupt
39bffca2 AL	521	* IRQ lines. We default to 64. Other boards may differ and should
55e00a19	522	* set the num-irq property appropriately.
39bffca2	523	*/
55e00a19 PM	524	s->num_irq = 64;
55e00a19 PM	525	}
39bffca2	526
999e12bb AL	527	static void armv7m_nvic_class_init(ObjectClass klass, void data)
999e12bb AL	528	{
1e8cae4d	529	NVICClass *nc = NVIC_CLASS(klass);
39bffca2	530	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	531
1e8cae4d	532	nc->parent_reset = dc->reset;
53111180	533	nc->parent_realize = dc->realize;
39bffca2	534	dc->vmsd = &vmstate_nvic;
aecff692	535	dc->reset = armv7m_nvic_reset;
53111180	536	dc->realize = armv7m_nvic_realize;
999e12bb AL	537	}
999e12bb AL	538
8c43a6f0	539	static const TypeInfo armv7m_nvic_info = {
1e8cae4d PM	540	.name = TYPE_NVIC,
1e8cae4d PM	541	.parent = TYPE_ARM_GIC_COMMON,
55e00a19	542	.instance_init = armv7m_nvic_instance_init,
39bffca2 AL	543	.instance_size = sizeof(nvic_state),
39bffca2 AL	544	.class_init = armv7m_nvic_class_init,
1e8cae4d	545	.class_size = sizeof(NVICClass),
a32134aa ML	546	};
a32134aa ML	547
83f7d43a	548	static void armv7m_nvic_register_types(void)
fe7e8758	549	{
39bffca2	550	type_register_static(&armv7m_nvic_info);
fe7e8758 PB	551	}
fe7e8758 PB	552
83f7d43a	553	type_init(armv7m_nvic_register_types)