[qemu.git] / hw / display / tc6393xb.c

/*
 * Toshiba TC6393XB I/O Controller.
 * Found in Sharp Zaurus SL-6000 (tosa) or some
 * Toshiba e-Series PDAs.
 *
 * Most features are currently unsupported!!!
 *
 * This code is licensed under the GNU GPL v2.
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */
#include "hw/hw.h"
#include "hw/devices.h"
#include "hw/block/flash.h"
#include "ui/console.h"
#include "ui/pixel_ops.h"
#include "sysemu/blockdev.h"

#define IRQ_TC6393_NAND		0
#define IRQ_TC6393_MMC		1
#define IRQ_TC6393_OHCI		2
#define IRQ_TC6393_SERIAL	3
#define IRQ_TC6393_FB		4

#define	TC6393XB_NR_IRQS	8

#define TC6393XB_GPIOS  16

#define SCR_REVID	0x08		/* b Revision ID	*/
#define SCR_ISR		0x50		/* b Interrupt Status	*/
#define SCR_IMR		0x52		/* b Interrupt Mask	*/
#define SCR_IRR		0x54		/* b Interrupt Routing	*/
#define SCR_GPER	0x60		/* w GP Enable		*/
#define SCR_GPI_SR(i)	(0x64 + (i))	/* b3 GPI Status	*/
#define SCR_GPI_IMR(i)	(0x68 + (i))	/* b3 GPI INT Mask	*/
#define SCR_GPI_EDER(i)	(0x6c + (i))	/* b3 GPI Edge Detect Enable */
#define SCR_GPI_LIR(i)	(0x70 + (i))	/* b3 GPI Level Invert	*/
#define SCR_GPO_DSR(i)	(0x78 + (i))	/* b3 GPO Data Set	*/
#define SCR_GPO_DOECR(i) (0x7c + (i))	/* b3 GPO Data OE Control */
#define SCR_GP_IARCR(i)	(0x80 + (i))	/* b3 GP Internal Active Register Control */
#define SCR_GP_IARLCR(i) (0x84 + (i))	/* b3 GP INTERNAL Active Register Level Control */
#define SCR_GPI_BCR(i)	(0x88 + (i))	/* b3 GPI Buffer Control */
#define SCR_GPA_IARCR	0x8c		/* w GPa Internal Active Register Control */
#define SCR_GPA_IARLCR	0x90		/* w GPa Internal Active Register Level Control */
#define SCR_GPA_BCR	0x94		/* w GPa Buffer Control */
#define SCR_CCR		0x98		/* w Clock Control	*/
#define SCR_PLL2CR	0x9a		/* w PLL2 Control	*/
#define SCR_PLL1CR	0x9c		/* l PLL1 Control	*/
#define SCR_DIARCR	0xa0		/* b Device Internal Active Register Control */
#define SCR_DBOCR	0xa1		/* b Device Buffer Off Control */
#define SCR_FER		0xe0		/* b Function Enable	*/
#define SCR_MCR		0xe4		/* w Mode Control	*/
#define SCR_CONFIG	0xfc		/* b Configuration Control */
#define SCR_DEBUG	0xff		/* b Debug		*/

#define NAND_CFG_COMMAND    0x04    /* w Command        */
#define NAND_CFG_BASE       0x10    /* l Control Base Address */
#define NAND_CFG_INTP       0x3d    /* b Interrupt Pin  */
#define NAND_CFG_INTE       0x48    /* b Int Enable     */
#define NAND_CFG_EC         0x4a    /* b Event Control  */
#define NAND_CFG_ICC        0x4c    /* b Internal Clock Control */
#define NAND_CFG_ECCC       0x5b    /* b ECC Control    */
#define NAND_CFG_NFTC       0x60    /* b NAND Flash Transaction Control */
#define NAND_CFG_NFM        0x61    /* b NAND Flash Monitor */
#define NAND_CFG_NFPSC      0x62    /* b NAND Flash Power Supply Control */
#define NAND_CFG_NFDC       0x63    /* b NAND Flash Detect Control */

#define NAND_DATA   0x00        /* l Data       */
#define NAND_MODE   0x04        /* b Mode       */
#define NAND_STATUS 0x05        /* b Status     */
#define NAND_ISR    0x06        /* b Interrupt Status */
#define NAND_IMR    0x07        /* b Interrupt Mask */

#define NAND_MODE_WP        0x80
#define NAND_MODE_CE        0x10
#define NAND_MODE_ALE       0x02
#define NAND_MODE_CLE       0x01
#define NAND_MODE_ECC_MASK  0x60
#define NAND_MODE_ECC_EN    0x20
#define NAND_MODE_ECC_READ  0x40
#define NAND_MODE_ECC_RST   0x60

struct TC6393xbState {
    MemoryRegion iomem;
    qemu_irq irq;
    qemu_irq *sub_irqs;
    struct {
        uint8_t ISR;
        uint8_t IMR;
        uint8_t IRR;
        uint16_t GPER;
        uint8_t GPI_SR[3];
        uint8_t GPI_IMR[3];
        uint8_t GPI_EDER[3];
        uint8_t GPI_LIR[3];
        uint8_t GP_IARCR[3];
        uint8_t GP_IARLCR[3];
        uint8_t GPI_BCR[3];
        uint16_t GPA_IARCR;
        uint16_t GPA_IARLCR;
        uint16_t CCR;
        uint16_t PLL2CR;
        uint32_t PLL1CR;
        uint8_t DIARCR;
        uint8_t DBOCR;
        uint8_t FER;
        uint16_t MCR;
        uint8_t CONFIG;
        uint8_t DEBUG;
    } scr;
    uint32_t gpio_dir;
    uint32_t gpio_level;
    uint32_t prev_level;
    qemu_irq handler[TC6393XB_GPIOS];
    qemu_irq *gpio_in;

    struct {
        uint8_t mode;
        uint8_t isr;
        uint8_t imr;
    } nand;
    int nand_enable;
    uint32_t nand_phys;
    DeviceState *flash;
    ECCState ecc;

    QemuConsole *con;
    MemoryRegion vram;
    uint16_t *vram_ptr;
    uint32_t scr_width, scr_height; /* in pixels */
    qemu_irq l3v;
    unsigned blank : 1,
             blanked : 1;
};

qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s)
{
    return s->gpio_in;
}

static void tc6393xb_gpio_set(void *opaque, int line, int level)
{
//    TC6393xbState *s = opaque;

    if (line > TC6393XB_GPIOS) {
        printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
        return;
    }

    // FIXME: how does the chip reflect the GPIO input level change?
}

void tc6393xb_gpio_out_set(TC6393xbState *s, int line,
                    qemu_irq handler)
{
    if (line >= TC6393XB_GPIOS) {
        fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line);
        return;
    }

    s->handler[line] = handler;
}

static void tc6393xb_gpio_handler_update(TC6393xbState *s)
{
    uint32_t level, diff;
    int bit;

    level = s->gpio_level & s->gpio_dir;

    for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
        bit = ffs(diff) - 1;
        qemu_set_irq(s->handler[bit], (level >> bit) & 1);
    }

    s->prev_level = level;
}

qemu_irq tc6393xb_l3v_get(TC6393xbState *s)
{
    return s->l3v;
}

static void tc6393xb_l3v(void *opaque, int line, int level)
{
    TC6393xbState *s = opaque;
    s->blank = !level;
    fprintf(stderr, "L3V: %d\n", level);
}

static void tc6393xb_sub_irq(void *opaque, int line, int level) {
    TC6393xbState *s = opaque;
    uint8_t isr = s->scr.ISR;
    if (level)
        isr |= 1 << line;
    else
        isr &= ~(1 << line);
    s->scr.ISR = isr;
    qemu_set_irq(s->irq, isr & s->scr.IMR);
}

#define SCR_REG_B(N)                            \
    case SCR_ ##N: return s->scr.N
#define SCR_REG_W(N)                            \
    case SCR_ ##N: return s->scr.N;             \
    case SCR_ ##N + 1: return s->scr.N >> 8;
#define SCR_REG_L(N)                            \
    case SCR_ ##N: return s->scr.N;             \
    case SCR_ ##N + 1: return s->scr.N >> 8;    \
    case SCR_ ##N + 2: return s->scr.N >> 16;   \
    case SCR_ ##N + 3: return s->scr.N >> 24;
#define SCR_REG_A(N)                            \
    case SCR_ ##N(0): return s->scr.N[0];       \
    case SCR_ ##N(1): return s->scr.N[1];       \
    case SCR_ ##N(2): return s->scr.N[2]

static uint32_t tc6393xb_scr_readb(TC6393xbState *s, hwaddr addr)
{
    switch (addr) {
        case SCR_REVID:
            return 3;
        case SCR_REVID+1:
            return 0;
        SCR_REG_B(ISR);
        SCR_REG_B(IMR);
        SCR_REG_B(IRR);
        SCR_REG_W(GPER);
        SCR_REG_A(GPI_SR);
        SCR_REG_A(GPI_IMR);
        SCR_REG_A(GPI_EDER);
        SCR_REG_A(GPI_LIR);
        case SCR_GPO_DSR(0):
        case SCR_GPO_DSR(1):
        case SCR_GPO_DSR(2):
            return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff;
        case SCR_GPO_DOECR(0):
        case SCR_GPO_DOECR(1):
        case SCR_GPO_DOECR(2):
            return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff;
        SCR_REG_A(GP_IARCR);
        SCR_REG_A(GP_IARLCR);
        SCR_REG_A(GPI_BCR);
        SCR_REG_W(GPA_IARCR);
        SCR_REG_W(GPA_IARLCR);
        SCR_REG_W(CCR);
        SCR_REG_W(PLL2CR);
        SCR_REG_L(PLL1CR);
        SCR_REG_B(DIARCR);
        SCR_REG_B(DBOCR);
        SCR_REG_B(FER);
        SCR_REG_W(MCR);
        SCR_REG_B(CONFIG);
        SCR_REG_B(DEBUG);
    }
    fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr);
    return 0;
}
#undef SCR_REG_B
#undef SCR_REG_W
#undef SCR_REG_L
#undef SCR_REG_A

#define SCR_REG_B(N)                                \
    case SCR_ ##N: s->scr.N = value; return;
#define SCR_REG_W(N)                                \
    case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \
    case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); return
#define SCR_REG_L(N)                                \
    case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return;   \
    case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); return;     \
    case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); return;   \
    case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); return;
#define SCR_REG_A(N)                                \
    case SCR_ ##N(0): s->scr.N[0] = value; return;   \
    case SCR_ ##N(1): s->scr.N[1] = value; return;   \
    case SCR_ ##N(2): s->scr.N[2] = value; return

static void tc6393xb_scr_writeb(TC6393xbState *s, hwaddr addr, uint32_t value)
{
    switch (addr) {
        SCR_REG_B(ISR);
        SCR_REG_B(IMR);
        SCR_REG_B(IRR);
        SCR_REG_W(GPER);
        SCR_REG_A(GPI_SR);
        SCR_REG_A(GPI_IMR);
        SCR_REG_A(GPI_EDER);
        SCR_REG_A(GPI_LIR);
        case SCR_GPO_DSR(0):
        case SCR_GPO_DSR(1):
        case SCR_GPO_DSR(2):
            s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8));
            tc6393xb_gpio_handler_update(s);
            return;
        case SCR_GPO_DOECR(0):
        case SCR_GPO_DOECR(1):
        case SCR_GPO_DOECR(2):
            s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8));
            tc6393xb_gpio_handler_update(s);
            return;
        SCR_REG_A(GP_IARCR);
        SCR_REG_A(GP_IARLCR);
        SCR_REG_A(GPI_BCR);
        SCR_REG_W(GPA_IARCR);
        SCR_REG_W(GPA_IARLCR);
        SCR_REG_W(CCR);
        SCR_REG_W(PLL2CR);
        SCR_REG_L(PLL1CR);
        SCR_REG_B(DIARCR);
        SCR_REG_B(DBOCR);
        SCR_REG_B(FER);
        SCR_REG_W(MCR);
        SCR_REG_B(CONFIG);
        SCR_REG_B(DEBUG);
    }
    fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n",
					(uint32_t) addr, value & 0xff);
}
#undef SCR_REG_B
#undef SCR_REG_W
#undef SCR_REG_L
#undef SCR_REG_A

static void tc6393xb_nand_irq(TC6393xbState *s) {
    qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND],
            (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
}

static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, hwaddr addr) {
    switch (addr) {
        case NAND_CFG_COMMAND:
            return s->nand_enable ? 2 : 0;
        case NAND_CFG_BASE:
        case NAND_CFG_BASE + 1:
        case NAND_CFG_BASE + 2:
        case NAND_CFG_BASE + 3:
            return s->nand_phys >> (addr - NAND_CFG_BASE);
    }
    fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
    return 0;
}
static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
    switch (addr) {
        case NAND_CFG_COMMAND:
            s->nand_enable = (value & 0x2);
            return;
        case NAND_CFG_BASE:
        case NAND_CFG_BASE + 1:
        case NAND_CFG_BASE + 2:
        case NAND_CFG_BASE + 3:
            s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8));
            s->nand_phys |= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8);
            return;
    }
    fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n",
					(uint32_t) addr, value & 0xff);
}

static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) {
    switch (addr) {
        case NAND_DATA + 0:
        case NAND_DATA + 1:
        case NAND_DATA + 2:
        case NAND_DATA + 3:
            return nand_getio(s->flash);
        case NAND_MODE:
            return s->nand.mode;
        case NAND_STATUS:
            return 0x14;
        case NAND_ISR:
            return s->nand.isr;
        case NAND_IMR:
            return s->nand.imr;
    }
    fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
    return 0;
}
static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
//    fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
//					(uint32_t) addr, value & 0xff);
    switch (addr) {
        case NAND_DATA + 0:
        case NAND_DATA + 1:
        case NAND_DATA + 2:
        case NAND_DATA + 3:
            nand_setio(s->flash, value);
            s->nand.isr |= 1;
            tc6393xb_nand_irq(s);
            return;
        case NAND_MODE:
            s->nand.mode = value;
            nand_setpins(s->flash,
                    value & NAND_MODE_CLE,
                    value & NAND_MODE_ALE,
                    !(value & NAND_MODE_CE),
                    value & NAND_MODE_WP,
                    0); // FIXME: gnd
            switch (value & NAND_MODE_ECC_MASK) {
                case NAND_MODE_ECC_RST:
                    ecc_reset(&s->ecc);
                    break;
                case NAND_MODE_ECC_READ:
                    // FIXME
                    break;
                case NAND_MODE_ECC_EN:
                    ecc_reset(&s->ecc);
            }
            return;
        case NAND_ISR:
            s->nand.isr = value;
            tc6393xb_nand_irq(s);
            return;
        case NAND_IMR:
            s->nand.imr = value;
            tc6393xb_nand_irq(s);
            return;
    }
    fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n",
					(uint32_t) addr, value & 0xff);
}

#define BITS 8
#include "tc6393xb_template.h"
#define BITS 15
#include "tc6393xb_template.h"
#define BITS 16
#include "tc6393xb_template.h"
#define BITS 24
#include "tc6393xb_template.h"
#define BITS 32
#include "tc6393xb_template.h"

static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update)
{
    DisplaySurface *surface = qemu_console_surface(s->con);

    switch (surface_bits_per_pixel(surface)) {
        case 8:
            tc6393xb_draw_graphic8(s);
            break;
        case 15:
            tc6393xb_draw_graphic15(s);
            break;
        case 16:
            tc6393xb_draw_graphic16(s);
            break;
        case 24:
            tc6393xb_draw_graphic24(s);
            break;
        case 32:
            tc6393xb_draw_graphic32(s);
            break;
        default:
            printf("tc6393xb: unknown depth %d\n",
                   surface_bits_per_pixel(surface));
            return;
    }

    dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height);
}

static void tc6393xb_draw_blank(TC6393xbState *s, int full_update)
{
    DisplaySurface *surface = qemu_console_surface(s->con);
    int i, w;
    uint8_t *d;

    if (!full_update)
        return;

    w = s->scr_width * surface_bytes_per_pixel(surface);
    d = surface_data(surface);
    for(i = 0; i < s->scr_height; i++) {
        memset(d, 0, w);
        d += surface_stride(surface);
    }

    dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height);
}

static void tc6393xb_update_display(void *opaque)
{
    TC6393xbState *s = opaque;
    DisplaySurface *surface = qemu_console_surface(s->con);
    int full_update;

    if (s->scr_width == 0 || s->scr_height == 0)
        return;

    full_update = 0;
    if (s->blanked != s->blank) {
        s->blanked = s->blank;
        full_update = 1;
    }
    if (s->scr_width != surface_width(surface) ||
        s->scr_height != surface_height(surface)) {
        qemu_console_resize(s->con, s->scr_width, s->scr_height);
        full_update = 1;
    }
    if (s->blanked)
        tc6393xb_draw_blank(s, full_update);
    else
        tc6393xb_draw_graphic(s, full_update);
}


static uint64_t tc6393xb_readb(void *opaque, hwaddr addr,
                               unsigned size)
{
    TC6393xbState *s = opaque;

    switch (addr >> 8) {
        case 0:
            return tc6393xb_scr_readb(s, addr & 0xff);
        case 1:
            return tc6393xb_nand_cfg_readb(s, addr & 0xff);
    };

    if ((addr &~0xff) == s->nand_phys && s->nand_enable) {
//        return tc6393xb_nand_readb(s, addr & 0xff);
        uint8_t d = tc6393xb_nand_readb(s, addr & 0xff);
//        fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d);
        return d;
    }

//    fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr);
    return 0;
}

static void tc6393xb_writeb(void *opaque, hwaddr addr,
                            uint64_t value, unsigned size) {
    TC6393xbState *s = opaque;

    switch (addr >> 8) {
        case 0:
            tc6393xb_scr_writeb(s, addr & 0xff, value);
            return;
        case 1:
            tc6393xb_nand_cfg_writeb(s, addr & 0xff, value);
            return;
    };

    if ((addr &~0xff) == s->nand_phys && s->nand_enable)
        tc6393xb_nand_writeb(s, addr & 0xff, value);
    else
        fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n",
                (uint32_t) addr, (int)value & 0xff);
}

TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq)
{
    TC6393xbState *s;
    DriveInfo *nand;
    static const MemoryRegionOps tc6393xb_ops = {
        .read = tc6393xb_readb,
        .write = tc6393xb_writeb,
        .endianness = DEVICE_NATIVE_ENDIAN,
        .impl = {
            .min_access_size = 1,
            .max_access_size = 1,
        },
    };

    s = (TC6393xbState *) g_malloc0(sizeof(TC6393xbState));
    s->irq = irq;
    s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);

    s->l3v = *qemu_allocate_irqs(tc6393xb_l3v, s, 1);
    s->blanked = 1;

    s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS);

    nand = drive_get(IF_MTD, 0, 0);
    s->flash = nand_init(nand ? nand->bdrv : NULL, NAND_MFR_TOSHIBA, 0x76);

    memory_region_init_io(&s->iomem, &tc6393xb_ops, s, "tc6393xb", 0x10000);
    memory_region_add_subregion(sysmem, base, &s->iomem);

    memory_region_init_ram(&s->vram, "tc6393xb.vram", 0x100000);
    vmstate_register_ram_global(&s->vram);
    s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
    memory_region_add_subregion(sysmem, base + 0x100000, &s->vram);
    s->scr_width = 480;
    s->scr_height = 640;
    s->con = graphic_console_init(tc6393xb_update_display,
            NULL, /* invalidate */
            NULL, /* screen_dump */
            NULL, /* text_update */
            s);

    return s;
}
Commit	Line	Data
7880febd PB	1	/*
	2	* Toshiba TC6393XB I/O Controller.
	3	* Found in Sharp Zaurus SL-6000 (tosa) or some
	4	* Toshiba e-Series PDAs.
	5	*
	6	* Most features are currently unsupported!!!
	7	*
	8	* This code is licensed under the GNU GPL v2.
6b620ca3 PB	9	*
	10	* Contributions after 2012-01-13 are licensed under the terms of the
	11	* GNU GPL, version 2 or (at your option) any later version.
7880febd	12	*/
83c9f4ca	13	#include "hw/hw.h"
bd2be150	14	#include "hw/devices.h"
0d09e41a	15	#include "hw/block/flash.h"
28ecbaee PB	16	#include "ui/console.h"
28ecbaee PB	17	#include "ui/pixel_ops.h"
9c17d615	18	#include "sysemu/blockdev.h"
a6569fc5 AZ	19
	20	#define IRQ_TC6393_NAND 0
	21	#define IRQ_TC6393_MMC 1
	22	#define IRQ_TC6393_OHCI 2
	23	#define IRQ_TC6393_SERIAL 3
	24	#define IRQ_TC6393_FB 4
	25
	26	#define TC6393XB_NR_IRQS 8
88d2c950 AZ	27
	28	#define TC6393XB_GPIOS 16
	29
	30	#define SCR_REVID 0x08 /* b Revision ID */
	31	#define SCR_ISR 0x50 /* b Interrupt Status */
	32	#define SCR_IMR 0x52 /* b Interrupt Mask */
	33	#define SCR_IRR 0x54 /* b Interrupt Routing */
	34	#define SCR_GPER 0x60 /* w GP Enable */
	35	#define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
	36	#define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
	37	#define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
	38	#define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
	39	#define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
	40	#define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
	41	#define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
	42	#define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
	43	#define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
	44	#define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
	45	#define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
	46	#define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
	47	#define SCR_CCR 0x98 /* w Clock Control */
	48	#define SCR_PLL2CR 0x9a /* w PLL2 Control */
	49	#define SCR_PLL1CR 0x9c /* l PLL1 Control */
	50	#define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
	51	#define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
	52	#define SCR_FER 0xe0 /* b Function Enable */
	53	#define SCR_MCR 0xe4 /* w Mode Control */
	54	#define SCR_CONFIG 0xfc /* b Configuration Control */
	55	#define SCR_DEBUG 0xff /* b Debug */
	56
a6569fc5 AZ	57	#define NAND_CFG_COMMAND 0x04 /* w Command */
	58	#define NAND_CFG_BASE 0x10 /* l Control Base Address */
	59	#define NAND_CFG_INTP 0x3d /* b Interrupt Pin */
	60	#define NAND_CFG_INTE 0x48 /* b Int Enable */
	61	#define NAND_CFG_EC 0x4a /* b Event Control */
	62	#define NAND_CFG_ICC 0x4c /* b Internal Clock Control */
	63	#define NAND_CFG_ECCC 0x5b /* b ECC Control */
	64	#define NAND_CFG_NFTC 0x60 /* b NAND Flash Transaction Control */
	65	#define NAND_CFG_NFM 0x61 /* b NAND Flash Monitor */
	66	#define NAND_CFG_NFPSC 0x62 /* b NAND Flash Power Supply Control */
	67	#define NAND_CFG_NFDC 0x63 /* b NAND Flash Detect Control */
	68
	69	#define NAND_DATA 0x00 /* l Data */
	70	#define NAND_MODE 0x04 /* b Mode */
	71	#define NAND_STATUS 0x05 /* b Status */
	72	#define NAND_ISR 0x06 /* b Interrupt Status */
	73	#define NAND_IMR 0x07 /* b Interrupt Mask */
	74
	75	#define NAND_MODE_WP 0x80
	76	#define NAND_MODE_CE 0x10
	77	#define NAND_MODE_ALE 0x02
	78	#define NAND_MODE_CLE 0x01
	79	#define NAND_MODE_ECC_MASK 0x60
	80	#define NAND_MODE_ECC_EN 0x20
	81	#define NAND_MODE_ECC_READ 0x40
	82	#define NAND_MODE_ECC_RST 0x60
	83
bc24a225	84	struct TC6393xbState {
fe06bd93	85	MemoryRegion iomem;
a6569fc5 AZ	86	qemu_irq irq;
a6569fc5 AZ	87	qemu_irq *sub_irqs;
88d2c950 AZ	88	struct {
	89	uint8_t ISR;
	90	uint8_t IMR;
	91	uint8_t IRR;
	92	uint16_t GPER;
	93	uint8_t GPI_SR[3];
	94	uint8_t GPI_IMR[3];
	95	uint8_t GPI_EDER[3];
	96	uint8_t GPI_LIR[3];
	97	uint8_t GP_IARCR[3];
	98	uint8_t GP_IARLCR[3];
	99	uint8_t GPI_BCR[3];
	100	uint16_t GPA_IARCR;
	101	uint16_t GPA_IARLCR;
	102	uint16_t CCR;
	103	uint16_t PLL2CR;
	104	uint32_t PLL1CR;
	105	uint8_t DIARCR;
	106	uint8_t DBOCR;
	107	uint8_t FER;
	108	uint16_t MCR;
	109	uint8_t CONFIG;
	110	uint8_t DEBUG;
	111	} scr;
	112	uint32_t gpio_dir;
	113	uint32_t gpio_level;
	114	uint32_t prev_level;
	115	qemu_irq handler[TC6393XB_GPIOS];
	116	qemu_irq *gpio_in;
a6569fc5 AZ	117
	118	struct {
	119	uint8_t mode;
	120	uint8_t isr;
	121	uint8_t imr;
	122	} nand;
	123	int nand_enable;
	124	uint32_t nand_phys;
d4220389	125	DeviceState *flash;
bc24a225	126	ECCState ecc;
64b40bc5	127
c78f7137	128	QemuConsole *con;
fe06bd93	129	MemoryRegion vram;
44654490	130	uint16_t *vram_ptr;
64b40bc5 AZ	131	uint32_t scr_width, scr_height; /* in pixels */
	132	qemu_irq l3v;
	133	unsigned blank : 1,
	134	blanked : 1;
88d2c950 AZ	135	};
88d2c950 AZ	136
bc24a225	137	qemu_irq tc6393xb_gpio_in_get(TC6393xbState s)
88d2c950 AZ	138	{
	139	return s->gpio_in;
	140	}
	141
	142	static void tc6393xb_gpio_set(void *opaque, int line, int level)
	143	{
bc24a225	144	// TC6393xbState *s = opaque;
88d2c950 AZ	145
	146	if (line > TC6393XB_GPIOS) {
	147	printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
	148	return;
	149	}
	150
	151	// FIXME: how does the chip reflect the GPIO input level change?
	152	}
	153
bc24a225	154	void tc6393xb_gpio_out_set(TC6393xbState *s, int line,
88d2c950 AZ	155	qemu_irq handler)
	156	{
	157	if (line >= TC6393XB_GPIOS) {
	158	fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line);
	159	return;
	160	}
	161
	162	s->handler[line] = handler;
	163	}
	164
bc24a225	165	static void tc6393xb_gpio_handler_update(TC6393xbState *s)
88d2c950 AZ	166	{
	167	uint32_t level, diff;
	168	int bit;
	169
	170	level = s->gpio_level & s->gpio_dir;
	171
	172	for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
	173	bit = ffs(diff) - 1;
	174	qemu_set_irq(s->handler[bit], (level >> bit) & 1);
	175	}
	176
	177	s->prev_level = level;
	178	}
	179
bc24a225	180	qemu_irq tc6393xb_l3v_get(TC6393xbState *s)
64b40bc5 AZ	181	{
	182	return s->l3v;
	183	}
	184
	185	static void tc6393xb_l3v(void *opaque, int line, int level)
	186	{
bc24a225	187	TC6393xbState *s = opaque;
64b40bc5 AZ	188	s->blank = !level;
	189	fprintf(stderr, "L3V: %d\n", level);
	190	}
	191
a6569fc5	192	static void tc6393xb_sub_irq(void *opaque, int line, int level) {
bc24a225	193	TC6393xbState *s = opaque;
a6569fc5 AZ	194	uint8_t isr = s->scr.ISR;
	195	if (level)
	196	isr \|= 1 << line;
	197	else
	198	isr &= ~(1 << line);
	199	s->scr.ISR = isr;
	200	qemu_set_irq(s->irq, isr & s->scr.IMR);
	201	}
	202
88d2c950 AZ	203	#define SCR_REG_B(N) \
	204	case SCR_ ##N: return s->scr.N
	205	#define SCR_REG_W(N) \
	206	case SCR_ ##N: return s->scr.N; \
	207	case SCR_ ##N + 1: return s->scr.N >> 8;
	208	#define SCR_REG_L(N) \
	209	case SCR_ ##N: return s->scr.N; \
	210	case SCR_ ##N + 1: return s->scr.N >> 8; \
	211	case SCR_ ##N + 2: return s->scr.N >> 16; \
	212	case SCR_ ##N + 3: return s->scr.N >> 24;
	213	#define SCR_REG_A(N) \
	214	case SCR_ ##N(0): return s->scr.N[0]; \
	215	case SCR_ ##N(1): return s->scr.N[1]; \
	216	case SCR_ ##N(2): return s->scr.N[2]
	217
a8170e5e	218	static uint32_t tc6393xb_scr_readb(TC6393xbState *s, hwaddr addr)
88d2c950	219	{
88d2c950 AZ	220	switch (addr) {
	221	case SCR_REVID:
	222	return 3;
	223	case SCR_REVID+1:
	224	return 0;
	225	SCR_REG_B(ISR);
	226	SCR_REG_B(IMR);
	227	SCR_REG_B(IRR);
	228	SCR_REG_W(GPER);
	229	SCR_REG_A(GPI_SR);
	230	SCR_REG_A(GPI_IMR);
	231	SCR_REG_A(GPI_EDER);
	232	SCR_REG_A(GPI_LIR);
	233	case SCR_GPO_DSR(0):
	234	case SCR_GPO_DSR(1):
	235	case SCR_GPO_DSR(2):
	236	return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff;
	237	case SCR_GPO_DOECR(0):
	238	case SCR_GPO_DOECR(1):
	239	case SCR_GPO_DOECR(2):
	240	return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff;
	241	SCR_REG_A(GP_IARCR);
	242	SCR_REG_A(GP_IARLCR);
	243	SCR_REG_A(GPI_BCR);
	244	SCR_REG_W(GPA_IARCR);
	245	SCR_REG_W(GPA_IARLCR);
	246	SCR_REG_W(CCR);
	247	SCR_REG_W(PLL2CR);
	248	SCR_REG_L(PLL1CR);
	249	SCR_REG_B(DIARCR);
	250	SCR_REG_B(DBOCR);
	251	SCR_REG_B(FER);
	252	SCR_REG_W(MCR);
	253	SCR_REG_B(CONFIG);
	254	SCR_REG_B(DEBUG);
	255	}
a6569fc5	256	fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr);
88d2c950 AZ	257	return 0;
	258	}
	259	#undef SCR_REG_B
	260	#undef SCR_REG_W
	261	#undef SCR_REG_L
	262	#undef SCR_REG_A
	263
	264	#define SCR_REG_B(N) \
a6569fc5	265	case SCR_ ##N: s->scr.N = value; return;
88d2c950	266	#define SCR_REG_W(N) \
a6569fc5 AZ	267	case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) \| (value & 0xff); return; \
a6569fc5 AZ	268	case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) \| (value << 8); return
88d2c950	269	#define SCR_REG_L(N) \
a6569fc5 AZ	270	case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) \| (value & 0xff); return; \
	271	case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) \| (value & (0xff << 8)); return; \
	272	case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) \| (value & (0xff << 16)); return; \
	273	case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) \| (value & (0xff << 24)); return;
88d2c950	274	#define SCR_REG_A(N) \
a6569fc5 AZ	275	case SCR_ ##N(0): s->scr.N[0] = value; return; \
	276	case SCR_ ##N(1): s->scr.N[1] = value; return; \
	277	case SCR_ ##N(2): s->scr.N[2] = value; return
88d2c950	278
a8170e5e	279	static void tc6393xb_scr_writeb(TC6393xbState *s, hwaddr addr, uint32_t value)
88d2c950	280	{
88d2c950 AZ	281	switch (addr) {
	282	SCR_REG_B(ISR);
	283	SCR_REG_B(IMR);
	284	SCR_REG_B(IRR);
	285	SCR_REG_W(GPER);
	286	SCR_REG_A(GPI_SR);
	287	SCR_REG_A(GPI_IMR);
	288	SCR_REG_A(GPI_EDER);
	289	SCR_REG_A(GPI_LIR);
	290	case SCR_GPO_DSR(0):
	291	case SCR_GPO_DSR(1):
	292	case SCR_GPO_DSR(2):
	293	s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))8))) \| ((value & 0xff) << ((addr - SCR_GPO_DSR(0))8));
	294	tc6393xb_gpio_handler_update(s);
a6569fc5	295	return;
88d2c950 AZ	296	case SCR_GPO_DOECR(0):
	297	case SCR_GPO_DOECR(1):
	298	case SCR_GPO_DOECR(2):
	299	s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))8))) \| ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))8));
	300	tc6393xb_gpio_handler_update(s);
a6569fc5	301	return;
88d2c950 AZ	302	SCR_REG_A(GP_IARCR);
	303	SCR_REG_A(GP_IARLCR);
	304	SCR_REG_A(GPI_BCR);
	305	SCR_REG_W(GPA_IARCR);
	306	SCR_REG_W(GPA_IARLCR);
	307	SCR_REG_W(CCR);
	308	SCR_REG_W(PLL2CR);
	309	SCR_REG_L(PLL1CR);
	310	SCR_REG_B(DIARCR);
	311	SCR_REG_B(DBOCR);
	312	SCR_REG_B(FER);
	313	SCR_REG_W(MCR);
	314	SCR_REG_B(CONFIG);
	315	SCR_REG_B(DEBUG);
88d2c950	316	}
a6569fc5 AZ	317	fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n",
a6569fc5 AZ	318	(uint32_t) addr, value & 0xff);
88d2c950 AZ	319	}
	320	#undef SCR_REG_B
	321	#undef SCR_REG_W
	322	#undef SCR_REG_L
	323	#undef SCR_REG_A
	324
bc24a225	325	static void tc6393xb_nand_irq(TC6393xbState *s) {
a6569fc5 AZ	326	qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND],
	327	(s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
	328	}
	329
a8170e5e	330	static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, hwaddr addr) {
a6569fc5 AZ	331	switch (addr) {
	332	case NAND_CFG_COMMAND:
	333	return s->nand_enable ? 2 : 0;
	334	case NAND_CFG_BASE:
	335	case NAND_CFG_BASE + 1:
	336	case NAND_CFG_BASE + 2:
	337	case NAND_CFG_BASE + 3:
	338	return s->nand_phys >> (addr - NAND_CFG_BASE);
	339	}
	340	fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
	341	return 0;
	342	}
a8170e5e	343	static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
a6569fc5 AZ	344	switch (addr) {
	345	case NAND_CFG_COMMAND:
	346	s->nand_enable = (value & 0x2);
	347	return;
	348	case NAND_CFG_BASE:
	349	case NAND_CFG_BASE + 1:
	350	case NAND_CFG_BASE + 2:
	351	case NAND_CFG_BASE + 3:
	352	s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8));
	353	s->nand_phys \|= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8);
	354	return;
	355	}
	356	fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n",
	357	(uint32_t) addr, value & 0xff);
	358	}
	359
a8170e5e	360	static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) {
a6569fc5 AZ	361	switch (addr) {
	362	case NAND_DATA + 0:
	363	case NAND_DATA + 1:
	364	case NAND_DATA + 2:
	365	case NAND_DATA + 3:
	366	return nand_getio(s->flash);
	367	case NAND_MODE:
	368	return s->nand.mode;
	369	case NAND_STATUS:
	370	return 0x14;
	371	case NAND_ISR:
	372	return s->nand.isr;
	373	case NAND_IMR:
	374	return s->nand.imr;
	375	}
	376	fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
	377	return 0;
	378	}
a8170e5e	379	static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
a6569fc5 AZ	380	// fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
	381	// (uint32_t) addr, value & 0xff);
	382	switch (addr) {
	383	case NAND_DATA + 0:
	384	case NAND_DATA + 1:
	385	case NAND_DATA + 2:
	386	case NAND_DATA + 3:
	387	nand_setio(s->flash, value);
f23c1b2a	388	s->nand.isr \|= 1;
a6569fc5 AZ	389	tc6393xb_nand_irq(s);
	390	return;
	391	case NAND_MODE:
	392	s->nand.mode = value;
	393	nand_setpins(s->flash,
	394	value & NAND_MODE_CLE,
	395	value & NAND_MODE_ALE,
	396	!(value & NAND_MODE_CE),
	397	value & NAND_MODE_WP,
	398	0); // FIXME: gnd
	399	switch (value & NAND_MODE_ECC_MASK) {
	400	case NAND_MODE_ECC_RST:
	401	ecc_reset(&s->ecc);
	402	break;
	403	case NAND_MODE_ECC_READ:
	404	// FIXME
	405	break;
	406	case NAND_MODE_ECC_EN:
	407	ecc_reset(&s->ecc);
	408	}
	409	return;
	410	case NAND_ISR:
	411	s->nand.isr = value;
	412	tc6393xb_nand_irq(s);
	413	return;
	414	case NAND_IMR:
	415	s->nand.imr = value;
	416	tc6393xb_nand_irq(s);
	417	return;
	418	}
	419	fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n",
	420	(uint32_t) addr, value & 0xff);
	421	}
	422
64b40bc5	423	#define BITS 8
47b43a1f	424	#include "tc6393xb_template.h"
64b40bc5	425	#define BITS 15
47b43a1f	426	#include "tc6393xb_template.h"
64b40bc5	427	#define BITS 16
47b43a1f	428	#include "tc6393xb_template.h"
64b40bc5	429	#define BITS 24
47b43a1f	430	#include "tc6393xb_template.h"
64b40bc5	431	#define BITS 32
47b43a1f	432	#include "tc6393xb_template.h"
64b40bc5	433
bc24a225	434	static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update)
64b40bc5	435	{
c78f7137 GH	436	DisplaySurface *surface = qemu_console_surface(s->con);
	437
	438	switch (surface_bits_per_pixel(surface)) {
64b40bc5 AZ	439	case 8:
	440	tc6393xb_draw_graphic8(s);
	441	break;
	442	case 15:
	443	tc6393xb_draw_graphic15(s);
	444	break;
	445	case 16:
	446	tc6393xb_draw_graphic16(s);
	447	break;
	448	case 24:
	449	tc6393xb_draw_graphic24(s);
	450	break;
	451	case 32:
	452	tc6393xb_draw_graphic32(s);
	453	break;
	454	default:
c78f7137 GH	455	printf("tc6393xb: unknown depth %d\n",
c78f7137 GH	456	surface_bits_per_pixel(surface));
64b40bc5 AZ	457	return;
	458	}
	459
c78f7137	460	dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height);
64b40bc5 AZ	461	}
64b40bc5 AZ	462
bc24a225	463	static void tc6393xb_draw_blank(TC6393xbState *s, int full_update)
64b40bc5	464	{
c78f7137	465	DisplaySurface *surface = qemu_console_surface(s->con);
64b40bc5 AZ	466	int i, w;
	467	uint8_t *d;
	468
	469	if (!full_update)
	470	return;
	471
c78f7137 GH	472	w = s->scr_width * surface_bytes_per_pixel(surface);
c78f7137 GH	473	d = surface_data(surface);
64b40bc5 AZ	474	for(i = 0; i < s->scr_height; i++) {
64b40bc5 AZ	475	memset(d, 0, w);
c78f7137	476	d += surface_stride(surface);
64b40bc5 AZ	477	}
64b40bc5 AZ	478
c78f7137	479	dpy_gfx_update(s->con, 0, 0, s->scr_width, s->scr_height);
64b40bc5 AZ	480	}
	481
	482	static void tc6393xb_update_display(void *opaque)
	483	{
bc24a225	484	TC6393xbState *s = opaque;
c78f7137	485	DisplaySurface *surface = qemu_console_surface(s->con);
64b40bc5 AZ	486	int full_update;
	487
	488	if (s->scr_width == 0 \|\| s->scr_height == 0)
	489	return;
	490
	491	full_update = 0;
	492	if (s->blanked != s->blank) {
	493	s->blanked = s->blank;
	494	full_update = 1;
	495	}
c78f7137 GH	496	if (s->scr_width != surface_width(surface) \|\|
	497	s->scr_height != surface_height(surface)) {
	498	qemu_console_resize(s->con, s->scr_width, s->scr_height);
64b40bc5 AZ	499	full_update = 1;
	500	}
	501	if (s->blanked)
	502	tc6393xb_draw_blank(s, full_update);
	503	else
	504	tc6393xb_draw_graphic(s, full_update);
	505	}
	506
	507
a8170e5e	508	static uint64_t tc6393xb_readb(void *opaque, hwaddr addr,
fe06bd93 AK	509	unsigned size)
fe06bd93 AK	510	{
bc24a225	511	TC6393xbState *s = opaque;
a6569fc5 AZ	512
	513	switch (addr >> 8) {
	514	case 0:
	515	return tc6393xb_scr_readb(s, addr & 0xff);
	516	case 1:
	517	return tc6393xb_nand_cfg_readb(s, addr & 0xff);
	518	};
	519
	520	if ((addr &~0xff) == s->nand_phys && s->nand_enable) {
	521	// return tc6393xb_nand_readb(s, addr & 0xff);
	522	uint8_t d = tc6393xb_nand_readb(s, addr & 0xff);
	523	// fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d);
	524	return d;
	525	}
	526
	527	// fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr);
	528	return 0;
	529	}
	530
a8170e5e	531	static void tc6393xb_writeb(void *opaque, hwaddr addr,
fe06bd93	532	uint64_t value, unsigned size) {
bc24a225	533	TC6393xbState *s = opaque;
a6569fc5 AZ	534
	535	switch (addr >> 8) {
	536	case 0:
	537	tc6393xb_scr_writeb(s, addr & 0xff, value);
	538	return;
	539	case 1:
	540	tc6393xb_nand_cfg_writeb(s, addr & 0xff, value);
	541	return;
	542	};
	543
	544	if ((addr &~0xff) == s->nand_phys && s->nand_enable)
	545	tc6393xb_nand_writeb(s, addr & 0xff, value);
	546	else
	547	fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n",
fe06bd93	548	(uint32_t) addr, (int)value & 0xff);
88d2c950 AZ	549	}
88d2c950 AZ	550
fe06bd93	551	TC6393xbState tc6393xb_init(MemoryRegion sysmem, uint32_t base, qemu_irq irq)
88d2c950	552	{
bc24a225	553	TC6393xbState *s;
522f253c	554	DriveInfo *nand;
fe06bd93 AK	555	static const MemoryRegionOps tc6393xb_ops = {
	556	.read = tc6393xb_readb,
	557	.write = tc6393xb_writeb,
	558	.endianness = DEVICE_NATIVE_ENDIAN,
	559	.impl = {
	560	.min_access_size = 1,
	561	.max_access_size = 1,
	562	},
88d2c950 AZ	563	};
88d2c950 AZ	564
7267c094	565	s = (TC6393xbState *) g_malloc0(sizeof(TC6393xbState));
a6569fc5	566	s->irq = irq;
88d2c950 AZ	567	s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);
88d2c950 AZ	568
64b40bc5 AZ	569	s->l3v = *qemu_allocate_irqs(tc6393xb_l3v, s, 1);
	570	s->blanked = 1;
	571
a6569fc5 AZ	572	s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS);
a6569fc5 AZ	573
522f253c PM	574	nand = drive_get(IF_MTD, 0, 0);
522f253c PM	575	s->flash = nand_init(nand ? nand->bdrv : NULL, NAND_MFR_TOSHIBA, 0x76);
a6569fc5	576
fe06bd93 AK	577	memory_region_init_io(&s->iomem, &tc6393xb_ops, s, "tc6393xb", 0x10000);
fe06bd93 AK	578	memory_region_add_subregion(sysmem, base, &s->iomem);
64b40bc5	579
c5705a77 AK	580	memory_region_init_ram(&s->vram, "tc6393xb.vram", 0x100000);
c5705a77 AK	581	vmstate_register_ram_global(&s->vram);
fe06bd93 AK	582	s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
fe06bd93 AK	583	memory_region_add_subregion(sysmem, base + 0x100000, &s->vram);
3023f332 AL	584	s->scr_width = 480;
3023f332 AL	585	s->scr_height = 640;
c78f7137	586	s->con = graphic_console_init(tc6393xb_update_display,
3023f332 AL	587	NULL, /* invalidate */
	588	NULL, /* screen_dump */
	589	NULL, /* text_update */
	590	s);
88d2c950 AZ	591
	592	return s;
	593	}