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softmmu_header: pass CPUState to tlb_fill
[qemu.git] / target-ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
3fc6c082
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
3fc6c082
FB		 18 */
19
20/* A lot of PowerPC definition have been included here.
21 * Most of them are not usable for now but have been kept
22 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
23 */
24
237c0af0 25#include "dis-asm.h"
4e47ea67 26#include "gdbstub.h"
237c0af0 27
3fc6c082
FB		 28//#define PPC_DUMP_CPU
29//#define PPC_DEBUG_SPR
80d11f44
JM		 30//#define PPC_DUMP_SPR_ACCESSES
31#if defined(CONFIG_USER_ONLY)
32#define TODO_USER_ONLY 1
33#endif
3fc6c082 34
c227f099 35struct ppc_def_t {
b55266b5 36 const char *name;
3fc6c082 37 uint32_t pvr;
80d11f44 38 uint32_t svr;
0487d6a8 39 uint64_t insns_flags;
a5858d7a 40 uint64_t insns_flags2;
3fc6c082 41 uint64_t msr_mask;
c227f099
AL		 42 powerpc_mmu_t mmu_model;
43 powerpc_excp_t excp_model;
44 powerpc_input_t bus_model;
d26bfc9a 45 uint32_t flags;
237c0af0 46 int bfd_mach;
a750fc0b 47 void (*init_proc)(CPUPPCState *env);
4c1b1bfe 48 int (*check_pow)(CPUPPCState *env);
3fc6c082
FB		 49};
50
e9df014c
JM		 51/* For user-mode emulation, we don't emulate any IRQ controller */
52#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 53#define PPC_IRQ_INIT_FN(name) \
54static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
55{ \
e9df014c
JM		 56}
57#else
a750fc0b 58#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 59void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
60#endif
a750fc0b 61
4e290a0b 62PPC_IRQ_INIT_FN(40x);
e9df014c 63PPC_IRQ_INIT_FN(6xx);
d0dfae6e 64PPC_IRQ_INIT_FN(970);
9d52e907 65PPC_IRQ_INIT_FN(POWER7);
9fdc60bf 66PPC_IRQ_INIT_FN(e500);
e9df014c 67
3fc6c082
FB		 68/* Generic callbacks:
69 * do nothing but store/retrieve spr value
70 */
45d827d2 71static void spr_read_generic (void *opaque, int gprn, int sprn)
a496775f 72{
45d827d2
AJ		 73 gen_load_spr(cpu_gpr[gprn], sprn);
74#ifdef PPC_DUMP_SPR_ACCESSES
75 {
1ff7854e 76 TCGv_i32 t0 = tcg_const_i32(sprn);
45d827d2
AJ		 77 gen_helper_load_dump_spr(t0);
78 tcg_temp_free_i32(t0);
79 }
80#endif
a496775f
JM		 81}
82
45d827d2 83static void spr_write_generic (void *opaque, int sprn, int gprn)
a496775f 84{
45d827d2
AJ		 85 gen_store_spr(sprn, cpu_gpr[gprn]);
86#ifdef PPC_DUMP_SPR_ACCESSES
87 {
1ff7854e 88 TCGv_i32 t0 = tcg_const_i32(sprn);
45d827d2
AJ		 89 gen_helper_store_dump_spr(t0);
90 tcg_temp_free_i32(t0);
91 }
04f20795 92#endif
45d827d2 93}
a496775f
JM		 94
95#if !defined(CONFIG_USER_ONLY)
45d827d2 96static void spr_write_clear (void *opaque, int sprn, int gprn)
a496775f 97{
45d827d2
AJ		 98 TCGv t0 = tcg_temp_new();
99 TCGv t1 = tcg_temp_new();
100 gen_load_spr(t0, sprn);
101 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
102 tcg_gen_and_tl(t0, t0, t1);
103 gen_store_spr(sprn, t0);
104 tcg_temp_free(t0);
105 tcg_temp_free(t1);
a496775f
JM		 106}
107#endif
108
76a66253 109/* SPR common to all PowerPC */
3fc6c082 110/* XER */
45d827d2 111static void spr_read_xer (void *opaque, int gprn, int sprn)
3fc6c082 112{
45d827d2 113 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
3fc6c082
FB		 114}
115
45d827d2 116static void spr_write_xer (void *opaque, int sprn, int gprn)
3fc6c082 117{
45d827d2 118 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
3fc6c082
FB		 119}
120
121/* LR */
45d827d2 122static void spr_read_lr (void *opaque, int gprn, int sprn)
3fc6c082 123{
45d827d2 124 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
3fc6c082
FB		 125}
126
45d827d2 127static void spr_write_lr (void *opaque, int sprn, int gprn)
3fc6c082 128{
45d827d2 129 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
3fc6c082
FB		 130}
131
132/* CTR */
45d827d2 133static void spr_read_ctr (void *opaque, int gprn, int sprn)
3fc6c082 134{
45d827d2 135 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
3fc6c082
FB		 136}
137
45d827d2 138static void spr_write_ctr (void *opaque, int sprn, int gprn)
3fc6c082 139{
45d827d2 140 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
3fc6c082
FB		 141}
142
143/* User read access to SPR */
144/* USPRx */
145/* UMMCRx */
146/* UPMCx */
147/* USIA */
148/* UDECR */
45d827d2 149static void spr_read_ureg (void *opaque, int gprn, int sprn)
3fc6c082 150{
45d827d2 151 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
3fc6c082
FB		 152}
153
76a66253 154/* SPR common to all non-embedded PowerPC */
3fc6c082 155/* DECR */
76a66253 156#if !defined(CONFIG_USER_ONLY)
45d827d2 157static void spr_read_decr (void *opaque, int gprn, int sprn)
3fc6c082 158{
630ecca0
TG		 159 if (use_icount) {
160 gen_io_start();
161 }
45d827d2 162 gen_helper_load_decr(cpu_gpr[gprn]);
630ecca0
TG		 163 if (use_icount) {
164 gen_io_end();
165 gen_stop_exception(opaque);
166 }
3fc6c082
FB		 167}
168
45d827d2 169static void spr_write_decr (void *opaque, int sprn, int gprn)
3fc6c082 170{
630ecca0
TG		 171 if (use_icount) {
172 gen_io_start();
173 }
45d827d2 174 gen_helper_store_decr(cpu_gpr[gprn]);
630ecca0
TG		 175 if (use_icount) {
176 gen_io_end();
177 gen_stop_exception(opaque);
178 }
3fc6c082 179}
76a66253 180#endif
3fc6c082 181
76a66253 182/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082 183/* Time base */
45d827d2 184static void spr_read_tbl (void *opaque, int gprn, int sprn)
3fc6c082 185{
630ecca0
TG		 186 if (use_icount) {
187 gen_io_start();
188 }
45d827d2 189 gen_helper_load_tbl(cpu_gpr[gprn]);
630ecca0
TG		 190 if (use_icount) {
191 gen_io_end();
192 gen_stop_exception(opaque);
193 }
3fc6c082
FB		 194}
195
45d827d2 196static void spr_read_tbu (void *opaque, int gprn, int sprn)
3fc6c082 197{
630ecca0
TG		 198 if (use_icount) {
199 gen_io_start();
200 }
45d827d2 201 gen_helper_load_tbu(cpu_gpr[gprn]);
630ecca0
TG		 202 if (use_icount) {
203 gen_io_end();
204 gen_stop_exception(opaque);
205 }
3fc6c082
FB		 206}
207
a062e36c 208__attribute__ (( unused ))
45d827d2 209static void spr_read_atbl (void *opaque, int gprn, int sprn)
a062e36c 210{
45d827d2 211 gen_helper_load_atbl(cpu_gpr[gprn]);
a062e36c
JM		 212}
213
214__attribute__ (( unused ))
45d827d2 215static void spr_read_atbu (void *opaque, int gprn, int sprn)
a062e36c 216{
45d827d2 217 gen_helper_load_atbu(cpu_gpr[gprn]);
a062e36c
JM		 218}
219
76a66253 220#if !defined(CONFIG_USER_ONLY)
45d827d2 221static void spr_write_tbl (void *opaque, int sprn, int gprn)
3fc6c082 222{
630ecca0
TG		 223 if (use_icount) {
224 gen_io_start();
225 }
45d827d2 226 gen_helper_store_tbl(cpu_gpr[gprn]);
630ecca0
TG		 227 if (use_icount) {
228 gen_io_end();
229 gen_stop_exception(opaque);
230 }
3fc6c082
FB		 231}
232
45d827d2 233static void spr_write_tbu (void *opaque, int sprn, int gprn)
3fc6c082 234{
630ecca0
TG		 235 if (use_icount) {
236 gen_io_start();
237 }
45d827d2 238 gen_helper_store_tbu(cpu_gpr[gprn]);
630ecca0
TG		 239 if (use_icount) {
240 gen_io_end();
241 gen_stop_exception(opaque);
242 }
3fc6c082 243}
a062e36c
JM		 244
245__attribute__ (( unused ))
45d827d2 246static void spr_write_atbl (void *opaque, int sprn, int gprn)
a062e36c 247{
45d827d2 248 gen_helper_store_atbl(cpu_gpr[gprn]);
a062e36c
JM		 249}
250
251__attribute__ (( unused ))
45d827d2 252static void spr_write_atbu (void *opaque, int sprn, int gprn)
a062e36c 253{
45d827d2 254 gen_helper_store_atbu(cpu_gpr[gprn]);
a062e36c 255}
3a7f009a
DG		 256
257#if defined(TARGET_PPC64)
258__attribute__ (( unused ))
259static void spr_read_purr (void *opaque, int gprn, int sprn)
260{
261 gen_helper_load_purr(cpu_gpr[gprn]);
262}
263#endif
76a66253 264#endif
3fc6c082 265
76a66253 266#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 267/* IBAT0U...IBAT0U */
268/* IBAT0L...IBAT7L */
45d827d2 269static void spr_read_ibat (void *opaque, int gprn, int sprn)
3fc6c082 270{
45d827d2 271 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
3fc6c082
FB		 272}
273
45d827d2 274static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
3fc6c082 275{
45d827d2 276 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
3fc6c082
FB		 277}
278
45d827d2 279static void spr_write_ibatu (void *opaque, int sprn, int gprn)
3fc6c082 280{
45d827d2
AJ		 281 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
282 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
283 tcg_temp_free_i32(t0);
3fc6c082
FB		 284}
285
45d827d2 286static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
3fc6c082 287{
8daf1781 288 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
45d827d2
AJ		 289 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
290 tcg_temp_free_i32(t0);
3fc6c082
FB		 291}
292
45d827d2 293static void spr_write_ibatl (void *opaque, int sprn, int gprn)
3fc6c082 294{
45d827d2
AJ		 295 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
296 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
297 tcg_temp_free_i32(t0);
3fc6c082
FB		 298}
299
45d827d2 300static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
3fc6c082 301{
8daf1781 302 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
45d827d2
AJ		 303 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
304 tcg_temp_free_i32(t0);
3fc6c082
FB		 305}
306
307/* DBAT0U...DBAT7U */
308/* DBAT0L...DBAT7L */
45d827d2 309static void spr_read_dbat (void *opaque, int gprn, int sprn)
3fc6c082 310{
45d827d2 311 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
3fc6c082
FB		 312}
313
45d827d2 314static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
3fc6c082 315{
45d827d2 316 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
3fc6c082
FB		 317}
318
45d827d2 319static void spr_write_dbatu (void *opaque, int sprn, int gprn)
3fc6c082 320{
45d827d2
AJ		 321 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
322 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
323 tcg_temp_free_i32(t0);
3fc6c082
FB		 324}
325
45d827d2 326static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
3fc6c082 327{
45d827d2
AJ		 328 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
329 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
330 tcg_temp_free_i32(t0);
3fc6c082
FB		 331}
332
45d827d2 333static void spr_write_dbatl (void *opaque, int sprn, int gprn)
3fc6c082 334{
45d827d2
AJ		 335 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
336 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
337 tcg_temp_free_i32(t0);
3fc6c082
FB		 338}
339
45d827d2 340static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
3fc6c082 341{
45d827d2
AJ		 342 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
343 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
344 tcg_temp_free_i32(t0);
3fc6c082
FB		 345}
346
347/* SDR1 */
45d827d2 348static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
3fc6c082 349{
45d827d2 350 gen_helper_store_sdr1(cpu_gpr[gprn]);
3fc6c082
FB		 351}
352
76a66253
JM		 353/* 64 bits PowerPC specific SPRs */
354/* ASR */
578bb252 355#if defined(TARGET_PPC64)
2adab7d6
BS		 356static void spr_read_hior (void *opaque, int gprn, int sprn)
357{
358 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
359}
360
361static void spr_write_hior (void *opaque, int sprn, int gprn)
362{
363 TCGv t0 = tcg_temp_new();
364 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
365 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
366 tcg_temp_free(t0);
367}
368
45d827d2 369static void spr_read_asr (void *opaque, int gprn, int sprn)
76a66253 370{
45d827d2 371 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
76a66253
JM		 372}
373
45d827d2 374static void spr_write_asr (void *opaque, int sprn, int gprn)
76a66253 375{
45d827d2 376 gen_helper_store_asr(cpu_gpr[gprn]);
76a66253
JM		 377}
378#endif
a750fc0b 379#endif
76a66253
JM		 380
381/* PowerPC 601 specific registers */
382/* RTC */
45d827d2 383static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
76a66253 384{
45d827d2 385 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
76a66253
JM		 386}
387
45d827d2 388static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
76a66253 389{
45d827d2 390 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
76a66253
JM		 391}
392
393#if !defined(CONFIG_USER_ONLY)
45d827d2 394static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
76a66253 395{
45d827d2 396 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
76a66253
JM		 397}
398
45d827d2 399static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
76a66253 400{
45d827d2 401 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
76a66253 402}
056401ea 403
45d827d2 404static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
056401ea
JM		 405{
406 DisasContext *ctx = opaque;
407
45d827d2 408 gen_helper_store_hid0_601(cpu_gpr[gprn]);
056401ea 409 /* Must stop the translation as endianness may have changed */
e06fcd75 410 gen_stop_exception(ctx);
056401ea 411}
76a66253
JM		 412#endif
413
414/* Unified bats */
415#if !defined(CONFIG_USER_ONLY)
45d827d2 416static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
76a66253 417{
45d827d2 418 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
76a66253
JM		 419}
420
45d827d2 421static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
76a66253 422{
45d827d2
AJ		 423 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
424 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
425 tcg_temp_free_i32(t0);
76a66253
JM		 426}
427
45d827d2 428static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
76a66253 429{
45d827d2
AJ		 430 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
431 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
432 tcg_temp_free_i32(t0);
76a66253
JM		 433}
434#endif
435
436/* PowerPC 40x specific registers */
437#if !defined(CONFIG_USER_ONLY)
45d827d2 438static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
76a66253 439{
45d827d2 440 gen_helper_load_40x_pit(cpu_gpr[gprn]);
76a66253
JM		 441}
442
45d827d2 443static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
76a66253 444{
45d827d2 445 gen_helper_store_40x_pit(cpu_gpr[gprn]);
76a66253
JM		 446}
447
45d827d2 448static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
8ecc7913
JM		 449{
450 DisasContext *ctx = opaque;
451
45d827d2 452 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
8ecc7913 453 /* We must stop translation as we may have rebooted */
e06fcd75 454 gen_stop_exception(ctx);
8ecc7913
JM		 455}
456
45d827d2 457static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
c294fc58 458{
45d827d2 459 gen_helper_store_40x_sler(cpu_gpr[gprn]);
c294fc58
JM		 460}
461
45d827d2 462static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
76a66253 463{
45d827d2 464 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
76a66253
JM		 465}
466
45d827d2 467static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
76a66253 468{
45d827d2 469 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
76a66253
JM		 470}
471#endif
472
473/* PowerPC 403 specific registers */
474/* PBL1 / PBU1 / PBL2 / PBU2 */
475#if !defined(CONFIG_USER_ONLY)
45d827d2 476static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
76a66253 477{
45d827d2 478 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
76a66253
JM		 479}
480
45d827d2 481static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
76a66253 482{
45d827d2
AJ		 483 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
484 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
485 tcg_temp_free_i32(t0);
76a66253
JM		 486}
487
45d827d2 488static void spr_write_pir (void *opaque, int sprn, int gprn)
3fc6c082 489{
45d827d2
AJ		 490 TCGv t0 = tcg_temp_new();
491 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
492 gen_store_spr(SPR_PIR, t0);
493 tcg_temp_free(t0);
3fc6c082 494}
76a66253 495#endif
3fc6c082 496
d34defbc
AJ		 497/* SPE specific registers */
498static void spr_read_spefscr (void *opaque, int gprn, int sprn)
499{
500 TCGv_i32 t0 = tcg_temp_new_i32();
515e2f7e 501 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
d34defbc
AJ		 502 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
503 tcg_temp_free_i32(t0);
504}
505
506static void spr_write_spefscr (void *opaque, int sprn, int gprn)
507{
508 TCGv_i32 t0 = tcg_temp_new_i32();
509 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
515e2f7e 510 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
d34defbc
AJ		 511 tcg_temp_free_i32(t0);
512}
513
6f5d427d
JM		 514#if !defined(CONFIG_USER_ONLY)
515/* Callback used to write the exception vector base */
45d827d2 516static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
6f5d427d 517{
45d827d2
AJ		 518 TCGv t0 = tcg_temp_new();
519 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
520 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
521 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
522 gen_store_spr(sprn, t0);
69bd5820 523 tcg_temp_free(t0);
6f5d427d
JM		 524}
525
45d827d2 526static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
6f5d427d
JM		 527{
528 DisasContext *ctx = opaque;
529
530 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
45d827d2
AJ		 531 TCGv t0 = tcg_temp_new();
532 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
533 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
534 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
535 gen_store_spr(sprn, t0);
536 tcg_temp_free(t0);
6f5d427d 537 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
45d827d2
AJ		 538 TCGv t0 = tcg_temp_new();
539 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
540 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
541 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
542 gen_store_spr(sprn, t0);
543 tcg_temp_free(t0);
6f5d427d
JM		 544 } else {
545 printf("Trying to write an unknown exception vector %d %03x\n",
546 sprn, sprn);
e06fcd75 547 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6f5d427d
JM		 548 }
549}
550#endif
551
cf8358c8
AJ		 552static inline void vscr_init (CPUPPCState *env, uint32_t val)
553{
554 env->vscr = val;
555 /* Altivec always uses round-to-nearest */
556 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
557 set_flush_to_zero(vscr_nj, &env->vec_status);
558}
559
76a66253
JM		 560#if defined(CONFIG_USER_ONLY)
561#define spr_register(env, num, name, uea_read, uea_write, \
562 oea_read, oea_write, initial_value) \
563do { \
564 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
565} while (0)
566static inline void _spr_register (CPUPPCState *env, int num,
b55266b5 567 const char *name,
45d827d2
AJ		 568 void (*uea_read)(void *opaque, int gprn, int sprn),
569 void (*uea_write)(void *opaque, int sprn, int gprn),
76a66253
JM		 570 target_ulong initial_value)
571#else
3fc6c082 572static inline void spr_register (CPUPPCState *env, int num,
b55266b5 573 const char *name,
45d827d2
AJ		 574 void (*uea_read)(void *opaque, int gprn, int sprn),
575 void (*uea_write)(void *opaque, int sprn, int gprn),
576 void (*oea_read)(void *opaque, int gprn, int sprn),
577 void (*oea_write)(void *opaque, int sprn, int gprn),
3fc6c082 578 target_ulong initial_value)
76a66253 579#endif
3fc6c082 580{
c227f099 581 ppc_spr_t *spr;
3fc6c082
FB		 582
583 spr = &env->spr_cb[num];
584 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 585#if !defined(CONFIG_USER_ONLY)
586 spr->oea_read != NULL || spr->oea_write != NULL ||
587#endif
588 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 589 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
590 exit(1);
591 }
592#if defined(PPC_DEBUG_SPR)
90e189ec
BS		 593 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
594 name, initial_value);
3fc6c082
FB		 595#endif
596 spr->name = name;
597 spr->uea_read = uea_read;
598 spr->uea_write = uea_write;
76a66253 599#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 600 spr->oea_read = oea_read;
601 spr->oea_write = oea_write;
76a66253 602#endif
3fc6c082
FB		 603 env->spr[num] = initial_value;
604}
605
606/* Generic PowerPC SPRs */
607static void gen_spr_generic (CPUPPCState *env)
608{
609 /* Integer processing */
610 spr_register(env, SPR_XER, "XER",
611 &spr_read_xer, &spr_write_xer,
612 &spr_read_xer, &spr_write_xer,
613 0x00000000);
614 /* Branch contol */
615 spr_register(env, SPR_LR, "LR",
616 &spr_read_lr, &spr_write_lr,
617 &spr_read_lr, &spr_write_lr,
618 0x00000000);
619 spr_register(env, SPR_CTR, "CTR",
620 &spr_read_ctr, &spr_write_ctr,
621 &spr_read_ctr, &spr_write_ctr,
622 0x00000000);
623 /* Interrupt processing */
624 spr_register(env, SPR_SRR0, "SRR0",
625 SPR_NOACCESS, SPR_NOACCESS,
626 &spr_read_generic, &spr_write_generic,
627 0x00000000);
628 spr_register(env, SPR_SRR1, "SRR1",
629 SPR_NOACCESS, SPR_NOACCESS,
630 &spr_read_generic, &spr_write_generic,
631 0x00000000);
632 /* Processor control */
633 spr_register(env, SPR_SPRG0, "SPRG0",
634 SPR_NOACCESS, SPR_NOACCESS,
635 &spr_read_generic, &spr_write_generic,
636 0x00000000);
637 spr_register(env, SPR_SPRG1, "SPRG1",
638 SPR_NOACCESS, SPR_NOACCESS,
639 &spr_read_generic, &spr_write_generic,
640 0x00000000);
641 spr_register(env, SPR_SPRG2, "SPRG2",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_generic, &spr_write_generic,
644 0x00000000);
645 spr_register(env, SPR_SPRG3, "SPRG3",
646 SPR_NOACCESS, SPR_NOACCESS,
647 &spr_read_generic, &spr_write_generic,
648 0x00000000);
649}
650
651/* SPR common to all non-embedded PowerPC, including 601 */
652static void gen_spr_ne_601 (CPUPPCState *env)
653{
654 /* Exception processing */
655 spr_register(env, SPR_DSISR, "DSISR",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_DAR, "DAR",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 /* Timer */
664 spr_register(env, SPR_DECR, "DECR",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_decr, &spr_write_decr,
667 0x00000000);
668 /* Memory management */
669 spr_register(env, SPR_SDR1, "SDR1",
670 SPR_NOACCESS, SPR_NOACCESS,
bb593904 671 &spr_read_generic, &spr_write_sdr1,
3fc6c082
FB		 672 0x00000000);
673}
674
675/* BATs 0-3 */
676static void gen_low_BATs (CPUPPCState *env)
677{
f2e63a42 678#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 679 spr_register(env, SPR_IBAT0U, "IBAT0U",
680 SPR_NOACCESS, SPR_NOACCESS,
681 &spr_read_ibat, &spr_write_ibatu,
682 0x00000000);
683 spr_register(env, SPR_IBAT0L, "IBAT0L",
684 SPR_NOACCESS, SPR_NOACCESS,
685 &spr_read_ibat, &spr_write_ibatl,
686 0x00000000);
687 spr_register(env, SPR_IBAT1U, "IBAT1U",
688 SPR_NOACCESS, SPR_NOACCESS,
689 &spr_read_ibat, &spr_write_ibatu,
690 0x00000000);
691 spr_register(env, SPR_IBAT1L, "IBAT1L",
692 SPR_NOACCESS, SPR_NOACCESS,
693 &spr_read_ibat, &spr_write_ibatl,
694 0x00000000);
695 spr_register(env, SPR_IBAT2U, "IBAT2U",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_ibat, &spr_write_ibatu,
698 0x00000000);
699 spr_register(env, SPR_IBAT2L, "IBAT2L",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_ibat, &spr_write_ibatl,
702 0x00000000);
703 spr_register(env, SPR_IBAT3U, "IBAT3U",
704 SPR_NOACCESS, SPR_NOACCESS,
705 &spr_read_ibat, &spr_write_ibatu,
706 0x00000000);
707 spr_register(env, SPR_IBAT3L, "IBAT3L",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_ibat, &spr_write_ibatl,
710 0x00000000);
711 spr_register(env, SPR_DBAT0U, "DBAT0U",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_dbat, &spr_write_dbatu,
714 0x00000000);
715 spr_register(env, SPR_DBAT0L, "DBAT0L",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_dbat, &spr_write_dbatl,
718 0x00000000);
719 spr_register(env, SPR_DBAT1U, "DBAT1U",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_dbat, &spr_write_dbatu,
722 0x00000000);
723 spr_register(env, SPR_DBAT1L, "DBAT1L",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_dbat, &spr_write_dbatl,
726 0x00000000);
727 spr_register(env, SPR_DBAT2U, "DBAT2U",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_dbat, &spr_write_dbatu,
730 0x00000000);
731 spr_register(env, SPR_DBAT2L, "DBAT2L",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_dbat, &spr_write_dbatl,
734 0x00000000);
735 spr_register(env, SPR_DBAT3U, "DBAT3U",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_dbat, &spr_write_dbatu,
738 0x00000000);
739 spr_register(env, SPR_DBAT3L, "DBAT3L",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_dbat, &spr_write_dbatl,
742 0x00000000);
a750fc0b 743 env->nb_BATs += 4;
f2e63a42 744#endif
3fc6c082
FB		 745}
746
747/* BATs 4-7 */
748static void gen_high_BATs (CPUPPCState *env)
749{
f2e63a42 750#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 751 spr_register(env, SPR_IBAT4U, "IBAT4U",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_ibat_h, &spr_write_ibatu_h,
754 0x00000000);
755 spr_register(env, SPR_IBAT4L, "IBAT4L",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_ibat_h, &spr_write_ibatl_h,
758 0x00000000);
759 spr_register(env, SPR_IBAT5U, "IBAT5U",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_ibat_h, &spr_write_ibatu_h,
762 0x00000000);
763 spr_register(env, SPR_IBAT5L, "IBAT5L",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_ibat_h, &spr_write_ibatl_h,
766 0x00000000);
767 spr_register(env, SPR_IBAT6U, "IBAT6U",
768 SPR_NOACCESS, SPR_NOACCESS,
769 &spr_read_ibat_h, &spr_write_ibatu_h,
770 0x00000000);
771 spr_register(env, SPR_IBAT6L, "IBAT6L",
772 SPR_NOACCESS, SPR_NOACCESS,
773 &spr_read_ibat_h, &spr_write_ibatl_h,
774 0x00000000);
775 spr_register(env, SPR_IBAT7U, "IBAT7U",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_ibat_h, &spr_write_ibatu_h,
778 0x00000000);
779 spr_register(env, SPR_IBAT7L, "IBAT7L",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_ibat_h, &spr_write_ibatl_h,
782 0x00000000);
783 spr_register(env, SPR_DBAT4U, "DBAT4U",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_dbat_h, &spr_write_dbatu_h,
786 0x00000000);
787 spr_register(env, SPR_DBAT4L, "DBAT4L",
788 SPR_NOACCESS, SPR_NOACCESS,
789 &spr_read_dbat_h, &spr_write_dbatl_h,
790 0x00000000);
791 spr_register(env, SPR_DBAT5U, "DBAT5U",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_dbat_h, &spr_write_dbatu_h,
794 0x00000000);
795 spr_register(env, SPR_DBAT5L, "DBAT5L",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_dbat_h, &spr_write_dbatl_h,
798 0x00000000);
799 spr_register(env, SPR_DBAT6U, "DBAT6U",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_dbat_h, &spr_write_dbatu_h,
802 0x00000000);
803 spr_register(env, SPR_DBAT6L, "DBAT6L",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_dbat_h, &spr_write_dbatl_h,
806 0x00000000);
807 spr_register(env, SPR_DBAT7U, "DBAT7U",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_dbat_h, &spr_write_dbatu_h,
810 0x00000000);
811 spr_register(env, SPR_DBAT7L, "DBAT7L",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_dbat_h, &spr_write_dbatl_h,
814 0x00000000);
a750fc0b 815 env->nb_BATs += 4;
f2e63a42 816#endif
3fc6c082
FB		 817}
818
819/* Generic PowerPC time base */
820static void gen_tbl (CPUPPCState *env)
821{
822 spr_register(env, SPR_VTBL, "TBL",
823 &spr_read_tbl, SPR_NOACCESS,
824 &spr_read_tbl, SPR_NOACCESS,
825 0x00000000);
826 spr_register(env, SPR_TBL, "TBL",
de6a1dec
DI		 827 &spr_read_tbl, SPR_NOACCESS,
828 &spr_read_tbl, &spr_write_tbl,
3fc6c082
FB		 829 0x00000000);
830 spr_register(env, SPR_VTBU, "TBU",
831 &spr_read_tbu, SPR_NOACCESS,
832 &spr_read_tbu, SPR_NOACCESS,
833 0x00000000);
834 spr_register(env, SPR_TBU, "TBU",
de6a1dec
DI		 835 &spr_read_tbu, SPR_NOACCESS,
836 &spr_read_tbu, &spr_write_tbu,
3fc6c082
FB		 837 0x00000000);
838}
839
76a66253
JM		 840/* Softare table search registers */
841static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
842{
f2e63a42 843#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 844 env->nb_tlb = nb_tlbs;
845 env->nb_ways = nb_ways;
846 env->id_tlbs = 1;
1c53accc 847 env->tlb_type = TLB_6XX;
76a66253
JM		 848 spr_register(env, SPR_DMISS, "DMISS",
849 SPR_NOACCESS, SPR_NOACCESS,
850 &spr_read_generic, SPR_NOACCESS,
851 0x00000000);
852 spr_register(env, SPR_DCMP, "DCMP",
853 SPR_NOACCESS, SPR_NOACCESS,
854 &spr_read_generic, SPR_NOACCESS,
855 0x00000000);
856 spr_register(env, SPR_HASH1, "HASH1",
857 SPR_NOACCESS, SPR_NOACCESS,
858 &spr_read_generic, SPR_NOACCESS,
859 0x00000000);
860 spr_register(env, SPR_HASH2, "HASH2",
861 SPR_NOACCESS, SPR_NOACCESS,
862 &spr_read_generic, SPR_NOACCESS,
863 0x00000000);
864 spr_register(env, SPR_IMISS, "IMISS",
865 SPR_NOACCESS, SPR_NOACCESS,
866 &spr_read_generic, SPR_NOACCESS,
867 0x00000000);
868 spr_register(env, SPR_ICMP, "ICMP",
869 SPR_NOACCESS, SPR_NOACCESS,
870 &spr_read_generic, SPR_NOACCESS,
871 0x00000000);
872 spr_register(env, SPR_RPA, "RPA",
873 SPR_NOACCESS, SPR_NOACCESS,
874 &spr_read_generic, &spr_write_generic,
875 0x00000000);
f2e63a42 876#endif
76a66253
JM		 877}
878
879/* SPR common to MPC755 and G2 */
880static void gen_spr_G2_755 (CPUPPCState *env)
881{
882 /* SGPRs */
883 spr_register(env, SPR_SPRG4, "SPRG4",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, &spr_write_generic,
886 0x00000000);
887 spr_register(env, SPR_SPRG5, "SPRG5",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, &spr_write_generic,
890 0x00000000);
891 spr_register(env, SPR_SPRG6, "SPRG6",
892 SPR_NOACCESS, SPR_NOACCESS,
893 &spr_read_generic, &spr_write_generic,
894 0x00000000);
895 spr_register(env, SPR_SPRG7, "SPRG7",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, &spr_write_generic,
898 0x00000000);
76a66253
JM		 899}
900
3fc6c082
FB		 901/* SPR common to all 7xx PowerPC implementations */
902static void gen_spr_7xx (CPUPPCState *env)
903{
904 /* Breakpoints */
905 /* XXX : not implemented */
906 spr_register(env, SPR_DABR, "DABR",
907 SPR_NOACCESS, SPR_NOACCESS,
908 &spr_read_generic, &spr_write_generic,
909 0x00000000);
910 /* XXX : not implemented */
911 spr_register(env, SPR_IABR, "IABR",
912 SPR_NOACCESS, SPR_NOACCESS,
913 &spr_read_generic, &spr_write_generic,
914 0x00000000);
915 /* Cache management */
916 /* XXX : not implemented */
917 spr_register(env, SPR_ICTC, "ICTC",
918 SPR_NOACCESS, SPR_NOACCESS,
919 &spr_read_generic, &spr_write_generic,
920 0x00000000);
921 /* Performance monitors */
922 /* XXX : not implemented */
923 spr_register(env, SPR_MMCR0, "MMCR0",
924 SPR_NOACCESS, SPR_NOACCESS,
925 &spr_read_generic, &spr_write_generic,
926 0x00000000);
927 /* XXX : not implemented */
928 spr_register(env, SPR_MMCR1, "MMCR1",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 0x00000000);
932 /* XXX : not implemented */
933 spr_register(env, SPR_PMC1, "PMC1",
934 SPR_NOACCESS, SPR_NOACCESS,
935 &spr_read_generic, &spr_write_generic,
936 0x00000000);
937 /* XXX : not implemented */
938 spr_register(env, SPR_PMC2, "PMC2",
939 SPR_NOACCESS, SPR_NOACCESS,
940 &spr_read_generic, &spr_write_generic,
941 0x00000000);
942 /* XXX : not implemented */
943 spr_register(env, SPR_PMC3, "PMC3",
944 SPR_NOACCESS, SPR_NOACCESS,
945 &spr_read_generic, &spr_write_generic,
946 0x00000000);
947 /* XXX : not implemented */
948 spr_register(env, SPR_PMC4, "PMC4",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_generic, &spr_write_generic,
951 0x00000000);
952 /* XXX : not implemented */
a750fc0b 953 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 954 SPR_NOACCESS, SPR_NOACCESS,
955 &spr_read_generic, SPR_NOACCESS,
956 0x00000000);
578bb252 957 /* XXX : not implemented */
3fc6c082
FB		 958 spr_register(env, SPR_UMMCR0, "UMMCR0",
959 &spr_read_ureg, SPR_NOACCESS,
960 &spr_read_ureg, SPR_NOACCESS,
961 0x00000000);
578bb252 962 /* XXX : not implemented */
3fc6c082
FB		 963 spr_register(env, SPR_UMMCR1, "UMMCR1",
964 &spr_read_ureg, SPR_NOACCESS,
965 &spr_read_ureg, SPR_NOACCESS,
966 0x00000000);
578bb252 967 /* XXX : not implemented */
3fc6c082
FB		 968 spr_register(env, SPR_UPMC1, "UPMC1",
969 &spr_read_ureg, SPR_NOACCESS,
970 &spr_read_ureg, SPR_NOACCESS,
971 0x00000000);
578bb252 972 /* XXX : not implemented */
3fc6c082
FB		 973 spr_register(env, SPR_UPMC2, "UPMC2",
974 &spr_read_ureg, SPR_NOACCESS,
975 &spr_read_ureg, SPR_NOACCESS,
976 0x00000000);
578bb252 977 /* XXX : not implemented */
3fc6c082
FB		 978 spr_register(env, SPR_UPMC3, "UPMC3",
979 &spr_read_ureg, SPR_NOACCESS,
980 &spr_read_ureg, SPR_NOACCESS,
981 0x00000000);
578bb252 982 /* XXX : not implemented */
3fc6c082
FB		 983 spr_register(env, SPR_UPMC4, "UPMC4",
984 &spr_read_ureg, SPR_NOACCESS,
985 &spr_read_ureg, SPR_NOACCESS,
986 0x00000000);
578bb252 987 /* XXX : not implemented */
a750fc0b 988 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 989 &spr_read_ureg, SPR_NOACCESS,
990 &spr_read_ureg, SPR_NOACCESS,
991 0x00000000);
a750fc0b 992 /* External access control */
3fc6c082 993 /* XXX : not implemented */
a750fc0b 994 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 995 SPR_NOACCESS, SPR_NOACCESS,
996 &spr_read_generic, &spr_write_generic,
997 0x00000000);
a750fc0b
JM		 998}
999
1000static void gen_spr_thrm (CPUPPCState *env)
1001{
1002 /* Thermal management */
3fc6c082 1003 /* XXX : not implemented */
a750fc0b 1004 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 1005 SPR_NOACCESS, SPR_NOACCESS,
1006 &spr_read_generic, &spr_write_generic,
1007 0x00000000);
1008 /* XXX : not implemented */
a750fc0b 1009 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 1010 SPR_NOACCESS, SPR_NOACCESS,
1011 &spr_read_generic, &spr_write_generic,
1012 0x00000000);
3fc6c082 1013 /* XXX : not implemented */
a750fc0b 1014 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 1015 SPR_NOACCESS, SPR_NOACCESS,
1016 &spr_read_generic, &spr_write_generic,
1017 0x00000000);
1018}
1019
1020/* SPR specific to PowerPC 604 implementation */
1021static void gen_spr_604 (CPUPPCState *env)
1022{
1023 /* Processor identification */
1024 spr_register(env, SPR_PIR, "PIR",
1025 SPR_NOACCESS, SPR_NOACCESS,
1026 &spr_read_generic, &spr_write_pir,
1027 0x00000000);
1028 /* Breakpoints */
1029 /* XXX : not implemented */
1030 spr_register(env, SPR_IABR, "IABR",
1031 SPR_NOACCESS, SPR_NOACCESS,
1032 &spr_read_generic, &spr_write_generic,
1033 0x00000000);
1034 /* XXX : not implemented */
1035 spr_register(env, SPR_DABR, "DABR",
1036 SPR_NOACCESS, SPR_NOACCESS,
1037 &spr_read_generic, &spr_write_generic,
1038 0x00000000);
1039 /* Performance counters */
1040 /* XXX : not implemented */
1041 spr_register(env, SPR_MMCR0, "MMCR0",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, &spr_write_generic,
1044 0x00000000);
1045 /* XXX : not implemented */
3fc6c082
FB		 1046 spr_register(env, SPR_PMC1, "PMC1",
1047 SPR_NOACCESS, SPR_NOACCESS,
1048 &spr_read_generic, &spr_write_generic,
1049 0x00000000);
1050 /* XXX : not implemented */
1051 spr_register(env, SPR_PMC2, "PMC2",
1052 SPR_NOACCESS, SPR_NOACCESS,
1053 &spr_read_generic, &spr_write_generic,
1054 0x00000000);
1055 /* XXX : not implemented */
a750fc0b 1056 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 1057 SPR_NOACCESS, SPR_NOACCESS,
1058 &spr_read_generic, SPR_NOACCESS,
1059 0x00000000);
1060 /* XXX : not implemented */
1061 spr_register(env, SPR_SDA, "SDA",
1062 SPR_NOACCESS, SPR_NOACCESS,
1063 &spr_read_generic, SPR_NOACCESS,
1064 0x00000000);
1065 /* External access control */
1066 /* XXX : not implemented */
1067 spr_register(env, SPR_EAR, "EAR",
1068 SPR_NOACCESS, SPR_NOACCESS,
1069 &spr_read_generic, &spr_write_generic,
1070 0x00000000);
1071}
1072
76a66253
JM		 1073/* SPR specific to PowerPC 603 implementation */
1074static void gen_spr_603 (CPUPPCState *env)
3fc6c082 1075{
76a66253
JM		 1076 /* External access control */
1077 /* XXX : not implemented */
1078 spr_register(env, SPR_EAR, "EAR",
3fc6c082 1079 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 1080 &spr_read_generic, &spr_write_generic,
1081 0x00000000);
3fc6c082
FB		 1082}
1083
76a66253
JM		 1084/* SPR specific to PowerPC G2 implementation */
1085static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 1086{
76a66253
JM		 1087 /* Memory base address */
1088 /* MBAR */
578bb252 1089 /* XXX : not implemented */
76a66253
JM		 1090 spr_register(env, SPR_MBAR, "MBAR",
1091 SPR_NOACCESS, SPR_NOACCESS,
1092 &spr_read_generic, &spr_write_generic,
1093 0x00000000);
76a66253 1094 /* Exception processing */
363be49c 1095 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1096 SPR_NOACCESS, SPR_NOACCESS,
1097 &spr_read_generic, &spr_write_generic,
1098 0x00000000);
363be49c 1099 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 1100 SPR_NOACCESS, SPR_NOACCESS,
1101 &spr_read_generic, &spr_write_generic,
1102 0x00000000);
1103 /* Breakpoints */
1104 /* XXX : not implemented */
1105 spr_register(env, SPR_DABR, "DABR",
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_generic, &spr_write_generic,
1108 0x00000000);
1109 /* XXX : not implemented */
1110 spr_register(env, SPR_DABR2, "DABR2",
1111 SPR_NOACCESS, SPR_NOACCESS,
1112 &spr_read_generic, &spr_write_generic,
1113 0x00000000);
1114 /* XXX : not implemented */
1115 spr_register(env, SPR_IABR, "IABR",
1116 SPR_NOACCESS, SPR_NOACCESS,
1117 &spr_read_generic, &spr_write_generic,
1118 0x00000000);
1119 /* XXX : not implemented */
1120 spr_register(env, SPR_IABR2, "IABR2",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_generic, &spr_write_generic,
1123 0x00000000);
1124 /* XXX : not implemented */
1125 spr_register(env, SPR_IBCR, "IBCR",
1126 SPR_NOACCESS, SPR_NOACCESS,
1127 &spr_read_generic, &spr_write_generic,
1128 0x00000000);
1129 /* XXX : not implemented */
1130 spr_register(env, SPR_DBCR, "DBCR",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_generic,
1133 0x00000000);
1134}
1135
1136/* SPR specific to PowerPC 602 implementation */
1137static void gen_spr_602 (CPUPPCState *env)
1138{
1139 /* ESA registers */
1140 /* XXX : not implemented */
1141 spr_register(env, SPR_SER, "SER",
1142 SPR_NOACCESS, SPR_NOACCESS,
1143 &spr_read_generic, &spr_write_generic,
1144 0x00000000);
1145 /* XXX : not implemented */
1146 spr_register(env, SPR_SEBR, "SEBR",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, &spr_write_generic,
1149 0x00000000);
1150 /* XXX : not implemented */
a750fc0b 1151 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_generic, &spr_write_generic,
1154 0x00000000);
1155 /* Floating point status */
1156 /* XXX : not implemented */
1157 spr_register(env, SPR_SP, "SP",
1158 SPR_NOACCESS, SPR_NOACCESS,
1159 &spr_read_generic, &spr_write_generic,
1160 0x00000000);
1161 /* XXX : not implemented */
1162 spr_register(env, SPR_LT, "LT",
1163 SPR_NOACCESS, SPR_NOACCESS,
1164 &spr_read_generic, &spr_write_generic,
1165 0x00000000);
1166 /* Watchdog timer */
1167 /* XXX : not implemented */
1168 spr_register(env, SPR_TCR, "TCR",
1169 SPR_NOACCESS, SPR_NOACCESS,
1170 &spr_read_generic, &spr_write_generic,
1171 0x00000000);
1172 /* Interrupt base */
1173 spr_register(env, SPR_IBR, "IBR",
1174 SPR_NOACCESS, SPR_NOACCESS,
1175 &spr_read_generic, &spr_write_generic,
1176 0x00000000);
a750fc0b
JM		 1177 /* XXX : not implemented */
1178 spr_register(env, SPR_IABR, "IABR",
1179 SPR_NOACCESS, SPR_NOACCESS,
1180 &spr_read_generic, &spr_write_generic,
1181 0x00000000);
76a66253
JM		 1182}
1183
1184/* SPR specific to PowerPC 601 implementation */
1185static void gen_spr_601 (CPUPPCState *env)
1186{
1187 /* Multiplication/division register */
1188 /* MQ */
1189 spr_register(env, SPR_MQ, "MQ",
1190 &spr_read_generic, &spr_write_generic,
1191 &spr_read_generic, &spr_write_generic,
1192 0x00000000);
1193 /* RTC registers */
1194 spr_register(env, SPR_601_RTCU, "RTCU",
1195 SPR_NOACCESS, SPR_NOACCESS,
1196 SPR_NOACCESS, &spr_write_601_rtcu,
1197 0x00000000);
1198 spr_register(env, SPR_601_VRTCU, "RTCU",
1199 &spr_read_601_rtcu, SPR_NOACCESS,
1200 &spr_read_601_rtcu, SPR_NOACCESS,
1201 0x00000000);
1202 spr_register(env, SPR_601_RTCL, "RTCL",
1203 SPR_NOACCESS, SPR_NOACCESS,
1204 SPR_NOACCESS, &spr_write_601_rtcl,
1205 0x00000000);
1206 spr_register(env, SPR_601_VRTCL, "RTCL",
1207 &spr_read_601_rtcl, SPR_NOACCESS,
1208 &spr_read_601_rtcl, SPR_NOACCESS,
1209 0x00000000);
1210 /* Timer */
1211#if 0 /* ? */
1212 spr_register(env, SPR_601_UDECR, "UDECR",
1213 &spr_read_decr, SPR_NOACCESS,
1214 &spr_read_decr, SPR_NOACCESS,
1215 0x00000000);
1216#endif
1217 /* External access control */
1218 /* XXX : not implemented */
1219 spr_register(env, SPR_EAR, "EAR",
1220 SPR_NOACCESS, SPR_NOACCESS,
1221 &spr_read_generic, &spr_write_generic,
1222 0x00000000);
1223 /* Memory management */
f2e63a42 1224#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1225 spr_register(env, SPR_IBAT0U, "IBAT0U",
1226 SPR_NOACCESS, SPR_NOACCESS,
1227 &spr_read_601_ubat, &spr_write_601_ubatu,
1228 0x00000000);
1229 spr_register(env, SPR_IBAT0L, "IBAT0L",
1230 SPR_NOACCESS, SPR_NOACCESS,
1231 &spr_read_601_ubat, &spr_write_601_ubatl,
1232 0x00000000);
1233 spr_register(env, SPR_IBAT1U, "IBAT1U",
1234 SPR_NOACCESS, SPR_NOACCESS,
1235 &spr_read_601_ubat, &spr_write_601_ubatu,
1236 0x00000000);
1237 spr_register(env, SPR_IBAT1L, "IBAT1L",
1238 SPR_NOACCESS, SPR_NOACCESS,
1239 &spr_read_601_ubat, &spr_write_601_ubatl,
1240 0x00000000);
1241 spr_register(env, SPR_IBAT2U, "IBAT2U",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_601_ubat, &spr_write_601_ubatu,
1244 0x00000000);
1245 spr_register(env, SPR_IBAT2L, "IBAT2L",
1246 SPR_NOACCESS, SPR_NOACCESS,
1247 &spr_read_601_ubat, &spr_write_601_ubatl,
1248 0x00000000);
1249 spr_register(env, SPR_IBAT3U, "IBAT3U",
1250 SPR_NOACCESS, SPR_NOACCESS,
1251 &spr_read_601_ubat, &spr_write_601_ubatu,
1252 0x00000000);
1253 spr_register(env, SPR_IBAT3L, "IBAT3L",
1254 SPR_NOACCESS, SPR_NOACCESS,
1255 &spr_read_601_ubat, &spr_write_601_ubatl,
1256 0x00000000);
a750fc0b 1257 env->nb_BATs = 4;
f2e63a42 1258#endif
a750fc0b
JM		 1259}
1260
1261static void gen_spr_74xx (CPUPPCState *env)
1262{
1263 /* Processor identification */
1264 spr_register(env, SPR_PIR, "PIR",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_pir,
1267 0x00000000);
1268 /* XXX : not implemented */
1269 spr_register(env, SPR_MMCR2, "MMCR2",
1270 SPR_NOACCESS, SPR_NOACCESS,
1271 &spr_read_generic, &spr_write_generic,
1272 0x00000000);
578bb252 1273 /* XXX : not implemented */
a750fc0b
JM		 1274 spr_register(env, SPR_UMMCR2, "UMMCR2",
1275 &spr_read_ureg, SPR_NOACCESS,
1276 &spr_read_ureg, SPR_NOACCESS,
1277 0x00000000);
1278 /* XXX: not implemented */
1279 spr_register(env, SPR_BAMR, "BAMR",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 &spr_read_generic, &spr_write_generic,
1282 0x00000000);
578bb252 1283 /* XXX : not implemented */
a750fc0b
JM		 1284 spr_register(env, SPR_MSSCR0, "MSSCR0",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_generic,
1287 0x00000000);
1288 /* Hardware implementation registers */
1289 /* XXX : not implemented */
1290 spr_register(env, SPR_HID0, "HID0",
1291 SPR_NOACCESS, SPR_NOACCESS,
1292 &spr_read_generic, &spr_write_generic,
1293 0x00000000);
1294 /* XXX : not implemented */
1295 spr_register(env, SPR_HID1, "HID1",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_generic,
1298 0x00000000);
1299 /* Altivec */
1300 spr_register(env, SPR_VRSAVE, "VRSAVE",
1301 &spr_read_generic, &spr_write_generic,
1302 &spr_read_generic, &spr_write_generic,
1303 0x00000000);
bd928eba
JM		 1304 /* XXX : not implemented */
1305 spr_register(env, SPR_L2CR, "L2CR",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
cf8358c8
AJ		 1309 /* Not strictly an SPR */
1310 vscr_init(env, 0x00010000);
a750fc0b
JM		 1311}
1312
a750fc0b
JM		 1313static void gen_l3_ctrl (CPUPPCState *env)
1314{
1315 /* L3CR */
1316 /* XXX : not implemented */
1317 spr_register(env, SPR_L3CR, "L3CR",
1318 SPR_NOACCESS, SPR_NOACCESS,
1319 &spr_read_generic, &spr_write_generic,
1320 0x00000000);
1321 /* L3ITCR0 */
578bb252 1322 /* XXX : not implemented */
a750fc0b
JM		 1323 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1324 SPR_NOACCESS, SPR_NOACCESS,
1325 &spr_read_generic, &spr_write_generic,
1326 0x00000000);
a750fc0b 1327 /* L3PM */
578bb252 1328 /* XXX : not implemented */
a750fc0b
JM		 1329 spr_register(env, SPR_L3PM, "L3PM",
1330 SPR_NOACCESS, SPR_NOACCESS,
1331 &spr_read_generic, &spr_write_generic,
1332 0x00000000);
1333}
a750fc0b 1334
578bb252 1335static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1336{
f2e63a42 1337#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1338 env->nb_tlb = nb_tlbs;
1339 env->nb_ways = nb_ways;
1340 env->id_tlbs = 1;
1c53accc 1341 env->tlb_type = TLB_6XX;
578bb252 1342 /* XXX : not implemented */
a750fc0b
JM		 1343 spr_register(env, SPR_PTEHI, "PTEHI",
1344 SPR_NOACCESS, SPR_NOACCESS,
1345 &spr_read_generic, &spr_write_generic,
1346 0x00000000);
578bb252 1347 /* XXX : not implemented */
a750fc0b
JM		 1348 spr_register(env, SPR_PTELO, "PTELO",
1349 SPR_NOACCESS, SPR_NOACCESS,
1350 &spr_read_generic, &spr_write_generic,
1351 0x00000000);
578bb252 1352 /* XXX : not implemented */
a750fc0b
JM		 1353 spr_register(env, SPR_TLBMISS, "TLBMISS",
1354 SPR_NOACCESS, SPR_NOACCESS,
1355 &spr_read_generic, &spr_write_generic,
1356 0x00000000);
f2e63a42 1357#endif
76a66253
JM		 1358}
1359
01662f3e
AG		 1360#if !defined(CONFIG_USER_ONLY)
1361static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1362{
1363 TCGv t0 = tcg_temp_new();
1364
1365 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1366 gen_store_spr(sprn, t0);
1367 tcg_temp_free(t0);
1368}
1369
1370static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1371{
1ff7854e 1372 TCGv_i32 t0 = tcg_const_i32(sprn);
01662f3e 1373 gen_helper_booke206_tlbflush(t0);
1ff7854e 1374 tcg_temp_free_i32(t0);
01662f3e
AG		 1375}
1376
1377static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1378{
1ff7854e 1379 TCGv_i32 t0 = tcg_const_i32(sprn);
01662f3e 1380 gen_helper_booke_setpid(t0, cpu_gpr[gprn]);
1ff7854e 1381 tcg_temp_free_i32(t0);
01662f3e
AG		 1382}
1383#endif
1384
80d11f44 1385static void gen_spr_usprgh (CPUPPCState *env)
76a66253 1386{
80d11f44
JM		 1387 spr_register(env, SPR_USPRG4, "USPRG4",
1388 &spr_read_ureg, SPR_NOACCESS,
1389 &spr_read_ureg, SPR_NOACCESS,
1390 0x00000000);
1391 spr_register(env, SPR_USPRG5, "USPRG5",
1392 &spr_read_ureg, SPR_NOACCESS,
1393 &spr_read_ureg, SPR_NOACCESS,
1394 0x00000000);
1395 spr_register(env, SPR_USPRG6, "USPRG6",
1396 &spr_read_ureg, SPR_NOACCESS,
1397 &spr_read_ureg, SPR_NOACCESS,
1398 0x00000000);
1399 spr_register(env, SPR_USPRG7, "USPRG7",
1400 &spr_read_ureg, SPR_NOACCESS,
1401 &spr_read_ureg, SPR_NOACCESS,
76a66253 1402 0x00000000);
80d11f44
JM		 1403}
1404
1405/* PowerPC BookE SPR */
1406static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1407{
b55266b5 1408 const char *ivor_names[64] = {
80d11f44
JM		 1409 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1410 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1411 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1412 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1413 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1414 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1415 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1416 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1417 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1418 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1419 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1420 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1421 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1422 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1423 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1424 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1425 };
1426#define SPR_BOOKE_IVORxx (-1)
1427 int ivor_sprn[64] = {
1428 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1429 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1430 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1431 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1432 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1433 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1434 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1435 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1436 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1437 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1438 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1439 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1440 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1441 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1442 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1443 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1444 };
1445 int i;
1446
76a66253 1447 /* Interrupt processing */
363be49c 1448 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1449 SPR_NOACCESS, SPR_NOACCESS,
1450 &spr_read_generic, &spr_write_generic,
1451 0x00000000);
363be49c
JM		 1452 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1453 SPR_NOACCESS, SPR_NOACCESS,
1454 &spr_read_generic, &spr_write_generic,
1455 0x00000000);
76a66253
JM		 1456 /* Debug */
1457 /* XXX : not implemented */
1458 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 &spr_read_generic, &spr_write_generic,
1461 0x00000000);
1462 /* XXX : not implemented */
1463 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1464 SPR_NOACCESS, SPR_NOACCESS,
1465 &spr_read_generic, &spr_write_generic,
1466 0x00000000);
1467 /* XXX : not implemented */
76a66253
JM		 1468 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1469 SPR_NOACCESS, SPR_NOACCESS,
1470 &spr_read_generic, &spr_write_generic,
1471 0x00000000);
1472 /* XXX : not implemented */
1473 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1474 SPR_NOACCESS, SPR_NOACCESS,
1475 &spr_read_generic, &spr_write_generic,
1476 0x00000000);
1477 /* XXX : not implemented */
76a66253
JM		 1478 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1479 SPR_NOACCESS, SPR_NOACCESS,
1480 &spr_read_generic, &spr_write_generic,
1481 0x00000000);
1482 /* XXX : not implemented */
1483 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1484 SPR_NOACCESS, SPR_NOACCESS,
1485 &spr_read_generic, &spr_write_generic,
1486 0x00000000);
1487 /* XXX : not implemented */
1488 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 &spr_read_generic, &spr_write_generic,
1491 0x00000000);
1492 /* XXX : not implemented */
1493 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1494 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1495 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1496 0x00000000);
1497 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1498 SPR_NOACCESS, SPR_NOACCESS,
1499 &spr_read_generic, &spr_write_generic,
1500 0x00000000);
1501 spr_register(env, SPR_BOOKE_ESR, "ESR",
1502 SPR_NOACCESS, SPR_NOACCESS,
1503 &spr_read_generic, &spr_write_generic,
1504 0x00000000);
363be49c
JM		 1505 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1506 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1507 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1508 0x00000000);
1509 /* Exception vectors */
80d11f44
JM		 1510 for (i = 0; i < 64; i++) {
1511 if (ivor_mask & (1ULL << i)) {
1512 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1513 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1514 exit(1);
1515 }
1516 spr_register(env, ivor_sprn[i], ivor_names[i],
1517 SPR_NOACCESS, SPR_NOACCESS,
1518 &spr_read_generic, &spr_write_excp_vector,
1519 0x00000000);
1520 }
1521 }
76a66253
JM		 1522 spr_register(env, SPR_BOOKE_PID, "PID",
1523 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1524 &spr_read_generic, &spr_write_booke_pid,
76a66253
JM		 1525 0x00000000);
1526 spr_register(env, SPR_BOOKE_TCR, "TCR",
1527 SPR_NOACCESS, SPR_NOACCESS,
1528 &spr_read_generic, &spr_write_booke_tcr,
1529 0x00000000);
1530 spr_register(env, SPR_BOOKE_TSR, "TSR",
1531 SPR_NOACCESS, SPR_NOACCESS,
1532 &spr_read_generic, &spr_write_booke_tsr,
1533 0x00000000);
1534 /* Timer */
1535 spr_register(env, SPR_DECR, "DECR",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_decr, &spr_write_decr,
1538 0x00000000);
1539 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1540 SPR_NOACCESS, SPR_NOACCESS,
1541 SPR_NOACCESS, &spr_write_generic,
1542 0x00000000);
1543 /* SPRGs */
1544 spr_register(env, SPR_USPRG0, "USPRG0",
1545 &spr_read_generic, &spr_write_generic,
1546 &spr_read_generic, &spr_write_generic,
1547 0x00000000);
1548 spr_register(env, SPR_SPRG4, "SPRG4",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_generic,
1551 0x00000000);
76a66253
JM		 1552 spr_register(env, SPR_SPRG5, "SPRG5",
1553 SPR_NOACCESS, SPR_NOACCESS,
1554 &spr_read_generic, &spr_write_generic,
1555 0x00000000);
76a66253
JM		 1556 spr_register(env, SPR_SPRG6, "SPRG6",
1557 SPR_NOACCESS, SPR_NOACCESS,
1558 &spr_read_generic, &spr_write_generic,
1559 0x00000000);
76a66253
JM		 1560 spr_register(env, SPR_SPRG7, "SPRG7",
1561 SPR_NOACCESS, SPR_NOACCESS,
1562 &spr_read_generic, &spr_write_generic,
1563 0x00000000);
76a66253
JM		 1564}
1565
01662f3e
AG		 1566static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1567 uint32_t maxsize, uint32_t flags,
1568 uint32_t nentries)
1569{
1570 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1571 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1572 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1573 flags | nentries;
1574}
1575
1576/* BookE 2.06 storage control registers */
1577static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1578 uint32_t *tlbncfg)
363be49c 1579{
f2e63a42 1580#if !defined(CONFIG_USER_ONLY)
b55266b5 1581 const char *mas_names[8] = {
80d11f44
JM		 1582 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1583 };
1584 int mas_sprn[8] = {
1585 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1586 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1587 };
1588 int i;
1589
363be49c 1590 /* TLB assist registers */
578bb252 1591 /* XXX : not implemented */
80d11f44
JM		 1592 for (i = 0; i < 8; i++) {
1593 if (mas_mask & (1 << i)) {
1594 spr_register(env, mas_sprn[i], mas_names[i],
1595 SPR_NOACCESS, SPR_NOACCESS,
1596 &spr_read_generic, &spr_write_generic,
1597 0x00000000);
1598 }
1599 }
363be49c 1600 if (env->nb_pids > 1) {
578bb252 1601 /* XXX : not implemented */
363be49c
JM		 1602 spr_register(env, SPR_BOOKE_PID1, "PID1",
1603 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1604 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 1605 0x00000000);
1606 }
1607 if (env->nb_pids > 2) {
578bb252 1608 /* XXX : not implemented */
363be49c
JM		 1609 spr_register(env, SPR_BOOKE_PID2, "PID2",
1610 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1611 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 1612 0x00000000);
1613 }
578bb252 1614 /* XXX : not implemented */
65f9ee8d 1615 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1616 SPR_NOACCESS, SPR_NOACCESS,
1617 &spr_read_generic, SPR_NOACCESS,
1618 0x00000000); /* TOFIX */
363be49c
JM		 1619 switch (env->nb_ways) {
1620 case 4:
1621 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1622 SPR_NOACCESS, SPR_NOACCESS,
1623 &spr_read_generic, SPR_NOACCESS,
01662f3e 1624 tlbncfg[3]);
363be49c
JM		 1625 /* Fallthru */
1626 case 3:
1627 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1628 SPR_NOACCESS, SPR_NOACCESS,
1629 &spr_read_generic, SPR_NOACCESS,
01662f3e 1630 tlbncfg[2]);
363be49c
JM		 1631 /* Fallthru */
1632 case 2:
1633 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1634 SPR_NOACCESS, SPR_NOACCESS,
1635 &spr_read_generic, SPR_NOACCESS,
01662f3e 1636 tlbncfg[1]);
363be49c
JM		 1637 /* Fallthru */
1638 case 1:
1639 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1640 SPR_NOACCESS, SPR_NOACCESS,
1641 &spr_read_generic, SPR_NOACCESS,
01662f3e 1642 tlbncfg[0]);
363be49c
JM		 1643 /* Fallthru */
1644 case 0:
1645 default:
1646 break;
1647 }
f2e63a42 1648#endif
01662f3e
AG		 1649
1650 gen_spr_usprgh(env);
363be49c
JM		 1651}
1652
76a66253
JM		 1653/* SPR specific to PowerPC 440 implementation */
1654static void gen_spr_440 (CPUPPCState *env)
1655{
1656 /* Cache control */
1657 /* XXX : not implemented */
1658 spr_register(env, SPR_440_DNV0, "DNV0",
1659 SPR_NOACCESS, SPR_NOACCESS,
1660 &spr_read_generic, &spr_write_generic,
1661 0x00000000);
1662 /* XXX : not implemented */
1663 spr_register(env, SPR_440_DNV1, "DNV1",
1664 SPR_NOACCESS, SPR_NOACCESS,
1665 &spr_read_generic, &spr_write_generic,
1666 0x00000000);
1667 /* XXX : not implemented */
1668 spr_register(env, SPR_440_DNV2, "DNV2",
1669 SPR_NOACCESS, SPR_NOACCESS,
1670 &spr_read_generic, &spr_write_generic,
1671 0x00000000);
1672 /* XXX : not implemented */
1673 spr_register(env, SPR_440_DNV3, "DNV3",
1674 SPR_NOACCESS, SPR_NOACCESS,
1675 &spr_read_generic, &spr_write_generic,
1676 0x00000000);
1677 /* XXX : not implemented */
2662a059 1678 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1679 SPR_NOACCESS, SPR_NOACCESS,
1680 &spr_read_generic, &spr_write_generic,
1681 0x00000000);
1682 /* XXX : not implemented */
2662a059 1683 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_generic,
1686 0x00000000);
1687 /* XXX : not implemented */
2662a059 1688 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1689 SPR_NOACCESS, SPR_NOACCESS,
1690 &spr_read_generic, &spr_write_generic,
1691 0x00000000);
1692 /* XXX : not implemented */
2662a059 1693 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697 /* XXX : not implemented */
1698 spr_register(env, SPR_440_DVLIM, "DVLIM",
1699 SPR_NOACCESS, SPR_NOACCESS,
1700 &spr_read_generic, &spr_write_generic,
1701 0x00000000);
1702 /* XXX : not implemented */
1703 spr_register(env, SPR_440_INV0, "INV0",
1704 SPR_NOACCESS, SPR_NOACCESS,
1705 &spr_read_generic, &spr_write_generic,
1706 0x00000000);
1707 /* XXX : not implemented */
1708 spr_register(env, SPR_440_INV1, "INV1",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, &spr_write_generic,
1711 0x00000000);
1712 /* XXX : not implemented */
1713 spr_register(env, SPR_440_INV2, "INV2",
1714 SPR_NOACCESS, SPR_NOACCESS,
1715 &spr_read_generic, &spr_write_generic,
1716 0x00000000);
1717 /* XXX : not implemented */
1718 spr_register(env, SPR_440_INV3, "INV3",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_generic,
1721 0x00000000);
1722 /* XXX : not implemented */
2662a059 1723 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, &spr_write_generic,
1726 0x00000000);
1727 /* XXX : not implemented */
2662a059 1728 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_generic,
1731 0x00000000);
1732 /* XXX : not implemented */
2662a059 1733 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, &spr_write_generic,
1736 0x00000000);
1737 /* XXX : not implemented */
2662a059 1738 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_generic,
1741 0x00000000);
1742 /* XXX : not implemented */
1743 spr_register(env, SPR_440_IVLIM, "IVLIM",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747 /* Cache debug */
1748 /* XXX : not implemented */
2662a059 1749 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1750 SPR_NOACCESS, SPR_NOACCESS,
1751 &spr_read_generic, SPR_NOACCESS,
1752 0x00000000);
1753 /* XXX : not implemented */
2662a059 1754 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1755 SPR_NOACCESS, SPR_NOACCESS,
1756 &spr_read_generic, SPR_NOACCESS,
1757 0x00000000);
1758 /* XXX : not implemented */
2662a059 1759 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1760 SPR_NOACCESS, SPR_NOACCESS,
1761 &spr_read_generic, SPR_NOACCESS,
1762 0x00000000);
1763 /* XXX : not implemented */
2662a059 1764 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1765 SPR_NOACCESS, SPR_NOACCESS,
1766 &spr_read_generic, SPR_NOACCESS,
1767 0x00000000);
1768 /* XXX : not implemented */
2662a059 1769 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1770 SPR_NOACCESS, SPR_NOACCESS,
1771 &spr_read_generic, SPR_NOACCESS,
1772 0x00000000);
1773 /* XXX : not implemented */
1774 spr_register(env, SPR_440_DBDR, "DBDR",
1775 SPR_NOACCESS, SPR_NOACCESS,
1776 &spr_read_generic, &spr_write_generic,
1777 0x00000000);
1778 /* Processor control */
1779 spr_register(env, SPR_4xx_CCR0, "CCR0",
1780 SPR_NOACCESS, SPR_NOACCESS,
1781 &spr_read_generic, &spr_write_generic,
1782 0x00000000);
1783 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, SPR_NOACCESS,
1786 0x00000000);
1787 /* Storage control */
1788 spr_register(env, SPR_440_MMUCR, "MMUCR",
1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_generic, &spr_write_generic,
1791 0x00000000);
1792}
1793
1794/* SPR shared between PowerPC 40x implementations */
1795static void gen_spr_40x (CPUPPCState *env)
1796{
1797 /* Cache */
035feb88 1798 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1799 spr_register(env, SPR_40x_DCCR, "DCCR",
1800 SPR_NOACCESS, SPR_NOACCESS,
1801 &spr_read_generic, &spr_write_generic,
1802 0x00000000);
035feb88 1803 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1804 spr_register(env, SPR_40x_ICCR, "ICCR",
1805 SPR_NOACCESS, SPR_NOACCESS,
1806 &spr_read_generic, &spr_write_generic,
1807 0x00000000);
578bb252 1808 /* not emulated, as Qemu do not emulate caches */
2662a059 1809 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1810 SPR_NOACCESS, SPR_NOACCESS,
1811 &spr_read_generic, SPR_NOACCESS,
1812 0x00000000);
76a66253
JM		 1813 /* Exception */
1814 spr_register(env, SPR_40x_DEAR, "DEAR",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
1818 spr_register(env, SPR_40x_ESR, "ESR",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_generic,
1821 0x00000000);
1822 spr_register(env, SPR_40x_EVPR, "EVPR",
1823 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1824 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1825 0x00000000);
1826 spr_register(env, SPR_40x_SRR2, "SRR2",
1827 &spr_read_generic, &spr_write_generic,
1828 &spr_read_generic, &spr_write_generic,
1829 0x00000000);
1830 spr_register(env, SPR_40x_SRR3, "SRR3",
1831 &spr_read_generic, &spr_write_generic,
1832 &spr_read_generic, &spr_write_generic,
1833 0x00000000);
1834 /* Timers */
1835 spr_register(env, SPR_40x_PIT, "PIT",
1836 SPR_NOACCESS, SPR_NOACCESS,
1837 &spr_read_40x_pit, &spr_write_40x_pit,
1838 0x00000000);
1839 spr_register(env, SPR_40x_TCR, "TCR",
1840 SPR_NOACCESS, SPR_NOACCESS,
1841 &spr_read_generic, &spr_write_booke_tcr,
1842 0x00000000);
1843 spr_register(env, SPR_40x_TSR, "TSR",
1844 SPR_NOACCESS, SPR_NOACCESS,
1845 &spr_read_generic, &spr_write_booke_tsr,
1846 0x00000000);
2662a059
JM		 1847}
1848
1849/* SPR specific to PowerPC 405 implementation */
1850static void gen_spr_405 (CPUPPCState *env)
1851{
1852 /* MMU */
1853 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1854 SPR_NOACCESS, SPR_NOACCESS,
1855 &spr_read_generic, &spr_write_generic,
1856 0x00000000);
2662a059 1857 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1858 SPR_NOACCESS, SPR_NOACCESS,
1859 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1860 0x00700000);
1861 /* Debug interface */
76a66253
JM		 1862 /* XXX : not implemented */
1863 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1864 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1865 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1866 0x00000000);
1867 /* XXX : not implemented */
2662a059
JM		 1868 spr_register(env, SPR_405_DBCR1, "DBCR1",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, &spr_write_generic,
1871 0x00000000);
1872 /* XXX : not implemented */
76a66253
JM		 1873 spr_register(env, SPR_40x_DBSR, "DBSR",
1874 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1875 &spr_read_generic, &spr_write_clear,
1876 /* Last reset was system reset */
76a66253
JM		 1877 0x00000300);
1878 /* XXX : not implemented */
2662a059 1879 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1880 SPR_NOACCESS, SPR_NOACCESS,
1881 &spr_read_generic, &spr_write_generic,
1882 0x00000000);
2662a059 1883 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, &spr_write_generic,
1886 0x00000000);
2662a059
JM		 1887 /* XXX : not implemented */
1888 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1889 SPR_NOACCESS, SPR_NOACCESS,
1890 &spr_read_generic, &spr_write_generic,
2662a059 1891 0x00000000);
76a66253 1892 /* XXX : not implemented */
2662a059 1893 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1894 SPR_NOACCESS, SPR_NOACCESS,
1895 &spr_read_generic, &spr_write_generic,
1896 0x00000000);
1897 /* XXX : not implemented */
2662a059 1898 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_generic,
1901 0x00000000);
2662a059 1902 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1903 SPR_NOACCESS, SPR_NOACCESS,
1904 &spr_read_generic, &spr_write_generic,
1905 0x00000000);
1906 /* XXX : not implemented */
1907 spr_register(env, SPR_405_IAC3, "IAC3",
1908 SPR_NOACCESS, SPR_NOACCESS,
1909 &spr_read_generic, &spr_write_generic,
1910 0x00000000);
1911 /* XXX : not implemented */
1912 spr_register(env, SPR_405_IAC4, "IAC4",
1913 SPR_NOACCESS, SPR_NOACCESS,
1914 &spr_read_generic, &spr_write_generic,
1915 0x00000000);
1916 /* Storage control */
035feb88 1917 /* XXX: TODO: not implemented */
76a66253
JM		 1918 spr_register(env, SPR_405_SLER, "SLER",
1919 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1920 &spr_read_generic, &spr_write_40x_sler,
76a66253 1921 0x00000000);
2662a059
JM		 1922 spr_register(env, SPR_40x_ZPR, "ZPR",
1923 SPR_NOACCESS, SPR_NOACCESS,
1924 &spr_read_generic, &spr_write_generic,
1925 0x00000000);
76a66253
JM		 1926 /* XXX : not implemented */
1927 spr_register(env, SPR_405_SU0R, "SU0R",
1928 SPR_NOACCESS, SPR_NOACCESS,
1929 &spr_read_generic, &spr_write_generic,
1930 0x00000000);
1931 /* SPRG */
1932 spr_register(env, SPR_USPRG0, "USPRG0",
1933 &spr_read_ureg, SPR_NOACCESS,
1934 &spr_read_ureg, SPR_NOACCESS,
1935 0x00000000);
1936 spr_register(env, SPR_SPRG4, "SPRG4",
1937 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1938 &spr_read_generic, &spr_write_generic,
76a66253 1939 0x00000000);
76a66253
JM		 1940 spr_register(env, SPR_SPRG5, "SPRG5",
1941 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1942 spr_read_generic, &spr_write_generic,
76a66253 1943 0x00000000);
76a66253
JM		 1944 spr_register(env, SPR_SPRG6, "SPRG6",
1945 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1946 spr_read_generic, &spr_write_generic,
76a66253 1947 0x00000000);
76a66253
JM		 1948 spr_register(env, SPR_SPRG7, "SPRG7",
1949 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1950 spr_read_generic, &spr_write_generic,
76a66253 1951 0x00000000);
80d11f44 1952 gen_spr_usprgh(env);
76a66253
JM		 1953}
1954
1955/* SPR shared between PowerPC 401 & 403 implementations */
1956static void gen_spr_401_403 (CPUPPCState *env)
1957{
1958 /* Time base */
1959 spr_register(env, SPR_403_VTBL, "TBL",
1960 &spr_read_tbl, SPR_NOACCESS,
1961 &spr_read_tbl, SPR_NOACCESS,
1962 0x00000000);
1963 spr_register(env, SPR_403_TBL, "TBL",
1964 SPR_NOACCESS, SPR_NOACCESS,
1965 SPR_NOACCESS, &spr_write_tbl,
1966 0x00000000);
1967 spr_register(env, SPR_403_VTBU, "TBU",
1968 &spr_read_tbu, SPR_NOACCESS,
1969 &spr_read_tbu, SPR_NOACCESS,
1970 0x00000000);
1971 spr_register(env, SPR_403_TBU, "TBU",
1972 SPR_NOACCESS, SPR_NOACCESS,
1973 SPR_NOACCESS, &spr_write_tbu,
1974 0x00000000);
1975 /* Debug */
578bb252 1976 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1977 spr_register(env, SPR_403_CDBCR, "CDBCR",
1978 SPR_NOACCESS, SPR_NOACCESS,
1979 &spr_read_generic, &spr_write_generic,
1980 0x00000000);
1981}
1982
2662a059
JM		 1983/* SPR specific to PowerPC 401 implementation */
1984static void gen_spr_401 (CPUPPCState *env)
1985{
1986 /* Debug interface */
1987 /* XXX : not implemented */
1988 spr_register(env, SPR_40x_DBCR0, "DBCR",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 &spr_read_generic, &spr_write_40x_dbcr0,
1991 0x00000000);
1992 /* XXX : not implemented */
1993 spr_register(env, SPR_40x_DBSR, "DBSR",
1994 SPR_NOACCESS, SPR_NOACCESS,
1995 &spr_read_generic, &spr_write_clear,
1996 /* Last reset was system reset */
1997 0x00000300);
1998 /* XXX : not implemented */
1999 spr_register(env, SPR_40x_DAC1, "DAC",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, &spr_write_generic,
2002 0x00000000);
2003 /* XXX : not implemented */
2004 spr_register(env, SPR_40x_IAC1, "IAC",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, &spr_write_generic,
2007 0x00000000);
2008 /* Storage control */
035feb88 2009 /* XXX: TODO: not implemented */
2662a059
JM		 2010 spr_register(env, SPR_405_SLER, "SLER",
2011 SPR_NOACCESS, SPR_NOACCESS,
2012 &spr_read_generic, &spr_write_40x_sler,
2013 0x00000000);
035feb88
JM		 2014 /* not emulated, as Qemu never does speculative access */
2015 spr_register(env, SPR_40x_SGR, "SGR",
2016 SPR_NOACCESS, SPR_NOACCESS,
2017 &spr_read_generic, &spr_write_generic,
2018 0xFFFFFFFF);
2019 /* not emulated, as Qemu do not emulate caches */
2020 spr_register(env, SPR_40x_DCWR, "DCWR",
2021 SPR_NOACCESS, SPR_NOACCESS,
2022 &spr_read_generic, &spr_write_generic,
2023 0x00000000);
2662a059
JM		 2024}
2025
a750fc0b
JM		 2026static void gen_spr_401x2 (CPUPPCState *env)
2027{
2028 gen_spr_401(env);
2029 spr_register(env, SPR_40x_PID, "PID",
2030 SPR_NOACCESS, SPR_NOACCESS,
2031 &spr_read_generic, &spr_write_generic,
2032 0x00000000);
2033 spr_register(env, SPR_40x_ZPR, "ZPR",
2034 SPR_NOACCESS, SPR_NOACCESS,
2035 &spr_read_generic, &spr_write_generic,
2036 0x00000000);
2037}
2038
76a66253
JM		 2039/* SPR specific to PowerPC 403 implementation */
2040static void gen_spr_403 (CPUPPCState *env)
2041{
2662a059
JM		 2042 /* Debug interface */
2043 /* XXX : not implemented */
2044 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2045 SPR_NOACCESS, SPR_NOACCESS,
2046 &spr_read_generic, &spr_write_40x_dbcr0,
2047 0x00000000);
2048 /* XXX : not implemented */
2049 spr_register(env, SPR_40x_DBSR, "DBSR",
2050 SPR_NOACCESS, SPR_NOACCESS,
2051 &spr_read_generic, &spr_write_clear,
2052 /* Last reset was system reset */
2053 0x00000300);
2054 /* XXX : not implemented */
2055 spr_register(env, SPR_40x_DAC1, "DAC1",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, &spr_write_generic,
2058 0x00000000);
578bb252 2059 /* XXX : not implemented */
2662a059
JM		 2060 spr_register(env, SPR_40x_DAC2, "DAC2",
2061 SPR_NOACCESS, SPR_NOACCESS,
2062 &spr_read_generic, &spr_write_generic,
2063 0x00000000);
2064 /* XXX : not implemented */
2065 spr_register(env, SPR_40x_IAC1, "IAC1",
2066 SPR_NOACCESS, SPR_NOACCESS,
2067 &spr_read_generic, &spr_write_generic,
2068 0x00000000);
578bb252 2069 /* XXX : not implemented */
2662a059
JM		 2070 spr_register(env, SPR_40x_IAC2, "IAC2",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 &spr_read_generic, &spr_write_generic,
2073 0x00000000);
a750fc0b
JM		 2074}
2075
2076static void gen_spr_403_real (CPUPPCState *env)
2077{
76a66253
JM		 2078 spr_register(env, SPR_403_PBL1, "PBL1",
2079 SPR_NOACCESS, SPR_NOACCESS,
2080 &spr_read_403_pbr, &spr_write_403_pbr,
2081 0x00000000);
2082 spr_register(env, SPR_403_PBU1, "PBU1",
2083 SPR_NOACCESS, SPR_NOACCESS,
2084 &spr_read_403_pbr, &spr_write_403_pbr,
2085 0x00000000);
2086 spr_register(env, SPR_403_PBL2, "PBL2",
2087 SPR_NOACCESS, SPR_NOACCESS,
2088 &spr_read_403_pbr, &spr_write_403_pbr,
2089 0x00000000);
2090 spr_register(env, SPR_403_PBU2, "PBU2",
2091 SPR_NOACCESS, SPR_NOACCESS,
2092 &spr_read_403_pbr, &spr_write_403_pbr,
2093 0x00000000);
a750fc0b
JM		 2094}
2095
2096static void gen_spr_403_mmu (CPUPPCState *env)
2097{
2098 /* MMU */
2099 spr_register(env, SPR_40x_PID, "PID",
2100 SPR_NOACCESS, SPR_NOACCESS,
2101 &spr_read_generic, &spr_write_generic,
2102 0x00000000);
2662a059 2103 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_generic, &spr_write_generic,
2106 0x00000000);
2107}
2108
2109/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 2110static void gen_spr_compress (CPUPPCState *env)
2111{
578bb252 2112 /* XXX : not implemented */
76a66253
JM		 2113 spr_register(env, SPR_401_SKR, "SKR",
2114 SPR_NOACCESS, SPR_NOACCESS,
2115 &spr_read_generic, &spr_write_generic,
2116 0x00000000);
2117}
a750fc0b
JM		 2118
2119#if defined (TARGET_PPC64)
a750fc0b
JM		 2120/* SPR specific to PowerPC 620 */
2121static void gen_spr_620 (CPUPPCState *env)
2122{
082c6681
JM		 2123 /* Processor identification */
2124 spr_register(env, SPR_PIR, "PIR",
2125 SPR_NOACCESS, SPR_NOACCESS,
2126 &spr_read_generic, &spr_write_pir,
2127 0x00000000);
2128 spr_register(env, SPR_ASR, "ASR",
2129 SPR_NOACCESS, SPR_NOACCESS,
2130 &spr_read_asr, &spr_write_asr,
2131 0x00000000);
2132 /* Breakpoints */
2133 /* XXX : not implemented */
2134 spr_register(env, SPR_IABR, "IABR",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_generic,
2137 0x00000000);
2138 /* XXX : not implemented */
2139 spr_register(env, SPR_DABR, "DABR",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_generic,
2142 0x00000000);
2143 /* XXX : not implemented */
2144 spr_register(env, SPR_SIAR, "SIAR",
2145 SPR_NOACCESS, SPR_NOACCESS,
2146 &spr_read_generic, SPR_NOACCESS,
2147 0x00000000);
2148 /* XXX : not implemented */
2149 spr_register(env, SPR_SDA, "SDA",
2150 SPR_NOACCESS, SPR_NOACCESS,
2151 &spr_read_generic, SPR_NOACCESS,
2152 0x00000000);
2153 /* XXX : not implemented */
2154 spr_register(env, SPR_620_PMC1R, "PMC1",
2155 SPR_NOACCESS, SPR_NOACCESS,
2156 &spr_read_generic, SPR_NOACCESS,
2157 0x00000000);
2158 spr_register(env, SPR_620_PMC1W, "PMC1",
2159 SPR_NOACCESS, SPR_NOACCESS,
2160 SPR_NOACCESS, &spr_write_generic,
2161 0x00000000);
2162 /* XXX : not implemented */
2163 spr_register(env, SPR_620_PMC2R, "PMC2",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_generic, SPR_NOACCESS,
2166 0x00000000);
2167 spr_register(env, SPR_620_PMC2W, "PMC2",
2168 SPR_NOACCESS, SPR_NOACCESS,
2169 SPR_NOACCESS, &spr_write_generic,
2170 0x00000000);
2171 /* XXX : not implemented */
2172 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2173 SPR_NOACCESS, SPR_NOACCESS,
2174 &spr_read_generic, SPR_NOACCESS,
2175 0x00000000);
2176 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2177 SPR_NOACCESS, SPR_NOACCESS,
2178 SPR_NOACCESS, &spr_write_generic,
2179 0x00000000);
2180 /* External access control */
2181 /* XXX : not implemented */
2182 spr_register(env, SPR_EAR, "EAR",
2183 SPR_NOACCESS, SPR_NOACCESS,
2184 &spr_read_generic, &spr_write_generic,
2185 0x00000000);
2186#if 0 // XXX: check this
578bb252 2187 /* XXX : not implemented */
a750fc0b
JM		 2188 spr_register(env, SPR_620_PMR0, "PMR0",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_generic, &spr_write_generic,
2191 0x00000000);
578bb252 2192 /* XXX : not implemented */
a750fc0b
JM		 2193 spr_register(env, SPR_620_PMR1, "PMR1",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, &spr_write_generic,
2196 0x00000000);
578bb252 2197 /* XXX : not implemented */
a750fc0b
JM		 2198 spr_register(env, SPR_620_PMR2, "PMR2",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, &spr_write_generic,
2201 0x00000000);
578bb252 2202 /* XXX : not implemented */
a750fc0b
JM		 2203 spr_register(env, SPR_620_PMR3, "PMR3",
2204 SPR_NOACCESS, SPR_NOACCESS,
2205 &spr_read_generic, &spr_write_generic,
2206 0x00000000);
578bb252 2207 /* XXX : not implemented */
a750fc0b
JM		 2208 spr_register(env, SPR_620_PMR4, "PMR4",
2209 SPR_NOACCESS, SPR_NOACCESS,
2210 &spr_read_generic, &spr_write_generic,
2211 0x00000000);
578bb252 2212 /* XXX : not implemented */
a750fc0b
JM		 2213 spr_register(env, SPR_620_PMR5, "PMR5",
2214 SPR_NOACCESS, SPR_NOACCESS,
2215 &spr_read_generic, &spr_write_generic,
2216 0x00000000);
578bb252 2217 /* XXX : not implemented */
a750fc0b
JM		 2218 spr_register(env, SPR_620_PMR6, "PMR6",
2219 SPR_NOACCESS, SPR_NOACCESS,
2220 &spr_read_generic, &spr_write_generic,
2221 0x00000000);
578bb252 2222 /* XXX : not implemented */
a750fc0b
JM		 2223 spr_register(env, SPR_620_PMR7, "PMR7",
2224 SPR_NOACCESS, SPR_NOACCESS,
2225 &spr_read_generic, &spr_write_generic,
2226 0x00000000);
578bb252 2227 /* XXX : not implemented */
a750fc0b
JM		 2228 spr_register(env, SPR_620_PMR8, "PMR8",
2229 SPR_NOACCESS, SPR_NOACCESS,
2230 &spr_read_generic, &spr_write_generic,
2231 0x00000000);
578bb252 2232 /* XXX : not implemented */
a750fc0b
JM		 2233 spr_register(env, SPR_620_PMR9, "PMR9",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 &spr_read_generic, &spr_write_generic,
2236 0x00000000);
578bb252 2237 /* XXX : not implemented */
a750fc0b
JM		 2238 spr_register(env, SPR_620_PMRA, "PMR10",
2239 SPR_NOACCESS, SPR_NOACCESS,
2240 &spr_read_generic, &spr_write_generic,
2241 0x00000000);
578bb252 2242 /* XXX : not implemented */
a750fc0b
JM		 2243 spr_register(env, SPR_620_PMRB, "PMR11",
2244 SPR_NOACCESS, SPR_NOACCESS,
2245 &spr_read_generic, &spr_write_generic,
2246 0x00000000);
578bb252 2247 /* XXX : not implemented */
a750fc0b
JM		 2248 spr_register(env, SPR_620_PMRC, "PMR12",
2249 SPR_NOACCESS, SPR_NOACCESS,
2250 &spr_read_generic, &spr_write_generic,
2251 0x00000000);
578bb252 2252 /* XXX : not implemented */
a750fc0b
JM		 2253 spr_register(env, SPR_620_PMRD, "PMR13",
2254 SPR_NOACCESS, SPR_NOACCESS,
2255 &spr_read_generic, &spr_write_generic,
2256 0x00000000);
578bb252 2257 /* XXX : not implemented */
a750fc0b
JM		 2258 spr_register(env, SPR_620_PMRE, "PMR14",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_generic,
2261 0x00000000);
578bb252 2262 /* XXX : not implemented */
a750fc0b
JM		 2263 spr_register(env, SPR_620_PMRF, "PMR15",
2264 SPR_NOACCESS, SPR_NOACCESS,
2265 &spr_read_generic, &spr_write_generic,
2266 0x00000000);
082c6681 2267#endif
578bb252 2268 /* XXX : not implemented */
082c6681 2269 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
a750fc0b
JM		 2270 SPR_NOACCESS, SPR_NOACCESS,
2271 &spr_read_generic, &spr_write_generic,
2272 0x00000000);
578bb252 2273 /* XXX : not implemented */
082c6681
JM		 2274 spr_register(env, SPR_620_L2CR, "L2CR",
2275 SPR_NOACCESS, SPR_NOACCESS,
2276 &spr_read_generic, &spr_write_generic,
2277 0x00000000);
2278 /* XXX : not implemented */
2279 spr_register(env, SPR_620_L2SR, "L2SR",
a750fc0b
JM		 2280 SPR_NOACCESS, SPR_NOACCESS,
2281 &spr_read_generic, &spr_write_generic,
2282 0x00000000);
2283}
a750fc0b 2284#endif /* defined (TARGET_PPC64) */
76a66253 2285
80d11f44 2286static void gen_spr_5xx_8xx (CPUPPCState *env)
e1833e1f 2287{
80d11f44
JM		 2288 /* Exception processing */
2289 spr_register(env, SPR_DSISR, "DSISR",
2290 SPR_NOACCESS, SPR_NOACCESS,
2291 &spr_read_generic, &spr_write_generic,
2292 0x00000000);
2293 spr_register(env, SPR_DAR, "DAR",
2294 SPR_NOACCESS, SPR_NOACCESS,
2295 &spr_read_generic, &spr_write_generic,
2296 0x00000000);
2297 /* Timer */
2298 spr_register(env, SPR_DECR, "DECR",
2299 SPR_NOACCESS, SPR_NOACCESS,
2300 &spr_read_decr, &spr_write_decr,
2301 0x00000000);
2302 /* XXX : not implemented */
2303 spr_register(env, SPR_MPC_EIE, "EIE",
2304 SPR_NOACCESS, SPR_NOACCESS,
2305 &spr_read_generic, &spr_write_generic,
2306 0x00000000);
2307 /* XXX : not implemented */
2308 spr_register(env, SPR_MPC_EID, "EID",
2309 SPR_NOACCESS, SPR_NOACCESS,
2310 &spr_read_generic, &spr_write_generic,
2311 0x00000000);
2312 /* XXX : not implemented */
2313 spr_register(env, SPR_MPC_NRI, "NRI",
2314 SPR_NOACCESS, SPR_NOACCESS,
2315 &spr_read_generic, &spr_write_generic,
2316 0x00000000);
2317 /* XXX : not implemented */
2318 spr_register(env, SPR_MPC_CMPA, "CMPA",
2319 SPR_NOACCESS, SPR_NOACCESS,
2320 &spr_read_generic, &spr_write_generic,
2321 0x00000000);
2322 /* XXX : not implemented */
2323 spr_register(env, SPR_MPC_CMPB, "CMPB",
2324 SPR_NOACCESS, SPR_NOACCESS,
2325 &spr_read_generic, &spr_write_generic,
2326 0x00000000);
2327 /* XXX : not implemented */
2328 spr_register(env, SPR_MPC_CMPC, "CMPC",
2329 SPR_NOACCESS, SPR_NOACCESS,
2330 &spr_read_generic, &spr_write_generic,
2331 0x00000000);
2332 /* XXX : not implemented */
2333 spr_register(env, SPR_MPC_CMPD, "CMPD",
2334 SPR_NOACCESS, SPR_NOACCESS,
2335 &spr_read_generic, &spr_write_generic,
2336 0x00000000);
2337 /* XXX : not implemented */
2338 spr_register(env, SPR_MPC_ECR, "ECR",
2339 SPR_NOACCESS, SPR_NOACCESS,
2340 &spr_read_generic, &spr_write_generic,
2341 0x00000000);
2342 /* XXX : not implemented */
2343 spr_register(env, SPR_MPC_DER, "DER",
2344 SPR_NOACCESS, SPR_NOACCESS,
2345 &spr_read_generic, &spr_write_generic,
2346 0x00000000);
2347 /* XXX : not implemented */
2348 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2349 SPR_NOACCESS, SPR_NOACCESS,
2350 &spr_read_generic, &spr_write_generic,
2351 0x00000000);
2352 /* XXX : not implemented */
2353 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2354 SPR_NOACCESS, SPR_NOACCESS,
2355 &spr_read_generic, &spr_write_generic,
2356 0x00000000);
2357 /* XXX : not implemented */
2358 spr_register(env, SPR_MPC_CMPE, "CMPE",
2359 SPR_NOACCESS, SPR_NOACCESS,
2360 &spr_read_generic, &spr_write_generic,
2361 0x00000000);
2362 /* XXX : not implemented */
2363 spr_register(env, SPR_MPC_CMPF, "CMPF",
2364 SPR_NOACCESS, SPR_NOACCESS,
2365 &spr_read_generic, &spr_write_generic,
2366 0x00000000);
2367 /* XXX : not implemented */
2368 spr_register(env, SPR_MPC_CMPG, "CMPG",
2369 SPR_NOACCESS, SPR_NOACCESS,
2370 &spr_read_generic, &spr_write_generic,
2371 0x00000000);
2372 /* XXX : not implemented */
2373 spr_register(env, SPR_MPC_CMPH, "CMPH",
2374 SPR_NOACCESS, SPR_NOACCESS,
2375 &spr_read_generic, &spr_write_generic,
2376 0x00000000);
2377 /* XXX : not implemented */
2378 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2379 SPR_NOACCESS, SPR_NOACCESS,
2380 &spr_read_generic, &spr_write_generic,
2381 0x00000000);
2382 /* XXX : not implemented */
2383 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2384 SPR_NOACCESS, SPR_NOACCESS,
2385 &spr_read_generic, &spr_write_generic,
2386 0x00000000);
2387 /* XXX : not implemented */
2388 spr_register(env, SPR_MPC_BAR, "BAR",
2389 SPR_NOACCESS, SPR_NOACCESS,
2390 &spr_read_generic, &spr_write_generic,
2391 0x00000000);
2392 /* XXX : not implemented */
2393 spr_register(env, SPR_MPC_DPDR, "DPDR",
2394 SPR_NOACCESS, SPR_NOACCESS,
2395 &spr_read_generic, &spr_write_generic,
2396 0x00000000);
2397 /* XXX : not implemented */
2398 spr_register(env, SPR_MPC_IMMR, "IMMR",
2399 SPR_NOACCESS, SPR_NOACCESS,
2400 &spr_read_generic, &spr_write_generic,
2401 0x00000000);
2402}
2403
2404static void gen_spr_5xx (CPUPPCState *env)
2405{
2406 /* XXX : not implemented */
2407 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2408 SPR_NOACCESS, SPR_NOACCESS,
2409 &spr_read_generic, &spr_write_generic,
2410 0x00000000);
2411 /* XXX : not implemented */
2412 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2413 SPR_NOACCESS, SPR_NOACCESS,
2414 &spr_read_generic, &spr_write_generic,
2415 0x00000000);
2416 /* XXX : not implemented */
2417 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2418 SPR_NOACCESS, SPR_NOACCESS,
2419 &spr_read_generic, &spr_write_generic,
2420 0x00000000);
2421 /* XXX : not implemented */
2422 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2423 SPR_NOACCESS, SPR_NOACCESS,
2424 &spr_read_generic, &spr_write_generic,
2425 0x00000000);
2426 /* XXX : not implemented */
2427 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2428 SPR_NOACCESS, SPR_NOACCESS,
2429 &spr_read_generic, &spr_write_generic,
2430 0x00000000);
2431 /* XXX : not implemented */
2432 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2433 SPR_NOACCESS, SPR_NOACCESS,
2434 &spr_read_generic, &spr_write_generic,
2435 0x00000000);
2436 /* XXX : not implemented */
2437 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2438 SPR_NOACCESS, SPR_NOACCESS,
2439 &spr_read_generic, &spr_write_generic,
2440 0x00000000);
2441 /* XXX : not implemented */
2442 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2443 SPR_NOACCESS, SPR_NOACCESS,
2444 &spr_read_generic, &spr_write_generic,
2445 0x00000000);
2446 /* XXX : not implemented */
2447 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2448 SPR_NOACCESS, SPR_NOACCESS,
2449 &spr_read_generic, &spr_write_generic,
2450 0x00000000);
2451 /* XXX : not implemented */
2452 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2453 SPR_NOACCESS, SPR_NOACCESS,
2454 &spr_read_generic, &spr_write_generic,
2455 0x00000000);
2456 /* XXX : not implemented */
2457 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2458 SPR_NOACCESS, SPR_NOACCESS,
2459 &spr_read_generic, &spr_write_generic,
2460 0x00000000);
2461 /* XXX : not implemented */
2462 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2463 SPR_NOACCESS, SPR_NOACCESS,
2464 &spr_read_generic, &spr_write_generic,
2465 0x00000000);
2466 /* XXX : not implemented */
2467 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2468 SPR_NOACCESS, SPR_NOACCESS,
2469 &spr_read_generic, &spr_write_generic,
2470 0x00000000);
2471 /* XXX : not implemented */
2472 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2473 SPR_NOACCESS, SPR_NOACCESS,
2474 &spr_read_generic, &spr_write_generic,
2475 0x00000000);
2476 /* XXX : not implemented */
2477 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2478 SPR_NOACCESS, SPR_NOACCESS,
2479 &spr_read_generic, &spr_write_generic,
2480 0x00000000);
2481 /* XXX : not implemented */
2482 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2483 SPR_NOACCESS, SPR_NOACCESS,
2484 &spr_read_generic, &spr_write_generic,
2485 0x00000000);
2486 /* XXX : not implemented */
2487 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2488 SPR_NOACCESS, SPR_NOACCESS,
2489 &spr_read_generic, &spr_write_generic,
2490 0x00000000);
2491 /* XXX : not implemented */
2492 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2493 SPR_NOACCESS, SPR_NOACCESS,
2494 &spr_read_generic, &spr_write_generic,
2495 0x00000000);
2496 /* XXX : not implemented */
2497 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2498 SPR_NOACCESS, SPR_NOACCESS,
2499 &spr_read_generic, &spr_write_generic,
2500 0x00000000);
2501 /* XXX : not implemented */
2502 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2503 SPR_NOACCESS, SPR_NOACCESS,
2504 &spr_read_generic, &spr_write_generic,
2505 0x00000000);
2506 /* XXX : not implemented */
2507 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2508 SPR_NOACCESS, SPR_NOACCESS,
2509 &spr_read_generic, &spr_write_generic,
2510 0x00000000);
2511}
2512
2513static void gen_spr_8xx (CPUPPCState *env)
2514{
2515 /* XXX : not implemented */
2516 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2517 SPR_NOACCESS, SPR_NOACCESS,
2518 &spr_read_generic, &spr_write_generic,
2519 0x00000000);
2520 /* XXX : not implemented */
2521 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2522 SPR_NOACCESS, SPR_NOACCESS,
2523 &spr_read_generic, &spr_write_generic,
2524 0x00000000);
2525 /* XXX : not implemented */
2526 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2527 SPR_NOACCESS, SPR_NOACCESS,
2528 &spr_read_generic, &spr_write_generic,
2529 0x00000000);
2530 /* XXX : not implemented */
2531 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2532 SPR_NOACCESS, SPR_NOACCESS,
2533 &spr_read_generic, &spr_write_generic,
2534 0x00000000);
2535 /* XXX : not implemented */
2536 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2537 SPR_NOACCESS, SPR_NOACCESS,
2538 &spr_read_generic, &spr_write_generic,
2539 0x00000000);
2540 /* XXX : not implemented */
2541 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2542 SPR_NOACCESS, SPR_NOACCESS,
2543 &spr_read_generic, &spr_write_generic,
2544 0x00000000);
2545 /* XXX : not implemented */
2546 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2547 SPR_NOACCESS, SPR_NOACCESS,
2548 &spr_read_generic, &spr_write_generic,
2549 0x00000000);
2550 /* XXX : not implemented */
2551 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2552 SPR_NOACCESS, SPR_NOACCESS,
2553 &spr_read_generic, &spr_write_generic,
2554 0x00000000);
2555 /* XXX : not implemented */
2556 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2557 SPR_NOACCESS, SPR_NOACCESS,
2558 &spr_read_generic, &spr_write_generic,
2559 0x00000000);
2560 /* XXX : not implemented */
2561 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2562 SPR_NOACCESS, SPR_NOACCESS,
2563 &spr_read_generic, &spr_write_generic,
2564 0x00000000);
2565 /* XXX : not implemented */
2566 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2567 SPR_NOACCESS, SPR_NOACCESS,
2568 &spr_read_generic, &spr_write_generic,
2569 0x00000000);
2570 /* XXX : not implemented */
2571 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2572 SPR_NOACCESS, SPR_NOACCESS,
2573 &spr_read_generic, &spr_write_generic,
2574 0x00000000);
2575 /* XXX : not implemented */
2576 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2577 SPR_NOACCESS, SPR_NOACCESS,
2578 &spr_read_generic, &spr_write_generic,
2579 0x00000000);
2580 /* XXX : not implemented */
2581 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2582 SPR_NOACCESS, SPR_NOACCESS,
2583 &spr_read_generic, &spr_write_generic,
2584 0x00000000);
2585 /* XXX : not implemented */
2586 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2587 SPR_NOACCESS, SPR_NOACCESS,
2588 &spr_read_generic, &spr_write_generic,
2589 0x00000000);
2590 /* XXX : not implemented */
2591 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2592 SPR_NOACCESS, SPR_NOACCESS,
2593 &spr_read_generic, &spr_write_generic,
2594 0x00000000);
2595 /* XXX : not implemented */
2596 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2597 SPR_NOACCESS, SPR_NOACCESS,
2598 &spr_read_generic, &spr_write_generic,
2599 0x00000000);
2600 /* XXX : not implemented */
2601 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2602 SPR_NOACCESS, SPR_NOACCESS,
2603 &spr_read_generic, &spr_write_generic,
2604 0x00000000);
2605 /* XXX : not implemented */
2606 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2607 SPR_NOACCESS, SPR_NOACCESS,
2608 &spr_read_generic, &spr_write_generic,
2609 0x00000000);
2610 /* XXX : not implemented */
2611 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2612 SPR_NOACCESS, SPR_NOACCESS,
2613 &spr_read_generic, &spr_write_generic,
2614 0x00000000);
2615 /* XXX : not implemented */
2616 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2617 SPR_NOACCESS, SPR_NOACCESS,
2618 &spr_read_generic, &spr_write_generic,
2619 0x00000000);
2620 /* XXX : not implemented */
2621 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2622 SPR_NOACCESS, SPR_NOACCESS,
2623 &spr_read_generic, &spr_write_generic,
2624 0x00000000);
2625 /* XXX : not implemented */
2626 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2627 SPR_NOACCESS, SPR_NOACCESS,
2628 &spr_read_generic, &spr_write_generic,
2629 0x00000000);
2630 /* XXX : not implemented */
2631 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2632 SPR_NOACCESS, SPR_NOACCESS,
2633 &spr_read_generic, &spr_write_generic,
2634 0x00000000);
2635 /* XXX : not implemented */
2636 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2637 SPR_NOACCESS, SPR_NOACCESS,
2638 &spr_read_generic, &spr_write_generic,
2639 0x00000000);
2640}
2641
2642// XXX: TODO
2643/*
2644 * AMR => SPR 29 (Power 2.04)
2645 * CTRL => SPR 136 (Power 2.04)
2646 * CTRL => SPR 152 (Power 2.04)
2647 * SCOMC => SPR 276 (64 bits ?)
2648 * SCOMD => SPR 277 (64 bits ?)
2649 * TBU40 => SPR 286 (Power 2.04 hypv)
2650 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2651 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2652 * HDSISR => SPR 306 (Power 2.04 hypv)
2653 * HDAR => SPR 307 (Power 2.04 hypv)
2654 * PURR => SPR 309 (Power 2.04 hypv)
2655 * HDEC => SPR 310 (Power 2.04 hypv)
2656 * HIOR => SPR 311 (hypv)
2657 * RMOR => SPR 312 (970)
2658 * HRMOR => SPR 313 (Power 2.04 hypv)
2659 * HSRR0 => SPR 314 (Power 2.04 hypv)
2660 * HSRR1 => SPR 315 (Power 2.04 hypv)
2661 * LPCR => SPR 316 (970)
2662 * LPIDR => SPR 317 (970)
80d11f44
JM		 2663 * EPR => SPR 702 (Power 2.04 emb)
2664 * perf => 768-783 (Power 2.04)
2665 * perf => 784-799 (Power 2.04)
2666 * PPR => SPR 896 (Power 2.04)
2667 * EPLC => SPR 947 (Power 2.04 emb)
2668 * EPSC => SPR 948 (Power 2.04 emb)
2669 * DABRX => 1015 (Power 2.04 hypv)
2670 * FPECR => SPR 1022 (?)
2671 * ... and more (thermal management, performance counters, ...)
2672 */
2673
2674/*****************************************************************************/
2675/* Exception vectors models */
2676static void init_excp_4xx_real (CPUPPCState *env)
2677{
2678#if !defined(CONFIG_USER_ONLY)
2679 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2680 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2681 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2682 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2683 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2684 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2685 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2686 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2687 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2688 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
fc1c67bc 2689 env->hreset_excp_prefix = 0x00000000UL;
80d11f44 2690 env->ivor_mask = 0x0000FFF0UL;
faadf50e 2691 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb
JM		 2692 /* Hardware reset vector */
2693 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2694#endif
2695}
2696
80d11f44
JM		 2697static void init_excp_4xx_softmmu (CPUPPCState *env)
2698{
2699#if !defined(CONFIG_USER_ONLY)
2700 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2701 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2702 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2703 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2704 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2705 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2706 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2707 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2708 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2709 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2710 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2711 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2712 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2713 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
fc1c67bc 2714 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2715 env->ivor_mask = 0x0000FFF0UL;
2716 env->ivpr_mask = 0xFFFF0000UL;
2717 /* Hardware reset vector */
2718 env->hreset_vector = 0xFFFFFFFCUL;
2719#endif
2720}
2721
2722static void init_excp_MPC5xx (CPUPPCState *env)
2723{
2724#if !defined(CONFIG_USER_ONLY)
2725 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2726 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2727 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2728 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2729 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2730 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2731 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2732 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2733 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2734 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2735 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2736 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2737 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2738 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2739 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
fc1c67bc 2740 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2741 env->ivor_mask = 0x0000FFF0UL;
2742 env->ivpr_mask = 0xFFFF0000UL;
2743 /* Hardware reset vector */
2744 env->hreset_vector = 0xFFFFFFFCUL;
2745#endif
2746}
2747
2748static void init_excp_MPC8xx (CPUPPCState *env)
e1833e1f
JM		 2749{
2750#if !defined(CONFIG_USER_ONLY)
2751 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2752 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2753 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2754 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2755 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2756 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2757 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
80d11f44 2758 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
e1833e1f 2759 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2760 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
80d11f44
JM		 2761 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2762 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2763 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2764 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2765 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2766 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2767 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2768 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2769 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2770 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2771 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
fc1c67bc 2772 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2773 env->ivor_mask = 0x0000FFF0UL;
2774 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb 2775 /* Hardware reset vector */
80d11f44 2776 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2777#endif
2778}
2779
80d11f44 2780static void init_excp_G2 (CPUPPCState *env)
e1833e1f
JM		 2781{
2782#if !defined(CONFIG_USER_ONLY)
2783 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2784 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2785 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2786 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2787 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2788 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2789 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2790 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2791 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
80d11f44 2792 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
e1833e1f
JM		 2793 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2794 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2795 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2796 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2797 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2798 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2799 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2800 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2801 /* Hardware reset vector */
2802 env->hreset_vector = 0xFFFFFFFCUL;
2803#endif
2804}
2805
2806static void init_excp_e200 (CPUPPCState *env)
2807{
2808#if !defined(CONFIG_USER_ONLY)
2809 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2810 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2811 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2812 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2813 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2814 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2815 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2816 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2817 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2818 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2819 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2820 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2821 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2822 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2823 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2824 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2825 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2826 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2827 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2828 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
fc1c67bc 2829 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2830 env->ivor_mask = 0x0000FFF7UL;
2831 env->ivpr_mask = 0xFFFF0000UL;
2832 /* Hardware reset vector */
2833 env->hreset_vector = 0xFFFFFFFCUL;
2834#endif
2835}
2836
2837static void init_excp_BookE (CPUPPCState *env)
2838{
2839#if !defined(CONFIG_USER_ONLY)
2840 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2841 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2844 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2845 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2855 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
fc1c67bc 2856 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2857 env->ivor_mask = 0x0000FFE0UL;
2858 env->ivpr_mask = 0xFFFF0000UL;
2859 /* Hardware reset vector */
2860 env->hreset_vector = 0xFFFFFFFCUL;
2861#endif
2862}
2863
2864static void init_excp_601 (CPUPPCState *env)
2865{
2866#if !defined(CONFIG_USER_ONLY)
2867 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2868 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2869 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2870 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2871 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2872 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2873 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2874 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2875 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2876 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2877 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2878 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
fc1c67bc 2879 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2880 /* Hardware reset vector */
80d11f44 2881 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2882#endif
2883}
2884
80d11f44 2885static void init_excp_602 (CPUPPCState *env)
e1833e1f
JM		 2886{
2887#if !defined(CONFIG_USER_ONLY)
082c6681 2888 /* XXX: exception prefix has a special behavior on 602 */
e1833e1f
JM		 2889 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2890 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2891 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2892 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2893 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2894 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2895 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2896 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2897 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2898 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2899 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2900 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2901 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2902 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2903 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2904 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2905 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2906 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
fc1c67bc 2907 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb
JM		 2908 /* Hardware reset vector */
2909 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2910#endif
2911}
2912
80d11f44 2913static void init_excp_603 (CPUPPCState *env)
e1833e1f
JM		 2914{
2915#if !defined(CONFIG_USER_ONLY)
2916 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2917 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2918 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2919 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2920 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2921 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2922 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2923 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2924 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f
JM		 2925 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2926 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2927 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2928 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2929 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2930 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2931 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2932 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2933 /* Hardware reset vector */
2934 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2935#endif
2936}
2937
2938static void init_excp_604 (CPUPPCState *env)
2939{
2940#if !defined(CONFIG_USER_ONLY)
2941 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2942 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2943 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2944 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2945 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2946 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2947 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2948 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2949 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2950 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2951 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2952 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2953 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2954 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2d3eb7bf 2955 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2956 /* Hardware reset vector */
2d3eb7bf 2957 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2958#endif
2959}
2960
578bb252 2961#if defined(TARGET_PPC64)
e1833e1f
JM		 2962static void init_excp_620 (CPUPPCState *env)
2963{
2964#if !defined(CONFIG_USER_ONLY)
2965 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2966 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2967 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2968 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2969 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2970 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2971 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2972 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2973 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2974 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2975 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2976 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2977 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2978 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2979 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2980 /* Hardware reset vector */
faadf50e 2981 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2982#endif
2983}
578bb252 2984#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 2985
2986static void init_excp_7x0 (CPUPPCState *env)
2987{
2988#if !defined(CONFIG_USER_ONLY)
2989 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2990 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2991 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2992 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2993 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2994 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2995 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2996 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2997 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2998 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2999 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3000 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3001 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
bd928eba 3002 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
e1833e1f 3003 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3004 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3005 /* Hardware reset vector */
3006 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3007#endif
3008}
3009
bd928eba 3010static void init_excp_750cl (CPUPPCState *env)
e1833e1f
JM		 3011{
3012#if !defined(CONFIG_USER_ONLY)
3013 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3014 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3015 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3016 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3017 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3018 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3019 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3020 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3021 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3022 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3023 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3024 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3025 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3026 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 3027 env->hreset_excp_prefix = 0x00000000UL;
bd928eba
JM		 3028 /* Hardware reset vector */
3029 env->hreset_vector = 0xFFFFFFFCUL;
3030#endif
3031}
3032
3033static void init_excp_750cx (CPUPPCState *env)
3034{
3035#if !defined(CONFIG_USER_ONLY)
3036 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3037 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3038 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3039 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3040 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3041 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3042 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3043 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3044 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3045 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3046 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3047 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3048 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
e1833e1f 3049 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3050 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3051 /* Hardware reset vector */
3052 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3053#endif
3054}
3055
7a3a6927
JM		 3056/* XXX: Check if this is correct */
3057static void init_excp_7x5 (CPUPPCState *env)
3058{
3059#if !defined(CONFIG_USER_ONLY)
3060 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3061 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3062 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3063 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3064 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3065 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3066 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3067 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3068 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3069 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3070 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
bd928eba 3071 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
7a3a6927
JM		 3072 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3073 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3074 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
7a3a6927
JM		 3075 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3076 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba 3077 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3078 env->hreset_excp_prefix = 0x00000000UL;
7a3a6927
JM		 3079 /* Hardware reset vector */
3080 env->hreset_vector = 0xFFFFFFFCUL;
3081#endif
3082}
3083
e1833e1f
JM		 3084static void init_excp_7400 (CPUPPCState *env)
3085{
3086#if !defined(CONFIG_USER_ONLY)
3087 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3088 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3089 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3090 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3091 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3092 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3093 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3094 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3095 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3096 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3097 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3098 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3099 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3100 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3101 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3102 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3103 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3104 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3105 /* Hardware reset vector */
3106 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3107#endif
3108}
3109
e1833e1f
JM		 3110static void init_excp_7450 (CPUPPCState *env)
3111{
3112#if !defined(CONFIG_USER_ONLY)
3113 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3114 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3115 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3116 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3117 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3118 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3119 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3120 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3121 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3122 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3123 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3124 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3125 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3126 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3127 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3128 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3129 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3130 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3131 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
fc1c67bc 3132 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3133 /* Hardware reset vector */
3134 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3135#endif
3136}
e1833e1f
JM		 3137
3138#if defined (TARGET_PPC64)
3139static void init_excp_970 (CPUPPCState *env)
3140{
3141#if !defined(CONFIG_USER_ONLY)
3142 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3143 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3144 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3145 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3146 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3147 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3148 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3149 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3150 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3151 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3152 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 3153 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
e1833e1f
JM		 3154 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3155 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3156 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3157 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3158 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3159 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3160 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3161 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
fc1c67bc 3162 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
1c27f8fb
JM		 3163 /* Hardware reset vector */
3164 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 3165#endif
3166}
9d52e907
DG		 3167
3168static void init_excp_POWER7 (CPUPPCState *env)
3169{
3170#if !defined(CONFIG_USER_ONLY)
3171 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3172 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3173 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3174 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3175 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3176 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3177 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3178 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3179 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3180 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3181 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3182 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3183 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3184 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3185 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3186 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3187 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3188 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3189 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3190 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3191 env->hreset_excp_prefix = 0;
3192 /* Hardware reset vector */
3193 env->hreset_vector = 0x0000000000000100ULL;
3194#endif
3195}
e1833e1f
JM		 3196#endif
3197
2f462816
JM		 3198/*****************************************************************************/
3199/* Power management enable checks */
3200static int check_pow_none (CPUPPCState *env)
3201{
3202 return 0;
3203}
3204
3205static int check_pow_nocheck (CPUPPCState *env)
3206{
3207 return 1;
3208}
3209
3210static int check_pow_hid0 (CPUPPCState *env)
3211{
3212 if (env->spr[SPR_HID0] & 0x00E00000)
3213 return 1;
3214
3215 return 0;
3216}
3217
4e777442
JM		 3218static int check_pow_hid0_74xx (CPUPPCState *env)
3219{
3220 if (env->spr[SPR_HID0] & 0x00600000)
3221 return 1;
3222
3223 return 0;
3224}
3225
a750fc0b
JM		 3226/*****************************************************************************/
3227/* PowerPC implementations definitions */
76a66253 3228
a750fc0b 3229/* PowerPC 401 */
082c6681
JM		 3230#define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3231 PPC_WRTEE | PPC_DCR | \
3232 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3233 PPC_CACHE_DCBZ | \
a750fc0b 3234 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3235 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3236#define POWERPC_INSNS2_401 (PPC_NONE)
a750fc0b 3237#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
b4095fed 3238#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
a750fc0b
JM		 3239#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3240#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
237c0af0 3241#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
4018bae9
JM		 3242#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3243 POWERPC_FLAG_BUS_CLK)
2f462816 3244#define check_pow_401 check_pow_nocheck
76a66253 3245
a750fc0b
JM		 3246static void init_proc_401 (CPUPPCState *env)
3247{
3248 gen_spr_40x(env);
3249 gen_spr_401_403(env);
3250 gen_spr_401(env);
e1833e1f 3251 init_excp_4xx_real(env);
d63001d1
JM		 3252 env->dcache_line_size = 32;
3253 env->icache_line_size = 32;
4e290a0b
JM		 3254 /* Allocate hardware IRQ controller */
3255 ppc40x_irq_init(env);
a750fc0b 3256}
76a66253 3257
a750fc0b 3258/* PowerPC 401x2 */
082c6681
JM		 3259#define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3260 PPC_DCR | PPC_WRTEE | \
3261 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3262 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3263 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3264 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3265 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3266#define POWERPC_INSNS2_401x2 (PPC_NONE)
a750fc0b
JM		 3267#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3268#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3269#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3270#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
237c0af0 3271#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
4018bae9
JM		 3272#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3273 POWERPC_FLAG_BUS_CLK)
2f462816 3274#define check_pow_401x2 check_pow_nocheck
a750fc0b
JM		 3275
3276static void init_proc_401x2 (CPUPPCState *env)
3277{
3278 gen_spr_40x(env);
3279 gen_spr_401_403(env);
3280 gen_spr_401x2(env);
3281 gen_spr_compress(env);
a750fc0b 3282 /* Memory management */
f2e63a42 3283#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3284 env->nb_tlb = 64;
3285 env->nb_ways = 1;
3286 env->id_tlbs = 0;
1c53accc 3287 env->tlb_type = TLB_EMB;
f2e63a42 3288#endif
e1833e1f 3289 init_excp_4xx_softmmu(env);
d63001d1
JM		 3290 env->dcache_line_size = 32;
3291 env->icache_line_size = 32;
4e290a0b
JM		 3292 /* Allocate hardware IRQ controller */
3293 ppc40x_irq_init(env);
76a66253
JM		 3294}
3295
a750fc0b 3296/* PowerPC 401x3 */
082c6681
JM		 3297#define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3298 PPC_DCR | PPC_WRTEE | \
3299 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3300 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3301 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3302 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3303 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3304#define POWERPC_INSNS2_401x3 (PPC_NONE)
a750fc0b
JM		 3305#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3306#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3307#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3308#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
237c0af0 3309#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
4018bae9
JM		 3310#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3311 POWERPC_FLAG_BUS_CLK)
2f462816 3312#define check_pow_401x3 check_pow_nocheck
a750fc0b 3313
578bb252 3314__attribute__ (( unused ))
e1833e1f 3315static void init_proc_401x3 (CPUPPCState *env)
76a66253 3316{
4e290a0b
JM		 3317 gen_spr_40x(env);
3318 gen_spr_401_403(env);
3319 gen_spr_401(env);
3320 gen_spr_401x2(env);
3321 gen_spr_compress(env);
e1833e1f 3322 init_excp_4xx_softmmu(env);
d63001d1
JM		 3323 env->dcache_line_size = 32;
3324 env->icache_line_size = 32;
4e290a0b
JM		 3325 /* Allocate hardware IRQ controller */
3326 ppc40x_irq_init(env);
3fc6c082 3327}
a750fc0b
JM		 3328
3329/* IOP480 */
082c6681
JM		 3330#define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3331 PPC_DCR | PPC_WRTEE | \
3332 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3333 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3334 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3335 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3336 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3337#define POWERPC_INSNS2_IOP480 (PPC_NONE)
a750fc0b
JM		 3338#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3339#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3340#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3341#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
237c0af0 3342#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
4018bae9
JM		 3343#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3344 POWERPC_FLAG_BUS_CLK)
2f462816 3345#define check_pow_IOP480 check_pow_nocheck
a750fc0b
JM		 3346
3347static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 3348{
a750fc0b
JM		 3349 gen_spr_40x(env);
3350 gen_spr_401_403(env);
3351 gen_spr_401x2(env);
3352 gen_spr_compress(env);
a750fc0b 3353 /* Memory management */
f2e63a42 3354#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3355 env->nb_tlb = 64;
3356 env->nb_ways = 1;
3357 env->id_tlbs = 0;
1c53accc 3358 env->tlb_type = TLB_EMB;
f2e63a42 3359#endif
e1833e1f 3360 init_excp_4xx_softmmu(env);
d63001d1
JM		 3361 env->dcache_line_size = 32;
3362 env->icache_line_size = 32;
4e290a0b
JM		 3363 /* Allocate hardware IRQ controller */
3364 ppc40x_irq_init(env);
3fc6c082
FB		 3365}
3366
a750fc0b 3367/* PowerPC 403 */
082c6681
JM		 3368#define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3369 PPC_DCR | PPC_WRTEE | \
3370 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3371 PPC_CACHE_DCBZ | \
a750fc0b 3372 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3373 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3374#define POWERPC_INSNS2_403 (PPC_NONE)
a750fc0b 3375#define POWERPC_MSRM_403 (0x000000000007D00DULL)
b4095fed 3376#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
a750fc0b
JM		 3377#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3378#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
237c0af0 3379#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
4018bae9
JM		 3380#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3381 POWERPC_FLAG_BUS_CLK)
2f462816 3382#define check_pow_403 check_pow_nocheck
a750fc0b
JM		 3383
3384static void init_proc_403 (CPUPPCState *env)
3fc6c082 3385{
a750fc0b
JM		 3386 gen_spr_40x(env);
3387 gen_spr_401_403(env);
3388 gen_spr_403(env);
3389 gen_spr_403_real(env);
e1833e1f 3390 init_excp_4xx_real(env);
d63001d1
JM		 3391 env->dcache_line_size = 32;
3392 env->icache_line_size = 32;
4e290a0b
JM		 3393 /* Allocate hardware IRQ controller */
3394 ppc40x_irq_init(env);
3fc6c082
FB		 3395}
3396
a750fc0b 3397/* PowerPC 403 GCX */
082c6681
JM		 3398#define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3399 PPC_DCR | PPC_WRTEE | \
3400 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3401 PPC_CACHE_DCBZ | \
a750fc0b
JM		 3402 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3403 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3404 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3405#define POWERPC_INSNS2_403GCX (PPC_NONE)
a750fc0b
JM		 3406#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3407#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3408#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3409#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
237c0af0 3410#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
4018bae9
JM		 3411#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3412 POWERPC_FLAG_BUS_CLK)
2f462816 3413#define check_pow_403GCX check_pow_nocheck
a750fc0b
JM		 3414
3415static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 3416{
a750fc0b
JM		 3417 gen_spr_40x(env);
3418 gen_spr_401_403(env);
3419 gen_spr_403(env);
3420 gen_spr_403_real(env);
3421 gen_spr_403_mmu(env);
3422 /* Bus access control */
035feb88 3423 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 3424 spr_register(env, SPR_40x_SGR, "SGR",
3425 SPR_NOACCESS, SPR_NOACCESS,
3426 &spr_read_generic, &spr_write_generic,
3427 0xFFFFFFFF);
035feb88 3428 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 3429 spr_register(env, SPR_40x_DCWR, "DCWR",
3430 SPR_NOACCESS, SPR_NOACCESS,
3431 &spr_read_generic, &spr_write_generic,
3432 0x00000000);
3433 /* Memory management */
f2e63a42 3434#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3435 env->nb_tlb = 64;
3436 env->nb_ways = 1;
3437 env->id_tlbs = 0;
1c53accc 3438 env->tlb_type = TLB_EMB;
f2e63a42 3439#endif
80d11f44
JM		 3440 init_excp_4xx_softmmu(env);
3441 env->dcache_line_size = 32;
3442 env->icache_line_size = 32;
3443 /* Allocate hardware IRQ controller */
3444 ppc40x_irq_init(env);
3445}
3446
3447/* PowerPC 405 */
082c6681
JM		 3448#define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3449 PPC_DCR | PPC_WRTEE | \
3450 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3451 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3452 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
80d11f44 3453 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3454 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
a5858d7a 3455#define POWERPC_INSNS2_405 (PPC_NONE)
80d11f44
JM		 3456#define POWERPC_MSRM_405 (0x000000000006E630ULL)
3457#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3458#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3459#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3460#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3461#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3462 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3463#define check_pow_405 check_pow_nocheck
3464
3465static void init_proc_405 (CPUPPCState *env)
3466{
3467 /* Time base */
3468 gen_tbl(env);
3469 gen_spr_40x(env);
3470 gen_spr_405(env);
3471 /* Bus access control */
3472 /* not emulated, as Qemu never does speculative access */
3473 spr_register(env, SPR_40x_SGR, "SGR",
3474 SPR_NOACCESS, SPR_NOACCESS,
3475 &spr_read_generic, &spr_write_generic,
3476 0xFFFFFFFF);
3477 /* not emulated, as Qemu do not emulate caches */
3478 spr_register(env, SPR_40x_DCWR, "DCWR",
3479 SPR_NOACCESS, SPR_NOACCESS,
3480 &spr_read_generic, &spr_write_generic,
3481 0x00000000);
3482 /* Memory management */
3483#if !defined(CONFIG_USER_ONLY)
3484 env->nb_tlb = 64;
3485 env->nb_ways = 1;
3486 env->id_tlbs = 0;
1c53accc 3487 env->tlb_type = TLB_EMB;
80d11f44
JM		 3488#endif
3489 init_excp_4xx_softmmu(env);
3490 env->dcache_line_size = 32;
3491 env->icache_line_size = 32;
3492 /* Allocate hardware IRQ controller */
3493 ppc40x_irq_init(env);
3494}
3495
3496/* PowerPC 440 EP */
082c6681
JM		 3497#define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3498 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3499 PPC_CACHE | PPC_CACHE_ICBI | \
3500 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3501 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44 3502 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3503 PPC_440_SPEC)
a5858d7a 3504#define POWERPC_INSNS2_440EP (PPC_NONE)
80d11f44
JM		 3505#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3506#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3507#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3508#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3509#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3510#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3511 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3512#define check_pow_440EP check_pow_nocheck
3513
3514__attribute__ (( unused ))
3515static void init_proc_440EP (CPUPPCState *env)
3516{
3517 /* Time base */
3518 gen_tbl(env);
3519 gen_spr_BookE(env, 0x000000000000FFFFULL);
3520 gen_spr_440(env);
3521 gen_spr_usprgh(env);
3522 /* Processor identification */
3523 spr_register(env, SPR_BOOKE_PIR, "PIR",
3524 SPR_NOACCESS, SPR_NOACCESS,
3525 &spr_read_generic, &spr_write_pir,
3526 0x00000000);
3527 /* XXX : not implemented */
3528 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3529 SPR_NOACCESS, SPR_NOACCESS,
3530 &spr_read_generic, &spr_write_generic,
3531 0x00000000);
3532 /* XXX : not implemented */
3533 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3534 SPR_NOACCESS, SPR_NOACCESS,
3535 &spr_read_generic, &spr_write_generic,
3536 0x00000000);
3537 /* XXX : not implemented */
3538 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3539 SPR_NOACCESS, SPR_NOACCESS,
3540 &spr_read_generic, &spr_write_generic,
3541 0x00000000);
3542 /* XXX : not implemented */
3543 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3544 SPR_NOACCESS, SPR_NOACCESS,
3545 &spr_read_generic, &spr_write_generic,
3546 0x00000000);
3547 /* XXX : not implemented */
3548 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3549 SPR_NOACCESS, SPR_NOACCESS,
3550 &spr_read_generic, &spr_write_generic,
3551 0x00000000);
3552 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3553 SPR_NOACCESS, SPR_NOACCESS,
3554 &spr_read_generic, &spr_write_generic,
3555 0x00000000);
3556 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3557 SPR_NOACCESS, SPR_NOACCESS,
3558 &spr_read_generic, &spr_write_generic,
3559 0x00000000);
3560 /* XXX : not implemented */
3561 spr_register(env, SPR_440_CCR1, "CCR1",
3562 SPR_NOACCESS, SPR_NOACCESS,
3563 &spr_read_generic, &spr_write_generic,
3564 0x00000000);
3565 /* Memory management */
3566#if !defined(CONFIG_USER_ONLY)
3567 env->nb_tlb = 64;
3568 env->nb_ways = 1;
3569 env->id_tlbs = 0;
1c53accc 3570 env->tlb_type = TLB_EMB;
80d11f44
JM		 3571#endif
3572 init_excp_BookE(env);
3573 env->dcache_line_size = 32;
3574 env->icache_line_size = 32;
3575 /* XXX: TODO: allocate internal IRQ controller */
3576}
3577
3578/* PowerPC 440 GP */
082c6681
JM		 3579#define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3580 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3581 PPC_CACHE | PPC_CACHE_ICBI | \
3582 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3583 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
082c6681
JM		 3584 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3585 PPC_440_SPEC)
a5858d7a 3586#define POWERPC_INSNS2_440GP (PPC_NONE)
80d11f44
JM		 3587#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3588#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3589#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3590#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3591#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3592#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3593 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3594#define check_pow_440GP check_pow_nocheck
3595
3596__attribute__ (( unused ))
3597static void init_proc_440GP (CPUPPCState *env)
3598{
3599 /* Time base */
3600 gen_tbl(env);
3601 gen_spr_BookE(env, 0x000000000000FFFFULL);
3602 gen_spr_440(env);
3603 gen_spr_usprgh(env);
3604 /* Processor identification */
3605 spr_register(env, SPR_BOOKE_PIR, "PIR",
3606 SPR_NOACCESS, SPR_NOACCESS,
3607 &spr_read_generic, &spr_write_pir,
3608 0x00000000);
3609 /* XXX : not implemented */
3610 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3611 SPR_NOACCESS, SPR_NOACCESS,
3612 &spr_read_generic, &spr_write_generic,
3613 0x00000000);
3614 /* XXX : not implemented */
3615 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3616 SPR_NOACCESS, SPR_NOACCESS,
3617 &spr_read_generic, &spr_write_generic,
3618 0x00000000);
3619 /* XXX : not implemented */
3620 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3621 SPR_NOACCESS, SPR_NOACCESS,
3622 &spr_read_generic, &spr_write_generic,
3623 0x00000000);
3624 /* XXX : not implemented */
3625 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3626 SPR_NOACCESS, SPR_NOACCESS,
3627 &spr_read_generic, &spr_write_generic,
3628 0x00000000);
3629 /* Memory management */
3630#if !defined(CONFIG_USER_ONLY)
3631 env->nb_tlb = 64;
3632 env->nb_ways = 1;
3633 env->id_tlbs = 0;
1c53accc 3634 env->tlb_type = TLB_EMB;
80d11f44
JM		 3635#endif
3636 init_excp_BookE(env);
3637 env->dcache_line_size = 32;
3638 env->icache_line_size = 32;
3639 /* XXX: TODO: allocate internal IRQ controller */
3640}
3641
3642/* PowerPC 440x4 */
082c6681
JM		 3643#define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3644 PPC_DCR | PPC_WRTEE | \
3645 PPC_CACHE | PPC_CACHE_ICBI | \
3646 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3647 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44
JM		 3648 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3649 PPC_440_SPEC)
a5858d7a 3650#define POWERPC_INSNS2_440x4 (PPC_NONE)
80d11f44
JM		 3651#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3652#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3653#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3654#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3655#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3656#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3657 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3658#define check_pow_440x4 check_pow_nocheck
3659
3660__attribute__ (( unused ))
3661static void init_proc_440x4 (CPUPPCState *env)
3662{
3663 /* Time base */
3664 gen_tbl(env);
3665 gen_spr_BookE(env, 0x000000000000FFFFULL);
3666 gen_spr_440(env);
3667 gen_spr_usprgh(env);
3668 /* Processor identification */
3669 spr_register(env, SPR_BOOKE_PIR, "PIR",
3670 SPR_NOACCESS, SPR_NOACCESS,
3671 &spr_read_generic, &spr_write_pir,
3672 0x00000000);
3673 /* XXX : not implemented */
3674 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3675 SPR_NOACCESS, SPR_NOACCESS,
3676 &spr_read_generic, &spr_write_generic,
3677 0x00000000);
3678 /* XXX : not implemented */
3679 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3680 SPR_NOACCESS, SPR_NOACCESS,
3681 &spr_read_generic, &spr_write_generic,
3682 0x00000000);
3683 /* XXX : not implemented */
3684 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3685 SPR_NOACCESS, SPR_NOACCESS,
3686 &spr_read_generic, &spr_write_generic,
3687 0x00000000);
3688 /* XXX : not implemented */
3689 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3690 SPR_NOACCESS, SPR_NOACCESS,
3691 &spr_read_generic, &spr_write_generic,
3692 0x00000000);
3693 /* Memory management */
3694#if !defined(CONFIG_USER_ONLY)
3695 env->nb_tlb = 64;
3696 env->nb_ways = 1;
3697 env->id_tlbs = 0;
1c53accc 3698 env->tlb_type = TLB_EMB;
80d11f44
JM		 3699#endif
3700 init_excp_BookE(env);
d63001d1
JM		 3701 env->dcache_line_size = 32;
3702 env->icache_line_size = 32;
80d11f44 3703 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3704}
3705
80d11f44 3706/* PowerPC 440x5 */
082c6681
JM		 3707#define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3708 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3709 PPC_CACHE | PPC_CACHE_ICBI | \
3710 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3711 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44 3712 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3713 PPC_440_SPEC)
a5858d7a 3714#define POWERPC_INSNS2_440x5 (PPC_NONE)
80d11f44
JM		 3715#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3716#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3717#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3718#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3719#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3720#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3721 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3722#define check_pow_440x5 check_pow_nocheck
a750fc0b 3723
80d11f44 3724static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 3725{
a750fc0b
JM		 3726 /* Time base */
3727 gen_tbl(env);
80d11f44
JM		 3728 gen_spr_BookE(env, 0x000000000000FFFFULL);
3729 gen_spr_440(env);
3730 gen_spr_usprgh(env);
3731 /* Processor identification */
3732 spr_register(env, SPR_BOOKE_PIR, "PIR",
3733 SPR_NOACCESS, SPR_NOACCESS,
3734 &spr_read_generic, &spr_write_pir,
3735 0x00000000);
3736 /* XXX : not implemented */
3737 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
a750fc0b
JM		 3738 SPR_NOACCESS, SPR_NOACCESS,
3739 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3740 0x00000000);
3741 /* XXX : not implemented */
3742 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3743 SPR_NOACCESS, SPR_NOACCESS,
3744 &spr_read_generic, &spr_write_generic,
3745 0x00000000);
3746 /* XXX : not implemented */
3747 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3748 SPR_NOACCESS, SPR_NOACCESS,
3749 &spr_read_generic, &spr_write_generic,
3750 0x00000000);
3751 /* XXX : not implemented */
3752 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3753 SPR_NOACCESS, SPR_NOACCESS,
3754 &spr_read_generic, &spr_write_generic,
3755 0x00000000);
3756 /* XXX : not implemented */
3757 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3758 SPR_NOACCESS, SPR_NOACCESS,
3759 &spr_read_generic, &spr_write_generic,
3760 0x00000000);
3761 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3762 SPR_NOACCESS, SPR_NOACCESS,
3763 &spr_read_generic, &spr_write_generic,
3764 0x00000000);
3765 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3766 SPR_NOACCESS, SPR_NOACCESS,
3767 &spr_read_generic, &spr_write_generic,
3768 0x00000000);
3769 /* XXX : not implemented */
3770 spr_register(env, SPR_440_CCR1, "CCR1",
a750fc0b
JM		 3771 SPR_NOACCESS, SPR_NOACCESS,
3772 &spr_read_generic, &spr_write_generic,
3773 0x00000000);
3774 /* Memory management */
f2e63a42 3775#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3776 env->nb_tlb = 64;
3777 env->nb_ways = 1;
3778 env->id_tlbs = 0;
1c53accc 3779 env->tlb_type = TLB_EMB;
f2e63a42 3780#endif
80d11f44 3781 init_excp_BookE(env);
d63001d1
JM		 3782 env->dcache_line_size = 32;
3783 env->icache_line_size = 32;
95070372 3784 ppc40x_irq_init(env);
3fc6c082
FB		 3785}
3786
80d11f44 3787/* PowerPC 460 (guessed) */
082c6681 3788#define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
80d11f44 3789 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
f4078236 3790 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
082c6681
JM		 3791 PPC_CACHE | PPC_CACHE_ICBI | \
3792 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3793 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3794 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3795 PPC_440_SPEC)
a5858d7a 3796#define POWERPC_INSNS2_460 (PPC_NONE)
80d11f44
JM		 3797#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3798#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3799#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3800#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3801#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3802#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3803 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3804#define check_pow_460 check_pow_nocheck
a750fc0b 3805
80d11f44
JM		 3806__attribute__ (( unused ))
3807static void init_proc_460 (CPUPPCState *env)
3fc6c082 3808{
a750fc0b
JM		 3809 /* Time base */
3810 gen_tbl(env);
80d11f44 3811 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3812 gen_spr_440(env);
80d11f44
JM		 3813 gen_spr_usprgh(env);
3814 /* Processor identification */
3815 spr_register(env, SPR_BOOKE_PIR, "PIR",
3816 SPR_NOACCESS, SPR_NOACCESS,
3817 &spr_read_generic, &spr_write_pir,
3818 0x00000000);
3819 /* XXX : not implemented */
3820 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3821 SPR_NOACCESS, SPR_NOACCESS,
3822 &spr_read_generic, &spr_write_generic,
3823 0x00000000);
3824 /* XXX : not implemented */
3825 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3826 SPR_NOACCESS, SPR_NOACCESS,
3827 &spr_read_generic, &spr_write_generic,
3828 0x00000000);
3829 /* XXX : not implemented */
3830 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3831 SPR_NOACCESS, SPR_NOACCESS,
3832 &spr_read_generic, &spr_write_generic,
3833 0x00000000);
3834 /* XXX : not implemented */
3835 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3836 SPR_NOACCESS, SPR_NOACCESS,
3837 &spr_read_generic, &spr_write_generic,
3838 0x00000000);
578bb252 3839 /* XXX : not implemented */
a750fc0b
JM		 3840 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3841 SPR_NOACCESS, SPR_NOACCESS,
3842 &spr_read_generic, &spr_write_generic,
3843 0x00000000);
3844 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3845 SPR_NOACCESS, SPR_NOACCESS,
3846 &spr_read_generic, &spr_write_generic,
3847 0x00000000);
3848 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3849 SPR_NOACCESS, SPR_NOACCESS,
3850 &spr_read_generic, &spr_write_generic,
3851 0x00000000);
578bb252 3852 /* XXX : not implemented */
a750fc0b
JM		 3853 spr_register(env, SPR_440_CCR1, "CCR1",
3854 SPR_NOACCESS, SPR_NOACCESS,
3855 &spr_read_generic, &spr_write_generic,
3856 0x00000000);
80d11f44
JM		 3857 /* XXX : not implemented */
3858 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3859 &spr_read_generic, &spr_write_generic,
3860 &spr_read_generic, &spr_write_generic,
3861 0x00000000);
a750fc0b 3862 /* Memory management */
f2e63a42 3863#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3864 env->nb_tlb = 64;
3865 env->nb_ways = 1;
3866 env->id_tlbs = 0;
1c53accc 3867 env->tlb_type = TLB_EMB;
f2e63a42 3868#endif
e1833e1f 3869 init_excp_BookE(env);
d63001d1
JM		 3870 env->dcache_line_size = 32;
3871 env->icache_line_size = 32;
a750fc0b 3872 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3873}
3874
80d11f44 3875/* PowerPC 460F (guessed) */
082c6681
JM		 3876#define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3877 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3878 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
f4078236 3879 PPC_FLOAT_STFIWX | PPC_MFTB | \
082c6681
JM		 3880 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3881 PPC_WRTEE | PPC_MFAPIDI | \
3882 PPC_CACHE | PPC_CACHE_ICBI | \
3883 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3884 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3885 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3886 PPC_440_SPEC)
a5858d7a 3887#define POWERPC_INSNS2_460F (PPC_NONE)
80d11f44
JM		 3888#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3889#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3890#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3891#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3892#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3893#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3894 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3895#define check_pow_460F check_pow_nocheck
a750fc0b 3896
80d11f44
JM		 3897__attribute__ (( unused ))
3898static void init_proc_460F (CPUPPCState *env)
3fc6c082 3899{
a750fc0b
JM		 3900 /* Time base */
3901 gen_tbl(env);
80d11f44 3902 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3903 gen_spr_440(env);
80d11f44
JM		 3904 gen_spr_usprgh(env);
3905 /* Processor identification */
3906 spr_register(env, SPR_BOOKE_PIR, "PIR",
3907 SPR_NOACCESS, SPR_NOACCESS,
3908 &spr_read_generic, &spr_write_pir,
3909 0x00000000);
3910 /* XXX : not implemented */
3911 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3912 SPR_NOACCESS, SPR_NOACCESS,
3913 &spr_read_generic, &spr_write_generic,
3914 0x00000000);
3915 /* XXX : not implemented */
3916 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3917 SPR_NOACCESS, SPR_NOACCESS,
3918 &spr_read_generic, &spr_write_generic,
3919 0x00000000);
3920 /* XXX : not implemented */
3921 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3922 SPR_NOACCESS, SPR_NOACCESS,
3923 &spr_read_generic, &spr_write_generic,
3924 0x00000000);
3925 /* XXX : not implemented */
3926 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3927 SPR_NOACCESS, SPR_NOACCESS,
3928 &spr_read_generic, &spr_write_generic,
3929 0x00000000);
3930 /* XXX : not implemented */
3931 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3932 SPR_NOACCESS, SPR_NOACCESS,
3933 &spr_read_generic, &spr_write_generic,
3934 0x00000000);
3935 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3936 SPR_NOACCESS, SPR_NOACCESS,
3937 &spr_read_generic, &spr_write_generic,
3938 0x00000000);
3939 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3940 SPR_NOACCESS, SPR_NOACCESS,
3941 &spr_read_generic, &spr_write_generic,
3942 0x00000000);
3943 /* XXX : not implemented */
3944 spr_register(env, SPR_440_CCR1, "CCR1",
3945 SPR_NOACCESS, SPR_NOACCESS,
3946 &spr_read_generic, &spr_write_generic,
3947 0x00000000);
3948 /* XXX : not implemented */
3949 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3950 &spr_read_generic, &spr_write_generic,
3951 &spr_read_generic, &spr_write_generic,
3952 0x00000000);
a750fc0b 3953 /* Memory management */
f2e63a42 3954#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3955 env->nb_tlb = 64;
3956 env->nb_ways = 1;
3957 env->id_tlbs = 0;
1c53accc 3958 env->tlb_type = TLB_EMB;
f2e63a42 3959#endif
e1833e1f 3960 init_excp_BookE(env);
d63001d1
JM		 3961 env->dcache_line_size = 32;
3962 env->icache_line_size = 32;
a750fc0b 3963 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3964}
3965
80d11f44
JM		 3966/* Freescale 5xx cores (aka RCPU) */
3967#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
3968 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3969 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3970 PPC_MFTB)
a5858d7a 3971#define POWERPC_INSNS2_MPC5xx (PPC_NONE)
80d11f44
JM		 3972#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
3973#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
3974#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
3975#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3976#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4018bae9
JM		 3977#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3978 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3979#define check_pow_MPC5xx check_pow_none
3980
3981__attribute__ (( unused ))
3982static void init_proc_MPC5xx (CPUPPCState *env)
3983{
3984 /* Time base */
3985 gen_tbl(env);
3986 gen_spr_5xx_8xx(env);
3987 gen_spr_5xx(env);
3988 init_excp_MPC5xx(env);
3989 env->dcache_line_size = 32;
3990 env->icache_line_size = 32;
3991 /* XXX: TODO: allocate internal IRQ controller */
3992}
3993
3994/* Freescale 8xx cores (aka PowerQUICC) */
3995#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
3996 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3997 PPC_CACHE_ICBI | PPC_MFTB)
a5858d7a 3998#define POWERPC_INSNS2_MPC8xx (PPC_NONE)
80d11f44
JM		 3999#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
4000#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
4001#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
4002#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
4003#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4018bae9
JM		 4004#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4005 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 4006#define check_pow_MPC8xx check_pow_none
4007
4008__attribute__ (( unused ))
4009static void init_proc_MPC8xx (CPUPPCState *env)
4010{
4011 /* Time base */
4012 gen_tbl(env);
4013 gen_spr_5xx_8xx(env);
4014 gen_spr_8xx(env);
4015 init_excp_MPC8xx(env);
4016 env->dcache_line_size = 32;
4017 env->icache_line_size = 32;
4018 /* XXX: TODO: allocate internal IRQ controller */
4019}
4020
4021/* Freescale 82xx cores (aka PowerQUICC-II) */
4022/* PowerPC G2 */
082c6681
JM		 4023#define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4024 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4025 PPC_FLOAT_STFIWX | \
4026 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4027 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4028 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4029 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4030#define POWERPC_INSNS2_G2 (PPC_NONE)
80d11f44
JM		 4031#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
4032#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
4033//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
4034#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
4035#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
4036#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4037 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4038#define check_pow_G2 check_pow_hid0
a750fc0b 4039
80d11f44 4040static void init_proc_G2 (CPUPPCState *env)
3fc6c082 4041{
80d11f44
JM		 4042 gen_spr_ne_601(env);
4043 gen_spr_G2_755(env);
4044 gen_spr_G2(env);
a750fc0b
JM		 4045 /* Time base */
4046 gen_tbl(env);
bd928eba
JM		 4047 /* External access control */
4048 /* XXX : not implemented */
4049 spr_register(env, SPR_EAR, "EAR",
4050 SPR_NOACCESS, SPR_NOACCESS,
4051 &spr_read_generic, &spr_write_generic,
4052 0x00000000);
80d11f44
JM		 4053 /* Hardware implementation register */
4054 /* XXX : not implemented */
4055 spr_register(env, SPR_HID0, "HID0",
4056 SPR_NOACCESS, SPR_NOACCESS,
4057 &spr_read_generic, &spr_write_generic,
4058 0x00000000);
4059 /* XXX : not implemented */
4060 spr_register(env, SPR_HID1, "HID1",
4061 SPR_NOACCESS, SPR_NOACCESS,
4062 &spr_read_generic, &spr_write_generic,
4063 0x00000000);
4064 /* XXX : not implemented */
4065 spr_register(env, SPR_HID2, "HID2",
4066 SPR_NOACCESS, SPR_NOACCESS,
4067 &spr_read_generic, &spr_write_generic,
4068 0x00000000);
a750fc0b 4069 /* Memory management */
80d11f44
JM		 4070 gen_low_BATs(env);
4071 gen_high_BATs(env);
4072 gen_6xx_7xx_soft_tlb(env, 64, 2);
4073 init_excp_G2(env);
d63001d1
JM		 4074 env->dcache_line_size = 32;
4075 env->icache_line_size = 32;
80d11f44
JM		 4076 /* Allocate hardware IRQ controller */
4077 ppc6xx_irq_init(env);
3fc6c082 4078}
a750fc0b 4079
80d11f44 4080/* PowerPC G2LE */
082c6681
JM		 4081#define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4082 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4083 PPC_FLOAT_STFIWX | \
4084 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4085 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4086 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4087 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4088#define POWERPC_INSNS2_G2LE (PPC_NONE)
80d11f44
JM		 4089#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
4090#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
4091#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
4092#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
4093#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
4094#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4095 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4096#define check_pow_G2LE check_pow_hid0
a750fc0b 4097
80d11f44 4098static void init_proc_G2LE (CPUPPCState *env)
3fc6c082 4099{
80d11f44
JM		 4100 gen_spr_ne_601(env);
4101 gen_spr_G2_755(env);
4102 gen_spr_G2(env);
a750fc0b
JM		 4103 /* Time base */
4104 gen_tbl(env);
bd928eba
JM		 4105 /* External access control */
4106 /* XXX : not implemented */
4107 spr_register(env, SPR_EAR, "EAR",
4108 SPR_NOACCESS, SPR_NOACCESS,
4109 &spr_read_generic, &spr_write_generic,
4110 0x00000000);
80d11f44 4111 /* Hardware implementation register */
578bb252 4112 /* XXX : not implemented */
80d11f44 4113 spr_register(env, SPR_HID0, "HID0",
a750fc0b
JM		 4114 SPR_NOACCESS, SPR_NOACCESS,
4115 &spr_read_generic, &spr_write_generic,
4116 0x00000000);
80d11f44
JM		 4117 /* XXX : not implemented */
4118 spr_register(env, SPR_HID1, "HID1",
a750fc0b
JM		 4119 SPR_NOACCESS, SPR_NOACCESS,
4120 &spr_read_generic, &spr_write_generic,
4121 0x00000000);
578bb252 4122 /* XXX : not implemented */
80d11f44 4123 spr_register(env, SPR_HID2, "HID2",
a750fc0b
JM		 4124 SPR_NOACCESS, SPR_NOACCESS,
4125 &spr_read_generic, &spr_write_generic,
4126 0x00000000);
4127 /* Memory management */
80d11f44
JM		 4128 gen_low_BATs(env);
4129 gen_high_BATs(env);
4130 gen_6xx_7xx_soft_tlb(env, 64, 2);
4131 init_excp_G2(env);
d63001d1
JM		 4132 env->dcache_line_size = 32;
4133 env->icache_line_size = 32;
80d11f44
JM		 4134 /* Allocate hardware IRQ controller */
4135 ppc6xx_irq_init(env);
3fc6c082
FB		 4136}
4137
80d11f44
JM		 4138/* e200 core */
4139/* XXX: unimplemented instructions:
4140 * dcblc
4141 * dcbtlst
4142 * dcbtstls
4143 * icblc
4144 * icbtls
4145 * tlbivax
4146 * all SPE multiply-accumulate instructions
4147 */
082c6681 4148#define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
40569b7e 4149 PPC_SPE | PPC_SPE_SINGLE | \
082c6681
JM		 4150 PPC_WRTEE | PPC_RFDI | \
4151 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4152 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
80d11f44 4153 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
082c6681 4154 PPC_BOOKE)
a5858d7a 4155#define POWERPC_INSNS2_e200 (PPC_NONE)
80d11f44 4156#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
01662f3e 4157#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
80d11f44
JM		 4158#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4159#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4160#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4161#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4018bae9
JM		 4162 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4163 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 4164#define check_pow_e200 check_pow_hid0
4165
578bb252 4166__attribute__ (( unused ))
80d11f44 4167static void init_proc_e200 (CPUPPCState *env)
3fc6c082 4168{
e1833e1f
JM		 4169 /* Time base */
4170 gen_tbl(env);
80d11f44 4171 gen_spr_BookE(env, 0x000000070000FFFFULL);
578bb252 4172 /* XXX : not implemented */
80d11f44 4173 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4174 &spr_read_spefscr, &spr_write_spefscr,
4175 &spr_read_spefscr, &spr_write_spefscr,
e1833e1f 4176 0x00000000);
80d11f44 4177 /* Memory management */
01662f3e 4178 gen_spr_BookE206(env, 0x0000005D, NULL);
80d11f44
JM		 4179 /* XXX : not implemented */
4180 spr_register(env, SPR_HID0, "HID0",
e1833e1f
JM		 4181 SPR_NOACCESS, SPR_NOACCESS,
4182 &spr_read_generic, &spr_write_generic,
4183 0x00000000);
80d11f44
JM		 4184 /* XXX : not implemented */
4185 spr_register(env, SPR_HID1, "HID1",
e1833e1f
JM		 4186 SPR_NOACCESS, SPR_NOACCESS,
4187 &spr_read_generic, &spr_write_generic,
4188 0x00000000);
578bb252 4189 /* XXX : not implemented */
80d11f44 4190 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
e1833e1f
JM		 4191 SPR_NOACCESS, SPR_NOACCESS,
4192 &spr_read_generic, &spr_write_generic,
4193 0x00000000);
578bb252 4194 /* XXX : not implemented */
80d11f44
JM		 4195 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4196 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f 4197 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4198 0x00000000);
4199 /* XXX : not implemented */
4200 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4201 SPR_NOACCESS, SPR_NOACCESS,
4202 &spr_read_generic, &spr_write_generic,
4203 0x00000000);
4204 /* XXX : not implemented */
4205 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4206 SPR_NOACCESS, SPR_NOACCESS,
4207 &spr_read_generic, &spr_write_generic,
4208 0x00000000);
4209 /* XXX : not implemented */
4210 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4211 SPR_NOACCESS, SPR_NOACCESS,
4212 &spr_read_generic, &spr_write_generic,
4213 0x00000000);
4214 /* XXX : not implemented */
4215 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4216 SPR_NOACCESS, SPR_NOACCESS,
4217 &spr_read_generic, &spr_write_generic,
4218 0x00000000);
4219 /* XXX : not implemented */
4220 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4221 SPR_NOACCESS, SPR_NOACCESS,
4222 &spr_read_generic, &spr_write_generic,
4223 0x00000000);
4224 /* XXX : not implemented */
4225 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4226 SPR_NOACCESS, SPR_NOACCESS,
4227 &spr_read_generic, &spr_write_generic,
4228 0x00000000);
4229 /* XXX : not implemented */
4230 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4231 SPR_NOACCESS, SPR_NOACCESS,
4232 &spr_read_generic, &spr_write_generic,
4233 0x00000000);
4234 /* XXX : not implemented */
4235 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4236 SPR_NOACCESS, SPR_NOACCESS,
4237 &spr_read_generic, &spr_write_generic,
4238 0x00000000);
4239 /* XXX : not implemented */
4240 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4241 SPR_NOACCESS, SPR_NOACCESS,
4242 &spr_read_generic, &spr_write_generic,
4243 0x00000000);
4244 /* XXX : not implemented */
4245 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4246 SPR_NOACCESS, SPR_NOACCESS,
4247 &spr_read_generic, &spr_write_generic,
4248 0x00000000);
01662f3e
AG		 4249 /* XXX : not implemented */
4250 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4251 SPR_NOACCESS, SPR_NOACCESS,
4252 &spr_read_generic, &spr_write_generic,
4253 0x00000000); /* TOFIX */
80d11f44
JM		 4254 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4255 SPR_NOACCESS, SPR_NOACCESS,
4256 &spr_read_generic, &spr_write_generic,
4257 0x00000000);
4258 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4259 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f
JM		 4260 &spr_read_generic, &spr_write_generic,
4261 0x00000000);
f2e63a42 4262#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 4263 env->nb_tlb = 64;
4264 env->nb_ways = 1;
4265 env->id_tlbs = 0;
1c53accc 4266 env->tlb_type = TLB_EMB;
f2e63a42 4267#endif
80d11f44 4268 init_excp_e200(env);
d63001d1
JM		 4269 env->dcache_line_size = 32;
4270 env->icache_line_size = 32;
e1833e1f 4271 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4272}
a750fc0b 4273
80d11f44 4274/* e300 core */
082c6681
JM		 4275#define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4276 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4277 PPC_FLOAT_STFIWX | \
4278 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4279 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4280 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4281 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4282#define POWERPC_INSNS2_e300 (PPC_NONE)
80d11f44
JM		 4283#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4284#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4285#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4286#define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4287#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4288#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4289 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4290#define check_pow_e300 check_pow_hid0
a750fc0b 4291
578bb252 4292__attribute__ (( unused ))
80d11f44 4293static void init_proc_e300 (CPUPPCState *env)
3fc6c082 4294{
80d11f44
JM		 4295 gen_spr_ne_601(env);
4296 gen_spr_603(env);
a750fc0b
JM		 4297 /* Time base */
4298 gen_tbl(env);
80d11f44
JM		 4299 /* hardware implementation registers */
4300 /* XXX : not implemented */
4301 spr_register(env, SPR_HID0, "HID0",
4302 SPR_NOACCESS, SPR_NOACCESS,
4303 &spr_read_generic, &spr_write_generic,
4304 0x00000000);
4305 /* XXX : not implemented */
4306 spr_register(env, SPR_HID1, "HID1",
4307 SPR_NOACCESS, SPR_NOACCESS,
4308 &spr_read_generic, &spr_write_generic,
4309 0x00000000);
8daf1781
TM		 4310 /* XXX : not implemented */
4311 spr_register(env, SPR_HID2, "HID2",
4312 SPR_NOACCESS, SPR_NOACCESS,
4313 &spr_read_generic, &spr_write_generic,
4314 0x00000000);
80d11f44
JM		 4315 /* Memory management */
4316 gen_low_BATs(env);
8daf1781 4317 gen_high_BATs(env);
80d11f44
JM		 4318 gen_6xx_7xx_soft_tlb(env, 64, 2);
4319 init_excp_603(env);
4320 env->dcache_line_size = 32;
4321 env->icache_line_size = 32;
4322 /* Allocate hardware IRQ controller */
4323 ppc6xx_irq_init(env);
4324}
4325
bd5ea513
AJ		 4326/* e500v1 core */
4327#define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4328 PPC_SPE | PPC_SPE_SINGLE | \
4329 PPC_WRTEE | PPC_RFDI | \
4330 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4331 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
01662f3e
AG		 4332 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4333#define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
bd5ea513 4334#define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
01662f3e 4335#define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
bd5ea513
AJ		 4336#define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4337#define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4338#define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4339#define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4340 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4341 POWERPC_FLAG_BUS_CLK)
4342#define check_pow_e500v1 check_pow_hid0
01662f3e 4343#define init_proc_e500v1 init_proc_e500v1
bd5ea513
AJ		 4344
4345/* e500v2 core */
4346#define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4347 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4348 PPC_WRTEE | PPC_RFDI | \
4349 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4350 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
01662f3e
AG		 4351 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4352#define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
bd5ea513 4353#define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
01662f3e 4354#define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
bd5ea513
AJ		 4355#define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4356#define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4357#define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4358#define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4359 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4360 POWERPC_FLAG_BUS_CLK)
4361#define check_pow_e500v2 check_pow_hid0
01662f3e 4362#define init_proc_e500v2 init_proc_e500v2
80d11f44 4363
01662f3e 4364static void init_proc_e500 (CPUPPCState *env, int version)
80d11f44 4365{
01662f3e
AG		 4366 uint32_t tlbncfg[2];
4367#if !defined(CONFIG_USER_ONLY)
4368 int i;
4369#endif
4370
80d11f44
JM		 4371 /* Time base */
4372 gen_tbl(env);
01662f3e
AG		 4373 /*
4374 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4375 * complain when accessing them.
4376 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4377 */
4378 gen_spr_BookE(env, 0x0000000F0000FFFFULL);
80d11f44
JM		 4379 /* Processor identification */
4380 spr_register(env, SPR_BOOKE_PIR, "PIR",
4381 SPR_NOACCESS, SPR_NOACCESS,
4382 &spr_read_generic, &spr_write_pir,
4383 0x00000000);
4384 /* XXX : not implemented */
4385 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4386 &spr_read_spefscr, &spr_write_spefscr,
4387 &spr_read_spefscr, &spr_write_spefscr,
80d11f44
JM		 4388 0x00000000);
4389 /* Memory management */
4390#if !defined(CONFIG_USER_ONLY)
4391 env->nb_pids = 3;
01662f3e
AG		 4392 env->nb_ways = 2;
4393 env->id_tlbs = 0;
4394 switch (version) {
4395 case 1:
4396 /* e500v1 */
4397 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4398 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4399 break;
4400 case 2:
4401 /* e500v2 */
4402 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4403 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4404 break;
4405 default:
4406 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4407 }
80d11f44 4408#endif
01662f3e 4409 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
80d11f44
JM		 4410 /* XXX : not implemented */
4411 spr_register(env, SPR_HID0, "HID0",
4412 SPR_NOACCESS, SPR_NOACCESS,
4413 &spr_read_generic, &spr_write_generic,
4414 0x00000000);
4415 /* XXX : not implemented */
4416 spr_register(env, SPR_HID1, "HID1",
4417 SPR_NOACCESS, SPR_NOACCESS,
4418 &spr_read_generic, &spr_write_generic,
4419 0x00000000);
4420 /* XXX : not implemented */
4421 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4422 SPR_NOACCESS, SPR_NOACCESS,
4423 &spr_read_generic, &spr_write_generic,
4424 0x00000000);
4425 /* XXX : not implemented */
4426 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4427 SPR_NOACCESS, SPR_NOACCESS,
4428 &spr_read_generic, &spr_write_generic,
4429 0x00000000);
4430 /* XXX : not implemented */
4431 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4432 SPR_NOACCESS, SPR_NOACCESS,
4433 &spr_read_generic, &spr_write_generic,
4434 0x00000000);
578bb252 4435 /* XXX : not implemented */
a750fc0b
JM		 4436 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4437 SPR_NOACCESS, SPR_NOACCESS,
4438 &spr_read_generic, &spr_write_generic,
4439 0x00000000);
80d11f44
JM		 4440 /* XXX : not implemented */
4441 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
a750fc0b
JM		 4442 SPR_NOACCESS, SPR_NOACCESS,
4443 &spr_read_generic, &spr_write_generic,
4444 0x00000000);
80d11f44
JM		 4445 /* XXX : not implemented */
4446 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
a750fc0b
JM		 4447 SPR_NOACCESS, SPR_NOACCESS,
4448 &spr_read_generic, &spr_write_generic,
4449 0x00000000);
578bb252 4450 /* XXX : not implemented */
80d11f44 4451 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
a750fc0b
JM		 4452 SPR_NOACCESS, SPR_NOACCESS,
4453 &spr_read_generic, &spr_write_generic,
4454 0x00000000);
578bb252 4455 /* XXX : not implemented */
80d11f44
JM		 4456 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4457 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 4458 &spr_read_generic, &spr_write_e500_l1csr0,
80d11f44
JM		 4459 0x00000000);
4460 /* XXX : not implemented */
4461 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4462 SPR_NOACCESS, SPR_NOACCESS,
4463 &spr_read_generic, &spr_write_generic,
4464 0x00000000);
80d11f44
JM		 4465 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4466 SPR_NOACCESS, SPR_NOACCESS,
4467 &spr_read_generic, &spr_write_generic,
4468 0x00000000);
4469 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4470 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b
JM		 4471 &spr_read_generic, &spr_write_generic,
4472 0x00000000);
01662f3e
AG		 4473 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4474 SPR_NOACCESS, SPR_NOACCESS,
4475 &spr_read_generic, &spr_write_booke206_mmucsr0,
4476 0x00000000);
4477
f2e63a42 4478#if !defined(CONFIG_USER_ONLY)
01662f3e 4479 env->nb_tlb = 0;
1c53accc 4480 env->tlb_type = TLB_MAS;
01662f3e
AG		 4481 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4482 env->nb_tlb += booke206_tlb_size(env, i);
4483 }
f2e63a42 4484#endif
01662f3e 4485
80d11f44 4486 init_excp_e200(env);
d63001d1
JM		 4487 env->dcache_line_size = 32;
4488 env->icache_line_size = 32;
9fdc60bf
AJ		 4489 /* Allocate hardware IRQ controller */
4490 ppce500_irq_init(env);
3fc6c082 4491}
a750fc0b 4492
01662f3e
AG		 4493static void init_proc_e500v1(CPUPPCState *env)
4494{
4495 init_proc_e500(env, 1);
4496}
4497
4498static void init_proc_e500v2(CPUPPCState *env)
4499{
4500 init_proc_e500(env, 2);
4501}
4502
a750fc0b 4503/* Non-embedded PowerPC */
a750fc0b
JM		 4504
4505/* POWER : same as 601, without mfmsr, mfsr */
4506#if defined(TODO)
4507#define POWERPC_INSNS_POWER (XXX_TODO)
4508/* POWER RSC (from RAD6000) */
4509#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4510#endif /* TODO */
4511
4512/* PowerPC 601 */
082c6681
JM		 4513#define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4514 PPC_FLOAT | \
4515 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4516 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4517 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4518#define POWERPC_INSNS2_601 (PPC_NONE)
25ba3a68 4519#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
082c6681 4520#define POWERPC_MSRR_601 (0x0000000000001040ULL)
faadf50e 4521//#define POWERPC_MMU_601 (POWERPC_MMU_601)
a750fc0b
JM		 4522//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4523#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
237c0af0 4524#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4018bae9 4525#define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
2f462816 4526#define check_pow_601 check_pow_none
a750fc0b
JM		 4527
4528static void init_proc_601 (CPUPPCState *env)
3fc6c082 4529{
a750fc0b
JM		 4530 gen_spr_ne_601(env);
4531 gen_spr_601(env);
4532 /* Hardware implementation registers */
4533 /* XXX : not implemented */
4534 spr_register(env, SPR_HID0, "HID0",
4535 SPR_NOACCESS, SPR_NOACCESS,
056401ea 4536 &spr_read_generic, &spr_write_hid0_601,
faadf50e 4537 0x80010080);
a750fc0b
JM		 4538 /* XXX : not implemented */
4539 spr_register(env, SPR_HID1, "HID1",
4540 SPR_NOACCESS, SPR_NOACCESS,
4541 &spr_read_generic, &spr_write_generic,
4542 0x00000000);
4543 /* XXX : not implemented */
4544 spr_register(env, SPR_601_HID2, "HID2",
4545 SPR_NOACCESS, SPR_NOACCESS,
4546 &spr_read_generic, &spr_write_generic,
4547 0x00000000);
4548 /* XXX : not implemented */
4549 spr_register(env, SPR_601_HID5, "HID5",
4550 SPR_NOACCESS, SPR_NOACCESS,
4551 &spr_read_generic, &spr_write_generic,
4552 0x00000000);
a750fc0b 4553 /* Memory management */
e1833e1f 4554 init_excp_601(env);
082c6681
JM		 4555 /* XXX: beware that dcache line size is 64
4556 * but dcbz uses 32 bytes "sectors"
4557 * XXX: this breaks clcs instruction !
4558 */
4559 env->dcache_line_size = 32;
d63001d1 4560 env->icache_line_size = 64;
faadf50e
JM		 4561 /* Allocate hardware IRQ controller */
4562 ppc6xx_irq_init(env);
3fc6c082
FB		 4563}
4564
082c6681
JM		 4565/* PowerPC 601v */
4566#define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4567 PPC_FLOAT | \
4568 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4569 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4570 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4571#define POWERPC_INSNS2_601v (PPC_NONE)
082c6681
JM		 4572#define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4573#define POWERPC_MSRR_601v (0x0000000000001040ULL)
4574#define POWERPC_MMU_601v (POWERPC_MMU_601)
4575#define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4576#define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4577#define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4578#define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4579#define check_pow_601v check_pow_none
4580
4581static void init_proc_601v (CPUPPCState *env)
4582{
4583 init_proc_601(env);
4584 /* XXX : not implemented */
4585 spr_register(env, SPR_601_HID15, "HID15",
4586 SPR_NOACCESS, SPR_NOACCESS,
4587 &spr_read_generic, &spr_write_generic,
4588 0x00000000);
4589}
4590
a750fc0b 4591/* PowerPC 602 */
082c6681
JM		 4592#define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4593 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4594 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4595 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4596 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4597 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
12de9a39 4598 PPC_SEGMENT | PPC_602_SPEC)
a5858d7a 4599#define POWERPC_INSNS2_602 (PPC_NONE)
082c6681
JM		 4600#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4601/* XXX: 602 MMU is quite specific. Should add a special case */
a750fc0b
JM		 4602#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4603//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4604#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
237c0af0 4605#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
25ba3a68 4606#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4607 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4608#define check_pow_602 check_pow_hid0
a750fc0b
JM		 4609
4610static void init_proc_602 (CPUPPCState *env)
3fc6c082 4611{
a750fc0b
JM		 4612 gen_spr_ne_601(env);
4613 gen_spr_602(env);
4614 /* Time base */
4615 gen_tbl(env);
4616 /* hardware implementation registers */
4617 /* XXX : not implemented */
4618 spr_register(env, SPR_HID0, "HID0",
4619 SPR_NOACCESS, SPR_NOACCESS,
4620 &spr_read_generic, &spr_write_generic,
4621 0x00000000);
4622 /* XXX : not implemented */
4623 spr_register(env, SPR_HID1, "HID1",
4624 SPR_NOACCESS, SPR_NOACCESS,
4625 &spr_read_generic, &spr_write_generic,
4626 0x00000000);
4627 /* Memory management */
4628 gen_low_BATs(env);
4629 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4630 init_excp_602(env);
d63001d1
JM		 4631 env->dcache_line_size = 32;
4632 env->icache_line_size = 32;
a750fc0b
JM		 4633 /* Allocate hardware IRQ controller */
4634 ppc6xx_irq_init(env);
4635}
3fc6c082 4636
a750fc0b 4637/* PowerPC 603 */
082c6681
JM		 4638#define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4639 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4640 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4641 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4642 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4643 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4644 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4645#define POWERPC_INSNS2_603 (PPC_NONE)
25ba3a68 4646#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
a750fc0b
JM		 4647#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4648//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4649#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
237c0af0 4650#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
25ba3a68 4651#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4652 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4653#define check_pow_603 check_pow_hid0
a750fc0b
JM		 4654
4655static void init_proc_603 (CPUPPCState *env)
4656{
4657 gen_spr_ne_601(env);
4658 gen_spr_603(env);
4659 /* Time base */
4660 gen_tbl(env);
4661 /* hardware implementation registers */
4662 /* XXX : not implemented */
4663 spr_register(env, SPR_HID0, "HID0",
4664 SPR_NOACCESS, SPR_NOACCESS,
4665 &spr_read_generic, &spr_write_generic,
4666 0x00000000);
4667 /* XXX : not implemented */
4668 spr_register(env, SPR_HID1, "HID1",
4669 SPR_NOACCESS, SPR_NOACCESS,
4670 &spr_read_generic, &spr_write_generic,
4671 0x00000000);
4672 /* Memory management */
4673 gen_low_BATs(env);
4674 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4675 init_excp_603(env);
d63001d1
JM		 4676 env->dcache_line_size = 32;
4677 env->icache_line_size = 32;
a750fc0b
JM		 4678 /* Allocate hardware IRQ controller */
4679 ppc6xx_irq_init(env);
3fc6c082
FB		 4680}
4681
a750fc0b 4682/* PowerPC 603e */
082c6681
JM		 4683#define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4684 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4685 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4686 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4687 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4688 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4689 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4690#define POWERPC_INSNS2_603E (PPC_NONE)
a750fc0b
JM		 4691#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4692#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4693//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4694#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
237c0af0 4695#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
25ba3a68 4696#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4697 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4698#define check_pow_603E check_pow_hid0
a750fc0b
JM		 4699
4700static void init_proc_603E (CPUPPCState *env)
4701{
4702 gen_spr_ne_601(env);
4703 gen_spr_603(env);
4704 /* Time base */
4705 gen_tbl(env);
4706 /* hardware implementation registers */
4707 /* XXX : not implemented */
4708 spr_register(env, SPR_HID0, "HID0",
4709 SPR_NOACCESS, SPR_NOACCESS,
4710 &spr_read_generic, &spr_write_generic,
4711 0x00000000);
4712 /* XXX : not implemented */
4713 spr_register(env, SPR_HID1, "HID1",
4714 SPR_NOACCESS, SPR_NOACCESS,
4715 &spr_read_generic, &spr_write_generic,
4716 0x00000000);
4717 /* XXX : not implemented */
4718 spr_register(env, SPR_IABR, "IABR",
4719 SPR_NOACCESS, SPR_NOACCESS,
4720 &spr_read_generic, &spr_write_generic,
4721 0x00000000);
4722 /* Memory management */
4723 gen_low_BATs(env);
4724 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4725 init_excp_603(env);
d63001d1
JM		 4726 env->dcache_line_size = 32;
4727 env->icache_line_size = 32;
a750fc0b
JM		 4728 /* Allocate hardware IRQ controller */
4729 ppc6xx_irq_init(env);
4730}
4731
a750fc0b 4732/* PowerPC 604 */
082c6681
JM		 4733#define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4734 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4735 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4736 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4737 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4738 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4739 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4740#define POWERPC_INSNS2_604 (PPC_NONE)
a750fc0b
JM		 4741#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4742#define POWERPC_MMU_604 (POWERPC_MMU_32B)
4743//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4744#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
237c0af0 4745#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
25ba3a68 4746#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4747 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 4748#define check_pow_604 check_pow_nocheck
a750fc0b
JM		 4749
4750static void init_proc_604 (CPUPPCState *env)
4751{
4752 gen_spr_ne_601(env);
4753 gen_spr_604(env);
4754 /* Time base */
4755 gen_tbl(env);
4756 /* Hardware implementation registers */
4757 /* XXX : not implemented */
082c6681
JM		 4758 spr_register(env, SPR_HID0, "HID0",
4759 SPR_NOACCESS, SPR_NOACCESS,
4760 &spr_read_generic, &spr_write_generic,
4761 0x00000000);
4762 /* Memory management */
4763 gen_low_BATs(env);
4764 init_excp_604(env);
4765 env->dcache_line_size = 32;
4766 env->icache_line_size = 32;
4767 /* Allocate hardware IRQ controller */
4768 ppc6xx_irq_init(env);
4769}
4770
4771/* PowerPC 604E */
4772#define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4773 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4774 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4775 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4776 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4777 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4778 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4779#define POWERPC_INSNS2_604E (PPC_NONE)
082c6681
JM		 4780#define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4781#define POWERPC_MMU_604E (POWERPC_MMU_32B)
4782#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4783#define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4784#define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4785#define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4786 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4787#define check_pow_604E check_pow_nocheck
4788
4789static void init_proc_604E (CPUPPCState *env)
4790{
4791 gen_spr_ne_601(env);
4792 gen_spr_604(env);
4793 /* XXX : not implemented */
4794 spr_register(env, SPR_MMCR1, "MMCR1",
4795 SPR_NOACCESS, SPR_NOACCESS,
4796 &spr_read_generic, &spr_write_generic,
4797 0x00000000);
4798 /* XXX : not implemented */
4799 spr_register(env, SPR_PMC3, "PMC3",
4800 SPR_NOACCESS, SPR_NOACCESS,
4801 &spr_read_generic, &spr_write_generic,
4802 0x00000000);
4803 /* XXX : not implemented */
4804 spr_register(env, SPR_PMC4, "PMC4",
4805 SPR_NOACCESS, SPR_NOACCESS,
4806 &spr_read_generic, &spr_write_generic,
4807 0x00000000);
4808 /* Time base */
4809 gen_tbl(env);
4810 /* Hardware implementation registers */
4811 /* XXX : not implemented */
a750fc0b
JM		 4812 spr_register(env, SPR_HID0, "HID0",
4813 SPR_NOACCESS, SPR_NOACCESS,
4814 &spr_read_generic, &spr_write_generic,
4815 0x00000000);
4816 /* XXX : not implemented */
4817 spr_register(env, SPR_HID1, "HID1",
4818 SPR_NOACCESS, SPR_NOACCESS,
4819 &spr_read_generic, &spr_write_generic,
4820 0x00000000);
4821 /* Memory management */
4822 gen_low_BATs(env);
e1833e1f 4823 init_excp_604(env);
d63001d1
JM		 4824 env->dcache_line_size = 32;
4825 env->icache_line_size = 32;
a750fc0b
JM		 4826 /* Allocate hardware IRQ controller */
4827 ppc6xx_irq_init(env);
4828}
4829
bd928eba
JM		 4830/* PowerPC 740 */
4831#define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 4832 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 4833 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 4834 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4835 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4836 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4837 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4838#define POWERPC_INSNS2_740 (PPC_NONE)
bd928eba
JM		 4839#define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4840#define POWERPC_MMU_740 (POWERPC_MMU_32B)
4841#define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4842#define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4843#define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4844#define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4845 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 4846#define check_pow_740 check_pow_hid0
a750fc0b 4847
bd928eba 4848static void init_proc_740 (CPUPPCState *env)
a750fc0b
JM		 4849{
4850 gen_spr_ne_601(env);
4851 gen_spr_7xx(env);
4852 /* Time base */
4853 gen_tbl(env);
4854 /* Thermal management */
4855 gen_spr_thrm(env);
4856 /* Hardware implementation registers */
4857 /* XXX : not implemented */
4858 spr_register(env, SPR_HID0, "HID0",
4859 SPR_NOACCESS, SPR_NOACCESS,
4860 &spr_read_generic, &spr_write_generic,
4861 0x00000000);
4862 /* XXX : not implemented */
4863 spr_register(env, SPR_HID1, "HID1",
4864 SPR_NOACCESS, SPR_NOACCESS,
4865 &spr_read_generic, &spr_write_generic,
4866 0x00000000);
4867 /* Memory management */
4868 gen_low_BATs(env);
e1833e1f 4869 init_excp_7x0(env);
d63001d1
JM		 4870 env->dcache_line_size = 32;
4871 env->icache_line_size = 32;
a750fc0b
JM		 4872 /* Allocate hardware IRQ controller */
4873 ppc6xx_irq_init(env);
4874}
4875
bd928eba
JM		 4876/* PowerPC 750 */
4877#define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4878 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4879 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4880 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4881 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4882 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4883 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4884#define POWERPC_INSNS2_750 (PPC_NONE)
bd928eba
JM		 4885#define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4886#define POWERPC_MMU_750 (POWERPC_MMU_32B)
4887#define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4888#define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4889#define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4890#define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4891 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4892#define check_pow_750 check_pow_hid0
4893
4894static void init_proc_750 (CPUPPCState *env)
4895{
4896 gen_spr_ne_601(env);
4897 gen_spr_7xx(env);
4898 /* XXX : not implemented */
4899 spr_register(env, SPR_L2CR, "L2CR",
4900 SPR_NOACCESS, SPR_NOACCESS,
4901 &spr_read_generic, &spr_write_generic,
4902 0x00000000);
4903 /* Time base */
4904 gen_tbl(env);
4905 /* Thermal management */
4906 gen_spr_thrm(env);
4907 /* Hardware implementation registers */
4908 /* XXX : not implemented */
4909 spr_register(env, SPR_HID0, "HID0",
4910 SPR_NOACCESS, SPR_NOACCESS,
4911 &spr_read_generic, &spr_write_generic,
4912 0x00000000);
4913 /* XXX : not implemented */
4914 spr_register(env, SPR_HID1, "HID1",
4915 SPR_NOACCESS, SPR_NOACCESS,
4916 &spr_read_generic, &spr_write_generic,
4917 0x00000000);
4918 /* Memory management */
4919 gen_low_BATs(env);
4920 /* XXX: high BATs are also present but are known to be bugged on
4921 * die version 1.x
4922 */
4923 init_excp_7x0(env);
4924 env->dcache_line_size = 32;
4925 env->icache_line_size = 32;
4926 /* Allocate hardware IRQ controller */
4927 ppc6xx_irq_init(env);
4928}
4929
4930/* PowerPC 750 CL */
4931/* XXX: not implemented:
4932 * cache lock instructions:
4933 * dcbz_l
4934 * floating point paired instructions
4935 * psq_lux
4936 * psq_lx
4937 * psq_stux
4938 * psq_stx
4939 * ps_abs
4940 * ps_add
4941 * ps_cmpo0
4942 * ps_cmpo1
4943 * ps_cmpu0
4944 * ps_cmpu1
4945 * ps_div
4946 * ps_madd
4947 * ps_madds0
4948 * ps_madds1
4949 * ps_merge00
4950 * ps_merge01
4951 * ps_merge10
4952 * ps_merge11
4953 * ps_mr
4954 * ps_msub
4955 * ps_mul
4956 * ps_muls0
4957 * ps_muls1
4958 * ps_nabs
4959 * ps_neg
4960 * ps_nmadd
4961 * ps_nmsub
4962 * ps_res
4963 * ps_rsqrte
4964 * ps_sel
4965 * ps_sub
4966 * ps_sum0
4967 * ps_sum1
4968 */
4969#define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4970 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4971 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4972 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4973 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4974 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4975 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4976#define POWERPC_INSNS2_750cl (PPC_NONE)
bd928eba
JM		 4977#define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
4978#define POWERPC_MMU_750cl (POWERPC_MMU_32B)
4979#define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
4980#define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
4981#define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
4982#define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4983 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4984#define check_pow_750cl check_pow_hid0
4985
4986static void init_proc_750cl (CPUPPCState *env)
4987{
4988 gen_spr_ne_601(env);
4989 gen_spr_7xx(env);
4990 /* XXX : not implemented */
4991 spr_register(env, SPR_L2CR, "L2CR",
4992 SPR_NOACCESS, SPR_NOACCESS,
4993 &spr_read_generic, &spr_write_generic,
4994 0x00000000);
4995 /* Time base */
4996 gen_tbl(env);
4997 /* Thermal management */
4998 /* Those registers are fake on 750CL */
4999 spr_register(env, SPR_THRM1, "THRM1",
5000 SPR_NOACCESS, SPR_NOACCESS,
5001 &spr_read_generic, &spr_write_generic,
5002 0x00000000);
5003 spr_register(env, SPR_THRM2, "THRM2",
5004 SPR_NOACCESS, SPR_NOACCESS,
5005 &spr_read_generic, &spr_write_generic,
5006 0x00000000);
5007 spr_register(env, SPR_THRM3, "THRM3",
5008 SPR_NOACCESS, SPR_NOACCESS,
5009 &spr_read_generic, &spr_write_generic,
5010 0x00000000);
5011 /* XXX: not implemented */
5012 spr_register(env, SPR_750_TDCL, "TDCL",
5013 SPR_NOACCESS, SPR_NOACCESS,
5014 &spr_read_generic, &spr_write_generic,
5015 0x00000000);
5016 spr_register(env, SPR_750_TDCH, "TDCH",
5017 SPR_NOACCESS, SPR_NOACCESS,
5018 &spr_read_generic, &spr_write_generic,
5019 0x00000000);
5020 /* DMA */
5021 /* XXX : not implemented */
5022 spr_register(env, SPR_750_WPAR, "WPAR",
5023 SPR_NOACCESS, SPR_NOACCESS,
5024 &spr_read_generic, &spr_write_generic,
5025 0x00000000);
5026 spr_register(env, SPR_750_DMAL, "DMAL",
5027 SPR_NOACCESS, SPR_NOACCESS,
5028 &spr_read_generic, &spr_write_generic,
5029 0x00000000);
5030 spr_register(env, SPR_750_DMAU, "DMAU",
5031 SPR_NOACCESS, SPR_NOACCESS,
5032 &spr_read_generic, &spr_write_generic,
5033 0x00000000);
5034 /* Hardware implementation registers */
5035 /* XXX : not implemented */
5036 spr_register(env, SPR_HID0, "HID0",
5037 SPR_NOACCESS, SPR_NOACCESS,
5038 &spr_read_generic, &spr_write_generic,
5039 0x00000000);
5040 /* XXX : not implemented */
5041 spr_register(env, SPR_HID1, "HID1",
5042 SPR_NOACCESS, SPR_NOACCESS,
5043 &spr_read_generic, &spr_write_generic,
5044 0x00000000);
5045 /* XXX : not implemented */
5046 spr_register(env, SPR_750CL_HID2, "HID2",
5047 SPR_NOACCESS, SPR_NOACCESS,
5048 &spr_read_generic, &spr_write_generic,
5049 0x00000000);
5050 /* XXX : not implemented */
5051 spr_register(env, SPR_750CL_HID4, "HID4",
5052 SPR_NOACCESS, SPR_NOACCESS,
5053 &spr_read_generic, &spr_write_generic,
5054 0x00000000);
5055 /* Quantization registers */
5056 /* XXX : not implemented */
5057 spr_register(env, SPR_750_GQR0, "GQR0",
5058 SPR_NOACCESS, SPR_NOACCESS,
5059 &spr_read_generic, &spr_write_generic,
5060 0x00000000);
5061 /* XXX : not implemented */
5062 spr_register(env, SPR_750_GQR1, "GQR1",
5063 SPR_NOACCESS, SPR_NOACCESS,
5064 &spr_read_generic, &spr_write_generic,
5065 0x00000000);
5066 /* XXX : not implemented */
5067 spr_register(env, SPR_750_GQR2, "GQR2",
5068 SPR_NOACCESS, SPR_NOACCESS,
5069 &spr_read_generic, &spr_write_generic,
5070 0x00000000);
5071 /* XXX : not implemented */
5072 spr_register(env, SPR_750_GQR3, "GQR3",
5073 SPR_NOACCESS, SPR_NOACCESS,
5074 &spr_read_generic, &spr_write_generic,
5075 0x00000000);
5076 /* XXX : not implemented */
5077 spr_register(env, SPR_750_GQR4, "GQR4",
5078 SPR_NOACCESS, SPR_NOACCESS,
5079 &spr_read_generic, &spr_write_generic,
5080 0x00000000);
5081 /* XXX : not implemented */
5082 spr_register(env, SPR_750_GQR5, "GQR5",
5083 SPR_NOACCESS, SPR_NOACCESS,
5084 &spr_read_generic, &spr_write_generic,
5085 0x00000000);
5086 /* XXX : not implemented */
5087 spr_register(env, SPR_750_GQR6, "GQR6",
5088 SPR_NOACCESS, SPR_NOACCESS,
5089 &spr_read_generic, &spr_write_generic,
5090 0x00000000);
5091 /* XXX : not implemented */
5092 spr_register(env, SPR_750_GQR7, "GQR7",
5093 SPR_NOACCESS, SPR_NOACCESS,
5094 &spr_read_generic, &spr_write_generic,
5095 0x00000000);
5096 /* Memory management */
5097 gen_low_BATs(env);
5098 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5099 gen_high_BATs(env);
5100 init_excp_750cl(env);
5101 env->dcache_line_size = 32;
5102 env->icache_line_size = 32;
5103 /* Allocate hardware IRQ controller */
5104 ppc6xx_irq_init(env);
5105}
5106
4e777442 5107/* PowerPC 750CX */
bd928eba
JM		 5108#define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5109 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5110 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5111 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5112 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5113 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5114 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5115#define POWERPC_INSNS2_750cx (PPC_NONE)
bd928eba
JM		 5116#define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
5117#define POWERPC_MMU_750cx (POWERPC_MMU_32B)
5118#define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
5119#define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
5120#define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
5121#define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5122 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5123#define check_pow_750cx check_pow_hid0
5124
5125static void init_proc_750cx (CPUPPCState *env)
5126{
5127 gen_spr_ne_601(env);
5128 gen_spr_7xx(env);
5129 /* XXX : not implemented */
5130 spr_register(env, SPR_L2CR, "L2CR",
5131 SPR_NOACCESS, SPR_NOACCESS,
5132 &spr_read_generic, &spr_write_generic,
5133 0x00000000);
5134 /* Time base */
5135 gen_tbl(env);
5136 /* Thermal management */
5137 gen_spr_thrm(env);
5138 /* This register is not implemented but is present for compatibility */
5139 spr_register(env, SPR_SDA, "SDA",
5140 SPR_NOACCESS, SPR_NOACCESS,
5141 &spr_read_generic, &spr_write_generic,
5142 0x00000000);
5143 /* Hardware implementation registers */
5144 /* XXX : not implemented */
5145 spr_register(env, SPR_HID0, "HID0",
5146 SPR_NOACCESS, SPR_NOACCESS,
5147 &spr_read_generic, &spr_write_generic,
5148 0x00000000);
5149 /* XXX : not implemented */
5150 spr_register(env, SPR_HID1, "HID1",
5151 SPR_NOACCESS, SPR_NOACCESS,
5152 &spr_read_generic, &spr_write_generic,
5153 0x00000000);
5154 /* Memory management */
5155 gen_low_BATs(env);
4e777442
JM		 5156 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5157 gen_high_BATs(env);
bd928eba
JM		 5158 init_excp_750cx(env);
5159 env->dcache_line_size = 32;
5160 env->icache_line_size = 32;
5161 /* Allocate hardware IRQ controller */
5162 ppc6xx_irq_init(env);
5163}
5164
5165/* PowerPC 750FX */
082c6681
JM		 5166#define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5167 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 5168 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 5169 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5170 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5171 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5172 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5173#define POWERPC_INSNS2_750fx (PPC_NONE)
25ba3a68 5174#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
a750fc0b
JM		 5175#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
5176#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
5177#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
237c0af0 5178#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
25ba3a68 5179#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5180 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 5181#define check_pow_750fx check_pow_hid0
a750fc0b
JM		 5182
5183static void init_proc_750fx (CPUPPCState *env)
5184{
5185 gen_spr_ne_601(env);
5186 gen_spr_7xx(env);
bd928eba
JM		 5187 /* XXX : not implemented */
5188 spr_register(env, SPR_L2CR, "L2CR",
5189 SPR_NOACCESS, SPR_NOACCESS,
5190 &spr_read_generic, &spr_write_generic,
5191 0x00000000);
a750fc0b
JM		 5192 /* Time base */
5193 gen_tbl(env);
5194 /* Thermal management */
5195 gen_spr_thrm(env);
bd928eba
JM		 5196 /* XXX : not implemented */
5197 spr_register(env, SPR_750_THRM4, "THRM4",
5198 SPR_NOACCESS, SPR_NOACCESS,
5199 &spr_read_generic, &spr_write_generic,
5200 0x00000000);
a750fc0b
JM		 5201 /* Hardware implementation registers */
5202 /* XXX : not implemented */
5203 spr_register(env, SPR_HID0, "HID0",
5204 SPR_NOACCESS, SPR_NOACCESS,
5205 &spr_read_generic, &spr_write_generic,
5206 0x00000000);
5207 /* XXX : not implemented */
5208 spr_register(env, SPR_HID1, "HID1",
5209 SPR_NOACCESS, SPR_NOACCESS,
5210 &spr_read_generic, &spr_write_generic,
5211 0x00000000);
5212 /* XXX : not implemented */
bd928eba 5213 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 5214 SPR_NOACCESS, SPR_NOACCESS,
5215 &spr_read_generic, &spr_write_generic,
5216 0x00000000);
5217 /* Memory management */
5218 gen_low_BATs(env);
5219 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5220 gen_high_BATs(env);
bd928eba 5221 init_excp_7x0(env);
d63001d1
JM		 5222 env->dcache_line_size = 32;
5223 env->icache_line_size = 32;
a750fc0b
JM		 5224 /* Allocate hardware IRQ controller */
5225 ppc6xx_irq_init(env);
5226}
5227
bd928eba
JM		 5228/* PowerPC 750GX */
5229#define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 5230 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba
JM		 5231 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5232 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5233 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5234 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5235 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5236#define POWERPC_INSNS2_750gx (PPC_NONE)
bd928eba
JM		 5237#define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5238#define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5239#define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5240#define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5241#define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5242#define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5243 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5244#define check_pow_750gx check_pow_hid0
5245
5246static void init_proc_750gx (CPUPPCState *env)
5247{
5248 gen_spr_ne_601(env);
5249 gen_spr_7xx(env);
5250 /* XXX : not implemented (XXX: different from 750fx) */
5251 spr_register(env, SPR_L2CR, "L2CR",
5252 SPR_NOACCESS, SPR_NOACCESS,
5253 &spr_read_generic, &spr_write_generic,
5254 0x00000000);
5255 /* Time base */
5256 gen_tbl(env);
5257 /* Thermal management */
5258 gen_spr_thrm(env);
5259 /* XXX : not implemented */
5260 spr_register(env, SPR_750_THRM4, "THRM4",
5261 SPR_NOACCESS, SPR_NOACCESS,
5262 &spr_read_generic, &spr_write_generic,
5263 0x00000000);
5264 /* Hardware implementation registers */
5265 /* XXX : not implemented (XXX: different from 750fx) */
5266 spr_register(env, SPR_HID0, "HID0",
5267 SPR_NOACCESS, SPR_NOACCESS,
5268 &spr_read_generic, &spr_write_generic,
5269 0x00000000);
5270 /* XXX : not implemented */
5271 spr_register(env, SPR_HID1, "HID1",
5272 SPR_NOACCESS, SPR_NOACCESS,
5273 &spr_read_generic, &spr_write_generic,
5274 0x00000000);
5275 /* XXX : not implemented (XXX: different from 750fx) */
5276 spr_register(env, SPR_750FX_HID2, "HID2",
5277 SPR_NOACCESS, SPR_NOACCESS,
5278 &spr_read_generic, &spr_write_generic,
5279 0x00000000);
5280 /* Memory management */
5281 gen_low_BATs(env);
5282 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5283 gen_high_BATs(env);
5284 init_excp_7x0(env);
5285 env->dcache_line_size = 32;
5286 env->icache_line_size = 32;
5287 /* Allocate hardware IRQ controller */
5288 ppc6xx_irq_init(env);
5289}
5290
5291/* PowerPC 745 */
5292#define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5293 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5294 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5295 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5296 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5297 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5298 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5299#define POWERPC_INSNS2_745 (PPC_NONE)
bd928eba
JM		 5300#define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5301#define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5302#define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5303#define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5304#define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5305#define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5306 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5307#define check_pow_745 check_pow_hid0
5308
5309static void init_proc_745 (CPUPPCState *env)
5310{
5311 gen_spr_ne_601(env);
5312 gen_spr_7xx(env);
5313 gen_spr_G2_755(env);
5314 /* Time base */
5315 gen_tbl(env);
5316 /* Thermal management */
5317 gen_spr_thrm(env);
5318 /* Hardware implementation registers */
5319 /* XXX : not implemented */
5320 spr_register(env, SPR_HID0, "HID0",
5321 SPR_NOACCESS, SPR_NOACCESS,
5322 &spr_read_generic, &spr_write_generic,
5323 0x00000000);
5324 /* XXX : not implemented */
5325 spr_register(env, SPR_HID1, "HID1",
5326 SPR_NOACCESS, SPR_NOACCESS,
5327 &spr_read_generic, &spr_write_generic,
5328 0x00000000);
5329 /* XXX : not implemented */
5330 spr_register(env, SPR_HID2, "HID2",
5331 SPR_NOACCESS, SPR_NOACCESS,
5332 &spr_read_generic, &spr_write_generic,
5333 0x00000000);
5334 /* Memory management */
5335 gen_low_BATs(env);
5336 gen_high_BATs(env);
5337 gen_6xx_7xx_soft_tlb(env, 64, 2);
5338 init_excp_7x5(env);
5339 env->dcache_line_size = 32;
5340 env->icache_line_size = 32;
5341 /* Allocate hardware IRQ controller */
5342 ppc6xx_irq_init(env);
5343}
5344
5345/* PowerPC 755 */
5346#define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5347 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5348 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 5349 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5350 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5351 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5352 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5353#define POWERPC_INSNS2_755 (PPC_NONE)
bd928eba
JM		 5354#define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5355#define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5356#define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5357#define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5358#define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5359#define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5360 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 5361#define check_pow_755 check_pow_hid0
a750fc0b 5362
bd928eba 5363static void init_proc_755 (CPUPPCState *env)
a750fc0b
JM		 5364{
5365 gen_spr_ne_601(env);
bd928eba 5366 gen_spr_7xx(env);
a750fc0b
JM		 5367 gen_spr_G2_755(env);
5368 /* Time base */
5369 gen_tbl(env);
5370 /* L2 cache control */
5371 /* XXX : not implemented */
bd928eba 5372 spr_register(env, SPR_L2CR, "L2CR",
a750fc0b
JM		 5373 SPR_NOACCESS, SPR_NOACCESS,
5374 &spr_read_generic, &spr_write_generic,
5375 0x00000000);
5376 /* XXX : not implemented */
5377 spr_register(env, SPR_L2PMCR, "L2PMCR",
5378 SPR_NOACCESS, SPR_NOACCESS,
5379 &spr_read_generic, &spr_write_generic,
5380 0x00000000);
bd928eba
JM		 5381 /* Thermal management */
5382 gen_spr_thrm(env);
a750fc0b
JM		 5383 /* Hardware implementation registers */
5384 /* XXX : not implemented */
5385 spr_register(env, SPR_HID0, "HID0",
5386 SPR_NOACCESS, SPR_NOACCESS,
5387 &spr_read_generic, &spr_write_generic,
5388 0x00000000);
5389 /* XXX : not implemented */
5390 spr_register(env, SPR_HID1, "HID1",
5391 SPR_NOACCESS, SPR_NOACCESS,
5392 &spr_read_generic, &spr_write_generic,
5393 0x00000000);
5394 /* XXX : not implemented */
5395 spr_register(env, SPR_HID2, "HID2",
5396 SPR_NOACCESS, SPR_NOACCESS,
5397 &spr_read_generic, &spr_write_generic,
5398 0x00000000);
5399 /* Memory management */
5400 gen_low_BATs(env);
5401 gen_high_BATs(env);
5402 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 5403 init_excp_7x5(env);
d63001d1
JM		 5404 env->dcache_line_size = 32;
5405 env->icache_line_size = 32;
a750fc0b
JM		 5406 /* Allocate hardware IRQ controller */
5407 ppc6xx_irq_init(env);
5408}
5409
5410/* PowerPC 7400 (aka G4) */
082c6681
JM		 5411#define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5412 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5413 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5414 PPC_FLOAT_STFIWX | \
5415 PPC_CACHE | PPC_CACHE_ICBI | \
5416 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5417 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5418 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5419 PPC_MEM_TLBIA | \
5420 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5421 PPC_ALTIVEC)
a5858d7a 5422#define POWERPC_INSNS2_7400 (PPC_NONE)
a750fc0b
JM		 5423#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5424#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5425#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5426#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
237c0af0 5427#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
25ba3a68 5428#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5429 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5430 POWERPC_FLAG_BUS_CLK)
488243b0 5431#define check_pow_7400 check_pow_hid0
a750fc0b
JM		 5432
5433static void init_proc_7400 (CPUPPCState *env)
5434{
5435 gen_spr_ne_601(env);
5436 gen_spr_7xx(env);
5437 /* Time base */
5438 gen_tbl(env);
5439 /* 74xx specific SPR */
5440 gen_spr_74xx(env);
4e777442
JM		 5441 /* XXX : not implemented */
5442 spr_register(env, SPR_UBAMR, "UBAMR",
5443 &spr_read_ureg, SPR_NOACCESS,
5444 &spr_read_ureg, SPR_NOACCESS,
5445 0x00000000);
5446 /* XXX: this seems not implemented on all revisions. */
5447 /* XXX : not implemented */
5448 spr_register(env, SPR_MSSCR1, "MSSCR1",
5449 SPR_NOACCESS, SPR_NOACCESS,
5450 &spr_read_generic, &spr_write_generic,
5451 0x00000000);
a750fc0b
JM		 5452 /* Thermal management */
5453 gen_spr_thrm(env);
5454 /* Memory management */
5455 gen_low_BATs(env);
e1833e1f 5456 init_excp_7400(env);
d63001d1
JM		 5457 env->dcache_line_size = 32;
5458 env->icache_line_size = 32;
a750fc0b
JM		 5459 /* Allocate hardware IRQ controller */
5460 ppc6xx_irq_init(env);
5461}
5462
5463/* PowerPC 7410 (aka G4) */
082c6681
JM		 5464#define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5465 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5466 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5467 PPC_FLOAT_STFIWX | \
5468 PPC_CACHE | PPC_CACHE_ICBI | \
5469 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5470 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5471 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5472 PPC_MEM_TLBIA | \
5473 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5474 PPC_ALTIVEC)
a5858d7a 5475#define POWERPC_INSNS2_7410 (PPC_NONE)
a750fc0b
JM		 5476#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5477#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5478#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5479#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
237c0af0 5480#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
25ba3a68 5481#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5482 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5483 POWERPC_FLAG_BUS_CLK)
488243b0 5484#define check_pow_7410 check_pow_hid0
a750fc0b
JM		 5485
5486static void init_proc_7410 (CPUPPCState *env)
5487{
5488 gen_spr_ne_601(env);
5489 gen_spr_7xx(env);
5490 /* Time base */
5491 gen_tbl(env);
5492 /* 74xx specific SPR */
5493 gen_spr_74xx(env);
4e777442
JM		 5494 /* XXX : not implemented */
5495 spr_register(env, SPR_UBAMR, "UBAMR",
5496 &spr_read_ureg, SPR_NOACCESS,
5497 &spr_read_ureg, SPR_NOACCESS,
5498 0x00000000);
a750fc0b
JM		 5499 /* Thermal management */
5500 gen_spr_thrm(env);
5501 /* L2PMCR */
5502 /* XXX : not implemented */
5503 spr_register(env, SPR_L2PMCR, "L2PMCR",
5504 SPR_NOACCESS, SPR_NOACCESS,
5505 &spr_read_generic, &spr_write_generic,
5506 0x00000000);
5507 /* LDSTDB */
5508 /* XXX : not implemented */
5509 spr_register(env, SPR_LDSTDB, "LDSTDB",
5510 SPR_NOACCESS, SPR_NOACCESS,
5511 &spr_read_generic, &spr_write_generic,
5512 0x00000000);
5513 /* Memory management */
5514 gen_low_BATs(env);
e1833e1f 5515 init_excp_7400(env);
d63001d1
JM		 5516 env->dcache_line_size = 32;
5517 env->icache_line_size = 32;
a750fc0b
JM		 5518 /* Allocate hardware IRQ controller */
5519 ppc6xx_irq_init(env);
5520}
5521
5522/* PowerPC 7440 (aka G4) */
082c6681
JM		 5523#define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5524 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5525 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5526 PPC_FLOAT_STFIWX | \
5527 PPC_CACHE | PPC_CACHE_ICBI | \
5528 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5529 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5530 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5531 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5532 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5533 PPC_ALTIVEC)
a5858d7a 5534#define POWERPC_INSNS2_7440 (PPC_NONE)
a750fc0b
JM		 5535#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5536#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5537#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5538#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
237c0af0 5539#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
25ba3a68 5540#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5541 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5542 POWERPC_FLAG_BUS_CLK)
4e777442 5543#define check_pow_7440 check_pow_hid0_74xx
a750fc0b 5544
578bb252 5545__attribute__ (( unused ))
a750fc0b
JM		 5546static void init_proc_7440 (CPUPPCState *env)
5547{
5548 gen_spr_ne_601(env);
5549 gen_spr_7xx(env);
5550 /* Time base */
5551 gen_tbl(env);
5552 /* 74xx specific SPR */
5553 gen_spr_74xx(env);
4e777442
JM		 5554 /* XXX : not implemented */
5555 spr_register(env, SPR_UBAMR, "UBAMR",
5556 &spr_read_ureg, SPR_NOACCESS,
5557 &spr_read_ureg, SPR_NOACCESS,
5558 0x00000000);
a750fc0b
JM		 5559 /* LDSTCR */
5560 /* XXX : not implemented */
5561 spr_register(env, SPR_LDSTCR, "LDSTCR",
5562 SPR_NOACCESS, SPR_NOACCESS,
5563 &spr_read_generic, &spr_write_generic,
5564 0x00000000);
5565 /* ICTRL */
5566 /* XXX : not implemented */
5567 spr_register(env, SPR_ICTRL, "ICTRL",
5568 SPR_NOACCESS, SPR_NOACCESS,
5569 &spr_read_generic, &spr_write_generic,
5570 0x00000000);
5571 /* MSSSR0 */
578bb252 5572 /* XXX : not implemented */
a750fc0b
JM		 5573 spr_register(env, SPR_MSSSR0, "MSSSR0",
5574 SPR_NOACCESS, SPR_NOACCESS,
5575 &spr_read_generic, &spr_write_generic,
5576 0x00000000);
5577 /* PMC */
5578 /* XXX : not implemented */
5579 spr_register(env, SPR_PMC5, "PMC5",
5580 SPR_NOACCESS, SPR_NOACCESS,
5581 &spr_read_generic, &spr_write_generic,
5582 0x00000000);
578bb252 5583 /* XXX : not implemented */
a750fc0b
JM		 5584 spr_register(env, SPR_UPMC5, "UPMC5",
5585 &spr_read_ureg, SPR_NOACCESS,
5586 &spr_read_ureg, SPR_NOACCESS,
5587 0x00000000);
578bb252 5588 /* XXX : not implemented */
a750fc0b
JM		 5589 spr_register(env, SPR_PMC6, "PMC6",
5590 SPR_NOACCESS, SPR_NOACCESS,
5591 &spr_read_generic, &spr_write_generic,
5592 0x00000000);
578bb252 5593 /* XXX : not implemented */
a750fc0b
JM		 5594 spr_register(env, SPR_UPMC6, "UPMC6",
5595 &spr_read_ureg, SPR_NOACCESS,
5596 &spr_read_ureg, SPR_NOACCESS,
5597 0x00000000);
5598 /* Memory management */
5599 gen_low_BATs(env);
578bb252 5600 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 5601 init_excp_7450(env);
d63001d1
JM		 5602 env->dcache_line_size = 32;
5603 env->icache_line_size = 32;
a750fc0b
JM		 5604 /* Allocate hardware IRQ controller */
5605 ppc6xx_irq_init(env);
5606}
a750fc0b
JM		 5607
5608/* PowerPC 7450 (aka G4) */
082c6681
JM		 5609#define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5610 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5611 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5612 PPC_FLOAT_STFIWX | \
5613 PPC_CACHE | PPC_CACHE_ICBI | \
5614 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5615 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5616 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5617 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5618 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5619 PPC_ALTIVEC)
a5858d7a 5620#define POWERPC_INSNS2_7450 (PPC_NONE)
a750fc0b
JM		 5621#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5622#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5623#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5624#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
237c0af0 5625#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
25ba3a68 5626#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5627 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5628 POWERPC_FLAG_BUS_CLK)
4e777442 5629#define check_pow_7450 check_pow_hid0_74xx
a750fc0b 5630
578bb252 5631__attribute__ (( unused ))
a750fc0b
JM		 5632static void init_proc_7450 (CPUPPCState *env)
5633{
5634 gen_spr_ne_601(env);
5635 gen_spr_7xx(env);
5636 /* Time base */
5637 gen_tbl(env);
5638 /* 74xx specific SPR */
5639 gen_spr_74xx(env);
5640 /* Level 3 cache control */
5641 gen_l3_ctrl(env);
4e777442
JM		 5642 /* L3ITCR1 */
5643 /* XXX : not implemented */
5644 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5645 SPR_NOACCESS, SPR_NOACCESS,
5646 &spr_read_generic, &spr_write_generic,
5647 0x00000000);
5648 /* L3ITCR2 */
5649 /* XXX : not implemented */
5650 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5651 SPR_NOACCESS, SPR_NOACCESS,
5652 &spr_read_generic, &spr_write_generic,
5653 0x00000000);
5654 /* L3ITCR3 */
5655 /* XXX : not implemented */
5656 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5657 SPR_NOACCESS, SPR_NOACCESS,
5658 &spr_read_generic, &spr_write_generic,
5659 0x00000000);
5660 /* L3OHCR */
5661 /* XXX : not implemented */
5662 spr_register(env, SPR_L3OHCR, "L3OHCR",
5663 SPR_NOACCESS, SPR_NOACCESS,
5664 &spr_read_generic, &spr_write_generic,
5665 0x00000000);
5666 /* XXX : not implemented */
5667 spr_register(env, SPR_UBAMR, "UBAMR",
5668 &spr_read_ureg, SPR_NOACCESS,
5669 &spr_read_ureg, SPR_NOACCESS,
5670 0x00000000);
a750fc0b
JM		 5671 /* LDSTCR */
5672 /* XXX : not implemented */
5673 spr_register(env, SPR_LDSTCR, "LDSTCR",
5674 SPR_NOACCESS, SPR_NOACCESS,
5675 &spr_read_generic, &spr_write_generic,
5676 0x00000000);
5677 /* ICTRL */
5678 /* XXX : not implemented */
5679 spr_register(env, SPR_ICTRL, "ICTRL",
5680 SPR_NOACCESS, SPR_NOACCESS,
5681 &spr_read_generic, &spr_write_generic,
5682 0x00000000);
5683 /* MSSSR0 */
578bb252 5684 /* XXX : not implemented */
a750fc0b
JM		 5685 spr_register(env, SPR_MSSSR0, "MSSSR0",
5686 SPR_NOACCESS, SPR_NOACCESS,
5687 &spr_read_generic, &spr_write_generic,
5688 0x00000000);
5689 /* PMC */
5690 /* XXX : not implemented */
5691 spr_register(env, SPR_PMC5, "PMC5",
5692 SPR_NOACCESS, SPR_NOACCESS,
5693 &spr_read_generic, &spr_write_generic,
5694 0x00000000);
578bb252 5695 /* XXX : not implemented */
a750fc0b
JM		 5696 spr_register(env, SPR_UPMC5, "UPMC5",
5697 &spr_read_ureg, SPR_NOACCESS,
5698 &spr_read_ureg, SPR_NOACCESS,
5699 0x00000000);
578bb252 5700 /* XXX : not implemented */
a750fc0b
JM		 5701 spr_register(env, SPR_PMC6, "PMC6",
5702 SPR_NOACCESS, SPR_NOACCESS,
5703 &spr_read_generic, &spr_write_generic,
5704 0x00000000);
578bb252 5705 /* XXX : not implemented */
a750fc0b
JM		 5706 spr_register(env, SPR_UPMC6, "UPMC6",
5707 &spr_read_ureg, SPR_NOACCESS,
5708 &spr_read_ureg, SPR_NOACCESS,
5709 0x00000000);
5710 /* Memory management */
5711 gen_low_BATs(env);
578bb252 5712 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5713 init_excp_7450(env);
d63001d1
JM		 5714 env->dcache_line_size = 32;
5715 env->icache_line_size = 32;
a750fc0b
JM		 5716 /* Allocate hardware IRQ controller */
5717 ppc6xx_irq_init(env);
5718}
a750fc0b
JM		 5719
5720/* PowerPC 7445 (aka G4) */
082c6681
JM		 5721#define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5722 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5723 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5724 PPC_FLOAT_STFIWX | \
5725 PPC_CACHE | PPC_CACHE_ICBI | \
5726 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5727 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5728 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5729 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5730 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5731 PPC_ALTIVEC)
a5858d7a 5732#define POWERPC_INSNS2_7445 (PPC_NONE)
a750fc0b
JM		 5733#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5734#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5735#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5736#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
237c0af0 5737#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
25ba3a68 5738#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5739 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5740 POWERPC_FLAG_BUS_CLK)
4e777442 5741#define check_pow_7445 check_pow_hid0_74xx
a750fc0b 5742
578bb252 5743__attribute__ (( unused ))
a750fc0b
JM		 5744static void init_proc_7445 (CPUPPCState *env)
5745{
5746 gen_spr_ne_601(env);
5747 gen_spr_7xx(env);
5748 /* Time base */
5749 gen_tbl(env);
5750 /* 74xx specific SPR */
5751 gen_spr_74xx(env);
5752 /* LDSTCR */
5753 /* XXX : not implemented */
5754 spr_register(env, SPR_LDSTCR, "LDSTCR",
5755 SPR_NOACCESS, SPR_NOACCESS,
5756 &spr_read_generic, &spr_write_generic,
5757 0x00000000);
5758 /* ICTRL */
5759 /* XXX : not implemented */
5760 spr_register(env, SPR_ICTRL, "ICTRL",
5761 SPR_NOACCESS, SPR_NOACCESS,
5762 &spr_read_generic, &spr_write_generic,
5763 0x00000000);
5764 /* MSSSR0 */
578bb252 5765 /* XXX : not implemented */
a750fc0b
JM		 5766 spr_register(env, SPR_MSSSR0, "MSSSR0",
5767 SPR_NOACCESS, SPR_NOACCESS,
5768 &spr_read_generic, &spr_write_generic,
5769 0x00000000);
5770 /* PMC */
5771 /* XXX : not implemented */
5772 spr_register(env, SPR_PMC5, "PMC5",
5773 SPR_NOACCESS, SPR_NOACCESS,
5774 &spr_read_generic, &spr_write_generic,
5775 0x00000000);
578bb252 5776 /* XXX : not implemented */
a750fc0b
JM		 5777 spr_register(env, SPR_UPMC5, "UPMC5",
5778 &spr_read_ureg, SPR_NOACCESS,
5779 &spr_read_ureg, SPR_NOACCESS,
5780 0x00000000);
578bb252 5781 /* XXX : not implemented */
a750fc0b
JM		 5782 spr_register(env, SPR_PMC6, "PMC6",
5783 SPR_NOACCESS, SPR_NOACCESS,
5784 &spr_read_generic, &spr_write_generic,
5785 0x00000000);
578bb252 5786 /* XXX : not implemented */
a750fc0b
JM		 5787 spr_register(env, SPR_UPMC6, "UPMC6",
5788 &spr_read_ureg, SPR_NOACCESS,
5789 &spr_read_ureg, SPR_NOACCESS,
5790 0x00000000);
5791 /* SPRGs */
5792 spr_register(env, SPR_SPRG4, "SPRG4",
5793 SPR_NOACCESS, SPR_NOACCESS,
5794 &spr_read_generic, &spr_write_generic,
5795 0x00000000);
5796 spr_register(env, SPR_USPRG4, "USPRG4",
5797 &spr_read_ureg, SPR_NOACCESS,
5798 &spr_read_ureg, SPR_NOACCESS,
5799 0x00000000);
5800 spr_register(env, SPR_SPRG5, "SPRG5",
5801 SPR_NOACCESS, SPR_NOACCESS,
5802 &spr_read_generic, &spr_write_generic,
5803 0x00000000);
5804 spr_register(env, SPR_USPRG5, "USPRG5",
5805 &spr_read_ureg, SPR_NOACCESS,
5806 &spr_read_ureg, SPR_NOACCESS,
5807 0x00000000);
5808 spr_register(env, SPR_SPRG6, "SPRG6",
5809 SPR_NOACCESS, SPR_NOACCESS,
5810 &spr_read_generic, &spr_write_generic,
5811 0x00000000);
5812 spr_register(env, SPR_USPRG6, "USPRG6",
5813 &spr_read_ureg, SPR_NOACCESS,
5814 &spr_read_ureg, SPR_NOACCESS,
5815 0x00000000);
5816 spr_register(env, SPR_SPRG7, "SPRG7",
5817 SPR_NOACCESS, SPR_NOACCESS,
5818 &spr_read_generic, &spr_write_generic,
5819 0x00000000);
5820 spr_register(env, SPR_USPRG7, "USPRG7",
5821 &spr_read_ureg, SPR_NOACCESS,
5822 &spr_read_ureg, SPR_NOACCESS,
5823 0x00000000);
5824 /* Memory management */
5825 gen_low_BATs(env);
5826 gen_high_BATs(env);
578bb252 5827 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5828 init_excp_7450(env);
d63001d1
JM		 5829 env->dcache_line_size = 32;
5830 env->icache_line_size = 32;
a750fc0b
JM		 5831 /* Allocate hardware IRQ controller */
5832 ppc6xx_irq_init(env);
5833}
a750fc0b
JM		 5834
5835/* PowerPC 7455 (aka G4) */
082c6681
JM		 5836#define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5837 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5838 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5839 PPC_FLOAT_STFIWX | \
5840 PPC_CACHE | PPC_CACHE_ICBI | \
5841 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5842 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5843 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5844 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5845 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5846 PPC_ALTIVEC)
a5858d7a 5847#define POWERPC_INSNS2_7455 (PPC_NONE)
a750fc0b
JM		 5848#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5849#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5850#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5851#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
237c0af0 5852#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
25ba3a68 5853#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5854 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5855 POWERPC_FLAG_BUS_CLK)
4e777442 5856#define check_pow_7455 check_pow_hid0_74xx
a750fc0b 5857
578bb252 5858__attribute__ (( unused ))
a750fc0b
JM		 5859static void init_proc_7455 (CPUPPCState *env)
5860{
5861 gen_spr_ne_601(env);
5862 gen_spr_7xx(env);
5863 /* Time base */
5864 gen_tbl(env);
5865 /* 74xx specific SPR */
5866 gen_spr_74xx(env);
5867 /* Level 3 cache control */
5868 gen_l3_ctrl(env);
5869 /* LDSTCR */
5870 /* XXX : not implemented */
5871 spr_register(env, SPR_LDSTCR, "LDSTCR",
5872 SPR_NOACCESS, SPR_NOACCESS,
5873 &spr_read_generic, &spr_write_generic,
5874 0x00000000);
5875 /* ICTRL */
5876 /* XXX : not implemented */
5877 spr_register(env, SPR_ICTRL, "ICTRL",
5878 SPR_NOACCESS, SPR_NOACCESS,
5879 &spr_read_generic, &spr_write_generic,
5880 0x00000000);
5881 /* MSSSR0 */
578bb252 5882 /* XXX : not implemented */
a750fc0b
JM		 5883 spr_register(env, SPR_MSSSR0, "MSSSR0",
5884 SPR_NOACCESS, SPR_NOACCESS,
5885 &spr_read_generic, &spr_write_generic,
5886 0x00000000);
5887 /* PMC */
5888 /* XXX : not implemented */
5889 spr_register(env, SPR_PMC5, "PMC5",
5890 SPR_NOACCESS, SPR_NOACCESS,
5891 &spr_read_generic, &spr_write_generic,
5892 0x00000000);
578bb252 5893 /* XXX : not implemented */
a750fc0b
JM		 5894 spr_register(env, SPR_UPMC5, "UPMC5",
5895 &spr_read_ureg, SPR_NOACCESS,
5896 &spr_read_ureg, SPR_NOACCESS,
5897 0x00000000);
578bb252 5898 /* XXX : not implemented */
a750fc0b
JM		 5899 spr_register(env, SPR_PMC6, "PMC6",
5900 SPR_NOACCESS, SPR_NOACCESS,
5901 &spr_read_generic, &spr_write_generic,
5902 0x00000000);
578bb252 5903 /* XXX : not implemented */
a750fc0b
JM		 5904 spr_register(env, SPR_UPMC6, "UPMC6",
5905 &spr_read_ureg, SPR_NOACCESS,
5906 &spr_read_ureg, SPR_NOACCESS,
5907 0x00000000);
5908 /* SPRGs */
5909 spr_register(env, SPR_SPRG4, "SPRG4",
5910 SPR_NOACCESS, SPR_NOACCESS,
5911 &spr_read_generic, &spr_write_generic,
5912 0x00000000);
5913 spr_register(env, SPR_USPRG4, "USPRG4",
5914 &spr_read_ureg, SPR_NOACCESS,
5915 &spr_read_ureg, SPR_NOACCESS,
5916 0x00000000);
5917 spr_register(env, SPR_SPRG5, "SPRG5",
5918 SPR_NOACCESS, SPR_NOACCESS,
5919 &spr_read_generic, &spr_write_generic,
5920 0x00000000);
5921 spr_register(env, SPR_USPRG5, "USPRG5",
5922 &spr_read_ureg, SPR_NOACCESS,
5923 &spr_read_ureg, SPR_NOACCESS,
5924 0x00000000);
5925 spr_register(env, SPR_SPRG6, "SPRG6",
5926 SPR_NOACCESS, SPR_NOACCESS,
5927 &spr_read_generic, &spr_write_generic,
5928 0x00000000);
5929 spr_register(env, SPR_USPRG6, "USPRG6",
5930 &spr_read_ureg, SPR_NOACCESS,
5931 &spr_read_ureg, SPR_NOACCESS,
5932 0x00000000);
5933 spr_register(env, SPR_SPRG7, "SPRG7",
5934 SPR_NOACCESS, SPR_NOACCESS,
5935 &spr_read_generic, &spr_write_generic,
5936 0x00000000);
5937 spr_register(env, SPR_USPRG7, "USPRG7",
5938 &spr_read_ureg, SPR_NOACCESS,
5939 &spr_read_ureg, SPR_NOACCESS,
5940 0x00000000);
5941 /* Memory management */
5942 gen_low_BATs(env);
5943 gen_high_BATs(env);
578bb252 5944 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5945 init_excp_7450(env);
d63001d1
JM		 5946 env->dcache_line_size = 32;
5947 env->icache_line_size = 32;
a750fc0b
JM		 5948 /* Allocate hardware IRQ controller */
5949 ppc6xx_irq_init(env);
5950}
a750fc0b 5951
4e777442
JM		 5952/* PowerPC 7457 (aka G4) */
5953#define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5954 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5955 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5956 PPC_FLOAT_STFIWX | \
5957 PPC_CACHE | PPC_CACHE_ICBI | \
5958 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5959 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5960 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5961 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5962 PPC_SEGMENT | PPC_EXTERN | \
5963 PPC_ALTIVEC)
a5858d7a 5964#define POWERPC_INSNS2_7457 (PPC_NONE)
4e777442
JM		 5965#define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
5966#define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
5967#define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
5968#define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
5969#define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
5970#define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5971 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5972 POWERPC_FLAG_BUS_CLK)
5973#define check_pow_7457 check_pow_hid0_74xx
5974
5975__attribute__ (( unused ))
5976static void init_proc_7457 (CPUPPCState *env)
5977{
5978 gen_spr_ne_601(env);
5979 gen_spr_7xx(env);
5980 /* Time base */
5981 gen_tbl(env);
5982 /* 74xx specific SPR */
5983 gen_spr_74xx(env);
5984 /* Level 3 cache control */
5985 gen_l3_ctrl(env);
5986 /* L3ITCR1 */
5987 /* XXX : not implemented */
5988 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5989 SPR_NOACCESS, SPR_NOACCESS,
5990 &spr_read_generic, &spr_write_generic,
5991 0x00000000);
5992 /* L3ITCR2 */
5993 /* XXX : not implemented */
5994 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5995 SPR_NOACCESS, SPR_NOACCESS,
5996 &spr_read_generic, &spr_write_generic,
5997 0x00000000);
5998 /* L3ITCR3 */
5999 /* XXX : not implemented */
6000 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6001 SPR_NOACCESS, SPR_NOACCESS,
6002 &spr_read_generic, &spr_write_generic,
6003 0x00000000);
6004 /* L3OHCR */
6005 /* XXX : not implemented */
6006 spr_register(env, SPR_L3OHCR, "L3OHCR",
6007 SPR_NOACCESS, SPR_NOACCESS,
6008 &spr_read_generic, &spr_write_generic,
6009 0x00000000);
6010 /* LDSTCR */
6011 /* XXX : not implemented */
6012 spr_register(env, SPR_LDSTCR, "LDSTCR",
6013 SPR_NOACCESS, SPR_NOACCESS,
6014 &spr_read_generic, &spr_write_generic,
6015 0x00000000);
6016 /* ICTRL */
6017 /* XXX : not implemented */
6018 spr_register(env, SPR_ICTRL, "ICTRL",
6019 SPR_NOACCESS, SPR_NOACCESS,
6020 &spr_read_generic, &spr_write_generic,
6021 0x00000000);
6022 /* MSSSR0 */
6023 /* XXX : not implemented */
6024 spr_register(env, SPR_MSSSR0, "MSSSR0",
6025 SPR_NOACCESS, SPR_NOACCESS,
6026 &spr_read_generic, &spr_write_generic,
6027 0x00000000);
6028 /* PMC */
6029 /* XXX : not implemented */
6030 spr_register(env, SPR_PMC5, "PMC5",
6031 SPR_NOACCESS, SPR_NOACCESS,
6032 &spr_read_generic, &spr_write_generic,
6033 0x00000000);
6034 /* XXX : not implemented */
6035 spr_register(env, SPR_UPMC5, "UPMC5",
6036 &spr_read_ureg, SPR_NOACCESS,
6037 &spr_read_ureg, SPR_NOACCESS,
6038 0x00000000);
6039 /* XXX : not implemented */
6040 spr_register(env, SPR_PMC6, "PMC6",
6041 SPR_NOACCESS, SPR_NOACCESS,
6042 &spr_read_generic, &spr_write_generic,
6043 0x00000000);
6044 /* XXX : not implemented */
6045 spr_register(env, SPR_UPMC6, "UPMC6",
6046 &spr_read_ureg, SPR_NOACCESS,
6047 &spr_read_ureg, SPR_NOACCESS,
6048 0x00000000);
6049 /* SPRGs */
6050 spr_register(env, SPR_SPRG4, "SPRG4",
6051 SPR_NOACCESS, SPR_NOACCESS,
6052 &spr_read_generic, &spr_write_generic,
6053 0x00000000);
6054 spr_register(env, SPR_USPRG4, "USPRG4",
6055 &spr_read_ureg, SPR_NOACCESS,
6056 &spr_read_ureg, SPR_NOACCESS,
6057 0x00000000);
6058 spr_register(env, SPR_SPRG5, "SPRG5",
6059 SPR_NOACCESS, SPR_NOACCESS,
6060 &spr_read_generic, &spr_write_generic,
6061 0x00000000);
6062 spr_register(env, SPR_USPRG5, "USPRG5",
6063 &spr_read_ureg, SPR_NOACCESS,
6064 &spr_read_ureg, SPR_NOACCESS,
6065 0x00000000);
6066 spr_register(env, SPR_SPRG6, "SPRG6",
6067 SPR_NOACCESS, SPR_NOACCESS,
6068 &spr_read_generic, &spr_write_generic,
6069 0x00000000);
6070 spr_register(env, SPR_USPRG6, "USPRG6",
6071 &spr_read_ureg, SPR_NOACCESS,
6072 &spr_read_ureg, SPR_NOACCESS,
6073 0x00000000);
6074 spr_register(env, SPR_SPRG7, "SPRG7",
6075 SPR_NOACCESS, SPR_NOACCESS,
6076 &spr_read_generic, &spr_write_generic,
6077 0x00000000);
6078 spr_register(env, SPR_USPRG7, "USPRG7",
6079 &spr_read_ureg, SPR_NOACCESS,
6080 &spr_read_ureg, SPR_NOACCESS,
6081 0x00000000);
6082 /* Memory management */
6083 gen_low_BATs(env);
6084 gen_high_BATs(env);
6085 gen_74xx_soft_tlb(env, 128, 2);
6086 init_excp_7450(env);
6087 env->dcache_line_size = 32;
6088 env->icache_line_size = 32;
6089 /* Allocate hardware IRQ controller */
6090 ppc6xx_irq_init(env);
6091}
6092
a750fc0b
JM		 6093#if defined (TARGET_PPC64)
6094/* PowerPC 970 */
082c6681
JM		 6095#define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6096 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6097 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6098 PPC_FLOAT_STFIWX | \
6099 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6100 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6101 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6102 PPC_64B | PPC_ALTIVEC | \
12de9a39 6103 PPC_SEGMENT_64B | PPC_SLBI)
a5858d7a 6104#define POWERPC_INSNS2_970 (PPC_NONE)
a750fc0b 6105#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
12de9a39 6106#define POWERPC_MMU_970 (POWERPC_MMU_64B)
a750fc0b
JM		 6107//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
6108#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
237c0af0 6109#define POWERPC_BFDM_970 (bfd_mach_ppc64)
25ba3a68 6110#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6111 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6112 POWERPC_FLAG_BUS_CLK)
a750fc0b 6113
417bf010
JM		 6114#if defined(CONFIG_USER_ONLY)
6115#define POWERPC970_HID5_INIT 0x00000080
6116#else
6117#define POWERPC970_HID5_INIT 0x00000000
6118#endif
6119
2f462816
JM		 6120static int check_pow_970 (CPUPPCState *env)
6121{
6122 if (env->spr[SPR_HID0] & 0x00600000)
6123 return 1;
6124
6125 return 0;
6126}
6127
a750fc0b
JM		 6128static void init_proc_970 (CPUPPCState *env)
6129{
6130 gen_spr_ne_601(env);
6131 gen_spr_7xx(env);
6132 /* Time base */
6133 gen_tbl(env);
6134 /* Hardware implementation registers */
6135 /* XXX : not implemented */
6136 spr_register(env, SPR_HID0, "HID0",
6137 SPR_NOACCESS, SPR_NOACCESS,
06403421 6138 &spr_read_generic, &spr_write_clear,
d63001d1 6139 0x60000000);
a750fc0b
JM		 6140 /* XXX : not implemented */
6141 spr_register(env, SPR_HID1, "HID1",
6142 SPR_NOACCESS, SPR_NOACCESS,
6143 &spr_read_generic, &spr_write_generic,
6144 0x00000000);
6145 /* XXX : not implemented */
bd928eba 6146 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6147 SPR_NOACCESS, SPR_NOACCESS,
6148 &spr_read_generic, &spr_write_generic,
6149 0x00000000);
e57448f1
JM		 6150 /* XXX : not implemented */
6151 spr_register(env, SPR_970_HID5, "HID5",
6152 SPR_NOACCESS, SPR_NOACCESS,
6153 &spr_read_generic, &spr_write_generic,
417bf010 6154 POWERPC970_HID5_INIT);
bd928eba
JM		 6155 /* XXX : not implemented */
6156 spr_register(env, SPR_L2CR, "L2CR",
6157 SPR_NOACCESS, SPR_NOACCESS,
6158 &spr_read_generic, &spr_write_generic,
6159 0x00000000);
a750fc0b
JM		 6160 /* Memory management */
6161 /* XXX: not correct */
6162 gen_low_BATs(env);
12de9a39
JM		 6163 /* XXX : not implemented */
6164 spr_register(env, SPR_MMUCFG, "MMUCFG",
6165 SPR_NOACCESS, SPR_NOACCESS,
6166 &spr_read_generic, SPR_NOACCESS,
6167 0x00000000); /* TOFIX */
6168 /* XXX : not implemented */
6169 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6170 SPR_NOACCESS, SPR_NOACCESS,
6171 &spr_read_generic, &spr_write_generic,
6172 0x00000000); /* TOFIX */
6173 spr_register(env, SPR_HIOR, "SPR_HIOR",
6174 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6175 &spr_read_hior, &spr_write_hior,
6176 0x00000000);
f2e63a42 6177#if !defined(CONFIG_USER_ONLY)
12de9a39 6178 env->slb_nr = 32;
f2e63a42 6179#endif
e1833e1f 6180 init_excp_970(env);
d63001d1
JM		 6181 env->dcache_line_size = 128;
6182 env->icache_line_size = 128;
a750fc0b
JM		 6183 /* Allocate hardware IRQ controller */
6184 ppc970_irq_init(env);
cf8358c8
AJ		 6185 /* Can't find information on what this should be on reset. This
6186 * value is the one used by 74xx processors. */
6187 vscr_init(env, 0x00010000);
a750fc0b 6188}
a750fc0b
JM		 6189
6190/* PowerPC 970FX (aka G5) */
082c6681
JM		 6191#define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6192 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6193 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6194 PPC_FLOAT_STFIWX | \
6195 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6196 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6197 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6198 PPC_64B | PPC_ALTIVEC | \
12de9a39 6199 PPC_SEGMENT_64B | PPC_SLBI)
a5858d7a 6200#define POWERPC_INSNS2_970FX (PPC_NONE)
a750fc0b 6201#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
12de9a39 6202#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
a750fc0b
JM		 6203#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6204#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
237c0af0 6205#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
25ba3a68 6206#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6207 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6208 POWERPC_FLAG_BUS_CLK)
a750fc0b 6209
2f462816
JM		 6210static int check_pow_970FX (CPUPPCState *env)
6211{
6212 if (env->spr[SPR_HID0] & 0x00600000)
6213 return 1;
6214
6215 return 0;
6216}
6217
a750fc0b
JM		 6218static void init_proc_970FX (CPUPPCState *env)
6219{
6220 gen_spr_ne_601(env);
6221 gen_spr_7xx(env);
6222 /* Time base */
6223 gen_tbl(env);
6224 /* Hardware implementation registers */
6225 /* XXX : not implemented */
6226 spr_register(env, SPR_HID0, "HID0",
6227 SPR_NOACCESS, SPR_NOACCESS,
06403421 6228 &spr_read_generic, &spr_write_clear,
d63001d1 6229 0x60000000);
a750fc0b
JM		 6230 /* XXX : not implemented */
6231 spr_register(env, SPR_HID1, "HID1",
6232 SPR_NOACCESS, SPR_NOACCESS,
6233 &spr_read_generic, &spr_write_generic,
6234 0x00000000);
6235 /* XXX : not implemented */
bd928eba 6236 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6237 SPR_NOACCESS, SPR_NOACCESS,
6238 &spr_read_generic, &spr_write_generic,
6239 0x00000000);
d63001d1
JM		 6240 /* XXX : not implemented */
6241 spr_register(env, SPR_970_HID5, "HID5",
6242 SPR_NOACCESS, SPR_NOACCESS,
6243 &spr_read_generic, &spr_write_generic,
417bf010 6244 POWERPC970_HID5_INIT);
bd928eba
JM		 6245 /* XXX : not implemented */
6246 spr_register(env, SPR_L2CR, "L2CR",
6247 SPR_NOACCESS, SPR_NOACCESS,
6248 &spr_read_generic, &spr_write_generic,
6249 0x00000000);
a750fc0b
JM		 6250 /* Memory management */
6251 /* XXX: not correct */
6252 gen_low_BATs(env);
12de9a39
JM		 6253 /* XXX : not implemented */
6254 spr_register(env, SPR_MMUCFG, "MMUCFG",
6255 SPR_NOACCESS, SPR_NOACCESS,
6256 &spr_read_generic, SPR_NOACCESS,
6257 0x00000000); /* TOFIX */
6258 /* XXX : not implemented */
6259 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6260 SPR_NOACCESS, SPR_NOACCESS,
6261 &spr_read_generic, &spr_write_generic,
6262 0x00000000); /* TOFIX */
6263 spr_register(env, SPR_HIOR, "SPR_HIOR",
6264 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6265 &spr_read_hior, &spr_write_hior,
6266 0x00000000);
4e98d8cf
BS		 6267 spr_register(env, SPR_CTRL, "SPR_CTRL",
6268 SPR_NOACCESS, SPR_NOACCESS,
6269 &spr_read_generic, &spr_write_generic,
6270 0x00000000);
6271 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6272 SPR_NOACCESS, SPR_NOACCESS,
6273 &spr_read_generic, &spr_write_generic,
6274 0x00000000);
6275 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6276 &spr_read_generic, &spr_write_generic,
6277 &spr_read_generic, &spr_write_generic,
6278 0x00000000);
f2e63a42 6279#if !defined(CONFIG_USER_ONLY)
8eee0af9 6280 env->slb_nr = 64;
f2e63a42 6281#endif
e1833e1f 6282 init_excp_970(env);
d63001d1
JM		 6283 env->dcache_line_size = 128;
6284 env->icache_line_size = 128;
a750fc0b
JM		 6285 /* Allocate hardware IRQ controller */
6286 ppc970_irq_init(env);
cf8358c8
AJ		 6287 /* Can't find information on what this should be on reset. This
6288 * value is the one used by 74xx processors. */
6289 vscr_init(env, 0x00010000);
a750fc0b 6290}
a750fc0b
JM		 6291
6292/* PowerPC 970 GX */
082c6681
JM		 6293#define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6294 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6295 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6296 PPC_FLOAT_STFIWX | \
6297 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6298 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6299 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6300 PPC_64B | PPC_ALTIVEC | \
12de9a39 6301 PPC_SEGMENT_64B | PPC_SLBI)
a5858d7a 6302#define POWERPC_INSNS2_970GX (PPC_NONE)
a750fc0b 6303#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
12de9a39 6304#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
a750fc0b
JM		 6305#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6306#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
237c0af0 6307#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
25ba3a68 6308#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6309 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6310 POWERPC_FLAG_BUS_CLK)
a750fc0b 6311
2f462816
JM		 6312static int check_pow_970GX (CPUPPCState *env)
6313{
6314 if (env->spr[SPR_HID0] & 0x00600000)
6315 return 1;
6316
6317 return 0;
6318}
6319
a750fc0b
JM		 6320static void init_proc_970GX (CPUPPCState *env)
6321{
6322 gen_spr_ne_601(env);
6323 gen_spr_7xx(env);
6324 /* Time base */
6325 gen_tbl(env);
6326 /* Hardware implementation registers */
6327 /* XXX : not implemented */
6328 spr_register(env, SPR_HID0, "HID0",
6329 SPR_NOACCESS, SPR_NOACCESS,
06403421 6330 &spr_read_generic, &spr_write_clear,
d63001d1 6331 0x60000000);
a750fc0b
JM		 6332 /* XXX : not implemented */
6333 spr_register(env, SPR_HID1, "HID1",
6334 SPR_NOACCESS, SPR_NOACCESS,
6335 &spr_read_generic, &spr_write_generic,
6336 0x00000000);
6337 /* XXX : not implemented */
bd928eba 6338 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6339 SPR_NOACCESS, SPR_NOACCESS,
6340 &spr_read_generic, &spr_write_generic,
6341 0x00000000);
d63001d1
JM		 6342 /* XXX : not implemented */
6343 spr_register(env, SPR_970_HID5, "HID5",
6344 SPR_NOACCESS, SPR_NOACCESS,
6345 &spr_read_generic, &spr_write_generic,
417bf010 6346 POWERPC970_HID5_INIT);
bd928eba
JM		 6347 /* XXX : not implemented */
6348 spr_register(env, SPR_L2CR, "L2CR",
6349 SPR_NOACCESS, SPR_NOACCESS,
6350 &spr_read_generic, &spr_write_generic,
6351 0x00000000);
a750fc0b
JM		 6352 /* Memory management */
6353 /* XXX: not correct */
6354 gen_low_BATs(env);
12de9a39
JM		 6355 /* XXX : not implemented */
6356 spr_register(env, SPR_MMUCFG, "MMUCFG",
6357 SPR_NOACCESS, SPR_NOACCESS,
6358 &spr_read_generic, SPR_NOACCESS,
6359 0x00000000); /* TOFIX */
6360 /* XXX : not implemented */
6361 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6362 SPR_NOACCESS, SPR_NOACCESS,
6363 &spr_read_generic, &spr_write_generic,
6364 0x00000000); /* TOFIX */
6365 spr_register(env, SPR_HIOR, "SPR_HIOR",
6366 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6367 &spr_read_hior, &spr_write_hior,
6368 0x00000000);
f2e63a42 6369#if !defined(CONFIG_USER_ONLY)
12de9a39 6370 env->slb_nr = 32;
f2e63a42 6371#endif
e1833e1f 6372 init_excp_970(env);
d63001d1
JM		 6373 env->dcache_line_size = 128;
6374 env->icache_line_size = 128;
a750fc0b
JM		 6375 /* Allocate hardware IRQ controller */
6376 ppc970_irq_init(env);
cf8358c8
AJ		 6377 /* Can't find information on what this should be on reset. This
6378 * value is the one used by 74xx processors. */
6379 vscr_init(env, 0x00010000);
a750fc0b 6380}
a750fc0b 6381
2f462816 6382/* PowerPC 970 MP */
082c6681
JM		 6383#define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6384 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6385 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6386 PPC_FLOAT_STFIWX | \
6387 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6388 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6389 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
2f462816
JM		 6390 PPC_64B | PPC_ALTIVEC | \
6391 PPC_SEGMENT_64B | PPC_SLBI)
a5858d7a 6392#define POWERPC_INSNS2_970MP (PPC_NONE)
2f462816
JM		 6393#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6394#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6395#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6396#define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6397#define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6398#define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6399 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6400 POWERPC_FLAG_BUS_CLK)
2f462816
JM		 6401
6402static int check_pow_970MP (CPUPPCState *env)
6403{
6404 if (env->spr[SPR_HID0] & 0x01C00000)
6405 return 1;
6406
6407 return 0;
6408}
6409
6410static void init_proc_970MP (CPUPPCState *env)
6411{
6412 gen_spr_ne_601(env);
6413 gen_spr_7xx(env);
6414 /* Time base */
6415 gen_tbl(env);
6416 /* Hardware implementation registers */
6417 /* XXX : not implemented */
6418 spr_register(env, SPR_HID0, "HID0",
6419 SPR_NOACCESS, SPR_NOACCESS,
6420 &spr_read_generic, &spr_write_clear,
6421 0x60000000);
6422 /* XXX : not implemented */
6423 spr_register(env, SPR_HID1, "HID1",
6424 SPR_NOACCESS, SPR_NOACCESS,
6425 &spr_read_generic, &spr_write_generic,
6426 0x00000000);
6427 /* XXX : not implemented */
bd928eba 6428 spr_register(env, SPR_750FX_HID2, "HID2",
2f462816
JM		 6429 SPR_NOACCESS, SPR_NOACCESS,
6430 &spr_read_generic, &spr_write_generic,
6431 0x00000000);
6432 /* XXX : not implemented */
6433 spr_register(env, SPR_970_HID5, "HID5",
6434 SPR_NOACCESS, SPR_NOACCESS,
6435 &spr_read_generic, &spr_write_generic,
6436 POWERPC970_HID5_INIT);
bd928eba
JM		 6437 /* XXX : not implemented */
6438 spr_register(env, SPR_L2CR, "L2CR",
6439 SPR_NOACCESS, SPR_NOACCESS,
6440 &spr_read_generic, &spr_write_generic,
6441 0x00000000);
2f462816
JM		 6442 /* Memory management */
6443 /* XXX: not correct */
6444 gen_low_BATs(env);
6445 /* XXX : not implemented */
6446 spr_register(env, SPR_MMUCFG, "MMUCFG",
6447 SPR_NOACCESS, SPR_NOACCESS,
6448 &spr_read_generic, SPR_NOACCESS,
6449 0x00000000); /* TOFIX */
6450 /* XXX : not implemented */
6451 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6452 SPR_NOACCESS, SPR_NOACCESS,
6453 &spr_read_generic, &spr_write_generic,
6454 0x00000000); /* TOFIX */
6455 spr_register(env, SPR_HIOR, "SPR_HIOR",
6456 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6457 &spr_read_hior, &spr_write_hior,
6458 0x00000000);
2f462816
JM		 6459#if !defined(CONFIG_USER_ONLY)
6460 env->slb_nr = 32;
6461#endif
6462 init_excp_970(env);
6463 env->dcache_line_size = 128;
6464 env->icache_line_size = 128;
6465 /* Allocate hardware IRQ controller */
6466 ppc970_irq_init(env);
cf8358c8
AJ		 6467 /* Can't find information on what this should be on reset. This
6468 * value is the one used by 74xx processors. */
6469 vscr_init(env, 0x00010000);
2f462816
JM		 6470}
6471
9d52e907
DG		 6472#if defined(TARGET_PPC64)
6473/* POWER7 */
6474#define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6475 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6476 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6477 PPC_FLOAT_STFIWX | \
6478 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6479 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6480 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6481 PPC_64B | PPC_ALTIVEC | \
6482 PPC_SEGMENT_64B | PPC_SLBI | \
6483 PPC_POPCNTB | PPC_POPCNTWD)
a5858d7a 6484#define POWERPC_INSNS2_POWER7 (PPC_NONE)
9d52e907
DG		 6485#define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
6486#define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
6487#define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
6488#define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
6489#define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
6490#define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6491 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6492 POWERPC_FLAG_BUS_CLK)
6493#define check_pow_POWER7 check_pow_nocheck
6494
6495static void init_proc_POWER7 (CPUPPCState *env)
6496{
6497 gen_spr_ne_601(env);
6498 gen_spr_7xx(env);
6499 /* Time base */
6500 gen_tbl(env);
6501#if !defined(CONFIG_USER_ONLY)
6502 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6503 spr_register(env, SPR_PURR, "PURR",
6504 &spr_read_purr, SPR_NOACCESS,
6505 &spr_read_purr, SPR_NOACCESS,
6506 0x00000000);
6507 spr_register(env, SPR_SPURR, "SPURR",
6508 &spr_read_purr, SPR_NOACCESS,
6509 &spr_read_purr, SPR_NOACCESS,
6510 0x00000000);
6511#endif /* !CONFIG_USER_ONLY */
6512 /* Memory management */
6513 /* XXX : not implemented */
6514 spr_register(env, SPR_MMUCFG, "MMUCFG",
6515 SPR_NOACCESS, SPR_NOACCESS,
6516 &spr_read_generic, SPR_NOACCESS,
6517 0x00000000); /* TOFIX */
6518 /* XXX : not implemented */
6519 spr_register(env, SPR_CTRL, "SPR_CTRLT",
6520 SPR_NOACCESS, SPR_NOACCESS,
6521 &spr_read_generic, &spr_write_generic,
6522 0x80800000);
6523 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6524 SPR_NOACCESS, SPR_NOACCESS,
6525 &spr_read_generic, &spr_write_generic,
6526 0x80800000);
6527 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6528 &spr_read_generic, &spr_write_generic,
6529 &spr_read_generic, &spr_write_generic,
6530 0x00000000);
6531#if !defined(CONFIG_USER_ONLY)
6532 env->slb_nr = 32;
6533#endif
6534 init_excp_POWER7(env);
6535 env->dcache_line_size = 128;
6536 env->icache_line_size = 128;
6537 /* Allocate hardware IRQ controller */
6538 ppcPOWER7_irq_init(env);
6539 /* Can't find information on what this should be on reset. This
6540 * value is the one used by 74xx processors. */
6541 vscr_init(env, 0x00010000);
6542}
6543#endif /* TARGET_PPC64 */
6544
a750fc0b 6545/* PowerPC 620 */
082c6681
JM		 6546#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6547 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6548 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6549 PPC_FLOAT_STFIWX | \
6550 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6551 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6552 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6553 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 6554 PPC_64B | PPC_SLBI)
a5858d7a 6555#define POWERPC_INSNS2_620 (PPC_NONE)
add78955
JM		 6556#define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6557//#define POWERPC_MMU_620 (POWERPC_MMU_620)
a750fc0b 6558#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
faadf50e 6559#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
237c0af0 6560#define POWERPC_BFDM_620 (bfd_mach_ppc64)
4018bae9 6561#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
add78955 6562 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 6563#define check_pow_620 check_pow_nocheck /* Check this */
a750fc0b 6564
578bb252 6565__attribute__ (( unused ))
a750fc0b
JM		 6566static void init_proc_620 (CPUPPCState *env)
6567{
6568 gen_spr_ne_601(env);
6569 gen_spr_620(env);
6570 /* Time base */
6571 gen_tbl(env);
6572 /* Hardware implementation registers */
6573 /* XXX : not implemented */
6574 spr_register(env, SPR_HID0, "HID0",
6575 SPR_NOACCESS, SPR_NOACCESS,
6576 &spr_read_generic, &spr_write_generic,
6577 0x00000000);
6578 /* Memory management */
6579 gen_low_BATs(env);
e1833e1f 6580 init_excp_620(env);
d63001d1
JM		 6581 env->dcache_line_size = 64;
6582 env->icache_line_size = 64;
faadf50e
JM		 6583 /* Allocate hardware IRQ controller */
6584 ppc6xx_irq_init(env);
a750fc0b 6585}
a750fc0b
JM		 6586#endif /* defined (TARGET_PPC64) */
6587
6588/* Default 32 bits PowerPC target will be 604 */
6589#define CPU_POWERPC_PPC32 CPU_POWERPC_604
6590#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
a5858d7a 6591#define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
a750fc0b
JM		 6592#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6593#define POWERPC_MMU_PPC32 POWERPC_MMU_604
6594#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6595#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
237c0af0 6596#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
d26bfc9a 6597#define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
2f462816
JM		 6598#define check_pow_PPC32 check_pow_604
6599#define init_proc_PPC32 init_proc_604
a750fc0b
JM		 6600
6601/* Default 64 bits PowerPC target will be 970 FX */
6602#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6603#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
a5858d7a 6604#define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
a750fc0b
JM		 6605#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6606#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6607#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6608#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
237c0af0 6609#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
d26bfc9a 6610#define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
2f462816
JM		 6611#define check_pow_PPC64 check_pow_970FX
6612#define init_proc_PPC64 init_proc_970FX
a750fc0b
JM		 6613
6614/* Default PowerPC target will be PowerPC 32 */
6615#if defined (TARGET_PPC64) && 0 // XXX: TODO
a5858d7a
AG		 6616#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6617#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6618#define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC64
6619#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6620#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6621#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6622#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6623#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
6624#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
6625#define check_pow_DEFAULT check_pow_PPC64
6626#define init_proc_DEFAULT init_proc_PPC64
a750fc0b 6627#else
a5858d7a
AG		 6628#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6629#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6630#define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC32
6631#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6632#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6633#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6634#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6635#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
6636#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
6637#define check_pow_DEFAULT check_pow_PPC32
6638#define init_proc_DEFAULT init_proc_PPC32
a750fc0b
JM		 6639#endif
6640
6641/*****************************************************************************/
6642/* PVR definitions for most known PowerPC */
6643enum {
6644 /* PowerPC 401 family */
6645 /* Generic PowerPC 401 */
80d11f44 6646#define CPU_POWERPC_401 CPU_POWERPC_401G2
a750fc0b 6647 /* PowerPC 401 cores */
80d11f44
JM		 6648 CPU_POWERPC_401A1 = 0x00210000,
6649 CPU_POWERPC_401B2 = 0x00220000,
a750fc0b 6650#if 0
80d11f44 6651 CPU_POWERPC_401B3 = xxx,
a750fc0b 6652#endif
80d11f44
JM		 6653 CPU_POWERPC_401C2 = 0x00230000,
6654 CPU_POWERPC_401D2 = 0x00240000,
6655 CPU_POWERPC_401E2 = 0x00250000,
6656 CPU_POWERPC_401F2 = 0x00260000,
6657 CPU_POWERPC_401G2 = 0x00270000,
a750fc0b
JM		 6658 /* PowerPC 401 microcontrolers */
6659#if 0
80d11f44 6660 CPU_POWERPC_401GF = xxx,
a750fc0b 6661#endif
80d11f44 6662#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
a750fc0b 6663 /* IBM Processor for Network Resources */
80d11f44 6664 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
a750fc0b 6665#if 0
80d11f44 6666 CPU_POWERPC_XIPCHIP = xxx,
a750fc0b
JM		 6667#endif
6668 /* PowerPC 403 family */
6669 /* Generic PowerPC 403 */
80d11f44 6670#define CPU_POWERPC_403 CPU_POWERPC_403GC
a750fc0b 6671 /* PowerPC 403 microcontrollers */
80d11f44
JM		 6672 CPU_POWERPC_403GA = 0x00200011,
6673 CPU_POWERPC_403GB = 0x00200100,
6674 CPU_POWERPC_403GC = 0x00200200,
6675 CPU_POWERPC_403GCX = 0x00201400,
a750fc0b 6676#if 0
80d11f44 6677 CPU_POWERPC_403GP = xxx,
a750fc0b
JM		 6678#endif
6679 /* PowerPC 405 family */
6680 /* Generic PowerPC 405 */
80d11f44 6681#define CPU_POWERPC_405 CPU_POWERPC_405D4
a750fc0b
JM		 6682 /* PowerPC 405 cores */
6683#if 0
80d11f44 6684 CPU_POWERPC_405A3 = xxx,
a750fc0b
JM		 6685#endif
6686#if 0
80d11f44 6687 CPU_POWERPC_405A4 = xxx,
a750fc0b
JM		 6688#endif
6689#if 0
80d11f44 6690 CPU_POWERPC_405B3 = xxx,
a750fc0b
JM		 6691#endif
6692#if 0
80d11f44 6693 CPU_POWERPC_405B4 = xxx,
a750fc0b
JM		 6694#endif
6695#if 0
80d11f44 6696 CPU_POWERPC_405C3 = xxx,
a750fc0b
JM		 6697#endif
6698#if 0
80d11f44 6699 CPU_POWERPC_405C4 = xxx,
a750fc0b 6700#endif
80d11f44 6701 CPU_POWERPC_405D2 = 0x20010000,
a750fc0b 6702#if 0
80d11f44 6703 CPU_POWERPC_405D3 = xxx,
a750fc0b 6704#endif
80d11f44 6705 CPU_POWERPC_405D4 = 0x41810000,
a750fc0b 6706#if 0
80d11f44 6707 CPU_POWERPC_405D5 = xxx,
a750fc0b
JM		 6708#endif
6709#if 0
80d11f44 6710 CPU_POWERPC_405E4 = xxx,
a750fc0b
JM		 6711#endif
6712#if 0
80d11f44 6713 CPU_POWERPC_405F4 = xxx,
a750fc0b
JM		 6714#endif
6715#if 0
80d11f44 6716 CPU_POWERPC_405F5 = xxx,
a750fc0b
JM		 6717#endif
6718#if 0
80d11f44 6719 CPU_POWERPC_405F6 = xxx,
a750fc0b
JM		 6720#endif
6721 /* PowerPC 405 microcontrolers */
6722 /* XXX: missing 0x200108a0 */
80d11f44
JM		 6723#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6724 CPU_POWERPC_405CRa = 0x40110041,
6725 CPU_POWERPC_405CRb = 0x401100C5,
6726 CPU_POWERPC_405CRc = 0x40110145,
6727 CPU_POWERPC_405EP = 0x51210950,
a750fc0b 6728#if 0
80d11f44 6729 CPU_POWERPC_405EXr = xxx,
a750fc0b 6730#endif
80d11f44 6731 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
a750fc0b 6732#if 0
80d11f44
JM		 6733 CPU_POWERPC_405FX = xxx,
6734#endif
6735#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6736 CPU_POWERPC_405GPa = 0x40110000,
6737 CPU_POWERPC_405GPb = 0x40110040,
6738 CPU_POWERPC_405GPc = 0x40110082,
6739 CPU_POWERPC_405GPd = 0x401100C4,
6740#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6741 CPU_POWERPC_405GPR = 0x50910951,
a750fc0b 6742#if 0
80d11f44 6743 CPU_POWERPC_405H = xxx,
a750fc0b
JM		 6744#endif
6745#if 0
80d11f44 6746 CPU_POWERPC_405L = xxx,
a750fc0b 6747#endif
80d11f44 6748 CPU_POWERPC_405LP = 0x41F10000,
a750fc0b 6749#if 0
80d11f44 6750 CPU_POWERPC_405PM = xxx,
a750fc0b
JM		 6751#endif
6752#if 0
80d11f44 6753 CPU_POWERPC_405PS = xxx,
a750fc0b
JM		 6754#endif
6755#if 0
80d11f44 6756 CPU_POWERPC_405S = xxx,
a750fc0b
JM		 6757#endif
6758 /* IBM network processors */
80d11f44
JM		 6759 CPU_POWERPC_NPE405H = 0x414100C0,
6760 CPU_POWERPC_NPE405H2 = 0x41410140,
6761 CPU_POWERPC_NPE405L = 0x416100C0,
6762 CPU_POWERPC_NPE4GS3 = 0x40B10000,
a750fc0b 6763#if 0
80d11f44 6764 CPU_POWERPC_NPCxx1 = xxx,
a750fc0b
JM		 6765#endif
6766#if 0
80d11f44 6767 CPU_POWERPC_NPR161 = xxx,
a750fc0b
JM		 6768#endif
6769#if 0
80d11f44 6770 CPU_POWERPC_LC77700 = xxx,
a750fc0b
JM		 6771#endif
6772 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6773#if 0
80d11f44 6774 CPU_POWERPC_STB01000 = xxx,
a750fc0b
JM		 6775#endif
6776#if 0
80d11f44 6777 CPU_POWERPC_STB01010 = xxx,
a750fc0b
JM		 6778#endif
6779#if 0
80d11f44 6780 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
a750fc0b 6781#endif
80d11f44 6782 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
a750fc0b 6783#if 0
80d11f44 6784 CPU_POWERPC_STB043 = xxx,
a750fc0b
JM		 6785#endif
6786#if 0
80d11f44 6787 CPU_POWERPC_STB045 = xxx,
a750fc0b 6788#endif
80d11f44
JM		 6789 CPU_POWERPC_STB04 = 0x41810000,
6790 CPU_POWERPC_STB25 = 0x51510950,
a750fc0b 6791#if 0
80d11f44 6792 CPU_POWERPC_STB130 = xxx,
a750fc0b
JM		 6793#endif
6794 /* Xilinx cores */
80d11f44
JM		 6795 CPU_POWERPC_X2VP4 = 0x20010820,
6796#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6797 CPU_POWERPC_X2VP20 = 0x20010860,
6798#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
a750fc0b 6799#if 0
80d11f44 6800 CPU_POWERPC_ZL10310 = xxx,
a750fc0b
JM		 6801#endif
6802#if 0
80d11f44 6803 CPU_POWERPC_ZL10311 = xxx,
a750fc0b
JM		 6804#endif
6805#if 0
80d11f44 6806 CPU_POWERPC_ZL10320 = xxx,
a750fc0b
JM		 6807#endif
6808#if 0
80d11f44 6809 CPU_POWERPC_ZL10321 = xxx,
a750fc0b
JM		 6810#endif
6811 /* PowerPC 440 family */
6812 /* Generic PowerPC 440 */
80d11f44 6813#define CPU_POWERPC_440 CPU_POWERPC_440GXf
a750fc0b
JM		 6814 /* PowerPC 440 cores */
6815#if 0
80d11f44 6816 CPU_POWERPC_440A4 = xxx,
a750fc0b 6817#endif
95070372 6818 CPU_POWERPC_440_XILINX = 0x7ff21910,
a750fc0b 6819#if 0
80d11f44 6820 CPU_POWERPC_440A5 = xxx,
a750fc0b
JM		 6821#endif
6822#if 0
80d11f44 6823 CPU_POWERPC_440B4 = xxx,
a750fc0b
JM		 6824#endif
6825#if 0
80d11f44 6826 CPU_POWERPC_440F5 = xxx,
a750fc0b
JM		 6827#endif
6828#if 0
80d11f44 6829 CPU_POWERPC_440G5 = xxx,
a750fc0b
JM		 6830#endif
6831#if 0
80d11f44 6832 CPU_POWERPC_440H4 = xxx,
a750fc0b
JM		 6833#endif
6834#if 0
80d11f44 6835 CPU_POWERPC_440H6 = xxx,
a750fc0b
JM		 6836#endif
6837 /* PowerPC 440 microcontrolers */
80d11f44
JM		 6838#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6839 CPU_POWERPC_440EPa = 0x42221850,
6840 CPU_POWERPC_440EPb = 0x422218D3,
6841#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6842 CPU_POWERPC_440GPb = 0x40120440,
6843 CPU_POWERPC_440GPc = 0x40120481,
6844#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6845#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6846 CPU_POWERPC_440GRX = 0x200008D0,
6847#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6848#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6849 CPU_POWERPC_440GXa = 0x51B21850,
6850 CPU_POWERPC_440GXb = 0x51B21851,
6851 CPU_POWERPC_440GXc = 0x51B21892,
6852 CPU_POWERPC_440GXf = 0x51B21894,
a750fc0b 6853#if 0
80d11f44 6854 CPU_POWERPC_440S = xxx,
a750fc0b 6855#endif
80d11f44
JM		 6856 CPU_POWERPC_440SP = 0x53221850,
6857 CPU_POWERPC_440SP2 = 0x53221891,
6858 CPU_POWERPC_440SPE = 0x53421890,
a750fc0b
JM		 6859 /* PowerPC 460 family */
6860#if 0
6861 /* Generic PowerPC 464 */
80d11f44 6862#define CPU_POWERPC_464 CPU_POWERPC_464H90
a750fc0b
JM		 6863#endif
6864 /* PowerPC 464 microcontrolers */
6865#if 0
80d11f44 6866 CPU_POWERPC_464H90 = xxx,
a750fc0b
JM		 6867#endif
6868#if 0
80d11f44 6869 CPU_POWERPC_464H90FP = xxx,
a750fc0b
JM		 6870#endif
6871 /* Freescale embedded PowerPC cores */
c3e36823 6872 /* PowerPC MPC 5xx cores (aka RCPU) */
80d11f44
JM		 6873 CPU_POWERPC_MPC5xx = 0x00020020,
6874#define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6875#define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6876#define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6877#define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6878#define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6879#define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6880#define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6881#define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6882#define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6883#define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6884#define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6885#define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6886#define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
c3e36823 6887 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
80d11f44
JM		 6888 CPU_POWERPC_MPC8xx = 0x00500000,
6889#define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6890#define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6891#define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
6892#define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
6893#define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
6894#define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
6895#define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
6896#define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
6897#define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
6898#define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
6899#define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
6900#define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
6901#define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
6902#define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
6903#define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
c3e36823 6904 /* G2 cores (aka PowerQUICC-II) */
80d11f44
JM		 6905 CPU_POWERPC_G2 = 0x00810011,
6906 CPU_POWERPC_G2H4 = 0x80811010,
6907 CPU_POWERPC_G2gp = 0x80821010,
6908 CPU_POWERPC_G2ls = 0x90810010,
6909 CPU_POWERPC_MPC603 = 0x00810100,
6910 CPU_POWERPC_G2_HIP3 = 0x00810101,
6911 CPU_POWERPC_G2_HIP4 = 0x80811014,
c3e36823 6912 /* G2_LE core (aka PowerQUICC-II) */
80d11f44
JM		 6913 CPU_POWERPC_G2LE = 0x80820010,
6914 CPU_POWERPC_G2LEgp = 0x80822010,
6915 CPU_POWERPC_G2LEls = 0xA0822010,
6916 CPU_POWERPC_G2LEgp1 = 0x80822011,
6917 CPU_POWERPC_G2LEgp3 = 0x80822013,
6918 /* MPC52xx microcontrollers */
c3e36823 6919 /* XXX: MPC 5121 ? */
80d11f44
JM		 6920#define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
6921#define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
6922#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
6923#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
6924#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
6925#define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
6926#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
6927#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
6928 /* MPC82xx microcontrollers */
6929#define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
6930#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
6931#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
6932#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
6933#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
6934#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
6935#define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
6936#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
6937#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
6938#define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
6939#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
6940#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
6941#define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
6942#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
6943#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
6944#define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
6945#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
6946#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
6947#define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
6948#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
6949#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
6950#define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
6951#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
6952#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
6953#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
6954#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
6955#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
6956#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
6957#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
a750fc0b 6958 /* e200 family */
80d11f44
JM		 6959 /* e200 cores */
6960#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
a750fc0b 6961#if 0
80d11f44 6962 CPU_POWERPC_e200z0 = xxx,
a750fc0b
JM		 6963#endif
6964#if 0
80d11f44 6965 CPU_POWERPC_e200z1 = xxx,
c3e36823
JM		 6966#endif
6967#if 0 /* ? */
80d11f44
JM		 6968 CPU_POWERPC_e200z3 = 0x81120000,
6969#endif
6970 CPU_POWERPC_e200z5 = 0x81000000,
6971 CPU_POWERPC_e200z6 = 0x81120000,
6972 /* MPC55xx microcontrollers */
6973#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
6974#if 0
6975#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
6976#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
6977#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
6978#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
6979#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
6980#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
6981#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
6982#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
6983#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
6984#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
6985#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
6986#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
6987#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
6988#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
6989#endif
6990#if 0
6991#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
6992#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
6993#endif
6994#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
6995#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
6996#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
6997#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
6998#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
6999#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
a750fc0b 7000 /* e300 family */
80d11f44
JM		 7001 /* e300 cores */
7002#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
7003 CPU_POWERPC_e300c1 = 0x00830010,
7004 CPU_POWERPC_e300c2 = 0x00840010,
7005 CPU_POWERPC_e300c3 = 0x00850010,
7006 CPU_POWERPC_e300c4 = 0x00860010,
7007 /* MPC83xx microcontrollers */
74d77cae
TM		 7008#define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
7009#define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
7010#define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
7011#define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
7012#define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
7013#define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
a750fc0b 7014 /* e500 family */
80d11f44
JM		 7015 /* e500 cores */
7016#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
bd5ea513 7017#define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
80d11f44 7018#define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
bd5ea513
AJ		 7019 CPU_POWERPC_e500v1_v10 = 0x80200010,
7020 CPU_POWERPC_e500v1_v20 = 0x80200020,
80d11f44
JM		 7021 CPU_POWERPC_e500v2_v10 = 0x80210010,
7022 CPU_POWERPC_e500v2_v11 = 0x80210011,
7023 CPU_POWERPC_e500v2_v20 = 0x80210020,
7024 CPU_POWERPC_e500v2_v21 = 0x80210021,
7025 CPU_POWERPC_e500v2_v22 = 0x80210022,
7026 CPU_POWERPC_e500v2_v30 = 0x80210030,
7027 /* MPC85xx microcontrollers */
7028#define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
7029#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
7030#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
7031#define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
7032#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
7033#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
7034#define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
bd5ea513
AJ		 7035#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
7036#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
7037#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
80d11f44 7038#define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
bd5ea513
AJ		 7039#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
7040#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
80d11f44 7041#define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
bd5ea513
AJ		 7042#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
7043#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
80d11f44
JM		 7044#define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
7045#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
7046#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
7047#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
7048#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
7049#define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
7050#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
7051#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
7052#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
7053#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
7054#define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
7055#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
7056#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
7057#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
7058#define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
7059#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
7060#define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
7061#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
7062#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
7063#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
7064#define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
7065#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
7066#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
7067#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
7068#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
7069#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
7070#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
7071#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
7072#define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
7073#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
7074#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
7075#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
7076#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
7077#define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
7078#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
7079#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
7080#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
7081#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
7082#define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
7083#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
7084#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
7085#define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
7086#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
7087#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
7088#define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
7089#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
7090#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
7091#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
7092#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
7093#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
7094#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
7095#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
7096#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
7097#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
a750fc0b 7098 /* e600 family */
80d11f44
JM		 7099 /* e600 cores */
7100 CPU_POWERPC_e600 = 0x80040010,
7101 /* MPC86xx microcontrollers */
7102#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
7103#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
7104#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
a750fc0b 7105 /* PowerPC 6xx cores */
80d11f44
JM		 7106#define CPU_POWERPC_601 CPU_POWERPC_601_v2
7107 CPU_POWERPC_601_v0 = 0x00010001,
7108 CPU_POWERPC_601_v1 = 0x00010001,
bd928eba 7109#define CPU_POWERPC_601v CPU_POWERPC_601_v2
80d11f44
JM		 7110 CPU_POWERPC_601_v2 = 0x00010002,
7111 CPU_POWERPC_602 = 0x00050100,
7112 CPU_POWERPC_603 = 0x00030100,
7113#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
7114 CPU_POWERPC_603E_v11 = 0x00060101,
7115 CPU_POWERPC_603E_v12 = 0x00060102,
7116 CPU_POWERPC_603E_v13 = 0x00060103,
7117 CPU_POWERPC_603E_v14 = 0x00060104,
7118 CPU_POWERPC_603E_v22 = 0x00060202,
7119 CPU_POWERPC_603E_v3 = 0x00060300,
7120 CPU_POWERPC_603E_v4 = 0x00060400,
7121 CPU_POWERPC_603E_v41 = 0x00060401,
7122 CPU_POWERPC_603E7t = 0x00071201,
7123 CPU_POWERPC_603E7v = 0x00070100,
7124 CPU_POWERPC_603E7v1 = 0x00070101,
7125 CPU_POWERPC_603E7v2 = 0x00070201,
7126 CPU_POWERPC_603E7 = 0x00070200,
7127 CPU_POWERPC_603P = 0x00070000,
7128#define CPU_POWERPC_603R CPU_POWERPC_603E7t
c3e36823 7129 /* XXX: missing 0x00040303 (604) */
80d11f44
JM		 7130 CPU_POWERPC_604 = 0x00040103,
7131#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
c3e36823
JM		 7132 /* XXX: missing 0x00091203 */
7133 /* XXX: missing 0x00092110 */
7134 /* XXX: missing 0x00092120 */
80d11f44
JM		 7135 CPU_POWERPC_604E_v10 = 0x00090100,
7136 CPU_POWERPC_604E_v22 = 0x00090202,
7137 CPU_POWERPC_604E_v24 = 0x00090204,
c3e36823
JM		 7138 /* XXX: missing 0x000a0100 */
7139 /* XXX: missing 0x00093102 */
80d11f44 7140 CPU_POWERPC_604R = 0x000a0101,
a750fc0b 7141#if 0
80d11f44 7142 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
a750fc0b
JM		 7143#endif
7144 /* PowerPC 740/750 cores (aka G3) */
7145 /* XXX: missing 0x00084202 */
80d11f44 7146#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
bd928eba 7147 CPU_POWERPC_7x0_v10 = 0x00080100,
80d11f44
JM		 7148 CPU_POWERPC_7x0_v20 = 0x00080200,
7149 CPU_POWERPC_7x0_v21 = 0x00080201,
7150 CPU_POWERPC_7x0_v22 = 0x00080202,
7151 CPU_POWERPC_7x0_v30 = 0x00080300,
7152 CPU_POWERPC_7x0_v31 = 0x00080301,
7153 CPU_POWERPC_740E = 0x00080100,
bd928eba 7154 CPU_POWERPC_750E = 0x00080200,
80d11f44 7155 CPU_POWERPC_7x0P = 0x10080000,
a750fc0b 7156 /* XXX: missing 0x00087010 (CL ?) */
bd928eba
JM		 7157#define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
7158 CPU_POWERPC_750CL_v10 = 0x00087200,
7159 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
80d11f44 7160#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
bd928eba
JM		 7161 CPU_POWERPC_750CX_v10 = 0x00082100,
7162 CPU_POWERPC_750CX_v20 = 0x00082200,
80d11f44
JM		 7163 CPU_POWERPC_750CX_v21 = 0x00082201,
7164 CPU_POWERPC_750CX_v22 = 0x00082202,
7165#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
7166 CPU_POWERPC_750CXE_v21 = 0x00082211,
7167 CPU_POWERPC_750CXE_v22 = 0x00082212,
7168 CPU_POWERPC_750CXE_v23 = 0x00082213,
7169 CPU_POWERPC_750CXE_v24 = 0x00082214,
7170 CPU_POWERPC_750CXE_v24b = 0x00083214,
bd928eba
JM		 7171 CPU_POWERPC_750CXE_v30 = 0x00082310,
7172 CPU_POWERPC_750CXE_v31 = 0x00082311,
80d11f44
JM		 7173 CPU_POWERPC_750CXE_v31b = 0x00083311,
7174 CPU_POWERPC_750CXR = 0x00083410,
bd928eba 7175 CPU_POWERPC_750FL = 0x70000203,
80d11f44
JM		 7176#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
7177 CPU_POWERPC_750FX_v10 = 0x70000100,
7178 CPU_POWERPC_750FX_v20 = 0x70000200,
7179 CPU_POWERPC_750FX_v21 = 0x70000201,
7180 CPU_POWERPC_750FX_v22 = 0x70000202,
7181 CPU_POWERPC_750FX_v23 = 0x70000203,
7182 CPU_POWERPC_750GL = 0x70020102,
7183#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
7184 CPU_POWERPC_750GX_v10 = 0x70020100,
7185 CPU_POWERPC_750GX_v11 = 0x70020101,
7186 CPU_POWERPC_750GX_v12 = 0x70020102,
7187#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
bd928eba
JM		 7188 CPU_POWERPC_750L_v20 = 0x00088200,
7189 CPU_POWERPC_750L_v21 = 0x00088201,
80d11f44
JM		 7190 CPU_POWERPC_750L_v22 = 0x00088202,
7191 CPU_POWERPC_750L_v30 = 0x00088300,
7192 CPU_POWERPC_750L_v32 = 0x00088302,
a750fc0b 7193 /* PowerPC 745/755 cores */
80d11f44
JM		 7194#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
7195 CPU_POWERPC_7x5_v10 = 0x00083100,
7196 CPU_POWERPC_7x5_v11 = 0x00083101,
7197 CPU_POWERPC_7x5_v20 = 0x00083200,
7198 CPU_POWERPC_7x5_v21 = 0x00083201,
7199 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
7200 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
7201 CPU_POWERPC_7x5_v24 = 0x00083204,
7202 CPU_POWERPC_7x5_v25 = 0x00083205,
7203 CPU_POWERPC_7x5_v26 = 0x00083206,
7204 CPU_POWERPC_7x5_v27 = 0x00083207,
7205 CPU_POWERPC_7x5_v28 = 0x00083208,
a750fc0b 7206#if 0
80d11f44 7207 CPU_POWERPC_7x5P = xxx,
a750fc0b
JM		 7208#endif
7209 /* PowerPC 74xx cores (aka G4) */
7210 /* XXX: missing 0x000C1101 */
80d11f44
JM		 7211#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
7212 CPU_POWERPC_7400_v10 = 0x000C0100,
7213 CPU_POWERPC_7400_v11 = 0x000C0101,
7214 CPU_POWERPC_7400_v20 = 0x000C0200,
4e777442 7215 CPU_POWERPC_7400_v21 = 0x000C0201,
80d11f44
JM		 7216 CPU_POWERPC_7400_v22 = 0x000C0202,
7217 CPU_POWERPC_7400_v26 = 0x000C0206,
7218 CPU_POWERPC_7400_v27 = 0x000C0207,
7219 CPU_POWERPC_7400_v28 = 0x000C0208,
7220 CPU_POWERPC_7400_v29 = 0x000C0209,
7221#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
7222 CPU_POWERPC_7410_v10 = 0x800C1100,
7223 CPU_POWERPC_7410_v11 = 0x800C1101,
7224 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
7225 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
7226 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
7227#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
7228 CPU_POWERPC_7448_v10 = 0x80040100,
7229 CPU_POWERPC_7448_v11 = 0x80040101,
7230 CPU_POWERPC_7448_v20 = 0x80040200,
7231 CPU_POWERPC_7448_v21 = 0x80040201,
7232#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
7233 CPU_POWERPC_7450_v10 = 0x80000100,
7234 CPU_POWERPC_7450_v11 = 0x80000101,
7235 CPU_POWERPC_7450_v12 = 0x80000102,
4e777442 7236 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
80d11f44 7237 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4e777442
JM		 7238#define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
7239 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
7240 /* XXX: this entry might be a bug in some documentation */
7241 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
80d11f44
JM		 7242#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
7243 CPU_POWERPC_74x5_v10 = 0x80010100,
c3e36823 7244 /* XXX: missing 0x80010200 */
80d11f44
JM		 7245 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
7246 CPU_POWERPC_74x5_v32 = 0x80010302,
7247 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
7248 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
7249#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
80d11f44 7250 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
082c6681 7251 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
80d11f44 7252 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
082c6681
JM		 7253#define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
7254 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
7255 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
7256 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
a750fc0b 7257 /* 64 bits PowerPC */
00af685f 7258#if defined(TARGET_PPC64)
80d11f44
JM		 7259 CPU_POWERPC_620 = 0x00140000,
7260 CPU_POWERPC_630 = 0x00400000,
7261 CPU_POWERPC_631 = 0x00410104,
7262 CPU_POWERPC_POWER4 = 0x00350000,
7263 CPU_POWERPC_POWER4P = 0x00380000,
c3e36823 7264 /* XXX: missing 0x003A0201 */
80d11f44
JM		 7265 CPU_POWERPC_POWER5 = 0x003A0203,
7266#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7267 CPU_POWERPC_POWER5P = 0x003B0000,
7268#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7269 CPU_POWERPC_POWER6 = 0x003E0000,
7270 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
7271 CPU_POWERPC_POWER6A = 0x0F000002,
9d52e907
DG		 7272#define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
7273 CPU_POWERPC_POWER7_v20 = 0x003F0200,
80d11f44
JM		 7274 CPU_POWERPC_970 = 0x00390202,
7275#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
7276 CPU_POWERPC_970FX_v10 = 0x00391100,
7277 CPU_POWERPC_970FX_v20 = 0x003C0200,
7278 CPU_POWERPC_970FX_v21 = 0x003C0201,
7279 CPU_POWERPC_970FX_v30 = 0x003C0300,
7280 CPU_POWERPC_970FX_v31 = 0x003C0301,
7281 CPU_POWERPC_970GX = 0x00450000,
7282#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
7283 CPU_POWERPC_970MP_v10 = 0x00440100,
7284 CPU_POWERPC_970MP_v11 = 0x00440101,
7285#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7286 CPU_POWERPC_CELL_v10 = 0x00700100,
7287 CPU_POWERPC_CELL_v20 = 0x00700400,
7288 CPU_POWERPC_CELL_v30 = 0x00700500,
7289 CPU_POWERPC_CELL_v31 = 0x00700501,
7290#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7291 CPU_POWERPC_RS64 = 0x00330000,
7292 CPU_POWERPC_RS64II = 0x00340000,
7293 CPU_POWERPC_RS64III = 0x00360000,
7294 CPU_POWERPC_RS64IV = 0x00370000,
00af685f 7295#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 7296 /* Original POWER */
7297 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7298 * POWER2 (RIOS2) & RSC2 (P2SC) here
7299 */
7300#if 0
80d11f44 7301 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
a750fc0b
JM		 7302#endif
7303#if 0
80d11f44 7304 CPU_POWER2 = xxx, /* 0x40000 ? */
a750fc0b
JM		 7305#endif
7306 /* PA Semi core */
80d11f44 7307 CPU_POWERPC_PA6T = 0x00900000,
a750fc0b
JM		 7308};
7309
7310/* System version register (used on MPC 8xxx) */
7311enum {
80d11f44
JM		 7312 POWERPC_SVR_NONE = 0x00000000,
7313#define POWERPC_SVR_52xx POWERPC_SVR_5200
7314#define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7315 POWERPC_SVR_5200_v10 = 0x80110010,
7316 POWERPC_SVR_5200_v11 = 0x80110011,
7317 POWERPC_SVR_5200_v12 = 0x80110012,
7318#define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7319 POWERPC_SVR_5200B_v20 = 0x80110020,
7320 POWERPC_SVR_5200B_v21 = 0x80110021,
7321#define POWERPC_SVR_55xx POWERPC_SVR_5567
c3e36823 7322#if 0
80d11f44 7323 POWERPC_SVR_5533 = xxx,
c3e36823
JM		 7324#endif
7325#if 0
80d11f44 7326 POWERPC_SVR_5534 = xxx,
c3e36823
JM		 7327#endif
7328#if 0
80d11f44 7329 POWERPC_SVR_5553 = xxx,
c3e36823
JM		 7330#endif
7331#if 0
80d11f44 7332 POWERPC_SVR_5554 = xxx,
c3e36823
JM		 7333#endif
7334#if 0
80d11f44 7335 POWERPC_SVR_5561 = xxx,
c3e36823
JM		 7336#endif
7337#if 0
80d11f44 7338 POWERPC_SVR_5565 = xxx,
c3e36823
JM		 7339#endif
7340#if 0
80d11f44 7341 POWERPC_SVR_5566 = xxx,
c3e36823
JM		 7342#endif
7343#if 0
80d11f44 7344 POWERPC_SVR_5567 = xxx,
c3e36823
JM		 7345#endif
7346#if 0
80d11f44 7347 POWERPC_SVR_8313 = xxx,
c3e36823
JM		 7348#endif
7349#if 0
80d11f44 7350 POWERPC_SVR_8313E = xxx,
c3e36823
JM		 7351#endif
7352#if 0
80d11f44 7353 POWERPC_SVR_8314 = xxx,
c3e36823
JM		 7354#endif
7355#if 0
80d11f44 7356 POWERPC_SVR_8314E = xxx,
c3e36823
JM		 7357#endif
7358#if 0
80d11f44 7359 POWERPC_SVR_8315 = xxx,
c3e36823
JM		 7360#endif
7361#if 0
80d11f44 7362 POWERPC_SVR_8315E = xxx,
c3e36823
JM		 7363#endif
7364#if 0
80d11f44 7365 POWERPC_SVR_8321 = xxx,
c3e36823
JM		 7366#endif
7367#if 0
80d11f44 7368 POWERPC_SVR_8321E = xxx,
c3e36823
JM		 7369#endif
7370#if 0
80d11f44 7371 POWERPC_SVR_8323 = xxx,
c3e36823
JM		 7372#endif
7373#if 0
80d11f44
JM		 7374 POWERPC_SVR_8323E = xxx,
7375#endif
492d7bf5 7376 POWERPC_SVR_8343 = 0x80570010,
80d11f44 7377 POWERPC_SVR_8343A = 0x80570030,
492d7bf5 7378 POWERPC_SVR_8343E = 0x80560010,
80d11f44 7379 POWERPC_SVR_8343EA = 0x80560030,
492d7bf5
TM		 7380#define POWERPC_SVR_8347 POWERPC_SVR_8347T
7381 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7382 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
80d11f44
JM		 7383#define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7384 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7385 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
492d7bf5
TM		 7386#define POWERPC_SVR_8347E POWERPC_SVR_8347ET
7387 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7388 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
80d11f44
JM		 7389#define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7390 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7391 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7392 POWERPC_SVR_8349 = 0x80510010,
7393 POWERPC_SVR_8349A = 0x80510030,
7394 POWERPC_SVR_8349E = 0x80500010,
7395 POWERPC_SVR_8349EA = 0x80500030,
c3e36823 7396#if 0
80d11f44 7397 POWERPC_SVR_8358E = xxx,
c3e36823
JM		 7398#endif
7399#if 0
80d11f44
JM		 7400 POWERPC_SVR_8360E = xxx,
7401#endif
7402#define POWERPC_SVR_E500 0x40000000
7403 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7404 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7405 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7406 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7407 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7408 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7409#define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7410 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7411 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7412#define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7413 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7414 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7415#define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7416 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7417 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7418 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7419#define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7420 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7421 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7422#define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7423 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7424 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7425#define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7426 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7427 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7428 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7429 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7430#define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7431 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7432 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7433 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7434 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7435#define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7436 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7437 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7438#define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7439 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7440 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7441#define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7442 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7443 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7444#define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7445 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7446 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7447#define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7448 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7449 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7450#define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7451 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7452 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7453 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7454 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7455#define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7456 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7457 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7458 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7459 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7460#define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7461 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7462 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7463#define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7464 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7465 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7466#define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7467 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7468 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7469 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7470 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7471 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7472 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7473 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7474 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7475 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
c3e36823 7476#if 0
80d11f44 7477 POWERPC_SVR_8610 = xxx,
c3e36823 7478#endif
80d11f44
JM		 7479 POWERPC_SVR_8641 = 0x80900021,
7480 POWERPC_SVR_8641D = 0x80900121,
a750fc0b
JM		 7481};
7482
3fc6c082 7483/*****************************************************************************/
a750fc0b 7484/* PowerPC CPU definitions */
80d11f44 7485#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
a750fc0b 7486 { \
a5858d7a
AG		 7487 .name = _name, \
7488 .pvr = _pvr, \
7489 .svr = _svr, \
7490 .insns_flags = glue(POWERPC_INSNS_,_type), \
7491 .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
7492 .msr_mask = glue(POWERPC_MSRM_,_type), \
7493 .mmu_model = glue(POWERPC_MMU_,_type), \
7494 .excp_model = glue(POWERPC_EXCP_,_type), \
7495 .bus_model = glue(POWERPC_INPUT_,_type), \
7496 .bfd_mach = glue(POWERPC_BFDM_,_type), \
7497 .flags = glue(POWERPC_FLAG_,_type), \
7498 .init_proc = &glue(init_proc_,_type), \
7499 .check_pow = &glue(check_pow_,_type), \
a750fc0b 7500 }
80d11f44
JM		 7501#define POWERPC_DEF(_name, _pvr, _type) \
7502POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
a750fc0b 7503
c227f099 7504static const ppc_def_t ppc_defs[] = {
a750fc0b
JM		 7505 /* Embedded PowerPC */
7506 /* PowerPC 401 family */
2662a059 7507 /* Generic PowerPC 401 */
80d11f44 7508 POWERPC_DEF("401", CPU_POWERPC_401, 401),
a750fc0b 7509 /* PowerPC 401 cores */
2662a059 7510 /* PowerPC 401A1 */
80d11f44 7511 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
a750fc0b 7512 /* PowerPC 401B2 */
80d11f44 7513 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
2662a059 7514#if defined (TODO)
a750fc0b 7515 /* PowerPC 401B3 */
80d11f44 7516 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
a750fc0b
JM		 7517#endif
7518 /* PowerPC 401C2 */
80d11f44 7519 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
a750fc0b 7520 /* PowerPC 401D2 */
80d11f44 7521 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
a750fc0b 7522 /* PowerPC 401E2 */
80d11f44 7523 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
a750fc0b 7524 /* PowerPC 401F2 */
80d11f44 7525 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
a750fc0b
JM		 7526 /* PowerPC 401G2 */
7527 /* XXX: to be checked */
80d11f44 7528 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
a750fc0b 7529 /* PowerPC 401 microcontrolers */
2662a059 7530#if defined (TODO)
a750fc0b 7531 /* PowerPC 401GF */
80d11f44 7532 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
3fc6c082 7533#endif
a750fc0b 7534 /* IOP480 (401 microcontroler) */
80d11f44 7535 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
a750fc0b 7536 /* IBM Processor for Network Resources */
80d11f44 7537 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
3fc6c082 7538#if defined (TODO)
80d11f44 7539 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
3fc6c082 7540#endif
a750fc0b
JM		 7541 /* PowerPC 403 family */
7542 /* Generic PowerPC 403 */
80d11f44 7543 POWERPC_DEF("403", CPU_POWERPC_403, 403),
a750fc0b
JM		 7544 /* PowerPC 403 microcontrolers */
7545 /* PowerPC 403 GA */
80d11f44 7546 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
a750fc0b 7547 /* PowerPC 403 GB */
80d11f44 7548 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
a750fc0b 7549 /* PowerPC 403 GC */
80d11f44 7550 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
a750fc0b 7551 /* PowerPC 403 GCX */
80d11f44 7552 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
3fc6c082 7553#if defined (TODO)
a750fc0b 7554 /* PowerPC 403 GP */
80d11f44 7555 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
3fc6c082 7556#endif
a750fc0b
JM		 7557 /* PowerPC 405 family */
7558 /* Generic PowerPC 405 */
80d11f44 7559 POWERPC_DEF("405", CPU_POWERPC_405, 405),
a750fc0b 7560 /* PowerPC 405 cores */
2662a059 7561#if defined (TODO)
a750fc0b 7562 /* PowerPC 405 A3 */
80d11f44 7563 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
3a607854 7564#endif
3a607854 7565#if defined (TODO)
a750fc0b 7566 /* PowerPC 405 A4 */
80d11f44 7567 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
3a607854 7568#endif
3a607854 7569#if defined (TODO)
a750fc0b 7570 /* PowerPC 405 B3 */
80d11f44 7571 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
3fc6c082
FB		 7572#endif
7573#if defined (TODO)
a750fc0b 7574 /* PowerPC 405 B4 */
80d11f44 7575 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
a750fc0b
JM		 7576#endif
7577#if defined (TODO)
7578 /* PowerPC 405 C3 */
80d11f44 7579 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
a750fc0b
JM		 7580#endif
7581#if defined (TODO)
7582 /* PowerPC 405 C4 */
80d11f44 7583 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
a750fc0b
JM		 7584#endif
7585 /* PowerPC 405 D2 */
80d11f44 7586 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
a750fc0b
JM		 7587#if defined (TODO)
7588 /* PowerPC 405 D3 */
80d11f44 7589 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
a750fc0b
JM		 7590#endif
7591 /* PowerPC 405 D4 */
80d11f44 7592 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
a750fc0b
JM		 7593#if defined (TODO)
7594 /* PowerPC 405 D5 */
80d11f44 7595 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
a750fc0b
JM		 7596#endif
7597#if defined (TODO)
7598 /* PowerPC 405 E4 */
80d11f44 7599 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
a750fc0b
JM		 7600#endif
7601#if defined (TODO)
7602 /* PowerPC 405 F4 */
80d11f44 7603 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
a750fc0b
JM		 7604#endif
7605#if defined (TODO)
7606 /* PowerPC 405 F5 */
80d11f44 7607 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
a750fc0b
JM		 7608#endif
7609#if defined (TODO)
7610 /* PowerPC 405 F6 */
80d11f44 7611 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
a750fc0b
JM		 7612#endif
7613 /* PowerPC 405 microcontrolers */
7614 /* PowerPC 405 CR */
80d11f44 7615 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
a750fc0b 7616 /* PowerPC 405 CRa */
80d11f44 7617 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
a750fc0b 7618 /* PowerPC 405 CRb */
80d11f44 7619 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
a750fc0b 7620 /* PowerPC 405 CRc */
80d11f44 7621 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
a750fc0b 7622 /* PowerPC 405 EP */
80d11f44 7623 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
a750fc0b
JM		 7624#if defined(TODO)
7625 /* PowerPC 405 EXr */
80d11f44 7626 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
a750fc0b
JM		 7627#endif
7628 /* PowerPC 405 EZ */
80d11f44 7629 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
a750fc0b
JM		 7630#if defined(TODO)
7631 /* PowerPC 405 FX */
80d11f44 7632 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
a750fc0b
JM		 7633#endif
7634 /* PowerPC 405 GP */
80d11f44 7635 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
a750fc0b 7636 /* PowerPC 405 GPa */
80d11f44 7637 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
a750fc0b 7638 /* PowerPC 405 GPb */
80d11f44 7639 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
a750fc0b 7640 /* PowerPC 405 GPc */
80d11f44 7641 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
a750fc0b 7642 /* PowerPC 405 GPd */
80d11f44 7643 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
a750fc0b 7644 /* PowerPC 405 GPe */
80d11f44 7645 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
a750fc0b 7646 /* PowerPC 405 GPR */
80d11f44 7647 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
a750fc0b
JM		 7648#if defined(TODO)
7649 /* PowerPC 405 H */
80d11f44 7650 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
a750fc0b
JM		 7651#endif
7652#if defined(TODO)
7653 /* PowerPC 405 L */
80d11f44 7654 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
a750fc0b
JM		 7655#endif
7656 /* PowerPC 405 LP */
80d11f44 7657 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
a750fc0b
JM		 7658#if defined(TODO)
7659 /* PowerPC 405 PM */
80d11f44 7660 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
a750fc0b
JM		 7661#endif
7662#if defined(TODO)
7663 /* PowerPC 405 PS */
80d11f44 7664 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
a750fc0b
JM		 7665#endif
7666#if defined(TODO)
7667 /* PowerPC 405 S */
80d11f44 7668 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
a750fc0b
JM		 7669#endif
7670 /* Npe405 H */
80d11f44 7671 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
a750fc0b 7672 /* Npe405 H2 */
80d11f44 7673 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
a750fc0b 7674 /* Npe405 L */
80d11f44 7675 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
a750fc0b 7676 /* Npe4GS3 */
80d11f44 7677 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
a750fc0b 7678#if defined (TODO)
80d11f44 7679 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
a750fc0b
JM		 7680#endif
7681#if defined (TODO)
80d11f44 7682 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
a750fc0b
JM		 7683#endif
7684#if defined (TODO)
7685 /* PowerPC LC77700 (Sanyo) */
80d11f44 7686 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
a750fc0b
JM		 7687#endif
7688 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7689#if defined (TODO)
7690 /* STB010000 */
80d11f44 7691 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
a750fc0b
JM		 7692#endif
7693#if defined (TODO)
7694 /* STB01010 */
80d11f44 7695 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
a750fc0b
JM		 7696#endif
7697#if defined (TODO)
7698 /* STB0210 */
80d11f44 7699 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
a750fc0b
JM		 7700#endif
7701 /* STB03xx */
80d11f44 7702 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
a750fc0b
JM		 7703#if defined (TODO)
7704 /* STB043x */
80d11f44 7705 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
a750fc0b
JM		 7706#endif
7707#if defined (TODO)
7708 /* STB045x */
80d11f44 7709 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
a750fc0b
JM		 7710#endif
7711 /* STB04xx */
80d11f44 7712 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
a750fc0b 7713 /* STB25xx */
80d11f44 7714 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
a750fc0b
JM		 7715#if defined (TODO)
7716 /* STB130 */
80d11f44 7717 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
a750fc0b
JM		 7718#endif
7719 /* Xilinx PowerPC 405 cores */
80d11f44
JM		 7720 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7721 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7722 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7723 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
a750fc0b
JM		 7724#if defined (TODO)
7725 /* Zarlink ZL10310 */
80d11f44 7726 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
a750fc0b
JM		 7727#endif
7728#if defined (TODO)
7729 /* Zarlink ZL10311 */
80d11f44 7730 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
a750fc0b
JM		 7731#endif
7732#if defined (TODO)
7733 /* Zarlink ZL10320 */
80d11f44 7734 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
a750fc0b
JM		 7735#endif
7736#if defined (TODO)
7737 /* Zarlink ZL10321 */
80d11f44 7738 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
a750fc0b
JM		 7739#endif
7740 /* PowerPC 440 family */
80d11f44 7741#if defined(TODO_USER_ONLY)
a750fc0b 7742 /* Generic PowerPC 440 */
80d11f44
JM		 7743 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7744#endif
a750fc0b
JM		 7745 /* PowerPC 440 cores */
7746#if defined (TODO)
7747 /* PowerPC 440 A4 */
80d11f44 7748 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
a750fc0b 7749#endif
95070372
EI		 7750 /* PowerPC 440 Xilinx 5 */
7751 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5),
a750fc0b
JM		 7752#if defined (TODO)
7753 /* PowerPC 440 A5 */
80d11f44 7754 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
a750fc0b
JM		 7755#endif
7756#if defined (TODO)
7757 /* PowerPC 440 B4 */
80d11f44 7758 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
a750fc0b
JM		 7759#endif
7760#if defined (TODO)
7761 /* PowerPC 440 G4 */
80d11f44 7762 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
a750fc0b
JM		 7763#endif
7764#if defined (TODO)
7765 /* PowerPC 440 F5 */
80d11f44 7766 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
a750fc0b
JM		 7767#endif
7768#if defined (TODO)
7769 /* PowerPC 440 G5 */
80d11f44 7770 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
a750fc0b
JM		 7771#endif
7772#if defined (TODO)
7773 /* PowerPC 440H4 */
80d11f44 7774 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
a750fc0b
JM		 7775#endif
7776#if defined (TODO)
7777 /* PowerPC 440H6 */
80d11f44 7778 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
a750fc0b
JM		 7779#endif
7780 /* PowerPC 440 microcontrolers */
80d11f44 7781#if defined(TODO_USER_ONLY)
a750fc0b 7782 /* PowerPC 440 EP */
80d11f44
JM		 7783 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
7784#endif
7785#if defined(TODO_USER_ONLY)
a750fc0b 7786 /* PowerPC 440 EPa */
80d11f44
JM		 7787 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
7788#endif
7789#if defined(TODO_USER_ONLY)
a750fc0b 7790 /* PowerPC 440 EPb */
80d11f44
JM		 7791 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
7792#endif
7793#if defined(TODO_USER_ONLY)
a750fc0b 7794 /* PowerPC 440 EPX */
80d11f44
JM		 7795 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
7796#endif
7797#if defined(TODO_USER_ONLY)
a750fc0b 7798 /* PowerPC 440 GP */
80d11f44
JM		 7799 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7800#endif
7801#if defined(TODO_USER_ONLY)
a750fc0b 7802 /* PowerPC 440 GPb */
80d11f44
JM		 7803 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
7804#endif
7805#if defined(TODO_USER_ONLY)
a750fc0b 7806 /* PowerPC 440 GPc */
80d11f44
JM		 7807 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
7808#endif
7809#if defined(TODO_USER_ONLY)
a750fc0b 7810 /* PowerPC 440 GR */
80d11f44
JM		 7811 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
7812#endif
7813#if defined(TODO_USER_ONLY)
a750fc0b 7814 /* PowerPC 440 GRa */
80d11f44
JM		 7815 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
7816#endif
7817#if defined(TODO_USER_ONLY)
a750fc0b 7818 /* PowerPC 440 GRX */
80d11f44
JM		 7819 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
7820#endif
7821#if defined(TODO_USER_ONLY)
a750fc0b 7822 /* PowerPC 440 GX */
80d11f44
JM		 7823 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
7824#endif
7825#if defined(TODO_USER_ONLY)
a750fc0b 7826 /* PowerPC 440 GXa */
80d11f44
JM		 7827 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
7828#endif
7829#if defined(TODO_USER_ONLY)
a750fc0b 7830 /* PowerPC 440 GXb */
80d11f44
JM		 7831 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
7832#endif
7833#if defined(TODO_USER_ONLY)
a750fc0b 7834 /* PowerPC 440 GXc */
80d11f44
JM		 7835 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
7836#endif
7837#if defined(TODO_USER_ONLY)
a750fc0b 7838 /* PowerPC 440 GXf */
80d11f44
JM		 7839 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
7840#endif
a750fc0b
JM		 7841#if defined(TODO)
7842 /* PowerPC 440 S */
80d11f44 7843 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
a750fc0b 7844#endif
80d11f44 7845#if defined(TODO_USER_ONLY)
a750fc0b 7846 /* PowerPC 440 SP */
80d11f44
JM		 7847 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
7848#endif
7849#if defined(TODO_USER_ONLY)
a750fc0b 7850 /* PowerPC 440 SP2 */
80d11f44
JM		 7851 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
7852#endif
7853#if defined(TODO_USER_ONLY)
a750fc0b 7854 /* PowerPC 440 SPE */
80d11f44
JM		 7855 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
7856#endif
a750fc0b
JM		 7857 /* PowerPC 460 family */
7858#if defined (TODO)
7859 /* Generic PowerPC 464 */
80d11f44 7860 POWERPC_DEF("464", CPU_POWERPC_464, 460),
a750fc0b
JM		 7861#endif
7862 /* PowerPC 464 microcontrolers */
7863#if defined (TODO)
7864 /* PowerPC 464H90 */
80d11f44 7865 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
a750fc0b
JM		 7866#endif
7867#if defined (TODO)
7868 /* PowerPC 464H90F */
80d11f44 7869 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
a750fc0b
JM		 7870#endif
7871 /* Freescale embedded PowerPC cores */
80d11f44
JM		 7872 /* MPC5xx family (aka RCPU) */
7873#if defined(TODO_USER_ONLY)
7874 /* Generic MPC5xx core */
7875 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
7876#endif
7877#if defined(TODO_USER_ONLY)
7878 /* Codename for MPC5xx core */
7879 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
7880#endif
7881 /* MPC5xx microcontrollers */
7882#if defined(TODO_USER_ONLY)
7883 /* MGT560 */
7884 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
7885#endif
7886#if defined(TODO_USER_ONLY)
7887 /* MPC509 */
7888 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
7889#endif
7890#if defined(TODO_USER_ONLY)
7891 /* MPC533 */
7892 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
7893#endif
7894#if defined(TODO_USER_ONLY)
7895 /* MPC534 */
7896 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
7897#endif
7898#if defined(TODO_USER_ONLY)
7899 /* MPC555 */
7900 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
7901#endif
7902#if defined(TODO_USER_ONLY)
7903 /* MPC556 */
7904 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
7905#endif
7906#if defined(TODO_USER_ONLY)
7907 /* MPC560 */
7908 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
7909#endif
7910#if defined(TODO_USER_ONLY)
7911 /* MPC561 */
7912 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
7913#endif
7914#if defined(TODO_USER_ONLY)
7915 /* MPC562 */
7916 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
7917#endif
7918#if defined(TODO_USER_ONLY)
7919 /* MPC563 */
7920 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
7921#endif
7922#if defined(TODO_USER_ONLY)
7923 /* MPC564 */
7924 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
7925#endif
7926#if defined(TODO_USER_ONLY)
7927 /* MPC565 */
7928 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
7929#endif
7930#if defined(TODO_USER_ONLY)
7931 /* MPC566 */
7932 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
7933#endif
7934 /* MPC8xx family (aka PowerQUICC) */
7935#if defined(TODO_USER_ONLY)
7936 /* Generic MPC8xx core */
7937 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
7938#endif
7939#if defined(TODO_USER_ONLY)
7940 /* Codename for MPC8xx core */
7941 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
7942#endif
7943 /* MPC8xx microcontrollers */
7944#if defined(TODO_USER_ONLY)
7945 /* MGT823 */
7946 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
7947#endif
7948#if defined(TODO_USER_ONLY)
7949 /* MPC821 */
7950 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
7951#endif
7952#if defined(TODO_USER_ONLY)
7953 /* MPC823 */
7954 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
7955#endif
7956#if defined(TODO_USER_ONLY)
7957 /* MPC850 */
7958 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
7959#endif
7960#if defined(TODO_USER_ONLY)
7961 /* MPC852T */
7962 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
7963#endif
7964#if defined(TODO_USER_ONLY)
7965 /* MPC855T */
7966 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
7967#endif
7968#if defined(TODO_USER_ONLY)
7969 /* MPC857 */
7970 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
7971#endif
7972#if defined(TODO_USER_ONLY)
7973 /* MPC859 */
7974 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
7975#endif
7976#if defined(TODO_USER_ONLY)
7977 /* MPC860 */
7978 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
7979#endif
7980#if defined(TODO_USER_ONLY)
7981 /* MPC862 */
7982 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
7983#endif
7984#if defined(TODO_USER_ONLY)
7985 /* MPC866 */
7986 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
7987#endif
7988#if defined(TODO_USER_ONLY)
7989 /* MPC870 */
7990 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
7991#endif
7992#if defined(TODO_USER_ONLY)
7993 /* MPC875 */
7994 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
7995#endif
7996#if defined(TODO_USER_ONLY)
7997 /* MPC880 */
7998 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
7999#endif
8000#if defined(TODO_USER_ONLY)
8001 /* MPC885 */
8002 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
8003#endif
8004 /* MPC82xx family (aka PowerQUICC-II) */
8005 /* Generic MPC52xx core */
8006 POWERPC_DEF_SVR("MPC52xx",
8007 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
8008 /* Generic MPC82xx core */
8009 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
8010 /* Codename for MPC82xx */
8011 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
8012 /* PowerPC G2 core */
8013 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
8014 /* PowerPC G2 H4 core */
8015 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
8016 /* PowerPC G2 GP core */
8017 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
8018 /* PowerPC G2 LS core */
8019 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
8020 /* PowerPC G2 HiP3 core */
8021 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
8022 /* PowerPC G2 HiP4 core */
8023 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
8024 /* PowerPC MPC603 core */
8025 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
8026 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
8027 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
8028 /* PowerPC G2LE GP core */
8029 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
8030 /* PowerPC G2LE LS core */
8031 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
8032 /* PowerPC G2LE GP1 core */
8033 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
8034 /* PowerPC G2LE GP3 core */
8035 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
8036 /* PowerPC MPC603 microcontrollers */
8037 /* MPC8240 */
8038 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
8039 /* PowerPC G2 microcontrollers */
082c6681 8040#if defined(TODO)
80d11f44
JM		 8041 /* MPC5121 */
8042 POWERPC_DEF_SVR("MPC5121",
8043 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
8044#endif
8045 /* MPC5200 */
8046 POWERPC_DEF_SVR("MPC5200",
8047 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
8048 /* MPC5200 v1.0 */
8049 POWERPC_DEF_SVR("MPC5200_v10",
8050 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
8051 /* MPC5200 v1.1 */
8052 POWERPC_DEF_SVR("MPC5200_v11",
8053 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
8054 /* MPC5200 v1.2 */
8055 POWERPC_DEF_SVR("MPC5200_v12",
8056 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
8057 /* MPC5200B */
8058 POWERPC_DEF_SVR("MPC5200B",
8059 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
8060 /* MPC5200B v2.0 */
8061 POWERPC_DEF_SVR("MPC5200B_v20",
8062 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
8063 /* MPC5200B v2.1 */
8064 POWERPC_DEF_SVR("MPC5200B_v21",
8065 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
8066 /* MPC8241 */
8067 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
8068 /* MPC8245 */
8069 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
8070 /* MPC8247 */
8071 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
8072 /* MPC8248 */
8073 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
8074 /* MPC8250 */
8075 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
8076 /* MPC8250 HiP3 */
8077 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
8078 /* MPC8250 HiP4 */
8079 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
8080 /* MPC8255 */
8081 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
8082 /* MPC8255 HiP3 */
8083 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
8084 /* MPC8255 HiP4 */
8085 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
8086 /* MPC8260 */
8087 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
8088 /* MPC8260 HiP3 */
8089 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
8090 /* MPC8260 HiP4 */
8091 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
8092 /* MPC8264 */
8093 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
8094 /* MPC8264 HiP3 */
8095 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
8096 /* MPC8264 HiP4 */
8097 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
8098 /* MPC8265 */
8099 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
8100 /* MPC8265 HiP3 */
8101 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
8102 /* MPC8265 HiP4 */
8103 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
8104 /* MPC8266 */
8105 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
8106 /* MPC8266 HiP3 */
8107 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
8108 /* MPC8266 HiP4 */
8109 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
8110 /* MPC8270 */
8111 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
8112 /* MPC8271 */
8113 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
8114 /* MPC8272 */
8115 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
8116 /* MPC8275 */
8117 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
8118 /* MPC8280 */
8119 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
a750fc0b 8120 /* e200 family */
a750fc0b 8121 /* Generic PowerPC e200 core */
80d11f44
JM		 8122 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
8123 /* Generic MPC55xx core */
8124#if defined (TODO)
8125 POWERPC_DEF_SVR("MPC55xx",
8126 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
a750fc0b
JM		 8127#endif
8128#if defined (TODO)
80d11f44
JM		 8129 /* PowerPC e200z0 core */
8130 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
a750fc0b
JM		 8131#endif
8132#if defined (TODO)
80d11f44
JM		 8133 /* PowerPC e200z1 core */
8134 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
8135#endif
8136#if defined (TODO)
8137 /* PowerPC e200z3 core */
8138 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
8139#endif
8140 /* PowerPC e200z5 core */
8141 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
a750fc0b 8142 /* PowerPC e200z6 core */
80d11f44
JM		 8143 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
8144 /* PowerPC e200 microcontrollers */
8145#if defined (TODO)
8146 /* MPC5514E */
8147 POWERPC_DEF_SVR("MPC5514E",
8148 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
a750fc0b 8149#endif
a750fc0b 8150#if defined (TODO)
80d11f44
JM		 8151 /* MPC5514E v0 */
8152 POWERPC_DEF_SVR("MPC5514E_v0",
8153 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
a750fc0b
JM		 8154#endif
8155#if defined (TODO)
80d11f44
JM		 8156 /* MPC5514E v1 */
8157 POWERPC_DEF_SVR("MPC5514E_v1",
8158 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
a750fc0b
JM		 8159#endif
8160#if defined (TODO)
80d11f44
JM		 8161 /* MPC5514G */
8162 POWERPC_DEF_SVR("MPC5514G",
8163 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
a750fc0b
JM		 8164#endif
8165#if defined (TODO)
80d11f44
JM		 8166 /* MPC5514G v0 */
8167 POWERPC_DEF_SVR("MPC5514G_v0",
8168 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
a750fc0b 8169#endif
a750fc0b 8170#if defined (TODO)
80d11f44
JM		 8171 /* MPC5514G v1 */
8172 POWERPC_DEF_SVR("MPC5514G_v1",
8173 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
a750fc0b
JM		 8174#endif
8175#if defined (TODO)
80d11f44
JM		 8176 /* MPC5515S */
8177 POWERPC_DEF_SVR("MPC5515S",
8178 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
a750fc0b
JM		 8179#endif
8180#if defined (TODO)
80d11f44
JM		 8181 /* MPC5516E */
8182 POWERPC_DEF_SVR("MPC5516E",
8183 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
a750fc0b
JM		 8184#endif
8185#if defined (TODO)
80d11f44
JM		 8186 /* MPC5516E v0 */
8187 POWERPC_DEF_SVR("MPC5516E_v0",
8188 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
a750fc0b
JM		 8189#endif
8190#if defined (TODO)
80d11f44
JM		 8191 /* MPC5516E v1 */
8192 POWERPC_DEF_SVR("MPC5516E_v1",
8193 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
a750fc0b 8194#endif
a750fc0b 8195#if defined (TODO)
80d11f44
JM		 8196 /* MPC5516G */
8197 POWERPC_DEF_SVR("MPC5516G",
8198 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
a750fc0b 8199#endif
a750fc0b 8200#if defined (TODO)
80d11f44
JM		 8201 /* MPC5516G v0 */
8202 POWERPC_DEF_SVR("MPC5516G_v0",
8203 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
a750fc0b 8204#endif
a750fc0b 8205#if defined (TODO)
80d11f44
JM		 8206 /* MPC5516G v1 */
8207 POWERPC_DEF_SVR("MPC5516G_v1",
8208 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
a750fc0b 8209#endif
a750fc0b 8210#if defined (TODO)
80d11f44
JM		 8211 /* MPC5516S */
8212 POWERPC_DEF_SVR("MPC5516S",
8213 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
a750fc0b
JM		 8214#endif
8215#if defined (TODO)
80d11f44
JM		 8216 /* MPC5533 */
8217 POWERPC_DEF_SVR("MPC5533",
8218 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
a750fc0b
JM		 8219#endif
8220#if defined (TODO)
80d11f44
JM		 8221 /* MPC5534 */
8222 POWERPC_DEF_SVR("MPC5534",
8223 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
a750fc0b 8224#endif
80d11f44
JM		 8225#if defined (TODO)
8226 /* MPC5553 */
8227 POWERPC_DEF_SVR("MPC5553",
8228 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
8229#endif
8230#if defined (TODO)
8231 /* MPC5554 */
8232 POWERPC_DEF_SVR("MPC5554",
8233 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
8234#endif
8235#if defined (TODO)
8236 /* MPC5561 */
8237 POWERPC_DEF_SVR("MPC5561",
8238 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
8239#endif
8240#if defined (TODO)
8241 /* MPC5565 */
8242 POWERPC_DEF_SVR("MPC5565",
8243 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
8244#endif
8245#if defined (TODO)
8246 /* MPC5566 */
8247 POWERPC_DEF_SVR("MPC5566",
8248 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
8249#endif
8250#if defined (TODO)
8251 /* MPC5567 */
8252 POWERPC_DEF_SVR("MPC5567",
8253 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
8254#endif
8255 /* e300 family */
8256 /* Generic PowerPC e300 core */
8257 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
8258 /* PowerPC e300c1 core */
8259 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
8260 /* PowerPC e300c2 core */
8261 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
8262 /* PowerPC e300c3 core */
8263 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
8264 /* PowerPC e300c4 core */
8265 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
8266 /* PowerPC e300 microcontrollers */
8267#if defined (TODO)
8268 /* MPC8313 */
8269 POWERPC_DEF_SVR("MPC8313",
74d77cae 8270 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300),
80d11f44
JM		 8271#endif
8272#if defined (TODO)
8273 /* MPC8313E */
8274 POWERPC_DEF_SVR("MPC8313E",
74d77cae 8275 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300),
80d11f44
JM		 8276#endif
8277#if defined (TODO)
8278 /* MPC8314 */
8279 POWERPC_DEF_SVR("MPC8314",
74d77cae 8280 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300),
80d11f44
JM		 8281#endif
8282#if defined (TODO)
8283 /* MPC8314E */
8284 POWERPC_DEF_SVR("MPC8314E",
74d77cae 8285 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300),
80d11f44
JM		 8286#endif
8287#if defined (TODO)
8288 /* MPC8315 */
8289 POWERPC_DEF_SVR("MPC8315",
74d77cae 8290 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300),
80d11f44
JM		 8291#endif
8292#if defined (TODO)
8293 /* MPC8315E */
8294 POWERPC_DEF_SVR("MPC8315E",
74d77cae 8295 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300),
80d11f44
JM		 8296#endif
8297#if defined (TODO)
8298 /* MPC8321 */
8299 POWERPC_DEF_SVR("MPC8321",
74d77cae 8300 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300),
80d11f44
JM		 8301#endif
8302#if defined (TODO)
8303 /* MPC8321E */
8304 POWERPC_DEF_SVR("MPC8321E",
74d77cae 8305 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300),
80d11f44
JM		 8306#endif
8307#if defined (TODO)
8308 /* MPC8323 */
8309 POWERPC_DEF_SVR("MPC8323",
74d77cae 8310 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300),
80d11f44
JM		 8311#endif
8312#if defined (TODO)
8313 /* MPC8323E */
8314 POWERPC_DEF_SVR("MPC8323E",
74d77cae 8315 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300),
80d11f44 8316#endif
492d7bf5
TM		 8317 /* MPC8343 */
8318 POWERPC_DEF_SVR("MPC8343",
74d77cae 8319 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300),
80d11f44
JM		 8320 /* MPC8343A */
8321 POWERPC_DEF_SVR("MPC8343A",
74d77cae 8322 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300),
492d7bf5
TM		 8323 /* MPC8343E */
8324 POWERPC_DEF_SVR("MPC8343E",
74d77cae 8325 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300),
80d11f44
JM		 8326 /* MPC8343EA */
8327 POWERPC_DEF_SVR("MPC8343EA",
74d77cae 8328 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300),
492d7bf5
TM		 8329 /* MPC8347 */
8330 POWERPC_DEF_SVR("MPC8347",
74d77cae 8331 CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300),
492d7bf5
TM		 8332 /* MPC8347T */
8333 POWERPC_DEF_SVR("MPC8347T",
74d77cae 8334 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300),
492d7bf5
TM		 8335 /* MPC8347P */
8336 POWERPC_DEF_SVR("MPC8347P",
74d77cae 8337 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300),
80d11f44
JM		 8338 /* MPC8347A */
8339 POWERPC_DEF_SVR("MPC8347A",
74d77cae 8340 CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300),
80d11f44
JM		 8341 /* MPC8347AT */
8342 POWERPC_DEF_SVR("MPC8347AT",
74d77cae 8343 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300),
80d11f44
JM		 8344 /* MPC8347AP */
8345 POWERPC_DEF_SVR("MPC8347AP",
74d77cae 8346 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300),
492d7bf5
TM		 8347 /* MPC8347E */
8348 POWERPC_DEF_SVR("MPC8347E",
74d77cae 8349 CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300),
492d7bf5
TM		 8350 /* MPC8347ET */
8351 POWERPC_DEF_SVR("MPC8347ET",
74d77cae 8352 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300),
492d7bf5
TM		 8353 /* MPC8343EP */
8354 POWERPC_DEF_SVR("MPC8347EP",
74d77cae 8355 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300),
80d11f44
JM		 8356 /* MPC8347EA */
8357 POWERPC_DEF_SVR("MPC8347EA",
74d77cae 8358 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300),
80d11f44
JM		 8359 /* MPC8347EAT */
8360 POWERPC_DEF_SVR("MPC8347EAT",
74d77cae 8361 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300),
80d11f44
JM		 8362 /* MPC8343EAP */
8363 POWERPC_DEF_SVR("MPC8347EAP",
74d77cae 8364 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300),
80d11f44
JM		 8365 /* MPC8349 */
8366 POWERPC_DEF_SVR("MPC8349",
74d77cae 8367 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300),
80d11f44
JM		 8368 /* MPC8349A */
8369 POWERPC_DEF_SVR("MPC8349A",
74d77cae 8370 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300),
80d11f44
JM		 8371 /* MPC8349E */
8372 POWERPC_DEF_SVR("MPC8349E",
74d77cae 8373 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300),
80d11f44
JM		 8374 /* MPC8349EA */
8375 POWERPC_DEF_SVR("MPC8349EA",
74d77cae 8376 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300),
80d11f44
JM		 8377#if defined (TODO)
8378 /* MPC8358E */
8379 POWERPC_DEF_SVR("MPC8358E",
74d77cae 8380 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300),
80d11f44
JM		 8381#endif
8382#if defined (TODO)
8383 /* MPC8360E */
8384 POWERPC_DEF_SVR("MPC8360E",
74d77cae 8385 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300),
80d11f44
JM		 8386#endif
8387 /* MPC8377 */
8388 POWERPC_DEF_SVR("MPC8377",
74d77cae 8389 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300),
80d11f44
JM		 8390 /* MPC8377E */
8391 POWERPC_DEF_SVR("MPC8377E",
74d77cae 8392 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300),
80d11f44
JM		 8393 /* MPC8378 */
8394 POWERPC_DEF_SVR("MPC8378",
74d77cae 8395 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300),
80d11f44
JM		 8396 /* MPC8378E */
8397 POWERPC_DEF_SVR("MPC8378E",
74d77cae 8398 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300),
80d11f44
JM		 8399 /* MPC8379 */
8400 POWERPC_DEF_SVR("MPC8379",
74d77cae 8401 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300),
80d11f44
JM		 8402 /* MPC8379E */
8403 POWERPC_DEF_SVR("MPC8379E",
74d77cae 8404 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300),
80d11f44
JM		 8405 /* e500 family */
8406 /* PowerPC e500 core */
bd5ea513
AJ		 8407 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8408 /* PowerPC e500v1 core */
8409 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
80d11f44 8410 /* PowerPC e500 v1.0 core */
bd5ea513 8411 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
80d11f44 8412 /* PowerPC e500 v2.0 core */
bd5ea513 8413 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
80d11f44 8414 /* PowerPC e500v2 core */
bd5ea513 8415 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
80d11f44 8416 /* PowerPC e500v2 v1.0 core */
bd5ea513 8417 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
80d11f44 8418 /* PowerPC e500v2 v2.0 core */
bd5ea513 8419 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
80d11f44 8420 /* PowerPC e500v2 v2.1 core */
bd5ea513 8421 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
80d11f44 8422 /* PowerPC e500v2 v2.2 core */
bd5ea513 8423 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
80d11f44 8424 /* PowerPC e500v2 v3.0 core */
bd5ea513 8425 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
80d11f44
JM		 8426 /* PowerPC e500 microcontrollers */
8427 /* MPC8533 */
8428 POWERPC_DEF_SVR("MPC8533",
bd5ea513 8429 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
80d11f44
JM		 8430 /* MPC8533 v1.0 */
8431 POWERPC_DEF_SVR("MPC8533_v10",
bd5ea513 8432 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
80d11f44
JM		 8433 /* MPC8533 v1.1 */
8434 POWERPC_DEF_SVR("MPC8533_v11",
bd5ea513 8435 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
80d11f44
JM		 8436 /* MPC8533E */
8437 POWERPC_DEF_SVR("MPC8533E",
bd5ea513 8438 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
80d11f44
JM		 8439 /* MPC8533E v1.0 */
8440 POWERPC_DEF_SVR("MPC8533E_v10",
bd5ea513 8441 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
80d11f44 8442 POWERPC_DEF_SVR("MPC8533E_v11",
bd5ea513 8443 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
80d11f44
JM		 8444 /* MPC8540 */
8445 POWERPC_DEF_SVR("MPC8540",
bd5ea513 8446 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
80d11f44
JM		 8447 /* MPC8540 v1.0 */
8448 POWERPC_DEF_SVR("MPC8540_v10",
bd5ea513 8449 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
80d11f44
JM		 8450 /* MPC8540 v2.0 */
8451 POWERPC_DEF_SVR("MPC8540_v20",
bd5ea513 8452 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
80d11f44
JM		 8453 /* MPC8540 v2.1 */
8454 POWERPC_DEF_SVR("MPC8540_v21",
bd5ea513 8455 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
80d11f44
JM		 8456 /* MPC8541 */
8457 POWERPC_DEF_SVR("MPC8541",
bd5ea513 8458 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
80d11f44
JM		 8459 /* MPC8541 v1.0 */
8460 POWERPC_DEF_SVR("MPC8541_v10",
bd5ea513 8461 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
80d11f44
JM		 8462 /* MPC8541 v1.1 */
8463 POWERPC_DEF_SVR("MPC8541_v11",
bd5ea513 8464 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
80d11f44
JM		 8465 /* MPC8541E */
8466 POWERPC_DEF_SVR("MPC8541E",
bd5ea513 8467 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
80d11f44
JM		 8468 /* MPC8541E v1.0 */
8469 POWERPC_DEF_SVR("MPC8541E_v10",
bd5ea513 8470 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
80d11f44
JM		 8471 /* MPC8541E v1.1 */
8472 POWERPC_DEF_SVR("MPC8541E_v11",
bd5ea513 8473 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
80d11f44
JM		 8474 /* MPC8543 */
8475 POWERPC_DEF_SVR("MPC8543",
bd5ea513 8476 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
80d11f44
JM		 8477 /* MPC8543 v1.0 */
8478 POWERPC_DEF_SVR("MPC8543_v10",
bd5ea513 8479 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
80d11f44
JM		 8480 /* MPC8543 v1.1 */
8481 POWERPC_DEF_SVR("MPC8543_v11",
bd5ea513 8482 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
80d11f44
JM		 8483 /* MPC8543 v2.0 */
8484 POWERPC_DEF_SVR("MPC8543_v20",
bd5ea513 8485 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
80d11f44
JM		 8486 /* MPC8543 v2.1 */
8487 POWERPC_DEF_SVR("MPC8543_v21",
bd5ea513 8488 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
80d11f44
JM		 8489 /* MPC8543E */
8490 POWERPC_DEF_SVR("MPC8543E",
bd5ea513 8491 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
80d11f44
JM		 8492 /* MPC8543E v1.0 */
8493 POWERPC_DEF_SVR("MPC8543E_v10",
bd5ea513 8494 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
80d11f44
JM		 8495 /* MPC8543E v1.1 */
8496 POWERPC_DEF_SVR("MPC8543E_v11",
bd5ea513 8497 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
80d11f44
JM		 8498 /* MPC8543E v2.0 */
8499 POWERPC_DEF_SVR("MPC8543E_v20",
bd5ea513 8500 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
80d11f44
JM		 8501 /* MPC8543E v2.1 */
8502 POWERPC_DEF_SVR("MPC8543E_v21",
bd5ea513 8503 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
80d11f44
JM		 8504 /* MPC8544 */
8505 POWERPC_DEF_SVR("MPC8544",
bd5ea513 8506 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
80d11f44
JM		 8507 /* MPC8544 v1.0 */
8508 POWERPC_DEF_SVR("MPC8544_v10",
bd5ea513 8509 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
80d11f44
JM		 8510 /* MPC8544 v1.1 */
8511 POWERPC_DEF_SVR("MPC8544_v11",
bd5ea513 8512 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
80d11f44
JM		 8513 /* MPC8544E */
8514 POWERPC_DEF_SVR("MPC8544E",
bd5ea513 8515 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
80d11f44
JM		 8516 /* MPC8544E v1.0 */
8517 POWERPC_DEF_SVR("MPC8544E_v10",
bd5ea513 8518 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
80d11f44
JM		 8519 /* MPC8544E v1.1 */
8520 POWERPC_DEF_SVR("MPC8544E_v11",
bd5ea513 8521 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
80d11f44
JM		 8522 /* MPC8545 */
8523 POWERPC_DEF_SVR("MPC8545",
bd5ea513 8524 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
80d11f44
JM		 8525 /* MPC8545 v2.0 */
8526 POWERPC_DEF_SVR("MPC8545_v20",
bd5ea513 8527 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
80d11f44
JM		 8528 /* MPC8545 v2.1 */
8529 POWERPC_DEF_SVR("MPC8545_v21",
bd5ea513 8530 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
80d11f44
JM		 8531 /* MPC8545E */
8532 POWERPC_DEF_SVR("MPC8545E",
bd5ea513 8533 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
80d11f44
JM		 8534 /* MPC8545E v2.0 */
8535 POWERPC_DEF_SVR("MPC8545E_v20",
bd5ea513 8536 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
80d11f44
JM		 8537 /* MPC8545E v2.1 */
8538 POWERPC_DEF_SVR("MPC8545E_v21",
bd5ea513 8539 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
80d11f44
JM		 8540 /* MPC8547E */
8541 POWERPC_DEF_SVR("MPC8547E",
bd5ea513 8542 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
80d11f44
JM		 8543 /* MPC8547E v2.0 */
8544 POWERPC_DEF_SVR("MPC8547E_v20",
bd5ea513 8545 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
80d11f44
JM		 8546 /* MPC8547E v2.1 */
8547 POWERPC_DEF_SVR("MPC8547E_v21",
bd5ea513 8548 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
80d11f44
JM		 8549 /* MPC8548 */
8550 POWERPC_DEF_SVR("MPC8548",
bd5ea513 8551 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
80d11f44
JM		 8552 /* MPC8548 v1.0 */
8553 POWERPC_DEF_SVR("MPC8548_v10",
bd5ea513 8554 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
80d11f44
JM		 8555 /* MPC8548 v1.1 */
8556 POWERPC_DEF_SVR("MPC8548_v11",
bd5ea513 8557 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
80d11f44
JM		 8558 /* MPC8548 v2.0 */
8559 POWERPC_DEF_SVR("MPC8548_v20",
bd5ea513 8560 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
80d11f44
JM		 8561 /* MPC8548 v2.1 */
8562 POWERPC_DEF_SVR("MPC8548_v21",
bd5ea513 8563 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
80d11f44
JM		 8564 /* MPC8548E */
8565 POWERPC_DEF_SVR("MPC8548E",
bd5ea513 8566 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
80d11f44
JM		 8567 /* MPC8548E v1.0 */
8568 POWERPC_DEF_SVR("MPC8548E_v10",
bd5ea513 8569 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
80d11f44
JM		 8570 /* MPC8548E v1.1 */
8571 POWERPC_DEF_SVR("MPC8548E_v11",
bd5ea513 8572 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
80d11f44
JM		 8573 /* MPC8548E v2.0 */
8574 POWERPC_DEF_SVR("MPC8548E_v20",
bd5ea513 8575 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
80d11f44
JM		 8576 /* MPC8548E v2.1 */
8577 POWERPC_DEF_SVR("MPC8548E_v21",
bd5ea513 8578 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
80d11f44
JM		 8579 /* MPC8555 */
8580 POWERPC_DEF_SVR("MPC8555",
bd5ea513 8581 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
80d11f44
JM		 8582 /* MPC8555 v1.0 */
8583 POWERPC_DEF_SVR("MPC8555_v10",
bd5ea513 8584 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
80d11f44
JM		 8585 /* MPC8555 v1.1 */
8586 POWERPC_DEF_SVR("MPC8555_v11",
bd5ea513 8587 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
80d11f44
JM		 8588 /* MPC8555E */
8589 POWERPC_DEF_SVR("MPC8555E",
bd5ea513 8590 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
80d11f44
JM		 8591 /* MPC8555E v1.0 */
8592 POWERPC_DEF_SVR("MPC8555E_v10",
bd5ea513 8593 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
80d11f44
JM		 8594 /* MPC8555E v1.1 */
8595 POWERPC_DEF_SVR("MPC8555E_v11",
bd5ea513 8596 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
80d11f44
JM		 8597 /* MPC8560 */
8598 POWERPC_DEF_SVR("MPC8560",
bd5ea513 8599 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
80d11f44
JM		 8600 /* MPC8560 v1.0 */
8601 POWERPC_DEF_SVR("MPC8560_v10",
bd5ea513 8602 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
80d11f44
JM		 8603 /* MPC8560 v2.0 */
8604 POWERPC_DEF_SVR("MPC8560_v20",
bd5ea513 8605 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
80d11f44
JM		 8606 /* MPC8560 v2.1 */
8607 POWERPC_DEF_SVR("MPC8560_v21",
bd5ea513 8608 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
80d11f44
JM		 8609 /* MPC8567 */
8610 POWERPC_DEF_SVR("MPC8567",
bd5ea513 8611 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
80d11f44
JM		 8612 /* MPC8567E */
8613 POWERPC_DEF_SVR("MPC8567E",
bd5ea513 8614 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
80d11f44
JM		 8615 /* MPC8568 */
8616 POWERPC_DEF_SVR("MPC8568",
bd5ea513 8617 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
80d11f44
JM		 8618 /* MPC8568E */
8619 POWERPC_DEF_SVR("MPC8568E",
bd5ea513 8620 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
80d11f44
JM		 8621 /* MPC8572 */
8622 POWERPC_DEF_SVR("MPC8572",
bd5ea513 8623 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
80d11f44
JM		 8624 /* MPC8572E */
8625 POWERPC_DEF_SVR("MPC8572E",
bd5ea513 8626 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
80d11f44
JM		 8627 /* e600 family */
8628 /* PowerPC e600 core */
8629 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8630 /* PowerPC e600 microcontrollers */
8631#if defined (TODO)
8632 /* MPC8610 */
8633 POWERPC_DEF_SVR("MPC8610",
8634 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8635#endif
8636 /* MPC8641 */
8637 POWERPC_DEF_SVR("MPC8641",
8638 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8639 /* MPC8641D */
8640 POWERPC_DEF_SVR("MPC8641D",
8641 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
a750fc0b
JM		 8642 /* 32 bits "classic" PowerPC */
8643 /* PowerPC 6xx family */
8644 /* PowerPC 601 */
bd928eba 8645 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
c3e36823 8646 /* PowerPC 601v0 */
082c6681 8647 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
c3e36823 8648 /* PowerPC 601v1 */
082c6681
JM		 8649 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8650 /* PowerPC 601v */
bd928eba 8651 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
a750fc0b 8652 /* PowerPC 601v2 */
082c6681 8653 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
a750fc0b 8654 /* PowerPC 602 */
80d11f44 8655 POWERPC_DEF("602", CPU_POWERPC_602, 602),
a750fc0b 8656 /* PowerPC 603 */
80d11f44 8657 POWERPC_DEF("603", CPU_POWERPC_603, 603),
a750fc0b 8658 /* Code name for PowerPC 603 */
80d11f44 8659 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
082c6681 8660 /* PowerPC 603e (aka PID6) */
80d11f44 8661 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
a750fc0b 8662 /* Code name for PowerPC 603e */
80d11f44 8663 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
a750fc0b 8664 /* PowerPC 603e v1.1 */
80d11f44 8665 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
a750fc0b 8666 /* PowerPC 603e v1.2 */
80d11f44 8667 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
a750fc0b 8668 /* PowerPC 603e v1.3 */
80d11f44 8669 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
a750fc0b 8670 /* PowerPC 603e v1.4 */
80d11f44 8671 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
a750fc0b 8672 /* PowerPC 603e v2.2 */
80d11f44 8673 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
a750fc0b 8674 /* PowerPC 603e v3 */
80d11f44 8675 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
a750fc0b 8676 /* PowerPC 603e v4 */
80d11f44 8677 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
a750fc0b 8678 /* PowerPC 603e v4.1 */
80d11f44 8679 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
082c6681 8680 /* PowerPC 603e (aka PID7) */
80d11f44 8681 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
a750fc0b 8682 /* PowerPC 603e7t */
80d11f44 8683 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
a750fc0b 8684 /* PowerPC 603e7v */
80d11f44 8685 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
a750fc0b 8686 /* Code name for PowerPC 603ev */
80d11f44 8687 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
a750fc0b 8688 /* PowerPC 603e7v1 */
80d11f44 8689 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
a750fc0b 8690 /* PowerPC 603e7v2 */
80d11f44 8691 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
082c6681
JM		 8692 /* PowerPC 603p (aka PID7v) */
8693 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8694 /* PowerPC 603r (aka PID7t) */
80d11f44 8695 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
a750fc0b 8696 /* Code name for PowerPC 603r */
80d11f44 8697 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
a750fc0b 8698 /* PowerPC 604 */
80d11f44 8699 POWERPC_DEF("604", CPU_POWERPC_604, 604),
082c6681
JM		 8700 /* PowerPC 604e (aka PID9) */
8701 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8702 /* Code name for PowerPC 604e */
8703 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
a750fc0b 8704 /* PowerPC 604e v1.0 */
082c6681 8705 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
a750fc0b 8706 /* PowerPC 604e v2.2 */
082c6681 8707 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
a750fc0b 8708 /* PowerPC 604e v2.4 */
082c6681
JM		 8709 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8710 /* PowerPC 604r (aka PIDA) */
8711 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8712 /* Code name for PowerPC 604r */
8713 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
a750fc0b
JM		 8714#if defined(TODO)
8715 /* PowerPC 604ev */
082c6681 8716 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
a750fc0b
JM		 8717#endif
8718 /* PowerPC 7xx family */
8719 /* Generic PowerPC 740 (G3) */
bd928eba 8720 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
082c6681 8721 /* Code name for PowerPC 740 */
bd928eba 8722 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
a750fc0b 8723 /* Generic PowerPC 750 (G3) */
bd928eba 8724 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
082c6681 8725 /* Code name for PowerPC 750 */
bd928eba 8726 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
a750fc0b 8727 /* PowerPC 740/750 is also known as G3 */
bd928eba
JM		 8728 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8729 /* PowerPC 740 v1.0 (G3) */
8730 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8731 /* PowerPC 750 v1.0 (G3) */
8732 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
a750fc0b 8733 /* PowerPC 740 v2.0 (G3) */
bd928eba 8734 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
a750fc0b 8735 /* PowerPC 750 v2.0 (G3) */
bd928eba 8736 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
a750fc0b 8737 /* PowerPC 740 v2.1 (G3) */
bd928eba 8738 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
a750fc0b 8739 /* PowerPC 750 v2.1 (G3) */
bd928eba 8740 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
a750fc0b 8741 /* PowerPC 740 v2.2 (G3) */
bd928eba 8742 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
a750fc0b 8743 /* PowerPC 750 v2.2 (G3) */
bd928eba 8744 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
a750fc0b 8745 /* PowerPC 740 v3.0 (G3) */
bd928eba 8746 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
a750fc0b 8747 /* PowerPC 750 v3.0 (G3) */
bd928eba 8748 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
a750fc0b 8749 /* PowerPC 740 v3.1 (G3) */
bd928eba 8750 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
a750fc0b 8751 /* PowerPC 750 v3.1 (G3) */
bd928eba 8752 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
a750fc0b 8753 /* PowerPC 740E (G3) */
bd928eba
JM		 8754 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8755 /* PowerPC 750E (G3) */
8756 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
a750fc0b 8757 /* PowerPC 740P (G3) */
bd928eba 8758 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
a750fc0b 8759 /* PowerPC 750P (G3) */
bd928eba 8760 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
a750fc0b 8761 /* Code name for PowerPC 740P/750P (G3) */
bd928eba 8762 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
a750fc0b 8763 /* PowerPC 750CL (G3 embedded) */
bd928eba
JM		 8764 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8765 /* PowerPC 750CL v1.0 */
8766 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8767 /* PowerPC 750CL v2.0 */
8768 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
a750fc0b 8769 /* PowerPC 750CX (G3 embedded) */
bd928eba
JM		 8770 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8771 /* PowerPC 750CX v1.0 (G3 embedded) */
8772 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8773 /* PowerPC 750CX v2.1 (G3 embedded) */
8774 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
a750fc0b 8775 /* PowerPC 750CX v2.1 (G3 embedded) */
bd928eba 8776 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
a750fc0b 8777 /* PowerPC 750CX v2.2 (G3 embedded) */
bd928eba 8778 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
a750fc0b 8779 /* PowerPC 750CXe (G3 embedded) */
bd928eba 8780 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
a750fc0b 8781 /* PowerPC 750CXe v2.1 (G3 embedded) */
bd928eba 8782 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
a750fc0b 8783 /* PowerPC 750CXe v2.2 (G3 embedded) */
bd928eba 8784 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
a750fc0b 8785 /* PowerPC 750CXe v2.3 (G3 embedded) */
bd928eba 8786 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
a750fc0b 8787 /* PowerPC 750CXe v2.4 (G3 embedded) */
bd928eba 8788 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
a750fc0b 8789 /* PowerPC 750CXe v2.4b (G3 embedded) */
bd928eba
JM		 8790 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8791 /* PowerPC 750CXe v3.0 (G3 embedded) */
8792 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
a750fc0b 8793 /* PowerPC 750CXe v3.1 (G3 embedded) */
bd928eba 8794 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
a750fc0b 8795 /* PowerPC 750CXe v3.1b (G3 embedded) */
bd928eba 8796 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
a750fc0b 8797 /* PowerPC 750CXr (G3 embedded) */
bd928eba 8798 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
a750fc0b 8799 /* PowerPC 750FL (G3 embedded) */
80d11f44 8800 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
a750fc0b 8801 /* PowerPC 750FX (G3 embedded) */
80d11f44 8802 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
a750fc0b 8803 /* PowerPC 750FX v1.0 (G3 embedded) */
80d11f44 8804 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
a750fc0b 8805 /* PowerPC 750FX v2.0 (G3 embedded) */
80d11f44 8806 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
a750fc0b 8807 /* PowerPC 750FX v2.1 (G3 embedded) */
80d11f44 8808 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
a750fc0b 8809 /* PowerPC 750FX v2.2 (G3 embedded) */
80d11f44 8810 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
a750fc0b 8811 /* PowerPC 750FX v2.3 (G3 embedded) */
80d11f44 8812 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
a750fc0b 8813 /* PowerPC 750GL (G3 embedded) */
bd928eba 8814 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
a750fc0b 8815 /* PowerPC 750GX (G3 embedded) */
bd928eba 8816 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
a750fc0b 8817 /* PowerPC 750GX v1.0 (G3 embedded) */
bd928eba 8818 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
a750fc0b 8819 /* PowerPC 750GX v1.1 (G3 embedded) */
bd928eba 8820 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
a750fc0b 8821 /* PowerPC 750GX v1.2 (G3 embedded) */
bd928eba 8822 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
a750fc0b 8823 /* PowerPC 750L (G3 embedded) */
bd928eba 8824 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
a750fc0b 8825 /* Code name for PowerPC 750L (G3 embedded) */
bd928eba
JM		 8826 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
8827 /* PowerPC 750L v2.0 (G3 embedded) */
8828 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
8829 /* PowerPC 750L v2.1 (G3 embedded) */
8830 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
a750fc0b 8831 /* PowerPC 750L v2.2 (G3 embedded) */
bd928eba 8832 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
a750fc0b 8833 /* PowerPC 750L v3.0 (G3 embedded) */
bd928eba 8834 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
a750fc0b 8835 /* PowerPC 750L v3.2 (G3 embedded) */
bd928eba 8836 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
a750fc0b 8837 /* Generic PowerPC 745 */
bd928eba 8838 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
a750fc0b 8839 /* Generic PowerPC 755 */
bd928eba 8840 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
a750fc0b 8841 /* Code name for PowerPC 745/755 */
bd928eba 8842 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
a750fc0b 8843 /* PowerPC 745 v1.0 */
bd928eba 8844 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
a750fc0b 8845 /* PowerPC 755 v1.0 */
bd928eba 8846 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
a750fc0b 8847 /* PowerPC 745 v1.1 */
bd928eba 8848 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
a750fc0b 8849 /* PowerPC 755 v1.1 */
bd928eba 8850 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
a750fc0b 8851 /* PowerPC 745 v2.0 */
bd928eba 8852 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
a750fc0b 8853 /* PowerPC 755 v2.0 */
bd928eba 8854 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
a750fc0b 8855 /* PowerPC 745 v2.1 */
bd928eba 8856 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
a750fc0b 8857 /* PowerPC 755 v2.1 */
bd928eba 8858 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
a750fc0b 8859 /* PowerPC 745 v2.2 */
bd928eba 8860 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
a750fc0b 8861 /* PowerPC 755 v2.2 */
bd928eba 8862 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
a750fc0b 8863 /* PowerPC 745 v2.3 */
bd928eba 8864 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
a750fc0b 8865 /* PowerPC 755 v2.3 */
bd928eba 8866 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
a750fc0b 8867 /* PowerPC 745 v2.4 */
bd928eba 8868 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
a750fc0b 8869 /* PowerPC 755 v2.4 */
bd928eba 8870 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
a750fc0b 8871 /* PowerPC 745 v2.5 */
bd928eba 8872 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
a750fc0b 8873 /* PowerPC 755 v2.5 */
bd928eba 8874 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
a750fc0b 8875 /* PowerPC 745 v2.6 */
bd928eba 8876 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
a750fc0b 8877 /* PowerPC 755 v2.6 */
bd928eba 8878 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
a750fc0b 8879 /* PowerPC 745 v2.7 */
bd928eba 8880 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
a750fc0b 8881 /* PowerPC 755 v2.7 */
bd928eba 8882 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
a750fc0b 8883 /* PowerPC 745 v2.8 */
bd928eba 8884 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
a750fc0b 8885 /* PowerPC 755 v2.8 */
bd928eba 8886 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
a750fc0b
JM		 8887#if defined (TODO)
8888 /* PowerPC 745P (G3) */
bd928eba 8889 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
a750fc0b 8890 /* PowerPC 755P (G3) */
bd928eba 8891 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
a750fc0b
JM		 8892#endif
8893 /* PowerPC 74xx family */
8894 /* PowerPC 7400 (G4) */
80d11f44 8895 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
a750fc0b 8896 /* Code name for PowerPC 7400 */
80d11f44 8897 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
a750fc0b 8898 /* PowerPC 74xx is also well known as G4 */
80d11f44 8899 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
a750fc0b 8900 /* PowerPC 7400 v1.0 (G4) */
80d11f44 8901 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
a750fc0b 8902 /* PowerPC 7400 v1.1 (G4) */
80d11f44 8903 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
a750fc0b 8904 /* PowerPC 7400 v2.0 (G4) */
80d11f44 8905 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
4e777442
JM		 8906 /* PowerPC 7400 v2.1 (G4) */
8907 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
a750fc0b 8908 /* PowerPC 7400 v2.2 (G4) */
80d11f44 8909 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
a750fc0b 8910 /* PowerPC 7400 v2.6 (G4) */
80d11f44 8911 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
a750fc0b 8912 /* PowerPC 7400 v2.7 (G4) */
80d11f44 8913 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
a750fc0b 8914 /* PowerPC 7400 v2.8 (G4) */
80d11f44 8915 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
a750fc0b 8916 /* PowerPC 7400 v2.9 (G4) */
80d11f44 8917 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
a750fc0b 8918 /* PowerPC 7410 (G4) */
80d11f44 8919 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
a750fc0b 8920 /* Code name for PowerPC 7410 */
80d11f44 8921 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
a750fc0b 8922 /* PowerPC 7410 v1.0 (G4) */
80d11f44 8923 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
a750fc0b 8924 /* PowerPC 7410 v1.1 (G4) */
80d11f44 8925 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
a750fc0b 8926 /* PowerPC 7410 v1.2 (G4) */
80d11f44 8927 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
a750fc0b 8928 /* PowerPC 7410 v1.3 (G4) */
80d11f44 8929 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
a750fc0b 8930 /* PowerPC 7410 v1.4 (G4) */
80d11f44 8931 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
a750fc0b 8932 /* PowerPC 7448 (G4) */
80d11f44 8933 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
a750fc0b 8934 /* PowerPC 7448 v1.0 (G4) */
80d11f44 8935 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
a750fc0b 8936 /* PowerPC 7448 v1.1 (G4) */
80d11f44 8937 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
a750fc0b 8938 /* PowerPC 7448 v2.0 (G4) */
80d11f44 8939 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
a750fc0b 8940 /* PowerPC 7448 v2.1 (G4) */
80d11f44 8941 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
a750fc0b 8942 /* PowerPC 7450 (G4) */
80d11f44 8943 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
a750fc0b 8944 /* Code name for PowerPC 7450 */
80d11f44 8945 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
a750fc0b 8946 /* PowerPC 7450 v1.0 (G4) */
80d11f44 8947 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
a750fc0b 8948 /* PowerPC 7450 v1.1 (G4) */
80d11f44 8949 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
a750fc0b 8950 /* PowerPC 7450 v1.2 (G4) */
80d11f44 8951 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
a750fc0b 8952 /* PowerPC 7450 v2.0 (G4) */
80d11f44 8953 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
a750fc0b 8954 /* PowerPC 7450 v2.1 (G4) */
80d11f44 8955 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
a750fc0b 8956 /* PowerPC 7441 (G4) */
80d11f44 8957 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
a750fc0b 8958 /* PowerPC 7451 (G4) */
80d11f44 8959 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
4e777442
JM		 8960 /* PowerPC 7441 v2.1 (G4) */
8961 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
8962 /* PowerPC 7441 v2.3 (G4) */
8963 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
8964 /* PowerPC 7451 v2.3 (G4) */
8965 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
8966 /* PowerPC 7441 v2.10 (G4) */
8967 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
8968 /* PowerPC 7451 v2.10 (G4) */
8969 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
a750fc0b 8970 /* PowerPC 7445 (G4) */
80d11f44 8971 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
a750fc0b 8972 /* PowerPC 7455 (G4) */
80d11f44 8973 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
a750fc0b 8974 /* Code name for PowerPC 7445/7455 */
80d11f44 8975 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
a750fc0b 8976 /* PowerPC 7445 v1.0 (G4) */
80d11f44 8977 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
a750fc0b 8978 /* PowerPC 7455 v1.0 (G4) */
80d11f44 8979 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
a750fc0b 8980 /* PowerPC 7445 v2.1 (G4) */
80d11f44 8981 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
a750fc0b 8982 /* PowerPC 7455 v2.1 (G4) */
80d11f44 8983 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
a750fc0b 8984 /* PowerPC 7445 v3.2 (G4) */
80d11f44 8985 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
a750fc0b 8986 /* PowerPC 7455 v3.2 (G4) */
80d11f44 8987 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
a750fc0b 8988 /* PowerPC 7445 v3.3 (G4) */
80d11f44 8989 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
a750fc0b 8990 /* PowerPC 7455 v3.3 (G4) */
80d11f44 8991 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
a750fc0b 8992 /* PowerPC 7445 v3.4 (G4) */
80d11f44 8993 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
a750fc0b 8994 /* PowerPC 7455 v3.4 (G4) */
80d11f44 8995 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
a750fc0b 8996 /* PowerPC 7447 (G4) */
80d11f44 8997 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
a750fc0b 8998 /* PowerPC 7457 (G4) */
80d11f44 8999 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
a750fc0b 9000 /* Code name for PowerPC 7447/7457 */
80d11f44 9001 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
a750fc0b 9002 /* PowerPC 7447 v1.0 (G4) */
80d11f44 9003 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
a750fc0b 9004 /* PowerPC 7457 v1.0 (G4) */
80d11f44 9005 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
a750fc0b 9006 /* PowerPC 7447 v1.1 (G4) */
80d11f44 9007 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
a750fc0b 9008 /* PowerPC 7457 v1.1 (G4) */
80d11f44 9009 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
a750fc0b 9010 /* PowerPC 7457 v1.2 (G4) */
80d11f44 9011 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
082c6681
JM		 9012 /* PowerPC 7447A (G4) */
9013 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
9014 /* PowerPC 7457A (G4) */
9015 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
9016 /* PowerPC 7447A v1.0 (G4) */
9017 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
9018 /* PowerPC 7457A v1.0 (G4) */
9019 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
9020 /* Code name for PowerPC 7447A/7457A */
9021 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
9022 /* PowerPC 7447A v1.1 (G4) */
9023 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
9024 /* PowerPC 7457A v1.1 (G4) */
9025 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
9026 /* PowerPC 7447A v1.2 (G4) */
9027 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
9028 /* PowerPC 7457A v1.2 (G4) */
9029 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
a750fc0b
JM		 9030 /* 64 bits PowerPC */
9031#if defined (TARGET_PPC64)
a750fc0b 9032 /* PowerPC 620 */
80d11f44 9033 POWERPC_DEF("620", CPU_POWERPC_620, 620),
082c6681
JM		 9034 /* Code name for PowerPC 620 */
9035 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
3fc6c082 9036#if defined (TODO)
a750fc0b 9037 /* PowerPC 630 (POWER3) */
80d11f44
JM		 9038 POWERPC_DEF("630", CPU_POWERPC_630, 630),
9039 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
082c6681
JM		 9040 /* Code names for POWER3 */
9041 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
9042 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
a750fc0b 9043#endif
3a607854 9044#if defined (TODO)
a750fc0b 9045 /* PowerPC 631 (Power 3+) */
80d11f44
JM		 9046 POWERPC_DEF("631", CPU_POWERPC_631, 631),
9047 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
3a607854
JM		 9048#endif
9049#if defined (TODO)
a750fc0b 9050 /* POWER4 */
80d11f44 9051 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
a750fc0b 9052#endif
3a607854 9053#if defined (TODO)
a750fc0b 9054 /* POWER4p */
80d11f44 9055 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
a750fc0b 9056#endif
2662a059 9057#if defined (TODO)
a750fc0b 9058 /* POWER5 */
80d11f44 9059 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
a750fc0b 9060 /* POWER5GR */
80d11f44 9061 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
2662a059 9062#endif
3a607854 9063#if defined (TODO)
a750fc0b 9064 /* POWER5+ */
80d11f44 9065 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
a750fc0b 9066 /* POWER5GS */
80d11f44 9067 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
a750fc0b 9068#endif
2662a059 9069#if defined (TODO)
a750fc0b 9070 /* POWER6 */
80d11f44 9071 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
a750fc0b 9072 /* POWER6 running in POWER5 mode */
80d11f44 9073 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
a750fc0b 9074 /* POWER6A */
80d11f44 9075 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
2662a059 9076#endif
9d52e907
DG		 9077 /* POWER7 */
9078 POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7),
9079 POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7),
a750fc0b 9080 /* PowerPC 970 */
80d11f44 9081 POWERPC_DEF("970", CPU_POWERPC_970, 970),
a750fc0b 9082 /* PowerPC 970FX (G5) */
80d11f44 9083 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
a750fc0b 9084 /* PowerPC 970FX v1.0 (G5) */
80d11f44 9085 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
a750fc0b 9086 /* PowerPC 970FX v2.0 (G5) */
80d11f44 9087 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
a750fc0b 9088 /* PowerPC 970FX v2.1 (G5) */
80d11f44 9089 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
a750fc0b 9090 /* PowerPC 970FX v3.0 (G5) */
80d11f44 9091 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
a750fc0b 9092 /* PowerPC 970FX v3.1 (G5) */
80d11f44 9093 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
a750fc0b 9094 /* PowerPC 970GX (G5) */
80d11f44 9095 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
a750fc0b 9096 /* PowerPC 970MP */
80d11f44 9097 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
a750fc0b 9098 /* PowerPC 970MP v1.0 */
80d11f44 9099 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
a750fc0b 9100 /* PowerPC 970MP v1.1 */
80d11f44 9101 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
3a607854 9102#if defined (TODO)
a750fc0b 9103 /* PowerPC Cell */
80d11f44 9104 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
2662a059
JM		 9105#endif
9106#if defined (TODO)
a750fc0b 9107 /* PowerPC Cell v1.0 */
80d11f44 9108 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
2662a059
JM		 9109#endif
9110#if defined (TODO)
a750fc0b 9111 /* PowerPC Cell v2.0 */
80d11f44 9112 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
2662a059
JM		 9113#endif
9114#if defined (TODO)
a750fc0b 9115 /* PowerPC Cell v3.0 */
80d11f44 9116 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
3a607854 9117#endif
3a607854 9118#if defined (TODO)
a750fc0b 9119 /* PowerPC Cell v3.1 */
80d11f44 9120 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
2662a059
JM		 9121#endif
9122#if defined (TODO)
a750fc0b 9123 /* PowerPC Cell v3.2 */
80d11f44 9124 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
2662a059
JM		 9125#endif
9126#if defined (TODO)
a750fc0b
JM		 9127 /* RS64 (Apache/A35) */
9128 /* This one seems to support the whole POWER2 instruction set
9129 * and the PowerPC 64 one.
9130 */
9131 /* What about A10 & A30 ? */
80d11f44
JM		 9132 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
9133 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
9134 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
3a607854
JM		 9135#endif
9136#if defined (TODO)
a750fc0b 9137 /* RS64-II (NorthStar/A50) */
80d11f44
JM		 9138 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
9139 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
9140 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
3a607854
JM		 9141#endif
9142#if defined (TODO)
a750fc0b 9143 /* RS64-III (Pulsar) */
80d11f44
JM		 9144 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
9145 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
2662a059
JM		 9146#endif
9147#if defined (TODO)
a750fc0b 9148 /* RS64-IV (IceStar/IStar/SStar) */
80d11f44
JM		 9149 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
9150 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
9151 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
9152 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
3a607854 9153#endif
a750fc0b
JM		 9154#endif /* defined (TARGET_PPC64) */
9155 /* POWER */
3fc6c082 9156#if defined (TODO)
a750fc0b 9157 /* Original POWER */
80d11f44
JM		 9158 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
9159 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
9160 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
9161 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
9162 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
76a66253
JM		 9163#endif
9164#if defined (TODO)
a750fc0b 9165 /* POWER2 */
80d11f44
JM		 9166 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
9167 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
9168 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
a750fc0b
JM		 9169#endif
9170 /* PA semi cores */
9171#if defined (TODO)
9172 /* PA PA6T */
80d11f44 9173 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
a750fc0b
JM		 9174#endif
9175 /* Generic PowerPCs */
9176#if defined (TARGET_PPC64)
80d11f44 9177 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
a750fc0b 9178#endif
80d11f44
JM		 9179 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
9180 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b 9181 /* Fallback */
80d11f44 9182 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b
JM		 9183};
9184
9185/*****************************************************************************/
60b14d95 9186/* Generic CPU instantiation routine */
c227f099 9187static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 9188{
9189#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 9190 int i;
9191
a750fc0b 9192 env->irq_inputs = NULL;
e1833e1f
JM		 9193 /* Set all exception vectors to an invalid address */
9194 for (i = 0; i < POWERPC_EXCP_NB; i++)
9195 env->excp_vectors[i] = (target_ulong)(-1ULL);
fc1c67bc 9196 env->hreset_excp_prefix = 0x00000000;
e1833e1f
JM		 9197 env->ivor_mask = 0x00000000;
9198 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 9199 /* Default MMU definitions */
9200 env->nb_BATs = 0;
9201 env->nb_tlb = 0;
9202 env->nb_ways = 0;
1c53accc 9203 env->tlb_type = TLB_NONE;
f2e63a42 9204#endif
a750fc0b
JM		 9205 /* Register SPR common to all PowerPC implementations */
9206 gen_spr_generic(env);
9207 spr_register(env, SPR_PVR, "PVR",
a139aa17
NF		 9208 /* Linux permits userspace to read PVR */
9209#if defined(CONFIG_LINUX_USER)
9210 &spr_read_generic,
9211#else
9212 SPR_NOACCESS,
9213#endif
9214 SPR_NOACCESS,
a750fc0b
JM		 9215 &spr_read_generic, SPR_NOACCESS,
9216 def->pvr);
80d11f44
JM		 9217 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9218 if (def->svr != POWERPC_SVR_NONE) {
9219 if (def->svr & POWERPC_SVR_E500) {
9220 spr_register(env, SPR_E500_SVR, "SVR",
9221 SPR_NOACCESS, SPR_NOACCESS,
9222 &spr_read_generic, SPR_NOACCESS,
9223 def->svr & ~POWERPC_SVR_E500);
9224 } else {
9225 spr_register(env, SPR_SVR, "SVR",
9226 SPR_NOACCESS, SPR_NOACCESS,
9227 &spr_read_generic, SPR_NOACCESS,
9228 def->svr);
9229 }
9230 }
a750fc0b
JM		 9231 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9232 (*def->init_proc)(env);
fc1c67bc
BS		 9233#if !defined(CONFIG_USER_ONLY)
9234 env->excp_prefix = env->hreset_excp_prefix;
9235#endif
25ba3a68
JM		 9236 /* MSR bits & flags consistency checks */
9237 if (env->msr_mask & (1 << 25)) {
9238 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9239 case POWERPC_FLAG_SPE:
9240 case POWERPC_FLAG_VRE:
9241 break;
9242 default:
9243 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9244 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9245 exit(1);
9246 }
9247 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9248 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9249 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9250 exit(1);
9251 }
9252 if (env->msr_mask & (1 << 17)) {
9253 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9254 case POWERPC_FLAG_TGPR:
9255 case POWERPC_FLAG_CE:
9256 break;
9257 default:
9258 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9259 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9260 exit(1);
9261 }
9262 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9263 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9264 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9265 exit(1);
9266 }
9267 if (env->msr_mask & (1 << 10)) {
9268 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9269 POWERPC_FLAG_UBLE)) {
9270 case POWERPC_FLAG_SE:
9271 case POWERPC_FLAG_DWE:
9272 case POWERPC_FLAG_UBLE:
9273 break;
9274 default:
9275 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9276 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9277 "POWERPC_FLAG_UBLE\n");
9278 exit(1);
9279 }
9280 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9281 POWERPC_FLAG_UBLE)) {
9282 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9283 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9284 "POWERPC_FLAG_UBLE\n");
9285 exit(1);
9286 }
9287 if (env->msr_mask & (1 << 9)) {
9288 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9289 case POWERPC_FLAG_BE:
9290 case POWERPC_FLAG_DE:
9291 break;
9292 default:
9293 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9294 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9295 exit(1);
9296 }
9297 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9298 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9299 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9300 exit(1);
9301 }
9302 if (env->msr_mask & (1 << 2)) {
9303 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9304 case POWERPC_FLAG_PX:
9305 case POWERPC_FLAG_PMM:
9306 break;
9307 default:
9308 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9309 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9310 exit(1);
9311 }
9312 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9313 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9314 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9315 exit(1);
9316 }
4018bae9
JM		 9317 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9318 fprintf(stderr, "PowerPC flags inconsistency\n"
9319 "Should define the time-base and decrementer clock source\n");
9320 exit(1);
9321 }
a750fc0b 9322 /* Allocate TLBs buffer when needed */
f2e63a42 9323#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 9324 if (env->nb_tlb != 0) {
9325 int nb_tlb = env->nb_tlb;
9326 if (env->id_tlbs != 0)
9327 nb_tlb *= 2;
1c53accc
AG		 9328 switch (env->tlb_type) {
9329 case TLB_6XX:
7267c094 9330 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
1c53accc
AG		 9331 break;
9332 case TLB_EMB:
7267c094 9333 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
1c53accc
AG		 9334 break;
9335 case TLB_MAS:
7267c094 9336 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
1c53accc
AG		 9337 break;
9338 }
a750fc0b
JM		 9339 /* Pre-compute some useful values */
9340 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9341 }
a750fc0b
JM		 9342 if (env->irq_inputs == NULL) {
9343 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9344 " Attempt Qemu to crash very soon !\n");
9345 }
9346#endif
2f462816
JM		 9347 if (env->check_pow == NULL) {
9348 fprintf(stderr, "WARNING: no power management check handler "
9349 "registered.\n"
9350 " Attempt Qemu to crash very soon !\n");
9351 }
a750fc0b
JM		 9352}
9353
9354#if defined(PPC_DUMP_CPU)
9355static void dump_ppc_sprs (CPUPPCState *env)
9356{
9357 ppc_spr_t *spr;
9358#if !defined(CONFIG_USER_ONLY)
9359 uint32_t sr, sw;
9360#endif
9361 uint32_t ur, uw;
9362 int i, j, n;
9363
9364 printf("Special purpose registers:\n");
9365 for (i = 0; i < 32; i++) {
9366 for (j = 0; j < 32; j++) {
9367 n = (i << 5) | j;
9368 spr = &env->spr_cb[n];
9369 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9370 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9371#if !defined(CONFIG_USER_ONLY)
9372 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9373 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9374 if (sw || sr || uw || ur) {
9375 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9376 (i << 5) | j, (i << 5) | j, spr->name,
9377 sw ? 'w' : '-', sr ? 'r' : '-',
9378 uw ? 'w' : '-', ur ? 'r' : '-');
9379 }
9380#else
9381 if (uw || ur) {
9382 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9383 (i << 5) | j, (i << 5) | j, spr->name,
9384 uw ? 'w' : '-', ur ? 'r' : '-');
9385 }
9386#endif
9387 }
9388 }
9389 fflush(stdout);
9390 fflush(stderr);
9391}
9392#endif
9393
9394/*****************************************************************************/
9395#include <stdlib.h>
9396#include <string.h>
9397
a750fc0b
JM		 9398/* Opcode types */
9399enum {
9400 PPC_DIRECT = 0, /* Opcode routine */
9401 PPC_INDIRECT = 1, /* Indirect opcode table */
9402};
9403
9404static inline int is_indirect_opcode (void *handler)
9405{
9406 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
9407}
9408
c227f099 9409static inline opc_handler_t **ind_table(void *handler)
a750fc0b 9410{
c227f099 9411 return (opc_handler_t **)((unsigned long)handler & ~3);
a750fc0b
JM		 9412}
9413
9414/* Instruction table creation */
9415/* Opcodes tables creation */
c227f099 9416static void fill_new_table (opc_handler_t **table, int len)
a750fc0b
JM		 9417{
9418 int i;
9419
9420 for (i = 0; i < len; i++)
9421 table[i] = &invalid_handler;
9422}
9423
c227f099 9424static int create_new_table (opc_handler_t **table, unsigned char idx)
a750fc0b 9425{
c227f099 9426 opc_handler_t **tmp;
a750fc0b 9427
c227f099 9428 tmp = malloc(0x20 * sizeof(opc_handler_t));
a750fc0b 9429 fill_new_table(tmp, 0x20);
c227f099 9430 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
a750fc0b
JM		 9431
9432 return 0;
9433}
9434
c227f099
AL		 9435static int insert_in_table (opc_handler_t **table, unsigned char idx,
9436 opc_handler_t *handler)
a750fc0b
JM		 9437{
9438 if (table[idx] != &invalid_handler)
9439 return -1;
9440 table[idx] = handler;
9441
9442 return 0;
9443}
9444
c227f099
AL		 9445static int register_direct_insn (opc_handler_t **ppc_opcodes,
9446 unsigned char idx, opc_handler_t *handler)
a750fc0b
JM		 9447{
9448 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9449 printf("*** ERROR: opcode %02x already assigned in main "
9450 "opcode table\n", idx);
4c1b1bfe
JM		 9451#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9452 printf(" Registered handler '%s' - new handler '%s'\n",
9453 ppc_opcodes[idx]->oname, handler->oname);
9454#endif
a750fc0b
JM		 9455 return -1;
9456 }
9457
9458 return 0;
9459}
9460
c227f099 9461static int register_ind_in_table (opc_handler_t **table,
a750fc0b 9462 unsigned char idx1, unsigned char idx2,
c227f099 9463 opc_handler_t *handler)
a750fc0b
JM		 9464{
9465 if (table[idx1] == &invalid_handler) {
9466 if (create_new_table(table, idx1) < 0) {
9467 printf("*** ERROR: unable to create indirect table "
9468 "idx=%02x\n", idx1);
9469 return -1;
9470 }
9471 } else {
9472 if (!is_indirect_opcode(table[idx1])) {
9473 printf("*** ERROR: idx %02x already assigned to a direct "
9474 "opcode\n", idx1);
4c1b1bfe
JM		 9475#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9476 printf(" Registered handler '%s' - new handler '%s'\n",
9477 ind_table(table[idx1])[idx2]->oname, handler->oname);
9478#endif
a750fc0b
JM		 9479 return -1;
9480 }
3a607854 9481 }
a750fc0b
JM		 9482 if (handler != NULL &&
9483 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9484 printf("*** ERROR: opcode %02x already assigned in "
9485 "opcode table %02x\n", idx2, idx1);
4c1b1bfe
JM		 9486#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9487 printf(" Registered handler '%s' - new handler '%s'\n",
9488 ind_table(table[idx1])[idx2]->oname, handler->oname);
9489#endif
a750fc0b 9490 return -1;
3a607854 9491 }
a750fc0b
JM		 9492
9493 return 0;
9494}
9495
c227f099 9496static int register_ind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 9497 unsigned char idx1, unsigned char idx2,
c227f099 9498 opc_handler_t *handler)
a750fc0b
JM		 9499{
9500 int ret;
9501
9502 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9503
9504 return ret;
9505}
9506
c227f099 9507static int register_dblind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 9508 unsigned char idx1, unsigned char idx2,
c227f099 9509 unsigned char idx3, opc_handler_t *handler)
a750fc0b
JM		 9510{
9511 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9512 printf("*** ERROR: unable to join indirect table idx "
9513 "[%02x-%02x]\n", idx1, idx2);
9514 return -1;
9515 }
9516 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9517 handler) < 0) {
9518 printf("*** ERROR: unable to insert opcode "
9519 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9520 return -1;
9521 }
9522
9523 return 0;
9524}
9525
c227f099 9526static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
a750fc0b
JM		 9527{
9528 if (insn->opc2 != 0xFF) {
9529 if (insn->opc3 != 0xFF) {
9530 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9531 insn->opc3, &insn->handler) < 0)
9532 return -1;
9533 } else {
9534 if (register_ind_insn(ppc_opcodes, insn->opc1,
9535 insn->opc2, &insn->handler) < 0)
9536 return -1;
9537 }
9538 } else {
9539 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9540 return -1;
9541 }
9542
9543 return 0;
9544}
9545
c227f099 9546static int test_opcode_table (opc_handler_t **table, int len)
a750fc0b
JM		 9547{
9548 int i, count, tmp;
9549
9550 for (i = 0, count = 0; i < len; i++) {
9551 /* Consistency fixup */
9552 if (table[i] == NULL)
9553 table[i] = &invalid_handler;
9554 if (table[i] != &invalid_handler) {
9555 if (is_indirect_opcode(table[i])) {
c227f099 9556 tmp = test_opcode_table(ind_table(table[i]), 0x20);
a750fc0b
JM		 9557 if (tmp == 0) {
9558 free(table[i]);
9559 table[i] = &invalid_handler;
9560 } else {
9561 count++;
9562 }
9563 } else {
9564 count++;
9565 }
9566 }
9567 }
9568
9569 return count;
9570}
9571
c227f099 9572static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
a750fc0b 9573{
c227f099 9574 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
a750fc0b
JM		 9575 printf("*** WARNING: no opcode defined !\n");
9576}
9577
9578/*****************************************************************************/
c227f099 9579static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
a750fc0b 9580{
c227f099 9581 opcode_t *opc;
a750fc0b
JM		 9582
9583 fill_new_table(env->opcodes, 0x40);
5c55ff99 9584 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
a5858d7a
AG		 9585 if (((opc->handler.type & def->insns_flags) != 0) ||
9586 ((opc->handler.type2 & def->insns_flags2) != 0)) {
a750fc0b
JM		 9587 if (register_insn(env->opcodes, opc) < 0) {
9588 printf("*** ERROR initializing PowerPC instruction "
9589 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9590 opc->opc3);
9591 return -1;
9592 }
9593 }
9594 }
c227f099 9595 fix_opcode_tables(env->opcodes);
a750fc0b
JM		 9596 fflush(stdout);
9597 fflush(stderr);
9598
9599 return 0;
9600}
9601
9602#if defined(PPC_DUMP_CPU)
25ba3a68 9603static void dump_ppc_insns (CPUPPCState *env)
a750fc0b 9604{
c227f099 9605 opc_handler_t **table, *handler;
b55266b5 9606 const char *p, *q;
a750fc0b
JM		 9607 uint8_t opc1, opc2, opc3;
9608
9609 printf("Instructions set:\n");
9610 /* opc1 is 6 bits long */
9611 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9612 table = env->opcodes;
9613 handler = table[opc1];
9614 if (is_indirect_opcode(handler)) {
9615 /* opc2 is 5 bits long */
9616 for (opc2 = 0; opc2 < 0x20; opc2++) {
9617 table = env->opcodes;
9618 handler = env->opcodes[opc1];
9619 table = ind_table(handler);
9620 handler = table[opc2];
9621 if (is_indirect_opcode(handler)) {
9622 table = ind_table(handler);
9623 /* opc3 is 5 bits long */
9624 for (opc3 = 0; opc3 < 0x20; opc3++) {
9625 handler = table[opc3];
9626 if (handler->handler != &gen_invalid) {
4c1b1bfe
JM		 9627 /* Special hack to properly dump SPE insns */
9628 p = strchr(handler->oname, '_');
9629 if (p == NULL) {
9630 printf("INSN: %02x %02x %02x (%02d %04d) : "
9631 "%s\n",
9632 opc1, opc2, opc3, opc1,
9633 (opc3 << 5) | opc2,
9634 handler->oname);
9635 } else {
9636 q = "speundef";
9637 if ((p - handler->oname) != strlen(q) ||
9638 memcmp(handler->oname, q, strlen(q)) != 0) {
9639 /* First instruction */
9640 printf("INSN: %02x %02x %02x (%02d %04d) : "
9641 "%.*s\n",
9642 opc1, opc2 << 1, opc3, opc1,
9643 (opc3 << 6) | (opc2 << 1),
9644 (int)(p - handler->oname),
9645 handler->oname);
9646 }
9647 if (strcmp(p + 1, q) != 0) {
9648 /* Second instruction */
9649 printf("INSN: %02x %02x %02x (%02d %04d) : "
9650 "%s\n",
9651 opc1, (opc2 << 1) | 1, opc3, opc1,
9652 (opc3 << 6) | (opc2 << 1) | 1,
9653 p + 1);
9654 }
9655 }
a750fc0b
JM		 9656 }
9657 }
9658 } else {
9659 if (handler->handler != &gen_invalid) {
9660 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9661 opc1, opc2, opc1, opc2, handler->oname);
9662 }
9663 }
9664 }
9665 } else {
9666 if (handler->handler != &gen_invalid) {
9667 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9668 opc1, opc1, handler->oname);
9669 }
9670 }
9671 }
9672}
3a607854 9673#endif
a750fc0b 9674
24951522
AJ		 9675static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9676{
9677 if (n < 32) {
9678 stfq_p(mem_buf, env->fpr[n]);
9679 return 8;
9680 }
9681 if (n == 32) {
9682 /* FPSCR not implemented */
9683 memset(mem_buf, 0, 4);
9684 return 4;
9685 }
9686 return 0;
9687}
9688
9689static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9690{
9691 if (n < 32) {
9692 env->fpr[n] = ldfq_p(mem_buf);
9693 return 8;
9694 }
9695 if (n == 32) {
9696 /* FPSCR not implemented */
9697 return 4;
9698 }
9699 return 0;
9700}
9701
b4f8d821
AJ		 9702static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9703{
9704 if (n < 32) {
e2542fe2 9705#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 9706 stq_p(mem_buf, env->avr[n].u64[0]);
9707 stq_p(mem_buf+8, env->avr[n].u64[1]);
9708#else
9709 stq_p(mem_buf, env->avr[n].u64[1]);
9710 stq_p(mem_buf+8, env->avr[n].u64[0]);
9711#endif
9712 return 16;
9713 }
70976a79 9714 if (n == 32) {
b4f8d821
AJ		 9715 stl_p(mem_buf, env->vscr);
9716 return 4;
9717 }
70976a79 9718 if (n == 33) {
b4f8d821
AJ		 9719 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9720 return 4;
9721 }
9722 return 0;
9723}
9724
9725static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9726{
9727 if (n < 32) {
e2542fe2 9728#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 9729 env->avr[n].u64[0] = ldq_p(mem_buf);
9730 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9731#else
9732 env->avr[n].u64[1] = ldq_p(mem_buf);
9733 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9734#endif
9735 return 16;
9736 }
70976a79 9737 if (n == 32) {
b4f8d821
AJ		 9738 env->vscr = ldl_p(mem_buf);
9739 return 4;
9740 }
70976a79 9741 if (n == 33) {
b4f8d821
AJ		 9742 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9743 return 4;
9744 }
9745 return 0;
9746}
9747
688890f7
AJ		 9748static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9749{
9750 if (n < 32) {
9751#if defined(TARGET_PPC64)
9752 stl_p(mem_buf, env->gpr[n] >> 32);
9753#else
9754 stl_p(mem_buf, env->gprh[n]);
9755#endif
9756 return 4;
9757 }
70976a79 9758 if (n == 32) {
688890f7
AJ		 9759 stq_p(mem_buf, env->spe_acc);
9760 return 8;
9761 }
70976a79 9762 if (n == 33) {
d34defbc 9763 stl_p(mem_buf, env->spe_fscr);
688890f7
AJ		 9764 return 4;
9765 }
9766 return 0;
9767}
9768
9769static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9770{
9771 if (n < 32) {
9772#if defined(TARGET_PPC64)
9773 target_ulong lo = (uint32_t)env->gpr[n];
9774 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9775 env->gpr[n] = lo | hi;
9776#else
9777 env->gprh[n] = ldl_p(mem_buf);
9778#endif
9779 return 4;
9780 }
70976a79 9781 if (n == 32) {
688890f7
AJ		 9782 env->spe_acc = ldq_p(mem_buf);
9783 return 8;
9784 }
70976a79 9785 if (n == 33) {
d34defbc 9786 env->spe_fscr = ldl_p(mem_buf);
688890f7
AJ		 9787 return 4;
9788 }
9789 return 0;
9790}
9791
c227f099 9792int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 9793{
9794 env->msr_mask = def->msr_mask;
9795 env->mmu_model = def->mmu_model;
9796 env->excp_model = def->excp_model;
9797 env->bus_model = def->bus_model;
c29b735c 9798 env->insns_flags = def->insns_flags;
a5858d7a 9799 env->insns_flags2 = def->insns_flags2;
d26bfc9a 9800 env->flags = def->flags;
237c0af0 9801 env->bfd_mach = def->bfd_mach;
2f462816 9802 env->check_pow = def->check_pow;
a750fc0b
JM		 9803 if (create_ppc_opcodes(env, def) < 0)
9804 return -1;
9805 init_ppc_proc(env, def);
24951522
AJ		 9806
9807 if (def->insns_flags & PPC_FLOAT) {
9808 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9809 33, "power-fpu.xml", 0);
9810 }
b4f8d821
AJ		 9811 if (def->insns_flags & PPC_ALTIVEC) {
9812 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9813 34, "power-altivec.xml", 0);
9814 }
40569b7e 9815 if (def->insns_flags & PPC_SPE) {
688890f7
AJ		 9816 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9817 34, "power-spe.xml", 0);
9818 }
9819
a750fc0b 9820#if defined(PPC_DUMP_CPU)
3a607854 9821 {
b55266b5 9822 const char *mmu_model, *excp_model, *bus_model;
a750fc0b
JM		 9823 switch (env->mmu_model) {
9824 case POWERPC_MMU_32B:
9825 mmu_model = "PowerPC 32";
9826 break;
a750fc0b
JM		 9827 case POWERPC_MMU_SOFT_6xx:
9828 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9829 break;
9830 case POWERPC_MMU_SOFT_74xx:
9831 mmu_model = "PowerPC 74xx with software driven TLBs";
9832 break;
9833 case POWERPC_MMU_SOFT_4xx:
9834 mmu_model = "PowerPC 4xx with software driven TLBs";
9835 break;
9836 case POWERPC_MMU_SOFT_4xx_Z:
9837 mmu_model = "PowerPC 4xx with software driven TLBs "
9838 "and zones protections";
9839 break;
b4095fed
JM		 9840 case POWERPC_MMU_REAL:
9841 mmu_model = "PowerPC real mode only";
9842 break;
9843 case POWERPC_MMU_MPC8xx:
9844 mmu_model = "PowerPC MPC8xx";
a750fc0b
JM		 9845 break;
9846 case POWERPC_MMU_BOOKE:
9847 mmu_model = "PowerPC BookE";
9848 break;
01662f3e
AG		 9849 case POWERPC_MMU_BOOKE206:
9850 mmu_model = "PowerPC BookE 2.06";
a750fc0b 9851 break;
b4095fed
JM		 9852 case POWERPC_MMU_601:
9853 mmu_model = "PowerPC 601";
9854 break;
00af685f
JM		 9855#if defined (TARGET_PPC64)
9856 case POWERPC_MMU_64B:
9857 mmu_model = "PowerPC 64";
9858 break;
add78955
JM		 9859 case POWERPC_MMU_620:
9860 mmu_model = "PowerPC 620";
9861 break;
00af685f 9862#endif
a750fc0b
JM		 9863 default:
9864 mmu_model = "Unknown or invalid";
9865 break;
9866 }
9867 switch (env->excp_model) {
9868 case POWERPC_EXCP_STD:
9869 excp_model = "PowerPC";
9870 break;
9871 case POWERPC_EXCP_40x:
9872 excp_model = "PowerPC 40x";
9873 break;
9874 case POWERPC_EXCP_601:
9875 excp_model = "PowerPC 601";
9876 break;
9877 case POWERPC_EXCP_602:
9878 excp_model = "PowerPC 602";
9879 break;
9880 case POWERPC_EXCP_603:
9881 excp_model = "PowerPC 603";
9882 break;
9883 case POWERPC_EXCP_603E:
9884 excp_model = "PowerPC 603e";
9885 break;
9886 case POWERPC_EXCP_604:
9887 excp_model = "PowerPC 604";
9888 break;
9889 case POWERPC_EXCP_7x0:
9890 excp_model = "PowerPC 740/750";
9891 break;
9892 case POWERPC_EXCP_7x5:
9893 excp_model = "PowerPC 745/755";
9894 break;
9895 case POWERPC_EXCP_74xx:
9896 excp_model = "PowerPC 74xx";
9897 break;
a750fc0b
JM		 9898 case POWERPC_EXCP_BOOKE:
9899 excp_model = "PowerPC BookE";
9900 break;
00af685f
JM		 9901#if defined (TARGET_PPC64)
9902 case POWERPC_EXCP_970:
9903 excp_model = "PowerPC 970";
9904 break;
9905#endif
a750fc0b
JM		 9906 default:
9907 excp_model = "Unknown or invalid";
9908 break;
9909 }
9910 switch (env->bus_model) {
9911 case PPC_FLAGS_INPUT_6xx:
9912 bus_model = "PowerPC 6xx";
9913 break;
9914 case PPC_FLAGS_INPUT_BookE:
9915 bus_model = "PowerPC BookE";
9916 break;
9917 case PPC_FLAGS_INPUT_405:
9918 bus_model = "PowerPC 405";
9919 break;
a750fc0b
JM		 9920 case PPC_FLAGS_INPUT_401:
9921 bus_model = "PowerPC 401/403";
9922 break;
b4095fed
JM		 9923 case PPC_FLAGS_INPUT_RCPU:
9924 bus_model = "RCPU / MPC8xx";
9925 break;
00af685f
JM		 9926#if defined (TARGET_PPC64)
9927 case PPC_FLAGS_INPUT_970:
9928 bus_model = "PowerPC 970";
9929 break;
9930#endif
a750fc0b
JM		 9931 default:
9932 bus_model = "Unknown or invalid";
9933 break;
9934 }
9935 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9936 " MMU model : %s\n",
9937 def->name, def->pvr, def->msr_mask, mmu_model);
f2e63a42 9938#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 9939 if (env->tlb != NULL) {
9940 printf(" %d %s TLB in %d ways\n",
9941 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9942 env->nb_ways);
9943 }
f2e63a42 9944#endif
a750fc0b
JM		 9945 printf(" Exceptions model : %s\n"
9946 " Bus model : %s\n",
9947 excp_model, bus_model);
25ba3a68
JM		 9948 printf(" MSR features :\n");
9949 if (env->flags & POWERPC_FLAG_SPE)
9950 printf(" signal processing engine enable"
9951 "\n");
9952 else if (env->flags & POWERPC_FLAG_VRE)
9953 printf(" vector processor enable\n");
9954 if (env->flags & POWERPC_FLAG_TGPR)
9955 printf(" temporary GPRs\n");
9956 else if (env->flags & POWERPC_FLAG_CE)
9957 printf(" critical input enable\n");
9958 if (env->flags & POWERPC_FLAG_SE)
9959 printf(" single-step trace mode\n");
9960 else if (env->flags & POWERPC_FLAG_DWE)
9961 printf(" debug wait enable\n");
9962 else if (env->flags & POWERPC_FLAG_UBLE)
9963 printf(" user BTB lock enable\n");
9964 if (env->flags & POWERPC_FLAG_BE)
9965 printf(" branch-step trace mode\n");
9966 else if (env->flags & POWERPC_FLAG_DE)
9967 printf(" debug interrupt enable\n");
9968 if (env->flags & POWERPC_FLAG_PX)
9969 printf(" inclusive protection\n");
9970 else if (env->flags & POWERPC_FLAG_PMM)
9971 printf(" performance monitor mark\n");
9972 if (env->flags == POWERPC_FLAG_NONE)
9973 printf(" none\n");
4018bae9
JM		 9974 printf(" Time-base/decrementer clock source: %s\n",
9975 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
a750fc0b
JM		 9976 }
9977 dump_ppc_insns(env);
9978 dump_ppc_sprs(env);
9979 fflush(stdout);
3a607854 9980#endif
a750fc0b
JM		 9981
9982 return 0;
9983}
3fc6c082 9984
c227f099 9985static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
3fc6c082 9986{
c227f099 9987 const ppc_def_t *ret;
ee4e83ed
JM		 9988 uint32_t pvr_rev;
9989 int i, best, match, best_match, max;
3fc6c082 9990
ee4e83ed 9991 ret = NULL;
b1503cda 9992 max = ARRAY_SIZE(ppc_defs);
ee4e83ed
JM		 9993 best = -1;
9994 pvr_rev = pvr & 0xFFFF;
9995 /* We want all specified bits to match */
9996 best_match = 32 - ctz32(pvr_rev);
068abdc8 9997 for (i = 0; i < max; i++) {
ee4e83ed
JM		 9998 /* We check that the 16 higher bits are the same to ensure the CPU
9999 * model will be the choosen one.
10000 */
10001 if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
10002 /* We want as much as possible of the low-level 16 bits
10003 * to be the same but we allow inexact matches.
10004 */
10005 match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
10006 /* We check '>=' instead of '>' because the PPC_defs table
10007 * is ordered by increasing revision.
4c1b1bfe 10008 * Then, we will match the higher revision compatible
ee4e83ed
JM		 10009 * with the requested PVR
10010 */
10011 if (match >= best_match) {
10012 best = i;
10013 best_match = match;
10014 }
3fc6c082
FB		 10015 }
10016 }
ee4e83ed
JM		 10017 if (best != -1)
10018 ret = &ppc_defs[best];
10019
10020 return ret;
3fc6c082
FB		 10021}
10022
ee4e83ed 10023#include <ctype.h>
3fc6c082 10024
c227f099 10025const ppc_def_t *cpu_ppc_find_by_name (const char *name)
ee4e83ed 10026{
c227f099 10027 const ppc_def_t *ret;
b55266b5 10028 const char *p;
ee4e83ed
JM		 10029 int i, max, len;
10030
10031 /* Check if the given name is a PVR */
10032 len = strlen(name);
10033 if (len == 10 && name[0] == '0' && name[1] == 'x') {
10034 p = name + 2;
10035 goto check_pvr;
10036 } else if (len == 8) {
10037 p = name;
10038 check_pvr:
10039 for (i = 0; i < 8; i++) {
cd390083 10040 if (!qemu_isxdigit(*p++))
ee4e83ed
JM		 10041 break;
10042 }
10043 if (i == 8)
10044 return ppc_find_by_pvr(strtoul(name, NULL, 16));
10045 }
10046 ret = NULL;
b1503cda 10047 max = ARRAY_SIZE(ppc_defs);
068abdc8 10048 for (i = 0; i < max; i++) {
ee4e83ed
JM		 10049 if (strcasecmp(name, ppc_defs[i].name) == 0) {
10050 ret = &ppc_defs[i];
10051 break;
3fc6c082
FB		 10052 }
10053 }
ee4e83ed
JM		 10054
10055 return ret;
3fc6c082
FB		 10056}
10057
9a78eead 10058void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
3fc6c082 10059{
068abdc8 10060 int i, max;
3fc6c082 10061
b1503cda 10062 max = ARRAY_SIZE(ppc_defs);
068abdc8 10063 for (i = 0; i < max; i++) {
a750fc0b
JM		 10064 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
10065 ppc_defs[i].name, ppc_defs[i].pvr);
3fc6c082
FB		 10066 }
10067}
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