]>
Commit | Line | Data |
---|---|---|
ef056e43 AZ |
1 | /* |
2 | * PXA270-based Intel Mainstone platforms. | |
3 | * | |
4 | * Copyright (c) 2007 by Armin Kuster <[email protected]> or | |
5 | * <[email protected]> | |
6 | * | |
7 | * Code based on spitz platform by Andrzej Zaborowski <[email protected]> | |
8 | * | |
9 | * This code is licensed under the GNU GPL v2. | |
10 | */ | |
11 | #include "hw.h" | |
12 | #include "pxa.h" | |
13 | #include "arm-misc.h" | |
ef056e43 AZ |
14 | #include "net.h" |
15 | #include "devices.h" | |
16 | #include "boards.h" | |
7233b355 TS |
17 | #include "mainstone.h" |
18 | #include "sysemu.h" | |
19 | #include "flash.h" | |
ef056e43 | 20 | |
bd464c2e AZ |
21 | static struct keymap map[0xE0] = { |
22 | [0 ... 0xDF] = { -1, -1 }, | |
23 | [0x1e] = {0,0}, /* a */ | |
24 | [0x30] = {0,1}, /* b */ | |
25 | [0x2e] = {0,2}, /* c */ | |
26 | [0x20] = {0,3}, /* d */ | |
27 | [0x12] = {0,4}, /* e */ | |
28 | [0x21] = {0,5}, /* f */ | |
29 | [0x22] = {1,0}, /* g */ | |
30 | [0x23] = {1,1}, /* h */ | |
31 | [0x17] = {1,2}, /* i */ | |
32 | [0x24] = {1,3}, /* j */ | |
33 | [0x25] = {1,4}, /* k */ | |
34 | [0x26] = {1,5}, /* l */ | |
35 | [0x32] = {2,0}, /* m */ | |
36 | [0x31] = {2,1}, /* n */ | |
37 | [0x18] = {2,2}, /* o */ | |
38 | [0x19] = {2,3}, /* p */ | |
39 | [0x10] = {2,4}, /* q */ | |
40 | [0x13] = {2,5}, /* r */ | |
41 | [0x1f] = {3,0}, /* s */ | |
42 | [0x14] = {3,1}, /* t */ | |
43 | [0x16] = {3,2}, /* u */ | |
44 | [0x2f] = {3,3}, /* v */ | |
45 | [0x11] = {3,4}, /* w */ | |
46 | [0x2d] = {3,5}, /* x */ | |
47 | [0x15] = {4,2}, /* y */ | |
48 | [0x2c] = {4,3}, /* z */ | |
49 | [0xc7] = {5,0}, /* Home */ | |
50 | [0x2a] = {5,1}, /* shift */ | |
51 | [0x39] = {5,2}, /* space */ | |
52 | [0x39] = {5,3}, /* space */ | |
53 | [0x1c] = {5,5}, /* enter */ | |
54 | [0xc8] = {6,0}, /* up */ | |
55 | [0xd0] = {6,1}, /* down */ | |
56 | [0xcb] = {6,2}, /* left */ | |
57 | [0xcd] = {6,3}, /* right */ | |
58 | }; | |
59 | ||
ef056e43 AZ |
60 | enum mainstone_model_e { mainstone }; |
61 | ||
7fb4fdcf AZ |
62 | #define MAINSTONE_RAM 0x04000000 |
63 | #define MAINSTONE_ROM 0x00800000 | |
64 | #define MAINSTONE_FLASH 0x02000000 | |
65 | ||
f93eb9ff AZ |
66 | static struct arm_boot_info mainstone_binfo = { |
67 | .loader_start = PXA2XX_SDRAM_BASE, | |
68 | .ram_size = 0x04000000, | |
69 | }; | |
70 | ||
00f82b8a | 71 | static void mainstone_common_init(ram_addr_t ram_size, int vga_ram_size, |
3023f332 | 72 | const char *kernel_filename, |
ef056e43 AZ |
73 | const char *kernel_cmdline, const char *initrd_filename, |
74 | const char *cpu_model, enum mainstone_model_e model, int arm_id) | |
75 | { | |
6d1f1778 AZ |
76 | uint32_t sector_len = 256 * 1024; |
77 | target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 }; | |
bc24a225 | 78 | PXA2xxState *cpu; |
ef056e43 | 79 | qemu_irq *mst_irq; |
6d1f1778 | 80 | int i, index; |
ef056e43 AZ |
81 | |
82 | if (!cpu_model) | |
83 | cpu_model = "pxa270-c5"; | |
84 | ||
85 | /* Setup CPU & memory */ | |
3023f332 | 86 | cpu = pxa270_init(mainstone_binfo.ram_size, cpu_model); |
7fb4fdcf AZ |
87 | cpu_register_physical_memory(0, MAINSTONE_ROM, |
88 | qemu_ram_alloc(MAINSTONE_ROM) | IO_MEM_ROM); | |
ef056e43 AZ |
89 | |
90 | /* Setup initial (reset) machine state */ | |
f93eb9ff | 91 | cpu->env->regs[15] = mainstone_binfo.loader_start; |
ef056e43 | 92 | |
e4bcb14c | 93 | /* There are two 32MiB flash devices on the board */ |
6d1f1778 AZ |
94 | for (i = 0; i < 2; i ++) { |
95 | index = drive_get_index(IF_PFLASH, 0, i); | |
96 | if (index == -1) { | |
97 | fprintf(stderr, "Two flash images must be given with the " | |
98 | "'pflash' parameter\n"); | |
99 | exit(1); | |
100 | } | |
101 | ||
102 | if (!pflash_cfi01_register(mainstone_flash_base[i], | |
7fb4fdcf | 103 | qemu_ram_alloc(MAINSTONE_FLASH), |
6d1f1778 | 104 | drives_table[index].bdrv, sector_len, |
7fb4fdcf | 105 | MAINSTONE_FLASH / sector_len, 4, 0, 0, 0, 0)) { |
6d1f1778 AZ |
106 | fprintf(stderr, "qemu: Error registering flash memory.\n"); |
107 | exit(1); | |
108 | } | |
e4bcb14c | 109 | } |
7233b355 TS |
110 | |
111 | mst_irq = mst_irq_init(cpu, MST_FPGA_PHYS, PXA2XX_PIC_GPIO_0); | |
f1de1334 | 112 | |
bd464c2e AZ |
113 | /* setup keypad */ |
114 | printf("map addr %p\n", &map); | |
115 | pxa27x_register_keypad(cpu->kp, map, 0xe0); | |
116 | ||
f1de1334 | 117 | /* MMC/SD host */ |
8543243c | 118 | pxa2xx_mmci_handlers(cpu->mmc, NULL, mst_irq[MMC_IRQ]); |
f1de1334 | 119 | |
ef056e43 AZ |
120 | smc91c111_init(&nd_table[0], MST_ETH_PHYS, mst_irq[ETHERNET_IRQ]); |
121 | ||
f93eb9ff AZ |
122 | mainstone_binfo.kernel_filename = kernel_filename; |
123 | mainstone_binfo.kernel_cmdline = kernel_cmdline; | |
124 | mainstone_binfo.initrd_filename = initrd_filename; | |
125 | mainstone_binfo.board_id = arm_id; | |
126 | arm_load_kernel(cpu->env, &mainstone_binfo); | |
ef056e43 AZ |
127 | } |
128 | ||
00f82b8a | 129 | static void mainstone_init(ram_addr_t ram_size, int vga_ram_size, |
3023f332 | 130 | const char *boot_device, |
ef056e43 AZ |
131 | const char *kernel_filename, const char *kernel_cmdline, |
132 | const char *initrd_filename, const char *cpu_model) | |
133 | { | |
3023f332 | 134 | mainstone_common_init(ram_size, vga_ram_size, kernel_filename, |
ef056e43 AZ |
135 | kernel_cmdline, initrd_filename, cpu_model, mainstone, 0x196); |
136 | } | |
137 | ||
138 | QEMUMachine mainstone2_machine = { | |
4b32e168 AL |
139 | .name = "mainstone", |
140 | .desc = "Mainstone II (PXA27x)", | |
141 | .init = mainstone_init, | |
ef056e43 | 142 | }; |