[qemu.git] / hw / pcnet-pci.c

/*
 * QEMU AMD PC-Net II (Am79C970A) PCI emulation
 *
 * Copyright (c) 2004 Antony T Curtis
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* This software was written to be compatible with the specification:
 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
 * AMD Publication# 19436  Rev:E  Amendment/0  Issue Date: June 2000
 */

#include "pci.h"
#include "net.h"
#include "loader.h"
#include "qemu-timer.h"

#include "pcnet.h"

//#define PCNET_DEBUG
//#define PCNET_DEBUG_IO
//#define PCNET_DEBUG_BCR
//#define PCNET_DEBUG_CSR
//#define PCNET_DEBUG_RMD
//#define PCNET_DEBUG_TMD
//#define PCNET_DEBUG_MATCH


typedef struct {
    PCIDevice pci_dev;
    PCNetState state;
    MemoryRegion io_bar;
} PCIPCNetState;

static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    PCNetState *s = opaque;
#ifdef PCNET_DEBUG
    printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val);
#endif
    /* Check APROMWE bit to enable write access */
    if (pcnet_bcr_readw(s,2) & 0x100)
        s->prom[addr & 15] = val;
}

static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
{
    PCNetState *s = opaque;
    uint32_t val = s->prom[addr & 15];
#ifdef PCNET_DEBUG
    printf("pcnet_aprom_readb addr=0x%08x val=0x%02x\n", addr, val);
#endif
    return val;
}

static uint64_t pcnet_ioport_read(void *opaque, target_phys_addr_t addr,
                                  unsigned size)
{
    PCNetState *d = opaque;

    if (addr < 16 && size == 1) {
        return pcnet_aprom_readb(d, addr);
    } else if (addr >= 0x10 && addr < 0x20 && size == 2) {
        return pcnet_ioport_readw(d, addr);
    } else if (addr >= 0x10 && addr < 0x20 && size == 4) {
        return pcnet_ioport_readl(d, addr);
    }
    return ((uint64_t)1 << (size * 8)) - 1;
}

static void pcnet_ioport_write(void *opaque, target_phys_addr_t addr,
                               uint64_t data, unsigned size)
{
    PCNetState *d = opaque;

    if (addr < 16 && size == 1) {
        return pcnet_aprom_writeb(d, addr, data);
    } else if (addr >= 0x10 && addr < 0x20 && size == 2) {
        return pcnet_ioport_writew(d, addr, data);
    } else if (addr >= 0x10 && addr < 0x20 && size == 4) {
        return pcnet_ioport_writel(d, addr, data);
    }
}

static const MemoryRegionOps pcnet_io_ops = {
    .read = pcnet_ioport_read,
    .write = pcnet_ioport_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_writeb addr=0x" TARGET_FMT_plx" val=0x%02x\n", addr,
           val);
#endif
    if (!(addr & 0x10))
        pcnet_aprom_writeb(d, addr & 0x0f, val);
}

static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr)
{
    PCNetState *d = opaque;
    uint32_t val = -1;
    if (!(addr & 0x10))
        val = pcnet_aprom_readb(d, addr & 0x0f);
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_readb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr,
           val & 0xff);
#endif
    return val;
}

static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr,
           val);
#endif
    if (addr & 0x10)
        pcnet_ioport_writew(d, addr & 0x0f, val);
    else {
        addr &= 0x0f;
        pcnet_aprom_writeb(d, addr, val & 0xff);
        pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
    }
}

static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr)
{
    PCNetState *d = opaque;
    uint32_t val = -1;
    if (addr & 0x10)
        val = pcnet_ioport_readw(d, addr & 0x0f);
    else {
        addr &= 0x0f;
        val = pcnet_aprom_readb(d, addr+1);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr);
    }
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_readw addr=0x" TARGET_FMT_plx" val = 0x%04x\n", addr,
           val & 0xffff);
#endif
    return val;
}

static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_writel addr=0x" TARGET_FMT_plx" val=0x%08x\n", addr,
           val);
#endif
    if (addr & 0x10)
        pcnet_ioport_writel(d, addr & 0x0f, val);
    else {
        addr &= 0x0f;
        pcnet_aprom_writeb(d, addr, val & 0xff);
        pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
        pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
        pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24);
    }
}

static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr)
{
    PCNetState *d = opaque;
    uint32_t val;
    if (addr & 0x10)
        val = pcnet_ioport_readl(d, addr & 0x0f);
    else {
        addr &= 0x0f;
        val = pcnet_aprom_readb(d, addr+3);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr+2);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr+1);
        val <<= 8;
        val |= pcnet_aprom_readb(d, addr);
    }
#ifdef PCNET_DEBUG_IO
    printf("pcnet_mmio_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr,
           val);
#endif
    return val;
}

static const VMStateDescription vmstate_pci_pcnet = {
    .name = "pcnet",
    .version_id = 3,
    .minimum_version_id = 2,
    .minimum_version_id_old = 2,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(pci_dev, PCIPCNetState),
        VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState),
        VMSTATE_END_OF_LIST()
    }
};

/* PCI interface */

static const MemoryRegionOps pcnet_mmio_ops = {
    .old_mmio = {
        .read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
        .write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t addr,
                                      uint8_t *buf, int len, int do_bswap)
{
    cpu_physical_memory_write(addr, buf, len);
}

static void pci_physical_memory_read(void *dma_opaque, target_phys_addr_t addr,
                                     uint8_t *buf, int len, int do_bswap)
{
    cpu_physical_memory_read(addr, buf, len);
}

static void pci_pcnet_cleanup(VLANClientState *nc)
{
    PCNetState *d = DO_UPCAST(NICState, nc, nc)->opaque;

    pcnet_common_cleanup(d);
}

static int pci_pcnet_uninit(PCIDevice *dev)
{
    PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, dev);

    memory_region_destroy(&d->state.mmio);
    memory_region_destroy(&d->io_bar);
    qemu_del_timer(d->state.poll_timer);
    qemu_free_timer(d->state.poll_timer);
    qemu_del_vlan_client(&d->state.nic->nc);
    return 0;
}

static NetClientInfo net_pci_pcnet_info = {
    .type = NET_CLIENT_TYPE_NIC,
    .size = sizeof(NICState),
    .can_receive = pcnet_can_receive,
    .receive = pcnet_receive,
    .cleanup = pci_pcnet_cleanup,
};

static int pci_pcnet_init(PCIDevice *pci_dev)
{
    PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, pci_dev);
    PCNetState *s = &d->state;
    uint8_t *pci_conf;

#if 0
    printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
        sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
#endif

    pci_conf = pci_dev->config;

    pci_set_word(pci_conf + PCI_STATUS,
                 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);

    pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
    pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);

    pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
    pci_conf[PCI_MIN_GNT] = 0x06;
    pci_conf[PCI_MAX_LAT] = 0xff;

    /* Handler for memory-mapped I/O */
    memory_region_init_io(&d->state.mmio, &pcnet_mmio_ops, s, "pcnet-mmio",
                          PCNET_PNPMMIO_SIZE);

    memory_region_init_io(&d->io_bar, &pcnet_io_ops, s, "pcnet-io",
                          PCNET_IOPORT_SIZE);
    pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);

    pci_register_bar(pci_dev, 1, 0, &s->mmio);

    s->irq = pci_dev->irq[0];
    s->phys_mem_read = pci_physical_memory_read;
    s->phys_mem_write = pci_physical_memory_write;

    if (!pci_dev->qdev.hotplugged) {
        static int loaded = 0;
        if (!loaded) {
            rom_add_option("pxe-pcnet.rom", -1);
            loaded = 1;
        }
    }

    return pcnet_common_init(&pci_dev->qdev, s, &net_pci_pcnet_info);
}

static void pci_reset(DeviceState *dev)
{
    PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev.qdev, dev);

    pcnet_h_reset(&d->state);
}

static PCIDeviceInfo pcnet_info = {
    .qdev.name  = "pcnet",
    .qdev.size  = sizeof(PCIPCNetState),
    .qdev.reset = pci_reset,
    .qdev.vmsd  = &vmstate_pci_pcnet,
    .init       = pci_pcnet_init,
    .exit       = pci_pcnet_uninit,
    .vendor_id  = PCI_VENDOR_ID_AMD,
    .device_id  = PCI_DEVICE_ID_AMD_LANCE,
    .revision   = 0x10,
    .class_id   = PCI_CLASS_NETWORK_ETHERNET,
    .qdev.props = (Property[]) {
        DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void pci_pcnet_register_devices(void)
{
    pci_qdev_register(&pcnet_info);
}

device_init(pci_pcnet_register_devices)
Commit	Line	Data
661a1799 PB	1	/*
	2	* QEMU AMD PC-Net II (Am79C970A) PCI emulation
	3	*
	4	* Copyright (c) 2004 Antony T Curtis
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	/* This software was written to be compatible with the specification:
	26	* AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
	27	* AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
	28	*/
	29
	30	#include "pci.h"
	31	#include "net.h"
	32	#include "loader.h"
	33	#include "qemu-timer.h"
	34
	35	#include "pcnet.h"
	36
	37	//#define PCNET_DEBUG
	38	//#define PCNET_DEBUG_IO
	39	//#define PCNET_DEBUG_BCR
	40	//#define PCNET_DEBUG_CSR
	41	//#define PCNET_DEBUG_RMD
	42	//#define PCNET_DEBUG_TMD
	43	//#define PCNET_DEBUG_MATCH
	44
	45
	46	typedef struct {
	47	PCIDevice pci_dev;
	48	PCNetState state;
bd8d6f7c	49	MemoryRegion io_bar;
661a1799 PB	50	} PCIPCNetState;
	51
	52	static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
	53	{
	54	PCNetState *s = opaque;
	55	#ifdef PCNET_DEBUG
	56	printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val);
	57	#endif
	58	/* Check APROMWE bit to enable write access */
	59	if (pcnet_bcr_readw(s,2) & 0x100)
	60	s->prom[addr & 15] = val;
	61	}
	62
	63	static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
	64	{
	65	PCNetState *s = opaque;
	66	uint32_t val = s->prom[addr & 15];
	67	#ifdef PCNET_DEBUG
	68	printf("pcnet_aprom_readb addr=0x%08x val=0x%02x\n", addr, val);
	69	#endif
	70	return val;
	71	}
	72
bd8d6f7c AK	73	static uint64_t pcnet_ioport_read(void *opaque, target_phys_addr_t addr,
bd8d6f7c AK	74	unsigned size)
661a1799	75	{
bd8d6f7c	76	PCNetState *d = opaque;
661a1799	77
bd8d6f7c AK	78	if (addr < 16 && size == 1) {
	79	return pcnet_aprom_readb(d, addr);
	80	} else if (addr >= 0x10 && addr < 0x20 && size == 2) {
	81	return pcnet_ioport_readw(d, addr);
	82	} else if (addr >= 0x10 && addr < 0x20 && size == 4) {
	83	return pcnet_ioport_readl(d, addr);
	84	}
	85	return ((uint64_t)1 << (size * 8)) - 1;
	86	}
661a1799	87
bd8d6f7c AK	88	static void pcnet_ioport_write(void *opaque, target_phys_addr_t addr,
	89	uint64_t data, unsigned size)
	90	{
	91	PCNetState *d = opaque;
661a1799	92
bd8d6f7c AK	93	if (addr < 16 && size == 1) {
	94	return pcnet_aprom_writeb(d, addr, data);
	95	} else if (addr >= 0x10 && addr < 0x20 && size == 2) {
	96	return pcnet_ioport_writew(d, addr, data);
	97	} else if (addr >= 0x10 && addr < 0x20 && size == 4) {
	98	return pcnet_ioport_writel(d, addr, data);
	99	}
661a1799 PB	100	}
661a1799 PB	101
bd8d6f7c AK	102	static const MemoryRegionOps pcnet_io_ops = {
	103	.read = pcnet_ioport_read,
	104	.write = pcnet_ioport_write,
	105	.endianness = DEVICE_NATIVE_ENDIAN,
	106	};
	107
661a1799 PB	108	static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
	109	{
	110	PCNetState *d = opaque;
	111	#ifdef PCNET_DEBUG_IO
	112	printf("pcnet_mmio_writeb addr=0x" TARGET_FMT_plx" val=0x%02x\n", addr,
	113	val);
	114	#endif
	115	if (!(addr & 0x10))
	116	pcnet_aprom_writeb(d, addr & 0x0f, val);
	117	}
	118
	119	static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr)
	120	{
	121	PCNetState *d = opaque;
	122	uint32_t val = -1;
	123	if (!(addr & 0x10))
	124	val = pcnet_aprom_readb(d, addr & 0x0f);
	125	#ifdef PCNET_DEBUG_IO
	126	printf("pcnet_mmio_readb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr,
	127	val & 0xff);
	128	#endif
	129	return val;
	130	}
	131
	132	static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
	133	{
	134	PCNetState *d = opaque;
	135	#ifdef PCNET_DEBUG_IO
	136	printf("pcnet_mmio_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr,
	137	val);
	138	#endif
	139	if (addr & 0x10)
	140	pcnet_ioport_writew(d, addr & 0x0f, val);
	141	else {
	142	addr &= 0x0f;
	143	pcnet_aprom_writeb(d, addr, val & 0xff);
	144	pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
	145	}
	146	}
	147
	148	static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr)
	149	{
	150	PCNetState *d = opaque;
	151	uint32_t val = -1;
	152	if (addr & 0x10)
	153	val = pcnet_ioport_readw(d, addr & 0x0f);
	154	else {
	155	addr &= 0x0f;
	156	val = pcnet_aprom_readb(d, addr+1);
	157	val <<= 8;
	158	val \|= pcnet_aprom_readb(d, addr);
	159	}
	160	#ifdef PCNET_DEBUG_IO
	161	printf("pcnet_mmio_readw addr=0x" TARGET_FMT_plx" val = 0x%04x\n", addr,
	162	val & 0xffff);
	163	#endif
	164	return val;
	165	}
	166
	167	static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	168	{
	169	PCNetState *d = opaque;
	170	#ifdef PCNET_DEBUG_IO
	171	printf("pcnet_mmio_writel addr=0x" TARGET_FMT_plx" val=0x%08x\n", addr,
172	val);
173	#endif
174	if (addr & 0x10)
175	pcnet_ioport_writel(d, addr & 0x0f, val);
176	else {
177	addr &= 0x0f;
178	pcnet_aprom_writeb(d, addr, val & 0xff);
179	pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
180	pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
181	pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24);
182	}
183	}
184
185	static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr)
186	{
187	PCNetState *d = opaque;
188	uint32_t val;
189	if (addr & 0x10)
190	val = pcnet_ioport_readl(d, addr & 0x0f);
191	else {
192	addr &= 0x0f;
193	val = pcnet_aprom_readb(d, addr+3);
194	val <<= 8;
195	val \|= pcnet_aprom_readb(d, addr+2);
196	val <<= 8;
197	val \|= pcnet_aprom_readb(d, addr+1);
198	val <<= 8;
199	val \|= pcnet_aprom_readb(d, addr);
200	}
201	#ifdef PCNET_DEBUG_IO
202	printf("pcnet_mmio_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr,
203	val);
204	#endif
205	return val;
206	}
207
208	static const VMStateDescription vmstate_pci_pcnet = {
209	.name = "pcnet",
210	.version_id = 3,
211	.minimum_version_id = 2,
212	.minimum_version_id_old = 2,
213	.fields = (VMStateField []) {
214	VMSTATE_PCI_DEVICE(pci_dev, PCIPCNetState),
215	VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState),
216	VMSTATE_END_OF_LIST()
217	}
218	};
219
220	/* PCI interface */
221
bd8d6f7c AK	222	static const MemoryRegionOps pcnet_mmio_ops = {
	223	.old_mmio = {
	224	.read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
	225	.write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
	226	},
	227	.endianness = DEVICE_NATIVE_ENDIAN,
661a1799 PB	228	};
661a1799 PB	229
661a1799 PB	230	static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t addr,
	231	uint8_t *buf, int len, int do_bswap)
	232	{
	233	cpu_physical_memory_write(addr, buf, len);
	234	}
	235
	236	static void pci_physical_memory_read(void *dma_opaque, target_phys_addr_t addr,
	237	uint8_t *buf, int len, int do_bswap)
	238	{
	239	cpu_physical_memory_read(addr, buf, len);
	240	}
	241
	242	static void pci_pcnet_cleanup(VLANClientState *nc)
	243	{
	244	PCNetState *d = DO_UPCAST(NICState, nc, nc)->opaque;
	245
	246	pcnet_common_cleanup(d);
	247	}
	248
	249	static int pci_pcnet_uninit(PCIDevice *dev)
	250	{
	251	PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, dev);
	252
bd8d6f7c AK	253	memory_region_destroy(&d->state.mmio);
bd8d6f7c AK	254	memory_region_destroy(&d->io_bar);
661a1799 PB	255	qemu_del_timer(d->state.poll_timer);
	256	qemu_free_timer(d->state.poll_timer);
	257	qemu_del_vlan_client(&d->state.nic->nc);
	258	return 0;
	259	}
	260
	261	static NetClientInfo net_pci_pcnet_info = {
	262	.type = NET_CLIENT_TYPE_NIC,
	263	.size = sizeof(NICState),
	264	.can_receive = pcnet_can_receive,
	265	.receive = pcnet_receive,
	266	.cleanup = pci_pcnet_cleanup,
	267	};
	268
	269	static int pci_pcnet_init(PCIDevice *pci_dev)
	270	{
	271	PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, pci_dev);
	272	PCNetState *s = &d->state;
	273	uint8_t *pci_conf;
	274
	275	#if 0
	276	printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
	277	sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
	278	#endif
	279
	280	pci_conf = pci_dev->config;
	281
661a1799 PB	282	pci_set_word(pci_conf + PCI_STATUS,
661a1799 PB	283	PCI_STATUS_FAST_BACK \| PCI_STATUS_DEVSEL_MEDIUM);
661a1799 PB	284
	285	pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
	286	pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);
	287
817e0b6f	288	pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
661a1799 PB	289	pci_conf[PCI_MIN_GNT] = 0x06;
	290	pci_conf[PCI_MAX_LAT] = 0xff;
	291
	292	/* Handler for memory-mapped I/O */
145aebec	293	memory_region_init_io(&d->state.mmio, &pcnet_mmio_ops, s, "pcnet-mmio",
bd8d6f7c	294	PCNET_PNPMMIO_SIZE);
661a1799	295
145aebec	296	memory_region_init_io(&d->io_bar, &pcnet_io_ops, s, "pcnet-io",
bd8d6f7c	297	PCNET_IOPORT_SIZE);
e824b2cc	298	pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);
661a1799	299
e824b2cc	300	pci_register_bar(pci_dev, 1, 0, &s->mmio);
661a1799 PB	301
	302	s->irq = pci_dev->irq[0];
	303	s->phys_mem_read = pci_physical_memory_read;
	304	s->phys_mem_write = pci_physical_memory_write;
	305
	306	if (!pci_dev->qdev.hotplugged) {
	307	static int loaded = 0;
	308	if (!loaded) {
5ee8ad71	309	rom_add_option("pxe-pcnet.rom", -1);
661a1799 PB	310	loaded = 1;
	311	}
	312	}
	313
	314	return pcnet_common_init(&pci_dev->qdev, s, &net_pci_pcnet_info);
	315	}
	316
	317	static void pci_reset(DeviceState *dev)
	318	{
	319	PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev.qdev, dev);
	320
	321	pcnet_h_reset(&d->state);
	322	}
	323
	324	static PCIDeviceInfo pcnet_info = {
	325	.qdev.name = "pcnet",
	326	.qdev.size = sizeof(PCIPCNetState),
	327	.qdev.reset = pci_reset,
	328	.qdev.vmsd = &vmstate_pci_pcnet,
	329	.init = pci_pcnet_init,
	330	.exit = pci_pcnet_uninit,
d7dccd11 IY	331	.vendor_id = PCI_VENDOR_ID_AMD,
	332	.device_id = PCI_DEVICE_ID_AMD_LANCE,
	333	.revision = 0x10,
	334	.class_id = PCI_CLASS_NETWORK_ETHERNET,
661a1799 PB	335	.qdev.props = (Property[]) {
	336	DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf),
	337	DEFINE_PROP_END_OF_LIST(),
	338	}
	339	};
	340
	341	static void pci_pcnet_register_devices(void)
	342	{
	343	pci_qdev_register(&pcnet_info);
	344	}
	345
	346	device_init(pci_pcnet_register_devices)