[qemu.git] / hw / mips_fulong2e.c

/*
 * QEMU fulong 2e mini pc support
 *
 * Copyright (c) 2008 yajin ([email protected])
 * Copyright (c) 2009 chenming ([email protected])
 * Copyright (c) 2010 Huacai Chen ([email protected])
 * This code is licensed under the GNU GPL v2.
 */

/*
 * Fulong 2e mini pc is based on ICT/ST Loongson 2e CPU (MIPS III like, 800MHz)
 * http://www.linux-mips.org/wiki/Fulong
 *
 * Loongson 2e user manual:
 * http://www.loongsondeveloper.com/doc/Loongson2EUserGuide.pdf
 */

#include "hw.h"
#include "pc.h"
#include "fdc.h"
#include "net.h"
#include "boards.h"
#include "smbus.h"
#include "block.h"
#include "flash.h"
#include "mips.h"
#include "mips_cpudevs.h"
#include "pci.h"
#include "usb-uhci.h"
#include "qemu-char.h"
#include "sysemu.h"
#include "audio/audio.h"
#include "qemu-log.h"
#include "loader.h"
#include "mips-bios.h"
#include "ide.h"
#include "elf.h"
#include "vt82c686.h"
#include "mc146818rtc.h"
#include "blockdev.h"
#include "exec-memory.h"

#define DEBUG_FULONG2E_INIT

#define ENVP_ADDR       0x80002000l
#define ENVP_NB_ENTRIES	 	16
#define ENVP_ENTRY_SIZE	 	256

#define MAX_IDE_BUS 2

/*
 * PMON is not part of qemu and released with BSD license, anyone
 * who want to build a pmon binary please first git-clone the source
 * from the git repository at:
 * http://www.loongson.cn/support/git/pmon
 * Then follow the "Compile Guide" available at:
 * http://dev.lemote.com/code/pmon
 *
 * Notes:
 * 1, don't use the source at http://dev.lemote.com/http_git/pmon.git
 * 2, use "Bonito2edev" to replace "dir_corresponding_to_your_target_hardware"
 * in the "Compile Guide".
 */
#define FULONG_BIOSNAME "pmon_fulong2e.bin"

/* PCI SLOT in fulong 2e */
#define FULONG2E_VIA_SLOT        5
#define FULONG2E_ATI_SLOT        6
#define FULONG2E_RTL8139_SLOT    7

static ISADevice *pit;

static struct _loaderparams {
    int ram_size;
    const char *kernel_filename;
    const char *kernel_cmdline;
    const char *initrd_filename;
} loaderparams;

static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
                                        const char *string, ...)
{
    va_list ap;
    int32_t table_addr;

    if (index >= ENVP_NB_ENTRIES)
        return;

    if (string == NULL) {
        prom_buf[index] = 0;
        return;
    }

    table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
    prom_buf[index] = tswap32(ENVP_ADDR + table_addr);

    va_start(ap, string);
    vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
    va_end(ap);
}

static int64_t load_kernel (CPUState *env)
{
    int64_t kernel_entry, kernel_low, kernel_high;
    int index = 0;
    long initrd_size;
    ram_addr_t initrd_offset;
    uint32_t *prom_buf;
    long prom_size;

    if (load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, NULL,
                 (uint64_t *)&kernel_entry, (uint64_t *)&kernel_low,
                 (uint64_t *)&kernel_high, 0, ELF_MACHINE, 1) < 0) {
        fprintf(stderr, "qemu: could not load kernel '%s'\n",
                loaderparams.kernel_filename);
        exit(1);
    }

    /* load initrd */
    initrd_size = 0;
    initrd_offset = 0;
    if (loaderparams.initrd_filename) {
        initrd_size = get_image_size (loaderparams.initrd_filename);
        if (initrd_size > 0) {
            initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
            if (initrd_offset + initrd_size > ram_size) {
                fprintf(stderr,
                        "qemu: memory too small for initial ram disk '%s'\n",
                        loaderparams.initrd_filename);
                exit(1);
            }
            initrd_size = load_image_targphys(loaderparams.initrd_filename,
                                     initrd_offset, ram_size - initrd_offset);
        }
        if (initrd_size == (target_ulong) -1) {
            fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
                    loaderparams.initrd_filename);
            exit(1);
        }
    }

    /* Setup prom parameters. */
    prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE);
    prom_buf = g_malloc(prom_size);

    prom_set(prom_buf, index++, "%s", loaderparams.kernel_filename);
    if (initrd_size > 0) {
        prom_set(prom_buf, index++, "rd_start=0x%" PRIx64 " rd_size=%li %s",
                 cpu_mips_phys_to_kseg0(NULL, initrd_offset), initrd_size,
                 loaderparams.kernel_cmdline);
    } else {
        prom_set(prom_buf, index++, "%s", loaderparams.kernel_cmdline);
    }

    /* Setup minimum environment variables */
    prom_set(prom_buf, index++, "busclock=33000000");
    prom_set(prom_buf, index++, "cpuclock=100000000");
    prom_set(prom_buf, index++, "memsize=%i", loaderparams.ram_size/1024/1024);
    prom_set(prom_buf, index++, "modetty0=38400n8r");
    prom_set(prom_buf, index++, NULL);

    rom_add_blob_fixed("prom", prom_buf, prom_size,
                       cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR));

    return kernel_entry;
}

static void write_bootloader (CPUState *env, uint8_t *base, int64_t kernel_addr)
{
    uint32_t *p;

    /* Small bootloader */
    p = (uint32_t *) base;

    stl_raw(p++, 0x0bf00010);                                      /* j 0x1fc00040 */
    stl_raw(p++, 0x00000000);                                      /* nop */

    /* Second part of the bootloader */
    p = (uint32_t *) (base + 0x040);

    stl_raw(p++, 0x3c040000);                                      /* lui a0, 0 */
    stl_raw(p++, 0x34840002);                                      /* ori a0, a0, 2 */
    stl_raw(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));       /* lui a1, high(ENVP_ADDR) */
    stl_raw(p++, 0x34a50000 | (ENVP_ADDR & 0xffff));               /* ori a1, a0, low(ENVP_ADDR) */
    stl_raw(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
    stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));         /* ori a2, a2, low(ENVP_ADDR + 8) */
    stl_raw(p++, 0x3c070000 | (loaderparams.ram_size >> 16));      /* lui a3, high(env->ram_size) */
    stl_raw(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff));   /* ori a3, a3, low(env->ram_size) */
    stl_raw(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff));     /* lui ra, high(kernel_addr) */;
    stl_raw(p++, 0x37ff0000 | (kernel_addr & 0xffff));             /* ori ra, ra, low(kernel_addr) */
    stl_raw(p++, 0x03e00008);                                      /* jr ra */
    stl_raw(p++, 0x00000000);                                      /* nop */
}


static void main_cpu_reset(void *opaque)
{
    CPUState *env = opaque;

    cpu_reset(env);
    /* TODO: 2E reset stuff */
    if (loaderparams.kernel_filename) {
        env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
    }
}

uint8_t eeprom_spd[0x80] = {
    0x80,0x08,0x07,0x0d,0x09,0x02,0x40,0x00,0x04,0x70,
    0x70,0x00,0x82,0x10,0x00,0x01,0x0e,0x04,0x0c,0x01,
    0x02,0x20,0x80,0x75,0x70,0x00,0x00,0x50,0x3c,0x50,
    0x2d,0x20,0xb0,0xb0,0x50,0x50,0x00,0x00,0x00,0x00,
    0x00,0x41,0x48,0x3c,0x32,0x75,0x00,0x00,0x00,0x00,
    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    0x00,0x00,0x00,0x9c,0x7b,0x07,0x00,0x00,0x00,0x00,
    0x00,0x00,0x00,0x00,0x48,0x42,0x35,0x34,0x41,0x32,
    0x35,0x36,0x38,0x4b,0x4e,0x2d,0x41,0x37,0x35,0x42,
    0x20,0x30,0x20
};

/* Audio support */
static void audio_init (PCIBus *pci_bus)
{
    vt82c686b_ac97_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 5));
    vt82c686b_mc97_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 6));
}

/* Network support */
static void network_init (void)
{
    int i;

    for(i = 0; i < nb_nics; i++) {
        NICInfo *nd = &nd_table[i];
        const char *default_devaddr = NULL;

        if (i == 0 && (!nd->model || strcmp(nd->model, "rtl8139") == 0)) {
            /* The fulong board has a RTL8139 card using PCI SLOT 7 */
            default_devaddr = "07";
        }

        pci_nic_init_nofail(nd, "rtl8139", default_devaddr);
    }
}

static void cpu_request_exit(void *opaque, int irq, int level)
{
    CPUState *env = cpu_single_env;

    if (env && level) {
        cpu_exit(env);
    }
}

static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
                        const char *kernel_filename, const char *kernel_cmdline,
                        const char *initrd_filename, const char *cpu_model)
{
    char *filename;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *ram = g_new(MemoryRegion, 1);
    MemoryRegion *bios = g_new(MemoryRegion, 1);
    long bios_size;
    int64_t kernel_entry;
    qemu_irq *i8259;
    qemu_irq *cpu_exit_irq;
    int via_devfn;
    PCIBus *pci_bus;
    i2c_bus *smbus;
    int i;
    DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
    CPUState *env;

    /* init CPUs */
    if (cpu_model == NULL) {
        cpu_model = "Loongson-2E";
    }
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find CPU definition\n");
        exit(1);
    }

    register_savevm(NULL, "cpu", 0, 3, cpu_save, cpu_load, env);
    qemu_register_reset(main_cpu_reset, env);

    /* fulong 2e has 256M ram. */
    ram_size = 256 * 1024 * 1024;

    /* fulong 2e has a 1M flash.Winbond W39L040AP70Z */
    bios_size = 1024 * 1024;

    /* allocate RAM */
    memory_region_init_ram(ram, NULL, "fulong2e.ram", ram_size);
    memory_region_init_ram(bios, NULL, "fulong2e.bios", bios_size);
    memory_region_set_readonly(bios, true);

    memory_region_add_subregion(address_space_mem, 0, ram);
    memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);

    /* We do not support flash operation, just loading pmon.bin as raw BIOS.
     * Please use -L to set the BIOS path and -bios to set bios name. */

    if (kernel_filename) {
        loaderparams.ram_size = ram_size;
        loaderparams.kernel_filename = kernel_filename;
        loaderparams.kernel_cmdline = kernel_cmdline;
        loaderparams.initrd_filename = initrd_filename;
        kernel_entry = load_kernel (env);
        write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
    } else {
        if (bios_name == NULL) {
                bios_name = FULONG_BIOSNAME;
        }
        filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
        if (filename) {
            bios_size = load_image_targphys(filename, 0x1fc00000LL,
                                            BIOS_SIZE);
            g_free(filename);
        } else {
            bios_size = -1;
        }

        if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) {
            fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n", bios_name);
            exit(1);
        }
    }

    /* Init internal devices */
    cpu_mips_irq_init_cpu(env);
    cpu_mips_clock_init(env);

    /* North bridge, Bonito --> IP2 */
    pci_bus = bonito_init((qemu_irq *)&(env->irq[2]));

    /* South bridge */
    ide_drive_get(hd, MAX_IDE_BUS);

    via_devfn = vt82c686b_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 0));
    if (via_devfn < 0) {
        fprintf(stderr, "vt82c686b_init error\n");
        exit(1);
    }

    /* Interrupt controller */
    /* The 8259 -> IP5  */
    i8259 = i8259_init(env->irq[5]);
    isa_bus_irqs(i8259);

    vt82c686b_ide_init(pci_bus, hd, PCI_DEVFN(FULONG2E_VIA_SLOT, 1));
    usb_uhci_vt82c686b_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 2));
    usb_uhci_vt82c686b_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 3));

    smbus = vt82c686b_pm_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 4),
                              0xeee1, NULL);
    /* TODO: Populate SPD eeprom data.  */
    smbus_eeprom_init(smbus, 1, eeprom_spd, sizeof(eeprom_spd));

    /* init other devices */
    pit = pit_init(0x40, 0);
    cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
    DMA_init(0, cpu_exit_irq);

    /* Super I/O */
    isa_create_simple("i8042");

    rtc_init(2000, NULL);

    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
        if (serial_hds[i]) {
            serial_isa_init(i, serial_hds[i]);
        }
    }

    if (parallel_hds[0]) {
        parallel_init(0, parallel_hds[0]);
    }

    /* Sound card */
    audio_init(pci_bus);
    /* Network card */
    network_init();
}

QEMUMachine mips_fulong2e_machine = {
    .name = "fulong2e",
    .desc = "Fulong 2e mini pc",
    .init = mips_fulong2e_init,
};

static void mips_fulong2e_machine_init(void)
{
    qemu_register_machine(&mips_fulong2e_machine);
}

machine_init(mips_fulong2e_machine_init);
Commit	Line	Data
051c190b HC	1	/*
	2	* QEMU fulong 2e mini pc support
	3	*
	4	* Copyright (c) 2008 yajin ([email protected])
	5	* Copyright (c) 2009 chenming ([email protected])
	6	* Copyright (c) 2010 Huacai Chen ([email protected])
	7	* This code is licensed under the GNU GPL v2.
	8	*/
	9
	10	/*
	11	* Fulong 2e mini pc is based on ICT/ST Loongson 2e CPU (MIPS III like, 800MHz)
	12	* http://www.linux-mips.org/wiki/Fulong
	13	*
	14	* Loongson 2e user manual:
	15	* http://www.loongsondeveloper.com/doc/Loongson2EUserGuide.pdf
	16	*/
	17
	18	#include "hw.h"
	19	#include "pc.h"
	20	#include "fdc.h"
	21	#include "net.h"
	22	#include "boards.h"
	23	#include "smbus.h"
	24	#include "block.h"
	25	#include "flash.h"
	26	#include "mips.h"
	27	#include "mips_cpudevs.h"
	28	#include "pci.h"
	29	#include "usb-uhci.h"
	30	#include "qemu-char.h"
	31	#include "sysemu.h"
	32	#include "audio/audio.h"
	33	#include "qemu-log.h"
	34	#include "loader.h"
	35	#include "mips-bios.h"
	36	#include "ide.h"
	37	#include "elf.h"
	38	#include "vt82c686.h"
	39	#include "mc146818rtc.h"
2446333c	40	#include "blockdev.h"
13faf2a7	41	#include "exec-memory.h"
051c190b HC	42
	43	#define DEBUG_FULONG2E_INIT
	44
	45	#define ENVP_ADDR 0x80002000l
	46	#define ENVP_NB_ENTRIES 16
	47	#define ENVP_ENTRY_SIZE 256
	48
	49	#define MAX_IDE_BUS 2
	50
	51	/*
	52	* PMON is not part of qemu and released with BSD license, anyone
	53	* who want to build a pmon binary please first git-clone the source
	54	* from the git repository at:
	55	* http://www.loongson.cn/support/git/pmon
	56	* Then follow the "Compile Guide" available at:
	57	* http://dev.lemote.com/code/pmon
	58	*
	59	* Notes:
	60	* 1, don't use the source at http://dev.lemote.com/http_git/pmon.git
	61	* 2, use "Bonito2edev" to replace "dir_corresponding_to_your_target_hardware"
	62	* in the "Compile Guide".
	63	*/
	64	#define FULONG_BIOSNAME "pmon_fulong2e.bin"
	65
	66	/* PCI SLOT in fulong 2e */
	67	#define FULONG2E_VIA_SLOT 5
	68	#define FULONG2E_ATI_SLOT 6
	69	#define FULONG2E_RTL8139_SLOT 7
	70
64d7e9a4	71	static ISADevice *pit;
051c190b HC	72
	73	static struct _loaderparams {
	74	int ram_size;
	75	const char *kernel_filename;
	76	const char *kernel_cmdline;
	77	const char *initrd_filename;
	78	} loaderparams;
	79
8b7968f7 SW	80	static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
8b7968f7 SW	81	const char *string, ...)
051c190b HC	82	{
	83	va_list ap;
	84	int32_t table_addr;
	85
	86	if (index >= ENVP_NB_ENTRIES)
	87	return;
	88
	89	if (string == NULL) {
	90	prom_buf[index] = 0;
	91	return;
	92	}
	93
	94	table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
	95	prom_buf[index] = tswap32(ENVP_ADDR + table_addr);
	96
	97	va_start(ap, string);
	98	vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
	99	va_end(ap);
	100	}
	101
	102	static int64_t load_kernel (CPUState *env)
	103	{
	104	int64_t kernel_entry, kernel_low, kernel_high;
	105	int index = 0;
	106	long initrd_size;
	107	ram_addr_t initrd_offset;
	108	uint32_t *prom_buf;
	109	long prom_size;
	110
	111	if (load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, NULL,
	112	(uint64_t )&kernel_entry, (uint64_t )&kernel_low,
	113	(uint64_t *)&kernel_high, 0, ELF_MACHINE, 1) < 0) {
	114	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	115	loaderparams.kernel_filename);
	116	exit(1);
	117	}
	118
	119	/* load initrd */
	120	initrd_size = 0;
	121	initrd_offset = 0;
	122	if (loaderparams.initrd_filename) {
	123	initrd_size = get_image_size (loaderparams.initrd_filename);
	124	if (initrd_size > 0) {
	125	initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
	126	if (initrd_offset + initrd_size > ram_size) {
	127	fprintf(stderr,
	128	"qemu: memory too small for initial ram disk '%s'\n",
	129	loaderparams.initrd_filename);
	130	exit(1);
	131	}
	132	initrd_size = load_image_targphys(loaderparams.initrd_filename,
	133	initrd_offset, ram_size - initrd_offset);
	134	}
	135	if (initrd_size == (target_ulong) -1) {
	136	fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
	137	loaderparams.initrd_filename);
	138	exit(1);
	139	}
	140	}
	141
	142	/* Setup prom parameters. */
	143	prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE);
7267c094	144	prom_buf = g_malloc(prom_size);
051c190b	145
1ed1139d	146	prom_set(prom_buf, index++, "%s", loaderparams.kernel_filename);
051c190b	147	if (initrd_size > 0) {
1ed1139d	148	prom_set(prom_buf, index++, "rd_start=0x%" PRIx64 " rd_size=%li %s",
051c190b HC	149	cpu_mips_phys_to_kseg0(NULL, initrd_offset), initrd_size,
	150	loaderparams.kernel_cmdline);
	151	} else {
1ed1139d	152	prom_set(prom_buf, index++, "%s", loaderparams.kernel_cmdline);
051c190b HC	153	}
	154
	155	/* Setup minimum environment variables */
	156	prom_set(prom_buf, index++, "busclock=33000000");
	157	prom_set(prom_buf, index++, "cpuclock=100000000");
	158	prom_set(prom_buf, index++, "memsize=%i", loaderparams.ram_size/1024/1024);
	159	prom_set(prom_buf, index++, "modetty0=38400n8r");
	160	prom_set(prom_buf, index++, NULL);
	161
	162	rom_add_blob_fixed("prom", prom_buf, prom_size,
	163	cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR));
	164
	165	return kernel_entry;
	166	}
	167
	168	static void write_bootloader (CPUState env, uint8_t base, int64_t kernel_addr)
	169	{
	170	uint32_t *p;
	171
	172	/* Small bootloader */
	173	p = (uint32_t *) base;
	174
	175	stl_raw(p++, 0x0bf00010); /* j 0x1fc00040 */
	176	stl_raw(p++, 0x00000000); /* nop */
	177
	178	/* Second part of the bootloader */
	179	p = (uint32_t *) (base + 0x040);
	180
	181	stl_raw(p++, 0x3c040000); /* lui a0, 0 */
	182	stl_raw(p++, 0x34840002); /* ori a0, a0, 2 */
	183	stl_raw(p++, 0x3c050000 \| ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
	184	stl_raw(p++, 0x34a50000 \| (ENVP_ADDR & 0xffff)); /* ori a1, a0, low(ENVP_ADDR) */
	185	stl_raw(p++, 0x3c060000 \| (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
	186	stl_raw(p++, 0x34c60000 \| ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
	187	stl_raw(p++, 0x3c070000 \| (loaderparams.ram_size >> 16)); /* lui a3, high(env->ram_size) */
	188	stl_raw(p++, 0x34e70000 \| (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(env->ram_size) */
	189	stl_raw(p++, 0x3c1f0000 \| ((kernel_addr >> 16) & 0xffff)); /* lui ra, high(kernel_addr) */;
	190	stl_raw(p++, 0x37ff0000 \| (kernel_addr & 0xffff)); /* ori ra, ra, low(kernel_addr) */
	191	stl_raw(p++, 0x03e00008); /* jr ra */
	192	stl_raw(p++, 0x00000000); /* nop */
	193	}
	194
	195
	196	static void main_cpu_reset(void *opaque)
	197	{
	198	CPUState *env = opaque;
	199
	200	cpu_reset(env);
	201	/* TODO: 2E reset stuff */
	202	if (loaderparams.kernel_filename) {
	203	env->CP0_Status &= ~((1 << CP0St_BEV) \| (1 << CP0St_ERL));
	204	}
	205	}
	206
	207	uint8_t eeprom_spd[0x80] = {
	208	0x80,0x08,0x07,0x0d,0x09,0x02,0x40,0x00,0x04,0x70,
	209	0x70,0x00,0x82,0x10,0x00,0x01,0x0e,0x04,0x0c,0x01,
	210	0x02,0x20,0x80,0x75,0x70,0x00,0x00,0x50,0x3c,0x50,
	211	0x2d,0x20,0xb0,0xb0,0x50,0x50,0x00,0x00,0x00,0x00,
	212	0x00,0x41,0x48,0x3c,0x32,0x75,0x00,0x00,0x00,0x00,
	213	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	214	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	215	0x00,0x00,0x00,0x9c,0x7b,0x07,0x00,0x00,0x00,0x00,
	216	0x00,0x00,0x00,0x00,0x48,0x42,0x35,0x34,0x41,0x32,
217	0x35,0x36,0x38,0x4b,0x4e,0x2d,0x41,0x37,0x35,0x42,
218	0x20,0x30,0x20
219	};
220
221	/* Audio support */
051c190b HC	222	static void audio_init (PCIBus *pci_bus)
051c190b HC	223	{
7899f799 IY	224	vt82c686b_ac97_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 5));
7899f799 IY	225	vt82c686b_mc97_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 6));
051c190b	226	}
051c190b HC	227
	228	/* Network support */
	229	static void network_init (void)
	230	{
	231	int i;
	232
	233	for(i = 0; i < nb_nics; i++) {
	234	NICInfo *nd = &nd_table[i];
	235	const char *default_devaddr = NULL;
	236
	237	if (i == 0 && (!nd->model \|\| strcmp(nd->model, "rtl8139") == 0)) {
	238	/* The fulong board has a RTL8139 card using PCI SLOT 7 */
	239	default_devaddr = "07";
	240	}
	241
	242	pci_nic_init_nofail(nd, "rtl8139", default_devaddr);
	243	}
	244	}
	245
	246	static void cpu_request_exit(void *opaque, int irq, int level)
	247	{
	248	CPUState *env = cpu_single_env;
	249
	250	if (env && level) {
	251	cpu_exit(env);
	252	}
	253	}
	254
	255	static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
	256	const char kernel_filename, const char kernel_cmdline,
	257	const char initrd_filename, const char cpu_model)
	258	{
	259	char *filename;
13faf2a7 AK	260	MemoryRegion *address_space_mem = get_system_memory();
	261	MemoryRegion *ram = g_new(MemoryRegion, 1);
	262	MemoryRegion *bios = g_new(MemoryRegion, 1);
093209cd	263	long bios_size;
051c190b HC	264	int64_t kernel_entry;
	265	qemu_irq *i8259;
	266	qemu_irq *cpu_exit_irq;
	267	int via_devfn;
	268	PCIBus *pci_bus;
051c190b HC	269	i2c_bus *smbus;
	270	int i;
	271	DriveInfo hd[MAX_IDE_BUS MAX_IDE_DEVS];
051c190b HC	272	CPUState *env;
	273
	274	/* init CPUs */
	275	if (cpu_model == NULL) {
	276	cpu_model = "Loongson-2E";
	277	}
	278	env = cpu_init(cpu_model);
	279	if (!env) {
	280	fprintf(stderr, "Unable to find CPU definition\n");
	281	exit(1);
	282	}
	283
0be71e32	284	register_savevm(NULL, "cpu", 0, 3, cpu_save, cpu_load, env);
051c190b HC	285	qemu_register_reset(main_cpu_reset, env);
	286
	287	/* fulong 2e has 256M ram. */
	288	ram_size = 256 * 1024 * 1024;
	289
	290	/* fulong 2e has a 1M flash.Winbond W39L040AP70Z */
	291	bios_size = 1024 * 1024;
	292
	293	/* allocate RAM */
13faf2a7 AK	294	memory_region_init_ram(ram, NULL, "fulong2e.ram", ram_size);
	295	memory_region_init_ram(bios, NULL, "fulong2e.bios", bios_size);
	296	memory_region_set_readonly(bios, true);
051c190b	297
13faf2a7 AK	298	memory_region_add_subregion(address_space_mem, 0, ram);
13faf2a7 AK	299	memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
051c190b HC	300
	301	/* We do not support flash operation, just loading pmon.bin as raw BIOS.
	302	* Please use -L to set the BIOS path and -bios to set bios name. */
	303
	304	if (kernel_filename) {
	305	loaderparams.ram_size = ram_size;
	306	loaderparams.kernel_filename = kernel_filename;
	307	loaderparams.kernel_cmdline = kernel_cmdline;
	308	loaderparams.initrd_filename = initrd_filename;
	309	kernel_entry = load_kernel (env);
13faf2a7	310	write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
051c190b	311	} else {
33dd2983 AJ	312	if (bios_name == NULL) {
33dd2983 AJ	313	bios_name = FULONG_BIOSNAME;
051c190b HC	314	}
	315	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
	316	if (filename) {
	317	bios_size = load_image_targphys(filename, 0x1fc00000LL,
	318	BIOS_SIZE);
7267c094	319	g_free(filename);
051c190b HC	320	} else {
	321	bios_size = -1;
	322	}
	323
33dd2983 AJ	324	if ((bios_size < 0 \|\| bios_size > BIOS_SIZE) && !kernel_filename) {
33dd2983 AJ	325	fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n", bios_name);
051c190b	326	exit(1);
33dd2983	327	}
051c190b HC	328	}
	329
	330	/* Init internal devices */
	331	cpu_mips_irq_init_cpu(env);
	332	cpu_mips_clock_init(env);
	333
051c190b HC	334	/* North bridge, Bonito --> IP2 */
	335	pci_bus = bonito_init((qemu_irq *)&(env->irq[2]));
	336
	337	/* South bridge */
75717903	338	ide_drive_get(hd, MAX_IDE_BUS);
051c190b	339
7899f799	340	via_devfn = vt82c686b_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 0));
051c190b	341	if (via_devfn < 0) {
b2bedb21	342	fprintf(stderr, "vt82c686b_init error\n");
051c190b HC	343	exit(1);
	344	}
	345
7e17a217 JK	346	/* Interrupt controller */
	347	/* The 8259 -> IP5 */
	348	i8259 = i8259_init(env->irq[5]);
051c190b	349	isa_bus_irqs(i8259);
7e17a217	350
7899f799 IY	351	vt82c686b_ide_init(pci_bus, hd, PCI_DEVFN(FULONG2E_VIA_SLOT, 1));
	352	usb_uhci_vt82c686b_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 2));
	353	usb_uhci_vt82c686b_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 3));
051c190b	354
7899f799	355	smbus = vt82c686b_pm_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 4),
051c190b	356	0xeee1, NULL);
051c190b	357	/* TODO: Populate SPD eeprom data. */
a88df0b9	358	smbus_eeprom_init(smbus, 1, eeprom_spd, sizeof(eeprom_spd));
051c190b HC	359
051c190b HC	360	/* init other devices */
64d7e9a4	361	pit = pit_init(0x40, 0);
051c190b HC	362	cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
	363	DMA_init(0, cpu_exit_irq);
	364
	365	/* Super I/O */
49a2942d	366	isa_create_simple("i8042");
051c190b	367
49a2942d	368	rtc_init(2000, NULL);
051c190b HC	369
	370	for(i = 0; i < MAX_SERIAL_PORTS; i++) {
	371	if (serial_hds[i]) {
	372	serial_isa_init(i, serial_hds[i]);
	373	}
	374	}
	375
	376	if (parallel_hds[0]) {
	377	parallel_init(0, parallel_hds[0]);
	378	}
	379
	380	/* Sound card */
051c190b	381	audio_init(pci_bus);
051c190b HC	382	/* Network card */
	383	network_init();
	384	}
	385
	386	QEMUMachine mips_fulong2e_machine = {
	387	.name = "fulong2e",
	388	.desc = "Fulong 2e mini pc",
	389	.init = mips_fulong2e_init,
	390	};
	391
	392	static void mips_fulong2e_machine_init(void)
	393	{
	394	qemu_register_machine(&mips_fulong2e_machine);
	395	}
	396
	397	machine_init(mips_fulong2e_machine_init);