[qemu.git] / hw / ppc4xx_pci.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 * Copyright IBM Corp. 2008
 *
 * Authors: Hollis Blanchard <[email protected]>
 */

/* This file implements emulation of the 32-bit PCI controller found in some
 * 4xx SoCs, such as the 440EP. */

#include "hw/hw.h"
#include "hw/ppc.h"
#include "hw/ppc4xx.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "exec/address-spaces.h"

#undef DEBUG
#ifdef DEBUG
#define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...)
#endif /* DEBUG */

struct PCIMasterMap {
    uint32_t la;
    uint32_t ma;
    uint32_t pcila;
    uint32_t pciha;
};

struct PCITargetMap {
    uint32_t ms;
    uint32_t la;
};

#define PPC4xx_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(PPC4xxPCIState, (obj), TYPE_PPC4xx_PCI_HOST_BRIDGE)

#define PPC4xx_PCI_NR_PMMS 3
#define PPC4xx_PCI_NR_PTMS 2

struct PPC4xxPCIState {
    PCIHostState parent_obj;

    struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
    struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
    qemu_irq irq[4];

    MemoryRegion container;
    MemoryRegion iomem;
};
typedef struct PPC4xxPCIState PPC4xxPCIState;

#define PCIC0_CFGADDR       0x0
#define PCIC0_CFGDATA       0x4

/* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
 * PCI accesses. */
#define PCIL0_PMM0LA        0x0
#define PCIL0_PMM0MA        0x4
#define PCIL0_PMM0PCILA     0x8
#define PCIL0_PMM0PCIHA     0xc
#define PCIL0_PMM1LA        0x10
#define PCIL0_PMM1MA        0x14
#define PCIL0_PMM1PCILA     0x18
#define PCIL0_PMM1PCIHA     0x1c
#define PCIL0_PMM2LA        0x20
#define PCIL0_PMM2MA        0x24
#define PCIL0_PMM2PCILA     0x28
#define PCIL0_PMM2PCIHA     0x2c

/* PCI Target Map (PTM) registers specify which PCI addresses are translated to
 * PLB accesses. */
#define PCIL0_PTM1MS        0x30
#define PCIL0_PTM1LA        0x34
#define PCIL0_PTM2MS        0x38
#define PCIL0_PTM2LA        0x3c
#define PCI_REG_BASE        0x800000
#define PCI_REG_SIZE        0x40

#define PCI_ALL_SIZE        (PCI_REG_BASE + PCI_REG_SIZE)

static uint64_t pci4xx_cfgaddr_read(void *opaque, hwaddr addr,
                                    unsigned size)
{
    PPC4xxPCIState *ppc4xx_pci = opaque;
    PCIHostState *phb = PCI_HOST_BRIDGE(ppc4xx_pci);

    return phb->config_reg;
}

static void pci4xx_cfgaddr_write(void *opaque, hwaddr addr,
                                  uint64_t value, unsigned size)
{
    PPC4xxPCIState *ppc4xx_pci = opaque;
    PCIHostState *phb = PCI_HOST_BRIDGE(ppc4xx_pci);

    phb->config_reg = value & ~0x3;
}

static const MemoryRegionOps pci4xx_cfgaddr_ops = {
    .read = pci4xx_cfgaddr_read,
    .write = pci4xx_cfgaddr_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
                                  uint64_t value, unsigned size)
{
    struct PPC4xxPCIState *pci = opaque;

    /* We ignore all target attempts at PCI configuration, effectively
     * assuming a bidirectional 1:1 mapping of PLB and PCI space. */

    switch (offset) {
    case PCIL0_PMM0LA:
        pci->pmm[0].la = value;
        break;
    case PCIL0_PMM0MA:
        pci->pmm[0].ma = value;
        break;
    case PCIL0_PMM0PCIHA:
        pci->pmm[0].pciha = value;
        break;
    case PCIL0_PMM0PCILA:
        pci->pmm[0].pcila = value;
        break;

    case PCIL0_PMM1LA:
        pci->pmm[1].la = value;
        break;
    case PCIL0_PMM1MA:
        pci->pmm[1].ma = value;
        break;
    case PCIL0_PMM1PCIHA:
        pci->pmm[1].pciha = value;
        break;
    case PCIL0_PMM1PCILA:
        pci->pmm[1].pcila = value;
        break;

    case PCIL0_PMM2LA:
        pci->pmm[2].la = value;
        break;
    case PCIL0_PMM2MA:
        pci->pmm[2].ma = value;
        break;
    case PCIL0_PMM2PCIHA:
        pci->pmm[2].pciha = value;
        break;
    case PCIL0_PMM2PCILA:
        pci->pmm[2].pcila = value;
        break;

    case PCIL0_PTM1MS:
        pci->ptm[0].ms = value;
        break;
    case PCIL0_PTM1LA:
        pci->ptm[0].la = value;
        break;
    case PCIL0_PTM2MS:
        pci->ptm[1].ms = value;
        break;
    case PCIL0_PTM2LA:
        pci->ptm[1].la = value;
        break;

    default:
        printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
               (unsigned long)offset);
        break;
    }
}

static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
                                     unsigned size)
{
    struct PPC4xxPCIState *pci = opaque;
    uint32_t value;

    switch (offset) {
    case PCIL0_PMM0LA:
        value = pci->pmm[0].la;
        break;
    case PCIL0_PMM0MA:
        value = pci->pmm[0].ma;
        break;
    case PCIL0_PMM0PCIHA:
        value = pci->pmm[0].pciha;
        break;
    case PCIL0_PMM0PCILA:
        value = pci->pmm[0].pcila;
        break;

    case PCIL0_PMM1LA:
        value = pci->pmm[1].la;
        break;
    case PCIL0_PMM1MA:
        value = pci->pmm[1].ma;
        break;
    case PCIL0_PMM1PCIHA:
        value = pci->pmm[1].pciha;
        break;
    case PCIL0_PMM1PCILA:
        value = pci->pmm[1].pcila;
        break;

    case PCIL0_PMM2LA:
        value = pci->pmm[2].la;
        break;
    case PCIL0_PMM2MA:
        value = pci->pmm[2].ma;
        break;
    case PCIL0_PMM2PCIHA:
        value = pci->pmm[2].pciha;
        break;
    case PCIL0_PMM2PCILA:
        value = pci->pmm[2].pcila;
        break;

    case PCIL0_PTM1MS:
        value = pci->ptm[0].ms;
        break;
    case PCIL0_PTM1LA:
        value = pci->ptm[0].la;
        break;
    case PCIL0_PTM2MS:
        value = pci->ptm[1].ms;
        break;
    case PCIL0_PTM2LA:
        value = pci->ptm[1].la;
        break;

    default:
        printf("%s: invalid PCI internal register 0x%lx\n", __func__,
               (unsigned long)offset);
        value = 0;
    }

    return value;
}

static const MemoryRegionOps pci_reg_ops = {
    .read = ppc4xx_pci_reg_read4,
    .write = ppc4xx_pci_reg_write4,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void ppc4xx_pci_reset(void *opaque)
{
    struct PPC4xxPCIState *pci = opaque;

    memset(pci->pmm, 0, sizeof(pci->pmm));
    memset(pci->ptm, 0, sizeof(pci->ptm));
}

/* On Bamboo, all pins from each slot are tied to a single board IRQ. This
 * may need further refactoring for other boards. */
static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int slot = pci_dev->devfn >> 3;

    DPRINTF("%s: devfn %x irq %d -> %d\n", __func__,
            pci_dev->devfn, irq_num, slot);

    return slot - 1;
}

static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pci_irqs = opaque;

    DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
    if (irq_num < 0) {
        fprintf(stderr, "%s: PCI irq %d\n", __func__, irq_num);
        return;
    }
    qemu_set_irq(pci_irqs[irq_num], level);
}

static const VMStateDescription vmstate_pci_master_map = {
    .name = "pci_master_map",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(la, struct PCIMasterMap),
        VMSTATE_UINT32(ma, struct PCIMasterMap),
        VMSTATE_UINT32(pcila, struct PCIMasterMap),
        VMSTATE_UINT32(pciha, struct PCIMasterMap),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pci_target_map = {
    .name = "pci_target_map",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(ms, struct PCITargetMap),
        VMSTATE_UINT32(la, struct PCITargetMap),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_ppc4xx_pci = {
    .name = "ppc4xx_pci",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
                             vmstate_pci_master_map,
                             struct PCIMasterMap),
        VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
                             vmstate_pci_target_map,
                             struct PCITargetMap),
        VMSTATE_END_OF_LIST()
    }
};

/* XXX Interrupt acknowledge cycles not supported. */
static int ppc4xx_pcihost_initfn(SysBusDevice *dev)
{
    PPC4xxPCIState *s;
    PCIHostState *h;
    PCIBus *b;
    int i;

    h = PCI_HOST_BRIDGE(dev);
    s = PPC4xx_PCI_HOST_BRIDGE(dev);

    for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
        sysbus_init_irq(dev, &s->irq[i]);
    }

    b = pci_register_bus(DEVICE(dev), NULL, ppc4xx_pci_set_irq,
                         ppc4xx_pci_map_irq, s->irq, get_system_memory(),
                         get_system_io(), 0, 4, TYPE_PCI_BUS);
    h->bus = b;

    pci_create_simple(b, 0, "ppc4xx-host-bridge");

    /* XXX split into 2 memory regions, one for config space, one for regs */
    memory_region_init(&s->container, "pci-container", PCI_ALL_SIZE);
    memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops, h,
                          "pci-conf-idx", 4);
    memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
                          "pci-conf-data", 4);
    memory_region_init_io(&s->iomem, &pci_reg_ops, s,
                          "pci.reg", PCI_REG_SIZE);
    memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
    memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
    memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
    sysbus_init_mmio(dev, &s->container);
    qemu_register_reset(ppc4xx_pci_reset, s);

    return 0;
}

static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc        = "Host bridge";
    k->vendor_id    = PCI_VENDOR_ID_IBM;
    k->device_id    = PCI_DEVICE_ID_IBM_440GX;
    k->class_id     = PCI_CLASS_BRIDGE_OTHER;
}

static const TypeInfo ppc4xx_host_bridge_info = {
    .name          = "ppc4xx-host-bridge",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIDevice),
    .class_init    = ppc4xx_host_bridge_class_init,
};

static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->init = ppc4xx_pcihost_initfn;
    dc->vmsd = &vmstate_ppc4xx_pci;
}

static const TypeInfo ppc4xx_pcihost_info = {
    .name          = TYPE_PPC4xx_PCI_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(PPC4xxPCIState),
    .class_init    = ppc4xx_pcihost_class_init,
};

static void ppc4xx_pci_register_types(void)
{
    type_register_static(&ppc4xx_pcihost_info);
    type_register_static(&ppc4xx_host_bridge_info);
}

type_init(ppc4xx_pci_register_types)
Commit	Line	Data
825bb581 AJ	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
8167ee88	12	* along with this program; if not, see <http://www.gnu.org/licenses/>.
825bb581 AJ	13	*
	14	* Copyright IBM Corp. 2008
	15	*
	16	* Authors: Hollis Blanchard <[email protected]>
	17	*/
	18
	19	/* This file implements emulation of the 32-bit PCI controller found in some
	20	* 4xx SoCs, such as the 440EP. */
	21
83c9f4ca PB	22	#include "hw/hw.h"
	23	#include "hw/ppc.h"
	24	#include "hw/ppc4xx.h"
	25	#include "hw/pci/pci.h"
	26	#include "hw/pci/pci_host.h"
022c62cb	27	#include "exec/address-spaces.h"
825bb581 AJ	28
	29	#undef DEBUG
	30	#ifdef DEBUG
	31	#define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
	32	#else
001faf32	33	#define DPRINTF(fmt, ...)
825bb581 AJ	34	#endif /* DEBUG */
	35
	36	struct PCIMasterMap {
	37	uint32_t la;
	38	uint32_t ma;
	39	uint32_t pcila;
	40	uint32_t pciha;
	41	};
	42
	43	struct PCITargetMap {
	44	uint32_t ms;
	45	uint32_t la;
	46	};
	47
42c281a2 AF	48	#define PPC4xx_PCI_HOST_BRIDGE(obj) \
	49	OBJECT_CHECK(PPC4xxPCIState, (obj), TYPE_PPC4xx_PCI_HOST_BRIDGE)
	50
825bb581 AJ	51	#define PPC4xx_PCI_NR_PMMS 3
	52	#define PPC4xx_PCI_NR_PTMS 2
	53
	54	struct PPC4xxPCIState {
67c332fd	55	PCIHostState parent_obj;
623f7c21	56
825bb581 AJ	57	struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
825bb581 AJ	58	struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
623f7c21	59	qemu_irq irq[4];
825bb581	60
623f7c21 AG	61	MemoryRegion container;
623f7c21 AG	62	MemoryRegion iomem;
825bb581 AJ	63	};
	64	typedef struct PPC4xxPCIState PPC4xxPCIState;
	65
	66	#define PCIC0_CFGADDR 0x0
	67	#define PCIC0_CFGDATA 0x4
	68
	69	/* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
	70	* PCI accesses. */
	71	#define PCIL0_PMM0LA 0x0
	72	#define PCIL0_PMM0MA 0x4
	73	#define PCIL0_PMM0PCILA 0x8
	74	#define PCIL0_PMM0PCIHA 0xc
	75	#define PCIL0_PMM1LA 0x10
	76	#define PCIL0_PMM1MA 0x14
	77	#define PCIL0_PMM1PCILA 0x18
	78	#define PCIL0_PMM1PCIHA 0x1c
	79	#define PCIL0_PMM2LA 0x20
	80	#define PCIL0_PMM2MA 0x24
	81	#define PCIL0_PMM2PCILA 0x28
	82	#define PCIL0_PMM2PCIHA 0x2c
	83
	84	/* PCI Target Map (PTM) registers specify which PCI addresses are translated to
	85	* PLB accesses. */
	86	#define PCIL0_PTM1MS 0x30
	87	#define PCIL0_PTM1LA 0x34
	88	#define PCIL0_PTM2MS 0x38
	89	#define PCIL0_PTM2LA 0x3c
623f7c21	90	#define PCI_REG_BASE 0x800000
825bb581 AJ	91	#define PCI_REG_SIZE 0x40
825bb581 AJ	92
623f7c21	93	#define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
825bb581	94
a8170e5e	95	static uint64_t pci4xx_cfgaddr_read(void *opaque, hwaddr addr,
da726e5e	96	unsigned size)
825bb581 AJ	97	{
825bb581 AJ	98	PPC4xxPCIState *ppc4xx_pci = opaque;
67c332fd	99	PCIHostState *phb = PCI_HOST_BRIDGE(ppc4xx_pci);
825bb581	100
67c332fd	101	return phb->config_reg;
825bb581 AJ	102	}
825bb581 AJ	103
a8170e5e	104	static void pci4xx_cfgaddr_write(void *opaque, hwaddr addr,
da726e5e	105	uint64_t value, unsigned size)
825bb581 AJ	106	{
825bb581 AJ	107	PPC4xxPCIState *ppc4xx_pci = opaque;
67c332fd	108	PCIHostState *phb = PCI_HOST_BRIDGE(ppc4xx_pci);
825bb581	109
67c332fd	110	phb->config_reg = value & ~0x3;
825bb581 AJ	111	}
825bb581 AJ	112
da726e5e AK	113	static const MemoryRegionOps pci4xx_cfgaddr_ops = {
	114	.read = pci4xx_cfgaddr_read,
	115	.write = pci4xx_cfgaddr_write,
	116	.endianness = DEVICE_LITTLE_ENDIAN,
825bb581 AJ	117	};
825bb581 AJ	118
a8170e5e	119	static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
da726e5e	120	uint64_t value, unsigned size)
825bb581 AJ	121	{
	122	struct PPC4xxPCIState *pci = opaque;
	123
825bb581 AJ	124	/* We ignore all target attempts at PCI configuration, effectively
	125	* assuming a bidirectional 1:1 mapping of PLB and PCI space. */
	126
	127	switch (offset) {
	128	case PCIL0_PMM0LA:
	129	pci->pmm[0].la = value;
	130	break;
	131	case PCIL0_PMM0MA:
	132	pci->pmm[0].ma = value;
	133	break;
	134	case PCIL0_PMM0PCIHA:
	135	pci->pmm[0].pciha = value;
	136	break;
	137	case PCIL0_PMM0PCILA:
	138	pci->pmm[0].pcila = value;
	139	break;
	140
	141	case PCIL0_PMM1LA:
	142	pci->pmm[1].la = value;
	143	break;
	144	case PCIL0_PMM1MA:
	145	pci->pmm[1].ma = value;
	146	break;
	147	case PCIL0_PMM1PCIHA:
	148	pci->pmm[1].pciha = value;
	149	break;
	150	case PCIL0_PMM1PCILA:
	151	pci->pmm[1].pcila = value;
	152	break;
	153
	154	case PCIL0_PMM2LA:
	155	pci->pmm[2].la = value;
	156	break;
	157	case PCIL0_PMM2MA:
	158	pci->pmm[2].ma = value;
	159	break;
	160	case PCIL0_PMM2PCIHA:
	161	pci->pmm[2].pciha = value;
	162	break;
	163	case PCIL0_PMM2PCILA:
	164	pci->pmm[2].pcila = value;
	165	break;
	166
	167	case PCIL0_PTM1MS:
	168	pci->ptm[0].ms = value;
	169	break;
	170	case PCIL0_PTM1LA:
	171	pci->ptm[0].la = value;
	172	break;
	173	case PCIL0_PTM2MS:
	174	pci->ptm[1].ms = value;
	175	break;
	176	case PCIL0_PTM2LA:
	177	pci->ptm[1].la = value;
	178	break;
	179
	180	default:
	181	printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
	182	(unsigned long)offset);
	183	break;
	184	}
	185	}
	186
a8170e5e	187	static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
da726e5e	188	unsigned size)
825bb581 AJ	189	{
	190	struct PPC4xxPCIState *pci = opaque;
	191	uint32_t value;
	192
	193	switch (offset) {
	194	case PCIL0_PMM0LA:
	195	value = pci->pmm[0].la;
	196	break;
	197	case PCIL0_PMM0MA:
	198	value = pci->pmm[0].ma;
	199	break;
	200	case PCIL0_PMM0PCIHA:
	201	value = pci->pmm[0].pciha;
	202	break;
	203	case PCIL0_PMM0PCILA:
	204	value = pci->pmm[0].pcila;
	205	break;
	206
	207	case PCIL0_PMM1LA:
	208	value = pci->pmm[1].la;
	209	break;
	210	case PCIL0_PMM1MA:
	211	value = pci->pmm[1].ma;
	212	break;
	213	case PCIL0_PMM1PCIHA:
	214	value = pci->pmm[1].pciha;
	215	break;
	216	case PCIL0_PMM1PCILA:
	217	value = pci->pmm[1].pcila;
	218	break;
	219
	220	case PCIL0_PMM2LA:
	221	value = pci->pmm[2].la;
	222	break;
	223	case PCIL0_PMM2MA:
	224	value = pci->pmm[2].ma;
	225	break;
	226	case PCIL0_PMM2PCIHA:
	227	value = pci->pmm[2].pciha;
	228	break;
	229	case PCIL0_PMM2PCILA:
	230	value = pci->pmm[2].pcila;
	231	break;
	232
	233	case PCIL0_PTM1MS:
	234	value = pci->ptm[0].ms;
	235	break;
	236	case PCIL0_PTM1LA:
	237	value = pci->ptm[0].la;
	238	break;
	239	case PCIL0_PTM2MS:
	240	value = pci->ptm[1].ms;
	241	break;
	242	case PCIL0_PTM2LA:
	243	value = pci->ptm[1].la;
	244	break;
	245
	246	default:
	247	printf("%s: invalid PCI internal register 0x%lx\n", __func__,
	248	(unsigned long)offset);
	249	value = 0;
	250	}
	251
825bb581 AJ	252	return value;
	253	}
	254
da726e5e AK	255	static const MemoryRegionOps pci_reg_ops = {
	256	.read = ppc4xx_pci_reg_read4,
	257	.write = ppc4xx_pci_reg_write4,
	258	.endianness = DEVICE_LITTLE_ENDIAN,
825bb581 AJ	259	};
	260
	261	static void ppc4xx_pci_reset(void *opaque)
	262	{
	263	struct PPC4xxPCIState *pci = opaque;
	264
	265	memset(pci->pmm, 0, sizeof(pci->pmm));
	266	memset(pci->ptm, 0, sizeof(pci->ptm));
	267	}
	268
	269	/* On Bamboo, all pins from each slot are tied to a single board IRQ. This
	270	* may need further refactoring for other boards. */
	271	static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
	272	{
	273	int slot = pci_dev->devfn >> 3;
	274
	275	DPRINTF("%s: devfn %x irq %d -> %d\n", __func__,
	276	pci_dev->devfn, irq_num, slot);
	277
	278	return slot - 1;
	279	}
	280
5d4e84c8	281	static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
825bb581	282	{
5d4e84c8 JQ	283	qemu_irq *pci_irqs = opaque;
5d4e84c8 JQ	284
825bb581	285	DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
d49bc1fb AG	286	if (irq_num < 0) {
	287	fprintf(stderr, "%s: PCI irq %d\n", __func__, irq_num);
	288	return;
	289	}
825bb581 AJ	290	qemu_set_irq(pci_irqs[irq_num], level);
	291	}
	292
b605f222 JQ	293	static const VMStateDescription vmstate_pci_master_map = {
	294	.name = "pci_master_map",
	295	.version_id = 0,
	296	.minimum_version_id = 0,
	297	.minimum_version_id_old = 0,
	298	.fields = (VMStateField[]) {
	299	VMSTATE_UINT32(la, struct PCIMasterMap),
	300	VMSTATE_UINT32(ma, struct PCIMasterMap),
	301	VMSTATE_UINT32(pcila, struct PCIMasterMap),
	302	VMSTATE_UINT32(pciha, struct PCIMasterMap),
	303	VMSTATE_END_OF_LIST()
825bb581	304	}
b605f222	305	};
825bb581	306
b605f222 JQ	307	static const VMStateDescription vmstate_pci_target_map = {
	308	.name = "pci_target_map",
	309	.version_id = 0,
	310	.minimum_version_id = 0,
	311	.minimum_version_id_old = 0,
	312	.fields = (VMStateField[]) {
	313	VMSTATE_UINT32(ms, struct PCITargetMap),
	314	VMSTATE_UINT32(la, struct PCITargetMap),
	315	VMSTATE_END_OF_LIST()
825bb581	316	}
b605f222	317	};
825bb581	318
b605f222 JQ	319	static const VMStateDescription vmstate_ppc4xx_pci = {
	320	.name = "ppc4xx_pci",
	321	.version_id = 1,
	322	.minimum_version_id = 1,
	323	.minimum_version_id_old = 1,
	324	.fields = (VMStateField[]) {
b605f222 JQ	325	VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
	326	vmstate_pci_master_map,
	327	struct PCIMasterMap),
	328	VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
	329	vmstate_pci_target_map,
	330	struct PCITargetMap),
	331	VMSTATE_END_OF_LIST()
825bb581	332	}
b605f222	333	};
825bb581 AJ	334
825bb581 AJ	335	/* XXX Interrupt acknowledge cycles not supported. */
623f7c21 AG	336	static int ppc4xx_pcihost_initfn(SysBusDevice *dev)
	337	{
	338	PPC4xxPCIState *s;
	339	PCIHostState *h;
	340	PCIBus *b;
	341	int i;
	342
8558d942	343	h = PCI_HOST_BRIDGE(dev);
42c281a2	344	s = PPC4xx_PCI_HOST_BRIDGE(dev);
623f7c21 AG	345
	346	for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
	347	sysbus_init_irq(dev, &s->irq[i]);
	348	}
	349
42c281a2	350	b = pci_register_bus(DEVICE(dev), NULL, ppc4xx_pci_set_irq,
623f7c21	351	ppc4xx_pci_map_irq, s->irq, get_system_memory(),
60a0e443	352	get_system_io(), 0, 4, TYPE_PCI_BUS);
42c281a2	353	h->bus = b;
623f7c21 AG	354
	355	pci_create_simple(b, 0, "ppc4xx-host-bridge");
	356
	357	/* XXX split into 2 memory regions, one for config space, one for regs */
	358	memory_region_init(&s->container, "pci-container", PCI_ALL_SIZE);
	359	memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops, h,
	360	"pci-conf-idx", 4);
	361	memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
	362	"pci-conf-data", 4);
	363	memory_region_init_io(&s->iomem, &pci_reg_ops, s,
	364	"pci.reg", PCI_REG_SIZE);
	365	memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
	366	memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
	367	memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
	368	sysbus_init_mmio(dev, &s->container);
	369	qemu_register_reset(ppc4xx_pci_reset, s);
	370
	371	return 0;
	372	}
	373
40021f08 AL	374	static void ppc4xx_host_bridge_class_init(ObjectClass klass, void data)
	375	{
	376	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
39bffca2	377	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08	378
39bffca2	379	dc->desc = "Host bridge";
40021f08 AL	380	k->vendor_id = PCI_VENDOR_ID_IBM;
	381	k->device_id = PCI_DEVICE_ID_IBM_440GX;
	382	k->class_id = PCI_CLASS_BRIDGE_OTHER;
	383	}
	384
4240abff	385	static const TypeInfo ppc4xx_host_bridge_info = {
39bffca2 AL	386	.name = "ppc4xx-host-bridge",
	387	.parent = TYPE_PCI_DEVICE,
	388	.instance_size = sizeof(PCIDevice),
	389	.class_init = ppc4xx_host_bridge_class_init,
623f7c21 AG	390	};
623f7c21 AG	391
999e12bb AL	392	static void ppc4xx_pcihost_class_init(ObjectClass klass, void data)
	393	{
	394	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
39bffca2	395	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	396
999e12bb AL	397	k->init = ppc4xx_pcihost_initfn;
39bffca2	398	dc->vmsd = &vmstate_ppc4xx_pci;
999e12bb AL	399	}
999e12bb AL	400
4240abff	401	static const TypeInfo ppc4xx_pcihost_info = {
42c281a2	402	.name = TYPE_PPC4xx_PCI_HOST_BRIDGE,
8558d942	403	.parent = TYPE_PCI_HOST_BRIDGE,
39bffca2 AL	404	.instance_size = sizeof(PPC4xxPCIState),
39bffca2 AL	405	.class_init = ppc4xx_pcihost_class_init,
623f7c21 AG	406	};
623f7c21 AG	407
83f7d43a	408	static void ppc4xx_pci_register_types(void)
825bb581	409	{
39bffca2 AL	410	type_register_static(&ppc4xx_pcihost_info);
39bffca2 AL	411	type_register_static(&ppc4xx_host_bridge_info);
825bb581	412	}
83f7d43a AF	413
83f7d43a AF	414	type_init(ppc4xx_pci_register_types)