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hda: do not mix output and input stream states, RHBZ #740493
[qemu.git] / hw / sh7750.c
CommitLineData
27c7ca7e
FB		 1/*
2 * SH7750 device
5fafdf24 3 *
80f515e6 4 * Copyright (c) 2007 Magnus Damm
27c7ca7e 5 * Copyright (c) 2005 Samuel Tardieu
5fafdf24 6 *
27c7ca7e
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25#include <stdio.h>
87ecb68b
PB		 26#include "hw.h"
27#include "sh.h"
28#include "sysemu.h"
27c7ca7e
FB		 29#include "sh7750_regs.h"
30#include "sh7750_regnames.h"
80f515e6 31#include "sh_intc.h"
29e179bc 32#include "cpu.h"
27c7ca7e 33
27c7ca7e
FB		 34#define NB_DEVICES 4
35
36typedef struct SH7750State {
37 /* CPU */
38 CPUSH4State *cpu;
39 /* Peripheral frequency in Hz */
40 uint32_t periph_freq;
41 /* SDRAM controller */
c2f01775 42 uint32_t bcr1;
c2432a42
AJ		 43 uint16_t bcr2;
44 uint16_t bcr3;
45 uint32_t bcr4;
27c7ca7e 46 uint16_t rfcr;
c2432a42
AJ		 47 /* PCMCIA controller */
48 uint16_t pcr;
27c7ca7e
FB		 49 /* IO ports */
50 uint16_t gpioic;
51 uint32_t pctra;
52 uint32_t pctrb;
53 uint16_t portdira; /* Cached */
54 uint16_t portpullupa; /* Cached */
55 uint16_t portdirb; /* Cached */
56 uint16_t portpullupb; /* Cached */
57 uint16_t pdtra;
58 uint16_t pdtrb;
59 uint16_t periph_pdtra; /* Imposed by the peripherals */
60 uint16_t periph_portdira; /* Direction seen from the peripherals */
61 uint16_t periph_pdtrb; /* Imposed by the peripherals */
62 uint16_t periph_portdirb; /* Direction seen from the peripherals */
63 sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */
3464c589 64
27c7ca7e
FB		 65 /* Cache */
66 uint32_t ccr;
27c7ca7e 67
80f515e6 68 struct intc_desc intc;
cd1a3f68 69} SH7750State;
27c7ca7e 70
86178a57 71static inline int has_bcr3_and_bcr4(SH7750State * s)
c2432a42
AJ		 72{
73 return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4);
74}
27c7ca7e
FB		 75/**********************************************************************
76 I/O ports
77**********************************************************************/
78
79int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
80{
81 int i;
82
83 for (i = 0; i < NB_DEVICES; i++) {
84 if (s->devices[i] == NULL) {
85 s->devices[i] = device;
86 return 0;
87 }
88 }
89 return -1;
90}
91
92static uint16_t portdir(uint32_t v)
93{
94#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
95 return
96 EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) |
97 EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) |
98 EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) |
99 EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) |
100 EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) |
101 EVENPORTMASK(0);
102}
103
104static uint16_t portpullup(uint32_t v)
105{
106#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
107 return
108 ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) |
109 ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) |
110 ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) |
111 ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) |
112 ODDPORTMASK(1) | ODDPORTMASK(0);
113}
114
115static uint16_t porta_lines(SH7750State * s)
116{
117 return (s->portdira & s->pdtra) | /* CPU */
118 (s->periph_portdira & s->periph_pdtra) | /* Peripherals */
119 (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */
120}
121
122static uint16_t portb_lines(SH7750State * s)
123{
124 return (s->portdirb & s->pdtrb) | /* CPU */
125 (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */
126 (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */
127}
128
129static void gen_port_interrupts(SH7750State * s)
130{
131 /* XXXXX interrupts not generated */
132}
133
134static void porta_changed(SH7750State * s, uint16_t prev)
135{
136 uint16_t currenta, changes;
137 int i, r = 0;
138
139#if 0
140 fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
141 prev, porta_lines(s));
142 fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
143#endif
144 currenta = porta_lines(s);
145 if (currenta == prev)
146 return;
147 changes = currenta ^ prev;
148
149 for (i = 0; i < NB_DEVICES; i++) {
150 if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
151 r |= s->devices[i]->port_change_cb(currenta, portb_lines(s),
152 &s->periph_pdtra,
153 &s->periph_portdira,
154 &s->periph_pdtrb,
155 &s->periph_portdirb);
156 }
157 }
158
159 if (r)
160 gen_port_interrupts(s);
161}
162
163static void portb_changed(SH7750State * s, uint16_t prev)
164{
165 uint16_t currentb, changes;
166 int i, r = 0;
167
168 currentb = portb_lines(s);
169 if (currentb == prev)
170 return;
171 changes = currentb ^ prev;
172
173 for (i = 0; i < NB_DEVICES; i++) {
174 if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
175 r |= s->devices[i]->port_change_cb(portb_lines(s), currentb,
176 &s->periph_pdtra,
177 &s->periph_portdira,
178 &s->periph_pdtrb,
179 &s->periph_portdirb);
180 }
181 }
182
183 if (r)
184 gen_port_interrupts(s);
185}
186
187/**********************************************************************
188 Memory
189**********************************************************************/
190
c227f099 191static void error_access(const char *kind, target_phys_addr_t addr)
27c7ca7e 192{
526ccb7a 193 fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n",
27c7ca7e
FB		 194 kind, regname(addr), addr);
195}
196
c227f099 197static void ignore_access(const char *kind, target_phys_addr_t addr)
27c7ca7e 198{
526ccb7a 199 fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n",
27c7ca7e
FB		 200 kind, regname(addr), addr);
201}
202
c227f099 203static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
27c7ca7e 204{
27c7ca7e 205 switch (addr) {
27c7ca7e
FB		 206 default:
207 error_access("byte read", addr);
43dc2a64 208 abort();
27c7ca7e
FB		 209 }
210}
211
c227f099 212static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
27c7ca7e
FB		 213{
214 SH7750State *s = opaque;
27c7ca7e
FB		 215
216 switch (addr) {
c2f01775
AZ		 217 case SH7750_BCR2_A7:
218 return s->bcr2;
c2432a42
AJ		 219 case SH7750_BCR3_A7:
220 if(!has_bcr3_and_bcr4(s))
221 error_access("word read", addr);
222 return s->bcr3;
ed8e0a4d
TS		 223 case SH7750_FRQCR_A7:
224 return 0;
c2432a42
AJ		 225 case SH7750_PCR_A7:
226 return s->pcr;
27c7ca7e
FB		 227 case SH7750_RFCR_A7:
228 fprintf(stderr,
229 "Read access to refresh count register, incrementing\n");
230 return s->rfcr++;
27c7ca7e
FB		 231 case SH7750_PDTRA_A7:
232 return porta_lines(s);
233 case SH7750_PDTRB_A7:
234 return portb_lines(s);
c2432a42
AJ		 235 case SH7750_RTCOR_A7:
236 case SH7750_RTCNT_A7:
237 case SH7750_RTCSR_A7:
238 ignore_access("word read", addr);
239 return 0;
27c7ca7e
FB		 240 default:
241 error_access("word read", addr);
43dc2a64 242 abort();
27c7ca7e
FB		 243 }
244}
245
c227f099 246static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
27c7ca7e
FB		 247{
248 SH7750State *s = opaque;
249
250 switch (addr) {
c2f01775
AZ		 251 case SH7750_BCR1_A7:
252 return s->bcr1;
253 case SH7750_BCR4_A7:
c2432a42
AJ		 254 if(!has_bcr3_and_bcr4(s))
255 error_access("long read", addr);
256 return s->bcr4;
c2f01775
AZ		 257 case SH7750_WCR1_A7:
258 case SH7750_WCR2_A7:
259 case SH7750_WCR3_A7:
260 case SH7750_MCR_A7:
261 ignore_access("long read", addr);
262 return 0;
27c7ca7e
FB		 263 case SH7750_MMUCR_A7:
264 return s->cpu->mmucr;
265 case SH7750_PTEH_A7:
266 return s->cpu->pteh;
267 case SH7750_PTEL_A7:
268 return s->cpu->ptel;
269 case SH7750_TTB_A7:
270 return s->cpu->ttb;
271 case SH7750_TEA_A7:
272 return s->cpu->tea;
273 case SH7750_TRA_A7:
274 return s->cpu->tra;
275 case SH7750_EXPEVT_A7:
276 return s->cpu->expevt;
277 case SH7750_INTEVT_A7:
278 return s->cpu->intevt;
279 case SH7750_CCR_A7:
280 return s->ccr;
0fd3ca30
AJ		 281 case 0x1f000030: /* Processor version */
282 return s->cpu->pvr;
283 case 0x1f000040: /* Cache version */
284 return s->cpu->cvr;
285 case 0x1f000044: /* Processor revision */
286 return s->cpu->prr;
27c7ca7e
FB		 287 default:
288 error_access("long read", addr);
43dc2a64 289 abort();
27c7ca7e
FB		 290 }
291}
292
c2432a42
AJ		 293#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
294 && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
c227f099 295static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
27c7ca7e
FB		 296 uint32_t mem_value)
297{
c2432a42
AJ		 298
299 if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
27c7ca7e
FB		 300 ignore_access("byte write", addr);
301 return;
27c7ca7e 302 }
c2432a42
AJ		 303
304 error_access("byte write", addr);
43dc2a64 305 abort();
27c7ca7e
FB		 306}
307
c227f099 308static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
27c7ca7e
FB		 309 uint32_t mem_value)
310{
311 SH7750State *s = opaque;
312 uint16_t temp;
313
314 switch (addr) {
315 /* SDRAM controller */
27c7ca7e 316 case SH7750_BCR2_A7:
c2f01775
AZ		 317 s->bcr2 = mem_value;
318 return;
27c7ca7e 319 case SH7750_BCR3_A7:
c2432a42
AJ		 320 if(!has_bcr3_and_bcr4(s))
321 error_access("word write", addr);
322 s->bcr3 = mem_value;
323 return;
324 case SH7750_PCR_A7:
325 s->pcr = mem_value;
326 return;
27c7ca7e 327 case SH7750_RTCNT_A7:
c2432a42 328 case SH7750_RTCOR_A7:
27c7ca7e
FB		 329 case SH7750_RTCSR_A7:
330 ignore_access("word write", addr);
331 return;
332 /* IO ports */
333 case SH7750_PDTRA_A7:
334 temp = porta_lines(s);
335 s->pdtra = mem_value;
336 porta_changed(s, temp);
337 return;
338 case SH7750_PDTRB_A7:
339 temp = portb_lines(s);
340 s->pdtrb = mem_value;
341 portb_changed(s, temp);
342 return;
343 case SH7750_RFCR_A7:
344 fprintf(stderr, "Write access to refresh count register\n");
345 s->rfcr = mem_value;
346 return;
27c7ca7e
FB		 347 case SH7750_GPIOIC_A7:
348 s->gpioic = mem_value;
349 if (mem_value != 0) {
350 fprintf(stderr, "I/O interrupts not implemented\n");
43dc2a64 351 abort();
27c7ca7e
FB		 352 }
353 return;
354 default:
355 error_access("word write", addr);
43dc2a64 356 abort();
27c7ca7e
FB		 357 }
358}
359
c227f099 360static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
27c7ca7e
FB		 361 uint32_t mem_value)
362{
363 SH7750State *s = opaque;
364 uint16_t temp;
365
366 switch (addr) {
367 /* SDRAM controller */
368 case SH7750_BCR1_A7:
c2f01775
AZ		 369 s->bcr1 = mem_value;
370 return;
27c7ca7e 371 case SH7750_BCR4_A7:
c2432a42
AJ		 372 if(!has_bcr3_and_bcr4(s))
373 error_access("long write", addr);
374 s->bcr4 = mem_value;
375 return;
27c7ca7e
FB		 376 case SH7750_WCR1_A7:
377 case SH7750_WCR2_A7:
378 case SH7750_WCR3_A7:
379 case SH7750_MCR_A7:
380 ignore_access("long write", addr);
381 return;
382 /* IO ports */
383 case SH7750_PCTRA_A7:
384 temp = porta_lines(s);
385 s->pctra = mem_value;
386 s->portdira = portdir(mem_value);
387 s->portpullupa = portpullup(mem_value);
388 porta_changed(s, temp);
389 return;
390 case SH7750_PCTRB_A7:
391 temp = portb_lines(s);
392 s->pctrb = mem_value;
393 s->portdirb = portdir(mem_value);
394 s->portpullupb = portpullup(mem_value);
395 portb_changed(s, temp);
396 return;
27c7ca7e 397 case SH7750_MMUCR_A7:
e0bcb9ca
AJ		 398 if (mem_value & MMUCR_TI) {
399 cpu_sh4_invalidate_tlb(s->cpu);
400 }
401 s->cpu->mmucr = mem_value & ~MMUCR_TI;
402 return;
27c7ca7e 403 case SH7750_PTEH_A7:
06afe2c8
AJ		 404 /* If asid changes, clear all registered tlb entries. */
405 if ((s->cpu->pteh & 0xff) != (mem_value & 0xff))
406 tlb_flush(s->cpu, 1);
27c7ca7e
FB		 407 s->cpu->pteh = mem_value;
408 return;
409 case SH7750_PTEL_A7:
410 s->cpu->ptel = mem_value;
411 return;
ea2b542a
AJ		 412 case SH7750_PTEA_A7:
413 s->cpu->ptea = mem_value & 0x0000000f;
414 return;
27c7ca7e
FB		 415 case SH7750_TTB_A7:
416 s->cpu->ttb = mem_value;
417 return;
418 case SH7750_TEA_A7:
419 s->cpu->tea = mem_value;
420 return;
421 case SH7750_TRA_A7:
422 s->cpu->tra = mem_value & 0x000007ff;
423 return;
424 case SH7750_EXPEVT_A7:
425 s->cpu->expevt = mem_value & 0x000007ff;
426 return;
427 case SH7750_INTEVT_A7:
428 s->cpu->intevt = mem_value & 0x000007ff;
429 return;
430 case SH7750_CCR_A7:
431 s->ccr = mem_value;
432 return;
433 default:
434 error_access("long write", addr);
43dc2a64 435 abort();
27c7ca7e
FB		 436 }
437}
438
d60efc6b 439static CPUReadMemoryFunc * const sh7750_mem_read[] = {
27c7ca7e
FB		 440 sh7750_mem_readb,
441 sh7750_mem_readw,
442 sh7750_mem_readl
443};
444
d60efc6b 445static CPUWriteMemoryFunc * const sh7750_mem_write[] = {
27c7ca7e
FB		 446 sh7750_mem_writeb,
447 sh7750_mem_writew,
448 sh7750_mem_writel
449};
450
80f515e6
AZ		 451/* sh775x interrupt controller tables for sh_intc.c
452 * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
453 */
454
455enum {
456 UNUSED = 0,
457
458 /* interrupt sources */
c6d86a33
AZ		 459 IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7,
460 IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E,
461 IRL0, IRL1, IRL2, IRL3,
80f515e6
AZ		 462 HUDI, GPIOI,
463 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
464 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
465 DMAC_DMAE,
466 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
467 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
468 TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
469 RTC_ATI, RTC_PRI, RTC_CUI,
470 SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
471 SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
472 WDT,
473 REF_RCMI, REF_ROVI,
474
475 /* interrupt groups */
476 DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
c6d86a33
AZ		 477 /* irl bundle */
478 IRL,
80f515e6
AZ		 479
480 NR_SOURCES,
481};
482
483static struct intc_vect vectors[] = {
484 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
485 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
486 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
487 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
488 INTC_VECT(RTC_CUI, 0x4c0),
489 INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
490 INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
491 INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
492 INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
493 INTC_VECT(WDT, 0x560),
494 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
495};
496
497static struct intc_group groups[] = {
498 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
499 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
500 INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
501 INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
502 INTC_GROUP(REF, REF_RCMI, REF_ROVI),
503};
504
505static struct intc_prio_reg prio_registers[] = {
506 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
507 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
508 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
509 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
510 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
511 TMU4, TMU3,
512 PCIC1, PCIC0_PCISERR } },
513};
514
515/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
516
517static struct intc_vect vectors_dma4[] = {
518 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
519 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
520 INTC_VECT(DMAC_DMAE, 0x6c0),
521};
522
523static struct intc_group groups_dma4[] = {
524 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
525 DMAC_DMTE3, DMAC_DMAE),
526};
527
528/* SH7750R and SH7751R both have 8-channel DMA controllers */
529
530static struct intc_vect vectors_dma8[] = {
531 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
532 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
533 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
534 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
535 INTC_VECT(DMAC_DMAE, 0x6c0),
536};
537
538static struct intc_group groups_dma8[] = {
539 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
540 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
541 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
542};
543
544/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
545
546static struct intc_vect vectors_tmu34[] = {
547 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
548};
549
550static struct intc_mask_reg mask_registers[] = {
551 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
552 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
553 0, 0, 0, 0, 0, 0, TMU4, TMU3,
554 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
555 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
556 PCIC1_PCIDMA3, PCIC0_PCISERR } },
557};
558
559/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
560
561static struct intc_vect vectors_irlm[] = {
562 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
563 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
564};
565
566/* SH7751 and SH7751R both have PCI */
567
568static struct intc_vect vectors_pci[] = {
569 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
570 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
571 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
572 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
573};
574
575static struct intc_group groups_pci[] = {
576 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
577 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
578};
579
c6d86a33
AZ		 580static struct intc_vect vectors_irl[] = {
581 INTC_VECT(IRL_0, 0x200),
582 INTC_VECT(IRL_1, 0x220),
583 INTC_VECT(IRL_2, 0x240),
584 INTC_VECT(IRL_3, 0x260),
585 INTC_VECT(IRL_4, 0x280),
586 INTC_VECT(IRL_5, 0x2a0),
587 INTC_VECT(IRL_6, 0x2c0),
588 INTC_VECT(IRL_7, 0x2e0),
589 INTC_VECT(IRL_8, 0x300),
590 INTC_VECT(IRL_9, 0x320),
591 INTC_VECT(IRL_A, 0x340),
592 INTC_VECT(IRL_B, 0x360),
593 INTC_VECT(IRL_C, 0x380),
594 INTC_VECT(IRL_D, 0x3a0),
595 INTC_VECT(IRL_E, 0x3c0),
596};
597
598static struct intc_group groups_irl[] = {
599 INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6,
600 IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E),
601};
602
29e179bc
AJ		 603/**********************************************************************
604 Memory mapped cache and TLB
605**********************************************************************/
606
607#define MM_REGION_MASK 0x07000000
608#define MM_ICACHE_ADDR (0)
609#define MM_ICACHE_DATA (1)
610#define MM_ITLB_ADDR (2)
611#define MM_ITLB_DATA (3)
612#define MM_OCACHE_ADDR (4)
613#define MM_OCACHE_DATA (5)
614#define MM_UTLB_ADDR (6)
615#define MM_UTLB_DATA (7)
616#define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24)
617
c227f099 618static uint32_t invalid_read(void *opaque, target_phys_addr_t addr)
29e179bc 619{
43dc2a64 620 abort();
29e179bc
AJ		 621
622 return 0;
623}
624
c227f099 625static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr)
29e179bc 626{
bc656a29 627 SH7750State *s = opaque;
29e179bc
AJ		 628 uint32_t ret = 0;
629
630 switch (MM_REGION_TYPE(addr)) {
631 case MM_ICACHE_ADDR:
632 case MM_ICACHE_DATA:
633 /* do nothing */
634 break;
635 case MM_ITLB_ADDR:
bc656a29
AJ		 636 ret = cpu_sh4_read_mmaped_itlb_addr(s->cpu, addr);
637 break;
29e179bc 638 case MM_ITLB_DATA:
bc656a29
AJ		 639 ret = cpu_sh4_read_mmaped_itlb_data(s->cpu, addr);
640 break;
29e179bc
AJ		 641 case MM_OCACHE_ADDR:
642 case MM_OCACHE_DATA:
643 /* do nothing */
644 break;
645 case MM_UTLB_ADDR:
bc656a29
AJ		 646 ret = cpu_sh4_read_mmaped_utlb_addr(s->cpu, addr);
647 break;
29e179bc 648 case MM_UTLB_DATA:
bc656a29
AJ		 649 ret = cpu_sh4_read_mmaped_utlb_data(s->cpu, addr);
650 break;
29e179bc 651 default:
43dc2a64 652 abort();
29e179bc
AJ		 653 }
654
655 return ret;
656}
657
c227f099 658static void invalid_write(void *opaque, target_phys_addr_t addr,
29e179bc
AJ		 659 uint32_t mem_value)
660{
43dc2a64 661 abort();
29e179bc
AJ		 662}
663
c227f099 664static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
29e179bc
AJ		 665 uint32_t mem_value)
666{
667 SH7750State *s = opaque;
668
669 switch (MM_REGION_TYPE(addr)) {
670 case MM_ICACHE_ADDR:
671 case MM_ICACHE_DATA:
672 /* do nothing */
673 break;
674 case MM_ITLB_ADDR:
c0f809c4
AJ		 675 cpu_sh4_write_mmaped_itlb_addr(s->cpu, addr, mem_value);
676 break;
29e179bc 677 case MM_ITLB_DATA:
9f97309a 678 cpu_sh4_write_mmaped_itlb_data(s->cpu, addr, mem_value);
43dc2a64 679 abort();
29e179bc
AJ		 680 break;
681 case MM_OCACHE_ADDR:
682 case MM_OCACHE_DATA:
683 /* do nothing */
684 break;
685 case MM_UTLB_ADDR:
686 cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value);
687 break;
688 case MM_UTLB_DATA:
9f97309a 689 cpu_sh4_write_mmaped_utlb_data(s->cpu, addr, mem_value);
29e179bc
AJ		 690 break;
691 default:
43dc2a64 692 abort();
29e179bc
AJ		 693 break;
694 }
695}
696
d60efc6b 697static CPUReadMemoryFunc * const sh7750_mmct_read[] = {
29e179bc
AJ		 698 invalid_read,
699 invalid_read,
700 sh7750_mmct_readl
701};
702
d60efc6b 703static CPUWriteMemoryFunc * const sh7750_mmct_write[] = {
29e179bc
AJ		 704 invalid_write,
705 invalid_write,
706 sh7750_mmct_writel
707};
708
27c7ca7e
FB		 709SH7750State *sh7750_init(CPUSH4State * cpu)
710{
711 SH7750State *s;
712 int sh7750_io_memory;
29e179bc 713 int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */
27c7ca7e 714
7267c094 715 s = g_malloc0(sizeof(SH7750State));
27c7ca7e
FB		 716 s->cpu = cpu;
717 s->periph_freq = 60000000; /* 60MHz */
1eed09cb 718 sh7750_io_memory = cpu_register_io_memory(sh7750_mem_read,
2507c12a
AG		 719 sh7750_mem_write, s,
720 DEVICE_NATIVE_ENDIAN);
486579de
AZ		 721 cpu_register_physical_memory_offset(0x1f000000, 0x1000,
722 sh7750_io_memory, 0x1f000000);
5c16736a
AZ		 723 cpu_register_physical_memory_offset(0xff000000, 0x1000,
724 sh7750_io_memory, 0x1f000000);
486579de
AZ		 725 cpu_register_physical_memory_offset(0x1f800000, 0x1000,
726 sh7750_io_memory, 0x1f800000);
5c16736a
AZ		 727 cpu_register_physical_memory_offset(0xff800000, 0x1000,
728 sh7750_io_memory, 0x1f800000);
486579de
AZ		 729 cpu_register_physical_memory_offset(0x1fc00000, 0x1000,
730 sh7750_io_memory, 0x1fc00000);
5c16736a
AZ		 731 cpu_register_physical_memory_offset(0xffc00000, 0x1000,
732 sh7750_io_memory, 0x1fc00000);
2f062c72 733
1eed09cb 734 sh7750_mm_cache_and_tlb = cpu_register_io_memory(sh7750_mmct_read,
2507c12a
AG		 735 sh7750_mmct_write, s,
736 DEVICE_NATIVE_ENDIAN);
29e179bc
AJ		 737 cpu_register_physical_memory(0xf0000000, 0x08000000,
738 sh7750_mm_cache_and_tlb);
739
80f515e6
AZ		 740 sh_intc_init(&s->intc, NR_SOURCES,
741 _INTC_ARRAY(mask_registers),
742 _INTC_ARRAY(prio_registers));
743
0fd3ca30 744 sh_intc_register_sources(&s->intc,
80f515e6
AZ		 745 _INTC_ARRAY(vectors),
746 _INTC_ARRAY(groups));
747
e96e2044
TS		 748 cpu->intc_handle = &s->intc;
749
bf5b7423 750 sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0],
4e7ed2d1
AJ		 751 s->intc.irqs[SCI1_ERI],
752 s->intc.irqs[SCI1_RXI],
753 s->intc.irqs[SCI1_TXI],
754 s->intc.irqs[SCI1_TEI],
bf5b7423 755 NULL);
2f062c72 756 sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
bf5b7423 757 s->periph_freq, serial_hds[1],
4e7ed2d1
AJ		 758 s->intc.irqs[SCIF_ERI],
759 s->intc.irqs[SCIF_RXI],
760 s->intc.irqs[SCIF_TXI],
bf5b7423 761 NULL,
4e7ed2d1 762 s->intc.irqs[SCIF_BRI]);
cd1a3f68
TS		 763
764 tmu012_init(0x1fd80000,
765 TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
703243a0 766 s->periph_freq,
96e2fc41
AJ		 767 s->intc.irqs[TMU0],
768 s->intc.irqs[TMU1],
769 s->intc.irqs[TMU2_TUNI],
770 s->intc.irqs[TMU2_TICPI]);
80f515e6 771
0fd3ca30
AJ		 772 if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
773 sh_intc_register_sources(&s->intc,
80f515e6
AZ		 774 _INTC_ARRAY(vectors_dma4),
775 _INTC_ARRAY(groups_dma4));
776 }
777
0fd3ca30
AJ		 778 if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
779 sh_intc_register_sources(&s->intc,
80f515e6
AZ		 780 _INTC_ARRAY(vectors_dma8),
781 _INTC_ARRAY(groups_dma8));
782 }
783
0fd3ca30
AJ		 784 if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
785 sh_intc_register_sources(&s->intc,
80f515e6 786 _INTC_ARRAY(vectors_tmu34),
f26ae302 787 NULL, 0);
703243a0 788 tmu012_init(0x1e100000, 0, s->periph_freq,
96e2fc41
AJ		 789 s->intc.irqs[TMU3],
790 s->intc.irqs[TMU4],
703243a0 791 NULL, NULL);
80f515e6
AZ		 792 }
793
0fd3ca30
AJ		 794 if (cpu->id & (SH_CPU_SH7751_ALL)) {
795 sh_intc_register_sources(&s->intc,
80f515e6
AZ		 796 _INTC_ARRAY(vectors_pci),
797 _INTC_ARRAY(groups_pci));
798 }
799
0fd3ca30
AJ		 800 if (cpu->id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
801 sh_intc_register_sources(&s->intc,
80f515e6 802 _INTC_ARRAY(vectors_irlm),
f26ae302 803 NULL, 0);
80f515e6
AZ		 804 }
805
c6d86a33
AZ		 806 sh_intc_register_sources(&s->intc,
807 _INTC_ARRAY(vectors_irl),
808 _INTC_ARRAY(groups_irl));
27c7ca7e
FB		 809 return s;
810}
c6d86a33
AZ		 811
812qemu_irq sh7750_irl(SH7750State *s)
813{
814 sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0); /* enable */
815 return qemu_allocate_irqs(sh_intc_set_irl, sh_intc_source(&s->intc, IRL),
816 1)[0];
817}
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