[qemu.git] / target-mips / cpu.h

#if !defined (__MIPS_CPU_H__)
#define __MIPS_CPU_H__

#define TARGET_HAS_ICE 1

#define ELF_MACHINE	EM_MIPS

#include "config.h"
#include "mips-defs.h"
#include "cpu-defs.h"
#include "softfloat.h"

// uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
// XXX: move that elsewhere
#if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
typedef unsigned char           uint_fast8_t;
typedef unsigned int            uint_fast16_t;
#endif

struct CPUMIPSState;

typedef struct r4k_tlb_t r4k_tlb_t;
struct r4k_tlb_t {
    target_ulong VPN;
    uint32_t PageMask;
    uint_fast8_t ASID;
    uint_fast16_t G:1;
    uint_fast16_t C0:3;
    uint_fast16_t C1:3;
    uint_fast16_t V0:1;
    uint_fast16_t V1:1;
    uint_fast16_t D0:1;
    uint_fast16_t D1:1;
    target_ulong PFN[2];
};

typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
struct CPUMIPSTLBContext {
    uint32_t nb_tlb;
    uint32_t tlb_in_use;
    int (*map_address) (struct CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
    void (*do_tlbwi) (void);
    void (*do_tlbwr) (void);
    void (*do_tlbp) (void);
    void (*do_tlbr) (void);
    union {
        struct {
            r4k_tlb_t tlb[MIPS_TLB_MAX];
        } r4k;
    } mmu;
};

typedef union fpr_t fpr_t;
union fpr_t {
    float64  fd;   /* ieee double precision */
    float32  fs[2];/* ieee single precision */
    uint64_t d;    /* binary double fixed-point */
    uint32_t w[2]; /* binary single fixed-point */
};
/* define FP_ENDIAN_IDX to access the same location
 * in the fpr_t union regardless of the host endianess
 */
#if defined(WORDS_BIGENDIAN)
#  define FP_ENDIAN_IDX 1
#else
#  define FP_ENDIAN_IDX 0
#endif

typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
struct CPUMIPSFPUContext {
    /* Floating point registers */
    fpr_t fpr[32];
#ifndef USE_HOST_FLOAT_REGS
    fpr_t ft0;
    fpr_t ft1;
    fpr_t ft2;
#endif
    float_status fp_status;
    /* fpu implementation/revision register (fir) */
    uint32_t fcr0;
#define FCR0_F64 22
#define FCR0_L 21
#define FCR0_W 20
#define FCR0_3D 19
#define FCR0_PS 18
#define FCR0_D 17
#define FCR0_S 16
#define FCR0_PRID 8
#define FCR0_REV 0
    /* fcsr */
    uint32_t fcr31;
#define SET_FP_COND(num,env)     do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
#define CLEAR_FP_COND(num,env)   do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
#define GET_FP_COND(env)         ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1))
#define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
#define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
#define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
#define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
#define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
#define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
#define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
#define FP_INEXACT        1
#define FP_UNDERFLOW      2
#define FP_OVERFLOW       4
#define FP_DIV0           8
#define FP_INVALID        16
#define FP_UNIMPLEMENTED  32
};

#define NB_MMU_MODES 3

typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
struct CPUMIPSMVPContext {
    int32_t CP0_MVPControl;
#define CP0MVPCo_CPA	3
#define CP0MVPCo_STLB	2
#define CP0MVPCo_VPC	1
#define CP0MVPCo_EVP	0
    int32_t CP0_MVPConf0;
#define CP0MVPC0_M	31
#define CP0MVPC0_TLBS	29
#define CP0MVPC0_GS	28
#define CP0MVPC0_PCP	27
#define CP0MVPC0_PTLBE	16
#define CP0MVPC0_TCA	15
#define CP0MVPC0_PVPE	10
#define CP0MVPC0_PTC	0
    int32_t CP0_MVPConf1;
#define CP0MVPC1_CIM	31
#define CP0MVPC1_CIF	30
#define CP0MVPC1_PCX	20
#define CP0MVPC1_PCP2	10
#define CP0MVPC1_PCP1	0
};

typedef struct mips_def_t mips_def_t;

#define MIPS_SHADOW_SET_MAX 16
#define MIPS_TC_MAX 5
#define MIPS_DSP_ACC 4

typedef struct CPUMIPSState CPUMIPSState;
struct CPUMIPSState {
    /* General integer registers */
    target_ulong gpr[32][MIPS_SHADOW_SET_MAX];
    /* Special registers */
    target_ulong PC[MIPS_TC_MAX];
#if TARGET_LONG_BITS > HOST_LONG_BITS
    target_ulong t0;
    target_ulong t1;
    target_ulong t2;
#endif
    target_ulong HI[MIPS_DSP_ACC][MIPS_TC_MAX];
    target_ulong LO[MIPS_DSP_ACC][MIPS_TC_MAX];
    target_ulong ACX[MIPS_DSP_ACC][MIPS_TC_MAX];
    target_ulong DSPControl[MIPS_TC_MAX];

    CPUMIPSMVPContext *mvp;
    CPUMIPSTLBContext *tlb;
    CPUMIPSFPUContext *fpu;
    uint32_t current_tc;

    uint32_t SEGBITS;
    target_ulong SEGMask;
    uint32_t PABITS;
    target_ulong PAMask;

    int32_t CP0_Index;
    /* CP0_MVP* are per MVP registers. */
    int32_t CP0_Random;
    int32_t CP0_VPEControl;
#define CP0VPECo_YSI	21
#define CP0VPECo_GSI	20
#define CP0VPECo_EXCPT	16
#define CP0VPECo_TE	15
#define CP0VPECo_TargTC	0
    int32_t CP0_VPEConf0;
#define CP0VPEC0_M	31
#define CP0VPEC0_XTC	21
#define CP0VPEC0_TCS	19
#define CP0VPEC0_SCS	18
#define CP0VPEC0_DSC	17
#define CP0VPEC0_ICS	16
#define CP0VPEC0_MVP	1
#define CP0VPEC0_VPA	0
    int32_t CP0_VPEConf1;
#define CP0VPEC1_NCX	20
#define CP0VPEC1_NCP2	10
#define CP0VPEC1_NCP1	0
    target_ulong CP0_YQMask;
    target_ulong CP0_VPESchedule;
    target_ulong CP0_VPEScheFBack;
    int32_t CP0_VPEOpt;
#define CP0VPEOpt_IWX7	15
#define CP0VPEOpt_IWX6	14
#define CP0VPEOpt_IWX5	13
#define CP0VPEOpt_IWX4	12
#define CP0VPEOpt_IWX3	11
#define CP0VPEOpt_IWX2	10
#define CP0VPEOpt_IWX1	9
#define CP0VPEOpt_IWX0	8
#define CP0VPEOpt_DWX7	7
#define CP0VPEOpt_DWX6	6
#define CP0VPEOpt_DWX5	5
#define CP0VPEOpt_DWX4	4
#define CP0VPEOpt_DWX3	3
#define CP0VPEOpt_DWX2	2
#define CP0VPEOpt_DWX1	1
#define CP0VPEOpt_DWX0	0
    target_ulong CP0_EntryLo0;
    int32_t CP0_TCStatus[MIPS_TC_MAX];
#define CP0TCSt_TCU3	31
#define CP0TCSt_TCU2	30
#define CP0TCSt_TCU1	29
#define CP0TCSt_TCU0	28
#define CP0TCSt_TMX	27
#define CP0TCSt_RNST	23
#define CP0TCSt_TDS	21
#define CP0TCSt_DT	20
#define CP0TCSt_DA	15
#define CP0TCSt_A	13
#define CP0TCSt_TKSU	11
#define CP0TCSt_IXMT	10
#define CP0TCSt_TASID	0
    int32_t CP0_TCBind[MIPS_TC_MAX];
#define CP0TCBd_CurTC	21
#define CP0TCBd_TBE	17
#define CP0TCBd_CurVPE	0
    target_ulong CP0_TCHalt[MIPS_TC_MAX];
    target_ulong CP0_TCContext[MIPS_TC_MAX];
    target_ulong CP0_TCSchedule[MIPS_TC_MAX];
    target_ulong CP0_TCScheFBack[MIPS_TC_MAX];
    target_ulong CP0_EntryLo1;
    target_ulong CP0_Context;
    int32_t CP0_PageMask;
    int32_t CP0_PageGrain;
    int32_t CP0_Wired;
    int32_t CP0_SRSConf0_rw_bitmask;
    int32_t CP0_SRSConf0;
#define CP0SRSC0_M	31
#define CP0SRSC0_SRS3	20
#define CP0SRSC0_SRS2	10
#define CP0SRSC0_SRS1	0
    int32_t CP0_SRSConf1_rw_bitmask;
    int32_t CP0_SRSConf1;
#define CP0SRSC1_M	31
#define CP0SRSC1_SRS6	20
#define CP0SRSC1_SRS5	10
#define CP0SRSC1_SRS4	0
    int32_t CP0_SRSConf2_rw_bitmask;
    int32_t CP0_SRSConf2;
#define CP0SRSC2_M	31
#define CP0SRSC2_SRS9	20
#define CP0SRSC2_SRS8	10
#define CP0SRSC2_SRS7	0
    int32_t CP0_SRSConf3_rw_bitmask;
    int32_t CP0_SRSConf3;
#define CP0SRSC3_M	31
#define CP0SRSC3_SRS12	20
#define CP0SRSC3_SRS11	10
#define CP0SRSC3_SRS10	0
    int32_t CP0_SRSConf4_rw_bitmask;
    int32_t CP0_SRSConf4;
#define CP0SRSC4_SRS15	20
#define CP0SRSC4_SRS14	10
#define CP0SRSC4_SRS13	0
    int32_t CP0_HWREna;
    target_ulong CP0_BadVAddr;
    int32_t CP0_Count;
    target_ulong CP0_EntryHi;
    int32_t CP0_Compare;
    int32_t CP0_Status;
#define CP0St_CU3   31
#define CP0St_CU2   30
#define CP0St_CU1   29
#define CP0St_CU0   28
#define CP0St_RP    27
#define CP0St_FR    26
#define CP0St_RE    25
#define CP0St_MX    24
#define CP0St_PX    23
#define CP0St_BEV   22
#define CP0St_TS    21
#define CP0St_SR    20
#define CP0St_NMI   19
#define CP0St_IM    8
#define CP0St_KX    7
#define CP0St_SX    6
#define CP0St_UX    5
#define CP0St_KSU   3
#define CP0St_ERL   2
#define CP0St_EXL   1
#define CP0St_IE    0
    int32_t CP0_IntCtl;
#define CP0IntCtl_IPTI 29
#define CP0IntCtl_IPPC1 26
#define CP0IntCtl_VS 5
    int32_t CP0_SRSCtl;
#define CP0SRSCtl_HSS 26
#define CP0SRSCtl_EICSS 18
#define CP0SRSCtl_ESS 12
#define CP0SRSCtl_PSS 6
#define CP0SRSCtl_CSS 0
    int32_t CP0_SRSMap;
#define CP0SRSMap_SSV7 28
#define CP0SRSMap_SSV6 24
#define CP0SRSMap_SSV5 20
#define CP0SRSMap_SSV4 16
#define CP0SRSMap_SSV3 12
#define CP0SRSMap_SSV2 8
#define CP0SRSMap_SSV1 4
#define CP0SRSMap_SSV0 0
    int32_t CP0_Cause;
#define CP0Ca_BD   31
#define CP0Ca_TI   30
#define CP0Ca_CE   28
#define CP0Ca_DC   27
#define CP0Ca_PCI  26
#define CP0Ca_IV   23
#define CP0Ca_WP   22
#define CP0Ca_IP    8
#define CP0Ca_IP_mask 0x0000FF00
#define CP0Ca_EC    2
    target_ulong CP0_EPC;
    int32_t CP0_PRid;
    int32_t CP0_EBase;
    int32_t CP0_Config0;
#define CP0C0_M    31
#define CP0C0_K23  28
#define CP0C0_KU   25
#define CP0C0_MDU  20
#define CP0C0_MM   17
#define CP0C0_BM   16
#define CP0C0_BE   15
#define CP0C0_AT   13
#define CP0C0_AR   10
#define CP0C0_MT   7
#define CP0C0_VI   3
#define CP0C0_K0   0
    int32_t CP0_Config1;
#define CP0C1_M    31
#define CP0C1_MMU  25
#define CP0C1_IS   22
#define CP0C1_IL   19
#define CP0C1_IA   16
#define CP0C1_DS   13
#define CP0C1_DL   10
#define CP0C1_DA   7
#define CP0C1_C2   6
#define CP0C1_MD   5
#define CP0C1_PC   4
#define CP0C1_WR   3
#define CP0C1_CA   2
#define CP0C1_EP   1
#define CP0C1_FP   0
    int32_t CP0_Config2;
#define CP0C2_M    31
#define CP0C2_TU   28
#define CP0C2_TS   24
#define CP0C2_TL   20
#define CP0C2_TA   16
#define CP0C2_SU   12
#define CP0C2_SS   8
#define CP0C2_SL   4
#define CP0C2_SA   0
    int32_t CP0_Config3;
#define CP0C3_M    31
#define CP0C3_DSPP 10
#define CP0C3_LPA  7
#define CP0C3_VEIC 6
#define CP0C3_VInt 5
#define CP0C3_SP   4
#define CP0C3_MT   2
#define CP0C3_SM   1
#define CP0C3_TL   0
    int32_t CP0_Config6;
    int32_t CP0_Config7;
    /* XXX: Maybe make LLAddr per-TC? */
    target_ulong CP0_LLAddr;
    target_ulong CP0_WatchLo[8];
    int32_t CP0_WatchHi[8];
    target_ulong CP0_XContext;
    int32_t CP0_Framemask;
    int32_t CP0_Debug;
#define CP0DB_DBD  31
#define CP0DB_DM   30
#define CP0DB_LSNM 28
#define CP0DB_Doze 27
#define CP0DB_Halt 26
#define CP0DB_CNT  25
#define CP0DB_IBEP 24
#define CP0DB_DBEP 21
#define CP0DB_IEXI 20
#define CP0DB_VER  15
#define CP0DB_DEC  10
#define CP0DB_SSt  8
#define CP0DB_DINT 5
#define CP0DB_DIB  4
#define CP0DB_DDBS 3
#define CP0DB_DDBL 2
#define CP0DB_DBp  1
#define CP0DB_DSS  0
    int32_t CP0_Debug_tcstatus[MIPS_TC_MAX];
    target_ulong CP0_DEPC;
    int32_t CP0_Performance0;
    int32_t CP0_TagLo;
    int32_t CP0_DataLo;
    int32_t CP0_TagHi;
    int32_t CP0_DataHi;
    target_ulong CP0_ErrorEPC;
    int32_t CP0_DESAVE;
    /* Qemu */
    int interrupt_request;
    jmp_buf jmp_env;
    int exception_index;
    int error_code;
    int user_mode_only; /* user mode only simulation */
    uint32_t hflags;    /* CPU State */
    /* TMASK defines different execution modes */
#define MIPS_HFLAG_TMASK  0x01FF
#define MIPS_HFLAG_MODE   0x0007 /* execution modes                    */
    /* The KSU flags must be the lowest bits in hflags. The flag order
       must be the same as defined for CP0 Status. This allows to use
       the bits as the value of mmu_idx. */
#define MIPS_HFLAG_KSU    0x0003 /* kernel/supervisor/user mode mask   */
#define MIPS_HFLAG_UM       0x0002 /* user mode flag */
#define MIPS_HFLAG_SM       0x0001 /* supervisor mode flag */
#define MIPS_HFLAG_KM       0x0000 /* kernel mode flag */
#define MIPS_HFLAG_DM     0x0004 /* Debug mode                         */
#define MIPS_HFLAG_64     0x0008 /* 64-bit instructions enabled        */
#define MIPS_HFLAG_CP0    0x0010 /* CP0 enabled                        */
#define MIPS_HFLAG_FPU    0x0020 /* FPU enabled                        */
#define MIPS_HFLAG_F64    0x0040 /* 64-bit FPU enabled                 */
    /* True if the MIPS IV COP1X instructions can be used.  This also
       controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
       and RSQRT.D.  */
#define MIPS_HFLAG_COP1X  0x0080 /* COP1X instructions enabled         */
#define MIPS_HFLAG_RE     0x0100 /* Reversed endianness                */
    /* If translation is interrupted between the branch instruction and
     * the delay slot, record what type of branch it is so that we can
     * resume translation properly.  It might be possible to reduce
     * this from three bits to two.  */
#define MIPS_HFLAG_BMASK  0x0e00
#define MIPS_HFLAG_B      0x0200 /* Unconditional branch               */
#define MIPS_HFLAG_BC     0x0400 /* Conditional branch                 */
#define MIPS_HFLAG_BL     0x0600 /* Likely branch                      */
#define MIPS_HFLAG_BR     0x0800 /* branch to register (can't link TB) */
    target_ulong btarget;        /* Jump / branch target               */
    int bcond;                   /* Branch condition (if needed)       */

    int halted; /* TRUE if the CPU is in suspend state */

    int SYNCI_Step; /* Address step size for SYNCI */
    int CCRes; /* Cycle count resolution/divisor */
    uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
    uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
    int insn_flags; /* Supported instruction set */

#ifdef CONFIG_USER_ONLY
    target_ulong tls_value;
#endif

    CPU_COMMON

    const mips_def_t *cpu_model;
#ifndef CONFIG_USER_ONLY
    void *irq[8];
#endif

    struct QEMUTimer *timer; /* Internal timer */
};

int no_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
                        target_ulong address, int rw, int access_type);
int fixed_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
                           target_ulong address, int rw, int access_type);
int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
                     target_ulong address, int rw, int access_type);
void r4k_do_tlbwi (void);
void r4k_do_tlbwr (void);
void r4k_do_tlbp (void);
void r4k_do_tlbr (void);
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));

void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
                          int unused);

#define CPUState CPUMIPSState
#define cpu_init cpu_mips_init
#define cpu_exec cpu_mips_exec
#define cpu_gen_code cpu_mips_gen_code
#define cpu_signal_handler cpu_mips_signal_handler
#define cpu_list mips_cpu_list

/* MMU modes definitions. We carefully match the indices with our
   hflags layout. */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _super
#define MMU_MODE2_SUFFIX _user
#define MMU_USER_IDX 2
static inline int cpu_mmu_index (CPUState *env)
{
    return env->hflags & MIPS_HFLAG_KSU;
}

#include "cpu-all.h"

/* Memory access type :
 * may be needed for precise access rights control and precise exceptions.
 */
enum {
    /* 1 bit to define user level / supervisor access */
    ACCESS_USER  = 0x00,
    ACCESS_SUPER = 0x01,
    /* 1 bit to indicate direction */
    ACCESS_STORE = 0x02,
    /* Type of instruction that generated the access */
    ACCESS_CODE  = 0x10, /* Code fetch access                */
    ACCESS_INT   = 0x20, /* Integer load/store access        */
    ACCESS_FLOAT = 0x30, /* floating point load/store access */
};

/* Exceptions */
enum {
    EXCP_NONE          = -1,
    EXCP_RESET         = 0,
    EXCP_SRESET,
    EXCP_DSS,
    EXCP_DINT,
    EXCP_DDBL,
    EXCP_DDBS,
    EXCP_NMI,
    EXCP_MCHECK,
    EXCP_EXT_INTERRUPT, /* 8 */
    EXCP_DFWATCH,
    EXCP_DIB,
    EXCP_IWATCH,
    EXCP_AdEL,
    EXCP_AdES,
    EXCP_TLBF,
    EXCP_IBE,
    EXCP_DBp, /* 16 */
    EXCP_SYSCALL,
    EXCP_BREAK,
    EXCP_CpU,
    EXCP_RI,
    EXCP_OVERFLOW,
    EXCP_TRAP,
    EXCP_FPE,
    EXCP_DWATCH, /* 24 */
    EXCP_LTLBL,
    EXCP_TLBL,
    EXCP_TLBS,
    EXCP_DBE,
    EXCP_THREAD,
    EXCP_MDMX,
    EXCP_C2E,
    EXCP_CACHE, /* 32 */

    EXCP_LAST = EXCP_CACHE,
};

int cpu_mips_exec(CPUMIPSState *s);
CPUMIPSState *cpu_mips_init(const char *cpu_model);
uint32_t cpu_mips_get_clock (void);
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);

#endif /* !defined (__MIPS_CPU_H__) */
Commit	Line	Data
6af0bf9c FB	1	#if !defined (__MIPS_CPU_H__)
	2	#define __MIPS_CPU_H__
	3
4ad40f36 FB	4	#define TARGET_HAS_ICE 1
4ad40f36 FB	5
9042c0e2 TS	6	#define ELF_MACHINE EM_MIPS
9042c0e2 TS	7
c5d6edc3	8	#include "config.h"
6af0bf9c FB	9	#include "mips-defs.h"
6af0bf9c FB	10	#include "cpu-defs.h"
6af0bf9c FB	11	#include "softfloat.h"
6af0bf9c FB	12
fdbb4691 FB	13	// uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
fdbb4691 FB	14	// XXX: move that elsewhere
36bb244b	15	#if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
fdbb4691 FB	16	typedef unsigned char uint_fast8_t;
	17	typedef unsigned int uint_fast16_t;
	18	#endif
	19
ead9360e	20	struct CPUMIPSState;
6af0bf9c	21
29929e34 TS	22	typedef struct r4k_tlb_t r4k_tlb_t;
29929e34 TS	23	struct r4k_tlb_t {
6af0bf9c	24	target_ulong VPN;
9c2149c8	25	uint32_t PageMask;
98c1b82b PB	26	uint_fast8_t ASID;
	27	uint_fast16_t G:1;
	28	uint_fast16_t C0:3;
	29	uint_fast16_t C1:3;
	30	uint_fast16_t V0:1;
	31	uint_fast16_t V1:1;
	32	uint_fast16_t D0:1;
	33	uint_fast16_t D1:1;
6af0bf9c FB	34	target_ulong PFN[2];
6af0bf9c FB	35	};
6af0bf9c	36
ead9360e TS	37	typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
	38	struct CPUMIPSTLBContext {
	39	uint32_t nb_tlb;
	40	uint32_t tlb_in_use;
	41	int (map_address) (struct CPUMIPSState env, target_ulong physical, int prot, target_ulong address, int rw, int access_type);
	42	void (*do_tlbwi) (void);
	43	void (*do_tlbwr) (void);
	44	void (*do_tlbp) (void);
	45	void (*do_tlbr) (void);
	46	union {
	47	struct {
	48	r4k_tlb_t tlb[MIPS_TLB_MAX];
	49	} r4k;
	50	} mmu;
	51	};
51b2772f	52
ead9360e TS	53	typedef union fpr_t fpr_t;
	54	union fpr_t {
	55	float64 fd; /* ieee double precision */
	56	float32 fs[2];/* ieee single precision */
	57	uint64_t d; /* binary double fixed-point */
	58	uint32_t w[2]; /* binary single fixed-point */
	59	};
	60	/* define FP_ENDIAN_IDX to access the same location
	61	* in the fpr_t union regardless of the host endianess
	62	*/
	63	#if defined(WORDS_BIGENDIAN)
	64	# define FP_ENDIAN_IDX 1
	65	#else
	66	# define FP_ENDIAN_IDX 0
c570fd16	67	#endif
ead9360e TS	68
	69	typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
	70	struct CPUMIPSFPUContext {
6af0bf9c	71	/* Floating point registers */
f7cfb2a1	72	fpr_t fpr[32];
6ea83fed FB	73	#ifndef USE_HOST_FLOAT_REGS
	74	fpr_t ft0;
	75	fpr_t ft1;
	76	fpr_t ft2;
	77	#endif
	78	float_status fp_status;
5a5012ec	79	/* fpu implementation/revision register (fir) */
6af0bf9c	80	uint32_t fcr0;
5a5012ec TS	81	#define FCR0_F64 22
	82	#define FCR0_L 21
	83	#define FCR0_W 20
	84	#define FCR0_3D 19
	85	#define FCR0_PS 18
	86	#define FCR0_D 17
	87	#define FCR0_S 16
	88	#define FCR0_PRID 8
	89	#define FCR0_REV 0
6ea83fed FB	90	/* fcsr */
6ea83fed FB	91	uint32_t fcr31;
fd4a04eb TS	92	#define SET_FP_COND(num,env) do { ((env)->fcr31) \|= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
	93	#define CLEAR_FP_COND(num,env) do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
	94	#define GET_FP_COND(env) ((((env)->fcr31 >> 24) & 0xfe) \| (((env)->fcr31 >> 23) & 0x1))
5a5012ec TS	95	#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
	96	#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
	97	#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
	98	#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) \| ((v & 0x3f) << 12); } while(0)
	99	#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) \| ((v & 0x1f) << 7); } while(0)
	100	#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) \| ((v & 0x1f) << 2); } while(0)
	101	#define UPDATE_FP_FLAGS(reg,v) do { (reg) \|= ((v & 0x1f) << 2); } while(0)
6ea83fed FB	102	#define FP_INEXACT 1
	103	#define FP_UNDERFLOW 2
	104	#define FP_OVERFLOW 4
	105	#define FP_DIV0 8
	106	#define FP_INVALID 16
	107	#define FP_UNIMPLEMENTED 32
ead9360e TS	108	};
ead9360e TS	109
623a930e	110	#define NB_MMU_MODES 3
6ebbf390	111
ead9360e TS	112	typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
	113	struct CPUMIPSMVPContext {
	114	int32_t CP0_MVPControl;
	115	#define CP0MVPCo_CPA 3
	116	#define CP0MVPCo_STLB 2
	117	#define CP0MVPCo_VPC 1
	118	#define CP0MVPCo_EVP 0
	119	int32_t CP0_MVPConf0;
	120	#define CP0MVPC0_M 31
	121	#define CP0MVPC0_TLBS 29
	122	#define CP0MVPC0_GS 28
	123	#define CP0MVPC0_PCP 27
	124	#define CP0MVPC0_PTLBE 16
	125	#define CP0MVPC0_TCA 15
	126	#define CP0MVPC0_PVPE 10
	127	#define CP0MVPC0_PTC 0
	128	int32_t CP0_MVPConf1;
	129	#define CP0MVPC1_CIM 31
	130	#define CP0MVPC1_CIF 30
	131	#define CP0MVPC1_PCX 20
	132	#define CP0MVPC1_PCP2 10
	133	#define CP0MVPC1_PCP1 0
	134	};
	135
	136	typedef struct mips_def_t mips_def_t;
	137
	138	#define MIPS_SHADOW_SET_MAX 16
	139	#define MIPS_TC_MAX 5
	140	#define MIPS_DSP_ACC 4
	141
	142	typedef struct CPUMIPSState CPUMIPSState;
	143	struct CPUMIPSState {
	144	/* General integer registers */
	145	target_ulong gpr[32][MIPS_SHADOW_SET_MAX];
	146	/* Special registers */
	147	target_ulong PC[MIPS_TC_MAX];
	148	#if TARGET_LONG_BITS > HOST_LONG_BITS
	149	target_ulong t0;
	150	target_ulong t1;
	151	target_ulong t2;
	152	#endif
	153	target_ulong HI[MIPS_DSP_ACC][MIPS_TC_MAX];
	154	target_ulong LO[MIPS_DSP_ACC][MIPS_TC_MAX];
	155	target_ulong ACX[MIPS_DSP_ACC][MIPS_TC_MAX];
	156	target_ulong DSPControl[MIPS_TC_MAX];
	157
	158	CPUMIPSMVPContext *mvp;
	159	CPUMIPSTLBContext *tlb;
	160	CPUMIPSFPUContext *fpu;
	161	uint32_t current_tc;
36d23958	162
e034e2c3 TS	163	uint32_t SEGBITS;
e034e2c3 TS	164	target_ulong SEGMask;
6d35524c TS	165	uint32_t PABITS;
6d35524c TS	166	target_ulong PAMask;
29929e34	167
9c2149c8	168	int32_t CP0_Index;
ead9360e	169	/* CP0_MVP* are per MVP registers. */
9c2149c8	170	int32_t CP0_Random;
ead9360e TS	171	int32_t CP0_VPEControl;
	172	#define CP0VPECo_YSI 21
	173	#define CP0VPECo_GSI 20
	174	#define CP0VPECo_EXCPT 16
	175	#define CP0VPECo_TE 15
	176	#define CP0VPECo_TargTC 0
	177	int32_t CP0_VPEConf0;
	178	#define CP0VPEC0_M 31
	179	#define CP0VPEC0_XTC 21
	180	#define CP0VPEC0_TCS 19
	181	#define CP0VPEC0_SCS 18
	182	#define CP0VPEC0_DSC 17
	183	#define CP0VPEC0_ICS 16
	184	#define CP0VPEC0_MVP 1
	185	#define CP0VPEC0_VPA 0
	186	int32_t CP0_VPEConf1;
	187	#define CP0VPEC1_NCX 20
	188	#define CP0VPEC1_NCP2 10
	189	#define CP0VPEC1_NCP1 0
	190	target_ulong CP0_YQMask;
	191	target_ulong CP0_VPESchedule;
	192	target_ulong CP0_VPEScheFBack;
	193	int32_t CP0_VPEOpt;
	194	#define CP0VPEOpt_IWX7 15
	195	#define CP0VPEOpt_IWX6 14
	196	#define CP0VPEOpt_IWX5 13
	197	#define CP0VPEOpt_IWX4 12
	198	#define CP0VPEOpt_IWX3 11
	199	#define CP0VPEOpt_IWX2 10
	200	#define CP0VPEOpt_IWX1 9
	201	#define CP0VPEOpt_IWX0 8
	202	#define CP0VPEOpt_DWX7 7
	203	#define CP0VPEOpt_DWX6 6
	204	#define CP0VPEOpt_DWX5 5
	205	#define CP0VPEOpt_DWX4 4
	206	#define CP0VPEOpt_DWX3 3
	207	#define CP0VPEOpt_DWX2 2
	208	#define CP0VPEOpt_DWX1 1
	209	#define CP0VPEOpt_DWX0 0
9c2149c8	210	target_ulong CP0_EntryLo0;
ead9360e TS	211	int32_t CP0_TCStatus[MIPS_TC_MAX];
	212	#define CP0TCSt_TCU3 31
	213	#define CP0TCSt_TCU2 30
	214	#define CP0TCSt_TCU1 29
	215	#define CP0TCSt_TCU0 28
	216	#define CP0TCSt_TMX 27
	217	#define CP0TCSt_RNST 23
	218	#define CP0TCSt_TDS 21
	219	#define CP0TCSt_DT 20
	220	#define CP0TCSt_DA 15
	221	#define CP0TCSt_A 13
	222	#define CP0TCSt_TKSU 11
	223	#define CP0TCSt_IXMT 10
	224	#define CP0TCSt_TASID 0
	225	int32_t CP0_TCBind[MIPS_TC_MAX];
	226	#define CP0TCBd_CurTC 21
	227	#define CP0TCBd_TBE 17
	228	#define CP0TCBd_CurVPE 0
	229	target_ulong CP0_TCHalt[MIPS_TC_MAX];
	230	target_ulong CP0_TCContext[MIPS_TC_MAX];
	231	target_ulong CP0_TCSchedule[MIPS_TC_MAX];
	232	target_ulong CP0_TCScheFBack[MIPS_TC_MAX];
9c2149c8 TS	233	target_ulong CP0_EntryLo1;
	234	target_ulong CP0_Context;
	235	int32_t CP0_PageMask;
	236	int32_t CP0_PageGrain;
	237	int32_t CP0_Wired;
ead9360e TS	238	int32_t CP0_SRSConf0_rw_bitmask;
	239	int32_t CP0_SRSConf0;
	240	#define CP0SRSC0_M 31
	241	#define CP0SRSC0_SRS3 20
	242	#define CP0SRSC0_SRS2 10
	243	#define CP0SRSC0_SRS1 0
	244	int32_t CP0_SRSConf1_rw_bitmask;
	245	int32_t CP0_SRSConf1;
	246	#define CP0SRSC1_M 31
	247	#define CP0SRSC1_SRS6 20
	248	#define CP0SRSC1_SRS5 10
	249	#define CP0SRSC1_SRS4 0
	250	int32_t CP0_SRSConf2_rw_bitmask;
	251	int32_t CP0_SRSConf2;
	252	#define CP0SRSC2_M 31
	253	#define CP0SRSC2_SRS9 20
	254	#define CP0SRSC2_SRS8 10
	255	#define CP0SRSC2_SRS7 0
	256	int32_t CP0_SRSConf3_rw_bitmask;
	257	int32_t CP0_SRSConf3;
	258	#define CP0SRSC3_M 31
	259	#define CP0SRSC3_SRS12 20
	260	#define CP0SRSC3_SRS11 10
	261	#define CP0SRSC3_SRS10 0
	262	int32_t CP0_SRSConf4_rw_bitmask;
	263	int32_t CP0_SRSConf4;
	264	#define CP0SRSC4_SRS15 20
	265	#define CP0SRSC4_SRS14 10
	266	#define CP0SRSC4_SRS13 0
9c2149c8	267	int32_t CP0_HWREna;
c570fd16	268	target_ulong CP0_BadVAddr;
9c2149c8 TS	269	int32_t CP0_Count;
	270	target_ulong CP0_EntryHi;
	271	int32_t CP0_Compare;
	272	int32_t CP0_Status;
6af0bf9c FB	273	#define CP0St_CU3 31
	274	#define CP0St_CU2 30
	275	#define CP0St_CU1 29
	276	#define CP0St_CU0 28
	277	#define CP0St_RP 27
6ea83fed	278	#define CP0St_FR 26
6af0bf9c	279	#define CP0St_RE 25
7a387fff TS	280	#define CP0St_MX 24
7a387fff TS	281	#define CP0St_PX 23
6af0bf9c FB	282	#define CP0St_BEV 22
	283	#define CP0St_TS 21
	284	#define CP0St_SR 20
	285	#define CP0St_NMI 19
	286	#define CP0St_IM 8
7a387fff TS	287	#define CP0St_KX 7
	288	#define CP0St_SX 6
	289	#define CP0St_UX 5
623a930e	290	#define CP0St_KSU 3
6af0bf9c FB	291	#define CP0St_ERL 2
	292	#define CP0St_EXL 1
	293	#define CP0St_IE 0
9c2149c8	294	int32_t CP0_IntCtl;
ead9360e TS	295	#define CP0IntCtl_IPTI 29
	296	#define CP0IntCtl_IPPC1 26
	297	#define CP0IntCtl_VS 5
9c2149c8	298	int32_t CP0_SRSCtl;
ead9360e TS	299	#define CP0SRSCtl_HSS 26
	300	#define CP0SRSCtl_EICSS 18
	301	#define CP0SRSCtl_ESS 12
	302	#define CP0SRSCtl_PSS 6
	303	#define CP0SRSCtl_CSS 0
9c2149c8	304	int32_t CP0_SRSMap;
ead9360e TS	305	#define CP0SRSMap_SSV7 28
	306	#define CP0SRSMap_SSV6 24
	307	#define CP0SRSMap_SSV5 20
	308	#define CP0SRSMap_SSV4 16
	309	#define CP0SRSMap_SSV3 12
	310	#define CP0SRSMap_SSV2 8
	311	#define CP0SRSMap_SSV1 4
	312	#define CP0SRSMap_SSV0 0
9c2149c8	313	int32_t CP0_Cause;
7a387fff TS	314	#define CP0Ca_BD 31
	315	#define CP0Ca_TI 30
	316	#define CP0Ca_CE 28
	317	#define CP0Ca_DC 27
	318	#define CP0Ca_PCI 26
6af0bf9c	319	#define CP0Ca_IV 23
7a387fff TS	320	#define CP0Ca_WP 22
7a387fff TS	321	#define CP0Ca_IP 8
4de9b249	322	#define CP0Ca_IP_mask 0x0000FF00
7a387fff	323	#define CP0Ca_EC 2
c570fd16	324	target_ulong CP0_EPC;
9c2149c8	325	int32_t CP0_PRid;
b29a0341	326	int32_t CP0_EBase;
9c2149c8	327	int32_t CP0_Config0;
6af0bf9c FB	328	#define CP0C0_M 31
	329	#define CP0C0_K23 28
	330	#define CP0C0_KU 25
	331	#define CP0C0_MDU 20
	332	#define CP0C0_MM 17
	333	#define CP0C0_BM 16
	334	#define CP0C0_BE 15
	335	#define CP0C0_AT 13
	336	#define CP0C0_AR 10
	337	#define CP0C0_MT 7
7a387fff	338	#define CP0C0_VI 3
6af0bf9c	339	#define CP0C0_K0 0
9c2149c8	340	int32_t CP0_Config1;
7a387fff	341	#define CP0C1_M 31
6af0bf9c FB	342	#define CP0C1_MMU 25
	343	#define CP0C1_IS 22
	344	#define CP0C1_IL 19
	345	#define CP0C1_IA 16
	346	#define CP0C1_DS 13
	347	#define CP0C1_DL 10
	348	#define CP0C1_DA 7
7a387fff TS	349	#define CP0C1_C2 6
7a387fff TS	350	#define CP0C1_MD 5
6af0bf9c FB	351	#define CP0C1_PC 4
	352	#define CP0C1_WR 3
	353	#define CP0C1_CA 2
	354	#define CP0C1_EP 1
	355	#define CP0C1_FP 0
9c2149c8	356	int32_t CP0_Config2;
7a387fff TS	357	#define CP0C2_M 31
	358	#define CP0C2_TU 28
	359	#define CP0C2_TS 24
	360	#define CP0C2_TL 20
	361	#define CP0C2_TA 16
	362	#define CP0C2_SU 12
	363	#define CP0C2_SS 8
	364	#define CP0C2_SL 4
	365	#define CP0C2_SA 0
9c2149c8	366	int32_t CP0_Config3;
7a387fff TS	367	#define CP0C3_M 31
	368	#define CP0C3_DSPP 10
	369	#define CP0C3_LPA 7
	370	#define CP0C3_VEIC 6
	371	#define CP0C3_VInt 5
	372	#define CP0C3_SP 4
	373	#define CP0C3_MT 2
	374	#define CP0C3_SM 1
	375	#define CP0C3_TL 0
e397ee33 TS	376	int32_t CP0_Config6;
e397ee33 TS	377	int32_t CP0_Config7;
ead9360e	378	/* XXX: Maybe make LLAddr per-TC? */
c570fd16	379	target_ulong CP0_LLAddr;
fd88b6ab TS	380	target_ulong CP0_WatchLo[8];
fd88b6ab TS	381	int32_t CP0_WatchHi[8];
9c2149c8 TS	382	target_ulong CP0_XContext;
	383	int32_t CP0_Framemask;
	384	int32_t CP0_Debug;
ead9360e	385	#define CP0DB_DBD 31
6af0bf9c FB	386	#define CP0DB_DM 30
	387	#define CP0DB_LSNM 28
	388	#define CP0DB_Doze 27
	389	#define CP0DB_Halt 26
	390	#define CP0DB_CNT 25
	391	#define CP0DB_IBEP 24
	392	#define CP0DB_DBEP 21
	393	#define CP0DB_IEXI 20
	394	#define CP0DB_VER 15
	395	#define CP0DB_DEC 10
	396	#define CP0DB_SSt 8
	397	#define CP0DB_DINT 5
	398	#define CP0DB_DIB 4
	399	#define CP0DB_DDBS 3
	400	#define CP0DB_DDBL 2
	401	#define CP0DB_DBp 1
	402	#define CP0DB_DSS 0
ead9360e	403	int32_t CP0_Debug_tcstatus[MIPS_TC_MAX];
c570fd16	404	target_ulong CP0_DEPC;
9c2149c8 TS	405	int32_t CP0_Performance0;
	406	int32_t CP0_TagLo;
	407	int32_t CP0_DataLo;
	408	int32_t CP0_TagHi;
	409	int32_t CP0_DataHi;
c570fd16	410	target_ulong CP0_ErrorEPC;
9c2149c8	411	int32_t CP0_DESAVE;
6af0bf9c	412	/* Qemu */
6af0bf9c FB	413	int interrupt_request;
	414	jmp_buf jmp_env;
	415	int exception_index;
	416	int error_code;
	417	int user_mode_only; /* user mode only simulation */
	418	uint32_t hflags; /* CPU State */
	419	/* TMASK defines different execution modes */
b8aa4598	420	#define MIPS_HFLAG_TMASK 0x01FF
78749ba8	421	#define MIPS_HFLAG_MODE 0x0007 /* execution modes */
623a930e TS	422	/* The KSU flags must be the lowest bits in hflags. The flag order
	423	must be the same as defined for CP0 Status. This allows to use
	424	the bits as the value of mmu_idx. */
	425	#define MIPS_HFLAG_KSU 0x0003 /* kernel/supervisor/user mode mask */
	426	#define MIPS_HFLAG_UM 0x0002 /* user mode flag */
	427	#define MIPS_HFLAG_SM 0x0001 /* supervisor mode flag */
	428	#define MIPS_HFLAG_KM 0x0000 /* kernel mode flag */
	429	#define MIPS_HFLAG_DM 0x0004 /* Debug mode */
5e755519	430	#define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */
387a8fe5 TS	431	#define MIPS_HFLAG_CP0 0x0010 /* CP0 enabled */
	432	#define MIPS_HFLAG_FPU 0x0020 /* FPU enabled */
	433	#define MIPS_HFLAG_F64 0x0040 /* 64-bit FPU enabled */
b8aa4598 TS	434	/* True if the MIPS IV COP1X instructions can be used. This also
	435	controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
	436	and RSQRT.D. */
	437	#define MIPS_HFLAG_COP1X 0x0080 /* COP1X instructions enabled */
	438	#define MIPS_HFLAG_RE 0x0100 /* Reversed endianness */
4ad40f36 FB	439	/* If translation is interrupted between the branch instruction and
	440	* the delay slot, record what type of branch it is so that we can
	441	* resume translation properly. It might be possible to reduce
	442	* this from three bits to two. */
b8aa4598 TS	443	#define MIPS_HFLAG_BMASK 0x0e00
	444	#define MIPS_HFLAG_B 0x0200 /* Unconditional branch */
	445	#define MIPS_HFLAG_BC 0x0400 /* Conditional branch */
	446	#define MIPS_HFLAG_BL 0x0600 /* Likely branch */
	447	#define MIPS_HFLAG_BR 0x0800 /* branch to register (can't link TB) */
6af0bf9c FB	448	target_ulong btarget; /* Jump / branch target */
6af0bf9c FB	449	int bcond; /* Branch condition (if needed) */
a316d335	450
4ad40f36 FB	451	int halted; /* TRUE if the CPU is in suspend state */
4ad40f36 FB	452
7a387fff TS	453	int SYNCI_Step; /* Address step size for SYNCI */
7a387fff TS	454	int CCRes; /* Cycle count resolution/divisor */
ead9360e TS	455	uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
ead9360e TS	456	uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
e189e748	457	int insn_flags; /* Supported instruction set */
7a387fff	458
33ac7f16	459	#ifdef CONFIG_USER_ONLY
6f5b89a0 TS	460	target_ulong tls_value;
	461	#endif
	462
a316d335	463	CPU_COMMON
6ae81775	464
aaed909a	465	const mips_def_t *cpu_model;
33ac7f16 TS	466	#ifndef CONFIG_USER_ONLY
	467	void *irq[8];
	468	#endif
51b2772f	469
6ae81775	470	struct QEMUTimer timer; / Internal timer */
6af0bf9c FB	471	};
6af0bf9c FB	472
29929e34 TS	473	int no_mmu_map_address (CPUMIPSState env, target_ulong physical, int *prot,
	474	target_ulong address, int rw, int access_type);
	475	int fixed_mmu_map_address (CPUMIPSState env, target_ulong physical, int *prot,
	476	target_ulong address, int rw, int access_type);
	477	int r4k_map_address (CPUMIPSState env, target_ulong physical, int *prot,
	478	target_ulong address, int rw, int access_type);
	479	void r4k_do_tlbwi (void);
	480	void r4k_do_tlbwr (void);
	481	void r4k_do_tlbp (void);
	482	void r4k_do_tlbr (void);
33d68b5f	483	void mips_cpu_list (FILE f, int (cpu_fprintf)(FILE f, const char fmt, ...));
33d68b5f	484
647de6ca TS	485	void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
	486	int unused);
	487
9467d44c TS	488	#define CPUState CPUMIPSState
	489	#define cpu_init cpu_mips_init
	490	#define cpu_exec cpu_mips_exec
	491	#define cpu_gen_code cpu_mips_gen_code
	492	#define cpu_signal_handler cpu_mips_signal_handler
c732abe2	493	#define cpu_list mips_cpu_list
9467d44c	494
623a930e TS	495	/* MMU modes definitions. We carefully match the indices with our
623a930e TS	496	hflags layout. */
6ebbf390	497	#define MMU_MODE0_SUFFIX _kernel
623a930e TS	498	#define MMU_MODE1_SUFFIX _super
	499	#define MMU_MODE2_SUFFIX _user
	500	#define MMU_USER_IDX 2
6ebbf390 JM	501	static inline int cpu_mmu_index (CPUState *env)
6ebbf390 JM	502	{
623a930e	503	return env->hflags & MIPS_HFLAG_KSU;
6ebbf390 JM	504	}
6ebbf390 JM	505
6af0bf9c FB	506	#include "cpu-all.h"
	507
	508	/* Memory access type :
	509	* may be needed for precise access rights control and precise exceptions.
	510	*/
	511	enum {
	512	/* 1 bit to define user level / supervisor access */
	513	ACCESS_USER = 0x00,
	514	ACCESS_SUPER = 0x01,
	515	/* 1 bit to indicate direction */
	516	ACCESS_STORE = 0x02,
	517	/* Type of instruction that generated the access */
	518	ACCESS_CODE = 0x10, /* Code fetch access */
	519	ACCESS_INT = 0x20, /* Integer load/store access */
	520	ACCESS_FLOAT = 0x30, /* floating point load/store access */
	521	};
	522
	523	/* Exceptions */
	524	enum {
	525	EXCP_NONE = -1,
	526	EXCP_RESET = 0,
	527	EXCP_SRESET,
	528	EXCP_DSS,
	529	EXCP_DINT,
14e51cc7 TS	530	EXCP_DDBL,
14e51cc7 TS	531	EXCP_DDBS,
6af0bf9c FB	532	EXCP_NMI,
6af0bf9c FB	533	EXCP_MCHECK,
14e51cc7	534	EXCP_EXT_INTERRUPT, /* 8 */
6af0bf9c	535	EXCP_DFWATCH,
14e51cc7	536	EXCP_DIB,
6af0bf9c FB	537	EXCP_IWATCH,
	538	EXCP_AdEL,
	539	EXCP_AdES,
	540	EXCP_TLBF,
	541	EXCP_IBE,
14e51cc7	542	EXCP_DBp, /* 16 */
6af0bf9c	543	EXCP_SYSCALL,
14e51cc7	544	EXCP_BREAK,
4ad40f36	545	EXCP_CpU,
6af0bf9c FB	546	EXCP_RI,
	547	EXCP_OVERFLOW,
	548	EXCP_TRAP,
5a5012ec	549	EXCP_FPE,
14e51cc7	550	EXCP_DWATCH, /* 24 */
6af0bf9c FB	551	EXCP_LTLBL,
	552	EXCP_TLBL,
	553	EXCP_TLBS,
	554	EXCP_DBE,
ead9360e	555	EXCP_THREAD,
14e51cc7 TS	556	EXCP_MDMX,
	557	EXCP_C2E,
	558	EXCP_CACHE, /* 32 */
	559
	560	EXCP_LAST = EXCP_CACHE,
6af0bf9c FB	561	};
6af0bf9c FB	562
6af0bf9c	563	int cpu_mips_exec(CPUMIPSState *s);
aaed909a	564	CPUMIPSState cpu_mips_init(const char cpu_model);
6af0bf9c	565	uint32_t cpu_mips_get_clock (void);
388bb21a	566	int cpu_mips_signal_handler(int host_signum, void pinfo, void puc);
6af0bf9c FB	567
6af0bf9c FB	568	#endif /* !defined (__MIPS_CPU_H__) */