[qemu.git] / hw / i8254.c

/*
 * QEMU 8253/8254 interval timer emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "pc.h"
#include "isa.h"
#include "qemu-timer.h"

//#define DEBUG_PIT

#define RW_STATE_LSB 1
#define RW_STATE_MSB 2
#define RW_STATE_WORD0 3
#define RW_STATE_WORD1 4

typedef struct PITChannelState {
    int count; /* can be 65536 */
    uint16_t latched_count;
    uint8_t count_latched;
    uint8_t status_latched;
    uint8_t status;
    uint8_t read_state;
    uint8_t write_state;
    uint8_t write_latch;
    uint8_t rw_mode;
    uint8_t mode;
    uint8_t bcd; /* not supported */
    uint8_t gate; /* timer start */
    int64_t count_load_time;
    /* irq handling */
    int64_t next_transition_time;
    QEMUTimer *irq_timer;
    qemu_irq irq;
} PITChannelState;

struct PITState {
    PITChannelState channels[3];
};

static PITState pit_state;

static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);

static int pit_get_count(PITChannelState *s)
{
    uint64_t d;
    int counter;

    d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, ticks_per_sec);
    switch(s->mode) {
    case 0:
    case 1:
    case 4:
    case 5:
        counter = (s->count - d) & 0xffff;
        break;
    case 3:
        /* XXX: may be incorrect for odd counts */
        counter = s->count - ((2 * d) % s->count);
        break;
    default:
        counter = s->count - (d % s->count);
        break;
    }
    return counter;
}

/* get pit output bit */
static int pit_get_out1(PITChannelState *s, int64_t current_time)
{
    uint64_t d;
    int out;

    d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
    switch(s->mode) {
    default:
    case 0:
        out = (d >= s->count);
        break;
    case 1:
        out = (d < s->count);
        break;
    case 2:
        if ((d % s->count) == 0 && d != 0)
            out = 1;
        else
            out = 0;
        break;
    case 3:
        out = (d % s->count) < ((s->count + 1) >> 1);
        break;
    case 4:
    case 5:
        out = (d == s->count);
        break;
    }
    return out;
}

int pit_get_out(PITState *pit, int channel, int64_t current_time)
{
    PITChannelState *s = &pit->channels[channel];
    return pit_get_out1(s, current_time);
}

/* return -1 if no transition will occur.  */
static int64_t pit_get_next_transition_time(PITChannelState *s,
                                            int64_t current_time)
{
    uint64_t d, next_time, base;
    int period2;

    d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
    switch(s->mode) {
    default:
    case 0:
    case 1:
        if (d < s->count)
            next_time = s->count;
        else
            return -1;
        break;
    case 2:
        base = (d / s->count) * s->count;
        if ((d - base) == 0 && d != 0)
            next_time = base + s->count;
        else
            next_time = base + s->count + 1;
        break;
    case 3:
        base = (d / s->count) * s->count;
        period2 = ((s->count + 1) >> 1);
        if ((d - base) < period2)
            next_time = base + period2;
        else
            next_time = base + s->count;
        break;
    case 4:
    case 5:
        if (d < s->count)
            next_time = s->count;
        else if (d == s->count)
            next_time = s->count + 1;
        else
            return -1;
        break;
    }
    /* convert to timer units */
    next_time = s->count_load_time + muldiv64(next_time, ticks_per_sec, PIT_FREQ);
    /* fix potential rounding problems */
    /* XXX: better solution: use a clock at PIT_FREQ Hz */
    if (next_time <= current_time)
        next_time = current_time + 1;
    return next_time;
}

/* val must be 0 or 1 */
void pit_set_gate(PITState *pit, int channel, int val)
{
    PITChannelState *s = &pit->channels[channel];

    switch(s->mode) {
    default:
    case 0:
    case 4:
        /* XXX: just disable/enable counting */
        break;
    case 1:
    case 5:
        if (s->gate < val) {
            /* restart counting on rising edge */
            s->count_load_time = qemu_get_clock(vm_clock);
            pit_irq_timer_update(s, s->count_load_time);
        }
        break;
    case 2:
    case 3:
        if (s->gate < val) {
            /* restart counting on rising edge */
            s->count_load_time = qemu_get_clock(vm_clock);
            pit_irq_timer_update(s, s->count_load_time);
        }
        /* XXX: disable/enable counting */
        break;
    }
    s->gate = val;
}

int pit_get_gate(PITState *pit, int channel)
{
    PITChannelState *s = &pit->channels[channel];
    return s->gate;
}

int pit_get_initial_count(PITState *pit, int channel)
{
    PITChannelState *s = &pit->channels[channel];
    return s->count;
}

int pit_get_mode(PITState *pit, int channel)
{
    PITChannelState *s = &pit->channels[channel];
    return s->mode;
}

static inline void pit_load_count(PITChannelState *s, int val)
{
    if (val == 0)
        val = 0x10000;
    s->count_load_time = qemu_get_clock(vm_clock);
    s->count = val;
    pit_irq_timer_update(s, s->count_load_time);
}

/* if already latched, do not latch again */
static void pit_latch_count(PITChannelState *s)
{
    if (!s->count_latched) {
        s->latched_count = pit_get_count(s);
        s->count_latched = s->rw_mode;
    }
}

static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    PITState *pit = opaque;
    int channel, access;
    PITChannelState *s;

    addr &= 3;
    if (addr == 3) {
        channel = val >> 6;
        if (channel == 3) {
            /* read back command */
            for(channel = 0; channel < 3; channel++) {
                s = &pit->channels[channel];
                if (val & (2 << channel)) {
                    if (!(val & 0x20)) {
                        pit_latch_count(s);
                    }
                    if (!(val & 0x10) && !s->status_latched) {
                        /* status latch */
                        /* XXX: add BCD and null count */
                        s->status =  (pit_get_out1(s, qemu_get_clock(vm_clock)) << 7) |
                            (s->rw_mode << 4) |
                            (s->mode << 1) |
                            s->bcd;
                        s->status_latched = 1;
                    }
                }
            }
        } else {
            s = &pit->channels[channel];
            access = (val >> 4) & 3;
            if (access == 0) {
                pit_latch_count(s);
            } else {
                s->rw_mode = access;
                s->read_state = access;
                s->write_state = access;

                s->mode = (val >> 1) & 7;
                s->bcd = val & 1;
                /* XXX: update irq timer ? */
            }
        }
    } else {
        s = &pit->channels[addr];
        switch(s->write_state) {
        default:
        case RW_STATE_LSB:
            pit_load_count(s, val);
            break;
        case RW_STATE_MSB:
            pit_load_count(s, val << 8);
            break;
        case RW_STATE_WORD0:
            s->write_latch = val;
            s->write_state = RW_STATE_WORD1;
            break;
        case RW_STATE_WORD1:
            pit_load_count(s, s->write_latch | (val << 8));
            s->write_state = RW_STATE_WORD0;
            break;
        }
    }
}

static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
{
    PITState *pit = opaque;
    int ret, count;
    PITChannelState *s;

    addr &= 3;
    s = &pit->channels[addr];
    if (s->status_latched) {
        s->status_latched = 0;
        ret = s->status;
    } else if (s->count_latched) {
        switch(s->count_latched) {
        default:
        case RW_STATE_LSB:
            ret = s->latched_count & 0xff;
            s->count_latched = 0;
            break;
        case RW_STATE_MSB:
            ret = s->latched_count >> 8;
            s->count_latched = 0;
            break;
        case RW_STATE_WORD0:
            ret = s->latched_count & 0xff;
            s->count_latched = RW_STATE_MSB;
            break;
        }
    } else {
        switch(s->read_state) {
        default:
        case RW_STATE_LSB:
            count = pit_get_count(s);
            ret = count & 0xff;
            break;
        case RW_STATE_MSB:
            count = pit_get_count(s);
            ret = (count >> 8) & 0xff;
            break;
        case RW_STATE_WORD0:
            count = pit_get_count(s);
            ret = count & 0xff;
            s->read_state = RW_STATE_WORD1;
            break;
        case RW_STATE_WORD1:
            count = pit_get_count(s);
            ret = (count >> 8) & 0xff;
            s->read_state = RW_STATE_WORD0;
            break;
        }
    }
    return ret;
}

static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
{
    int64_t expire_time;
    int irq_level;

    if (!s->irq_timer)
        return;
    expire_time = pit_get_next_transition_time(s, current_time);
    irq_level = pit_get_out1(s, current_time);
    qemu_set_irq(s->irq, irq_level);
#ifdef DEBUG_PIT
    printf("irq_level=%d next_delay=%f\n",
           irq_level,
           (double)(expire_time - current_time) / ticks_per_sec);
#endif
    s->next_transition_time = expire_time;
    if (expire_time != -1)
        qemu_mod_timer(s->irq_timer, expire_time);
    else
        qemu_del_timer(s->irq_timer);
}

static void pit_irq_timer(void *opaque)
{
    PITChannelState *s = opaque;

    pit_irq_timer_update(s, s->next_transition_time);
}

static void pit_save(QEMUFile *f, void *opaque)
{
    PITState *pit = opaque;
    PITChannelState *s;
    int i;

    for(i = 0; i < 3; i++) {
        s = &pit->channels[i];
        qemu_put_be32s(f, &s->count);
        qemu_put_be16s(f, &s->latched_count);
        qemu_put_8s(f, &s->count_latched);
        qemu_put_8s(f, &s->status_latched);
        qemu_put_8s(f, &s->status);
        qemu_put_8s(f, &s->read_state);
        qemu_put_8s(f, &s->write_state);
        qemu_put_8s(f, &s->write_latch);
        qemu_put_8s(f, &s->rw_mode);
        qemu_put_8s(f, &s->mode);
        qemu_put_8s(f, &s->bcd);
        qemu_put_8s(f, &s->gate);
        qemu_put_be64s(f, &s->count_load_time);
        if (s->irq_timer) {
            qemu_put_be64s(f, &s->next_transition_time);
            qemu_put_timer(f, s->irq_timer);
        }
    }
}

static int pit_load(QEMUFile *f, void *opaque, int version_id)
{
    PITState *pit = opaque;
    PITChannelState *s;
    int i;

    if (version_id != 1)
        return -EINVAL;

    for(i = 0; i < 3; i++) {
        s = &pit->channels[i];
        qemu_get_be32s(f, &s->count);
        qemu_get_be16s(f, &s->latched_count);
        qemu_get_8s(f, &s->count_latched);
        qemu_get_8s(f, &s->status_latched);
        qemu_get_8s(f, &s->status);
        qemu_get_8s(f, &s->read_state);
        qemu_get_8s(f, &s->write_state);
        qemu_get_8s(f, &s->write_latch);
        qemu_get_8s(f, &s->rw_mode);
        qemu_get_8s(f, &s->mode);
        qemu_get_8s(f, &s->bcd);
        qemu_get_8s(f, &s->gate);
        qemu_get_be64s(f, &s->count_load_time);
        if (s->irq_timer) {
            qemu_get_be64s(f, &s->next_transition_time);
            qemu_get_timer(f, s->irq_timer);
        }
    }
    return 0;
}

static void pit_reset(void *opaque)
{
    PITState *pit = opaque;
    PITChannelState *s;
    int i;

    for(i = 0;i < 3; i++) {
        s = &pit->channels[i];
        s->mode = 3;
        s->gate = (i != 2);
        pit_load_count(s, 0);
    }
}

PITState *pit_init(int base, qemu_irq irq)
{
    PITState *pit = &pit_state;
    PITChannelState *s;

    s = &pit->channels[0];
    /* the timer 0 is connected to an IRQ */
    s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
    s->irq = irq;

    register_savevm("i8254", base, 1, pit_save, pit_load, pit);

    qemu_register_reset(pit_reset, pit);
    register_ioport_write(base, 4, 1, pit_ioport_write, pit);
    register_ioport_read(base, 3, 1, pit_ioport_read, pit);

    pit_reset(pit);

    return pit;
}
Commit	Line	Data
80cabfad FB	1	/*
80cabfad FB	2	* QEMU 8253/8254 interval timer emulation
5fafdf24	3	*
80cabfad	4	* Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24	5	*
80cabfad FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "pc.h"
	26	#include "isa.h"
	27	#include "qemu-timer.h"
80cabfad	28
b0a21b53 FB	29	//#define DEBUG_PIT
b0a21b53 FB	30
ec844b96 FB	31	#define RW_STATE_LSB 1
	32	#define RW_STATE_MSB 2
	33	#define RW_STATE_WORD0 3
	34	#define RW_STATE_WORD1 4
80cabfad	35
ec844b96 FB	36	typedef struct PITChannelState {
	37	int count; /* can be 65536 */
	38	uint16_t latched_count;
	39	uint8_t count_latched;
	40	uint8_t status_latched;
	41	uint8_t status;
	42	uint8_t read_state;
	43	uint8_t write_state;
	44	uint8_t write_latch;
	45	uint8_t rw_mode;
	46	uint8_t mode;
	47	uint8_t bcd; /* not supported */
	48	uint8_t gate; /* timer start */
	49	int64_t count_load_time;
	50	/* irq handling */
	51	int64_t next_transition_time;
	52	QEMUTimer *irq_timer;
d537cf6c	53	qemu_irq irq;
ec844b96 FB	54	} PITChannelState;
	55
	56	struct PITState {
	57	PITChannelState channels[3];
	58	};
	59
	60	static PITState pit_state;
80cabfad	61
b0a21b53 FB	62	static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
b0a21b53 FB	63
80cabfad FB	64	static int pit_get_count(PITChannelState *s)
	65	{
	66	uint64_t d;
	67	int counter;
	68
b0a21b53	69	d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, ticks_per_sec);
80cabfad FB	70	switch(s->mode) {
	71	case 0:
	72	case 1:
	73	case 4:
	74	case 5:
	75	counter = (s->count - d) & 0xffff;
	76	break;
	77	case 3:
	78	/* XXX: may be incorrect for odd counts */
	79	counter = s->count - ((2 * d) % s->count);
	80	break;
	81	default:
	82	counter = s->count - (d % s->count);
	83	break;
	84	}
	85	return counter;
	86	}
	87
	88	/* get pit output bit */
ec844b96	89	static int pit_get_out1(PITChannelState *s, int64_t current_time)
80cabfad FB	90	{
	91	uint64_t d;
	92	int out;
	93
b0a21b53	94	d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
80cabfad FB	95	switch(s->mode) {
	96	default:
	97	case 0:
	98	out = (d >= s->count);
	99	break;
	100	case 1:
	101	out = (d < s->count);
	102	break;
	103	case 2:
	104	if ((d % s->count) == 0 && d != 0)
	105	out = 1;
	106	else
	107	out = 0;
	108	break;
	109	case 3:
	110	out = (d % s->count) < ((s->count + 1) >> 1);
	111	break;
	112	case 4:
	113	case 5:
	114	out = (d == s->count);
	115	break;
	116	}
	117	return out;
	118	}
	119
ec844b96 FB	120	int pit_get_out(PITState *pit, int channel, int64_t current_time)
	121	{
	122	PITChannelState *s = &pit->channels[channel];
	123	return pit_get_out1(s, current_time);
	124	}
	125
b0a21b53	126	/* return -1 if no transition will occur. */
5fafdf24	127	static int64_t pit_get_next_transition_time(PITChannelState *s,
b0a21b53	128	int64_t current_time)
80cabfad	129	{
b0a21b53 FB	130	uint64_t d, next_time, base;
b0a21b53 FB	131	int period2;
80cabfad	132
b0a21b53	133	d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
80cabfad FB	134	switch(s->mode) {
	135	default:
	136	case 0:
80cabfad	137	case 1:
b0a21b53 FB	138	if (d < s->count)
	139	next_time = s->count;
	140	else
	141	return -1;
80cabfad FB	142	break;
80cabfad FB	143	case 2:
b0a21b53 FB	144	base = (d / s->count) * s->count;
	145	if ((d - base) == 0 && d != 0)
	146	next_time = base + s->count;
	147	else
	148	next_time = base + s->count + 1;
80cabfad FB	149	break;
80cabfad FB	150	case 3:
b0a21b53 FB	151	base = (d / s->count) * s->count;
b0a21b53 FB	152	period2 = ((s->count + 1) >> 1);
5fafdf24	153	if ((d - base) < period2)
b0a21b53 FB	154	next_time = base + period2;
	155	else
	156	next_time = base + s->count;
80cabfad FB	157	break;
	158	case 4:
	159	case 5:
b0a21b53 FB	160	if (d < s->count)
	161	next_time = s->count;
	162	else if (d == s->count)
	163	next_time = s->count + 1;
80cabfad	164	else
b0a21b53	165	return -1;
80cabfad FB	166	break;
80cabfad FB	167	}
b0a21b53 FB	168	/* convert to timer units */
b0a21b53 FB	169	next_time = s->count_load_time + muldiv64(next_time, ticks_per_sec, PIT_FREQ);
1154e441 FB	170	/* fix potential rounding problems */
	171	/* XXX: better solution: use a clock at PIT_FREQ Hz */
	172	if (next_time <= current_time)
	173	next_time = current_time + 1;
b0a21b53	174	return next_time;
80cabfad FB	175	}
	176
	177	/* val must be 0 or 1 */
ec844b96	178	void pit_set_gate(PITState *pit, int channel, int val)
80cabfad	179	{
ec844b96 FB	180	PITChannelState *s = &pit->channels[channel];
ec844b96 FB	181
80cabfad FB	182	switch(s->mode) {
	183	default:
	184	case 0:
	185	case 4:
	186	/* XXX: just disable/enable counting */
	187	break;
	188	case 1:
	189	case 5:
	190	if (s->gate < val) {
	191	/* restart counting on rising edge */
b0a21b53 FB	192	s->count_load_time = qemu_get_clock(vm_clock);
b0a21b53 FB	193	pit_irq_timer_update(s, s->count_load_time);
80cabfad FB	194	}
	195	break;
	196	case 2:
	197	case 3:
	198	if (s->gate < val) {
	199	/* restart counting on rising edge */
b0a21b53 FB	200	s->count_load_time = qemu_get_clock(vm_clock);
b0a21b53 FB	201	pit_irq_timer_update(s, s->count_load_time);
80cabfad FB	202	}
	203	/* XXX: disable/enable counting */
	204	break;
	205	}
	206	s->gate = val;
	207	}
	208
ec844b96 FB	209	int pit_get_gate(PITState *pit, int channel)
	210	{
	211	PITChannelState *s = &pit->channels[channel];
	212	return s->gate;
	213	}
	214
fd06c375 FB	215	int pit_get_initial_count(PITState *pit, int channel)
	216	{
	217	PITChannelState *s = &pit->channels[channel];
	218	return s->count;
	219	}
	220
	221	int pit_get_mode(PITState *pit, int channel)
	222	{
	223	PITChannelState *s = &pit->channels[channel];
	224	return s->mode;
	225	}
	226
80cabfad FB	227	static inline void pit_load_count(PITChannelState *s, int val)
	228	{
	229	if (val == 0)
	230	val = 0x10000;
b0a21b53	231	s->count_load_time = qemu_get_clock(vm_clock);
80cabfad	232	s->count = val;
b0a21b53	233	pit_irq_timer_update(s, s->count_load_time);
80cabfad FB	234	}
80cabfad FB	235
ec844b96 FB	236	/* if already latched, do not latch again */
	237	static void pit_latch_count(PITChannelState *s)
	238	{
	239	if (!s->count_latched) {
	240	s->latched_count = pit_get_count(s);
	241	s->count_latched = s->rw_mode;
	242	}
	243	}
	244
b41a2cd1	245	static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
80cabfad	246	{
ec844b96	247	PITState *pit = opaque;
80cabfad FB	248	int channel, access;
	249	PITChannelState *s;
	250
	251	addr &= 3;
	252	if (addr == 3) {
	253	channel = val >> 6;
ec844b96 FB	254	if (channel == 3) {
	255	/* read back command */
	256	for(channel = 0; channel < 3; channel++) {
	257	s = &pit->channels[channel];
	258	if (val & (2 << channel)) {
	259	if (!(val & 0x20)) {
	260	pit_latch_count(s);
	261	}
	262	if (!(val & 0x10) && !s->status_latched) {
	263	/* status latch */
	264	/* XXX: add BCD and null count */
	265	s->status = (pit_get_out1(s, qemu_get_clock(vm_clock)) << 7) \|
	266	(s->rw_mode << 4) \|
	267	(s->mode << 1) \|
	268	s->bcd;
	269	s->status_latched = 1;
	270	}
	271	}
	272	}
	273	} else {
	274	s = &pit->channels[channel];
	275	access = (val >> 4) & 3;
	276	if (access == 0) {
	277	pit_latch_count(s);
	278	} else {
	279	s->rw_mode = access;
	280	s->read_state = access;
	281	s->write_state = access;
	282
	283	s->mode = (val >> 1) & 7;
	284	s->bcd = val & 1;
	285	/* XXX: update irq timer ? */
	286	}
80cabfad FB	287	}
80cabfad FB	288	} else {
ec844b96 FB	289	s = &pit->channels[addr];
	290	switch(s->write_state) {
	291	default:
80cabfad FB	292	case RW_STATE_LSB:
	293	pit_load_count(s, val);
	294	break;
	295	case RW_STATE_MSB:
	296	pit_load_count(s, val << 8);
	297	break;
	298	case RW_STATE_WORD0:
ec844b96 FB	299	s->write_latch = val;
	300	s->write_state = RW_STATE_WORD1;
	301	break;
80cabfad	302	case RW_STATE_WORD1:
ec844b96 FB	303	pit_load_count(s, s->write_latch \| (val << 8));
ec844b96 FB	304	s->write_state = RW_STATE_WORD0;
80cabfad FB	305	break;
	306	}
	307	}
	308	}
	309
b41a2cd1	310	static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
80cabfad	311	{
ec844b96	312	PITState *pit = opaque;
80cabfad FB	313	int ret, count;
80cabfad FB	314	PITChannelState *s;
3b46e624	315
80cabfad	316	addr &= 3;
ec844b96 FB	317	s = &pit->channels[addr];
	318	if (s->status_latched) {
	319	s->status_latched = 0;
	320	ret = s->status;
	321	} else if (s->count_latched) {
	322	switch(s->count_latched) {
	323	default:
	324	case RW_STATE_LSB:
	325	ret = s->latched_count & 0xff;
	326	s->count_latched = 0;
	327	break;
	328	case RW_STATE_MSB:
80cabfad	329	ret = s->latched_count >> 8;
ec844b96 FB	330	s->count_latched = 0;
	331	break;
	332	case RW_STATE_WORD0:
80cabfad	333	ret = s->latched_count & 0xff;
ec844b96 FB	334	s->count_latched = RW_STATE_MSB;
	335	break;
	336	}
	337	} else {
	338	switch(s->read_state) {
	339	default:
	340	case RW_STATE_LSB:
	341	count = pit_get_count(s);
	342	ret = count & 0xff;
	343	break;
	344	case RW_STATE_MSB:
	345	count = pit_get_count(s);
	346	ret = (count >> 8) & 0xff;
	347	break;
	348	case RW_STATE_WORD0:
	349	count = pit_get_count(s);
	350	ret = count & 0xff;
	351	s->read_state = RW_STATE_WORD1;
	352	break;
	353	case RW_STATE_WORD1:
	354	count = pit_get_count(s);
	355	ret = (count >> 8) & 0xff;
	356	s->read_state = RW_STATE_WORD0;
	357	break;
	358	}
80cabfad FB	359	}
	360	return ret;
	361	}
	362
b0a21b53 FB	363	static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
	364	{
	365	int64_t expire_time;
	366	int irq_level;
	367
	368	if (!s->irq_timer)
	369	return;
	370	expire_time = pit_get_next_transition_time(s, current_time);
ec844b96	371	irq_level = pit_get_out1(s, current_time);
d537cf6c	372	qemu_set_irq(s->irq, irq_level);
b0a21b53 FB	373	#ifdef DEBUG_PIT
b0a21b53 FB	374	printf("irq_level=%d next_delay=%f\n",
5fafdf24	375	irq_level,
b0a21b53 FB	376	(double)(expire_time - current_time) / ticks_per_sec);
	377	#endif
	378	s->next_transition_time = expire_time;
	379	if (expire_time != -1)
	380	qemu_mod_timer(s->irq_timer, expire_time);
	381	else
	382	qemu_del_timer(s->irq_timer);
	383	}
	384
	385	static void pit_irq_timer(void *opaque)
	386	{
	387	PITChannelState *s = opaque;
	388
	389	pit_irq_timer_update(s, s->next_transition_time);
	390	}
	391
	392	static void pit_save(QEMUFile f, void opaque)
	393	{
ec844b96	394	PITState *pit = opaque;
b0a21b53 FB	395	PITChannelState *s;
b0a21b53 FB	396	int i;
3b46e624	397
b0a21b53	398	for(i = 0; i < 3; i++) {
ec844b96	399	s = &pit->channels[i];
b0a21b53 FB	400	qemu_put_be32s(f, &s->count);
b0a21b53 FB	401	qemu_put_be16s(f, &s->latched_count);
ec844b96 FB	402	qemu_put_8s(f, &s->count_latched);
	403	qemu_put_8s(f, &s->status_latched);
	404	qemu_put_8s(f, &s->status);
	405	qemu_put_8s(f, &s->read_state);
	406	qemu_put_8s(f, &s->write_state);
	407	qemu_put_8s(f, &s->write_latch);
	408	qemu_put_8s(f, &s->rw_mode);
b0a21b53 FB	409	qemu_put_8s(f, &s->mode);
	410	qemu_put_8s(f, &s->bcd);
	411	qemu_put_8s(f, &s->gate);
	412	qemu_put_be64s(f, &s->count_load_time);
	413	if (s->irq_timer) {
	414	qemu_put_be64s(f, &s->next_transition_time);
	415	qemu_put_timer(f, s->irq_timer);
	416	}
	417	}
	418	}
	419
	420	static int pit_load(QEMUFile f, void opaque, int version_id)
	421	{
ec844b96	422	PITState *pit = opaque;
b0a21b53 FB	423	PITChannelState *s;
b0a21b53 FB	424	int i;
3b46e624	425
b0a21b53 FB	426	if (version_id != 1)
	427	return -EINVAL;
	428
	429	for(i = 0; i < 3; i++) {
ec844b96	430	s = &pit->channels[i];
b0a21b53 FB	431	qemu_get_be32s(f, &s->count);
b0a21b53 FB	432	qemu_get_be16s(f, &s->latched_count);
ec844b96 FB	433	qemu_get_8s(f, &s->count_latched);
	434	qemu_get_8s(f, &s->status_latched);
	435	qemu_get_8s(f, &s->status);
	436	qemu_get_8s(f, &s->read_state);
	437	qemu_get_8s(f, &s->write_state);
	438	qemu_get_8s(f, &s->write_latch);
	439	qemu_get_8s(f, &s->rw_mode);
b0a21b53 FB	440	qemu_get_8s(f, &s->mode);
	441	qemu_get_8s(f, &s->bcd);
	442	qemu_get_8s(f, &s->gate);
	443	qemu_get_be64s(f, &s->count_load_time);
	444	if (s->irq_timer) {
	445	qemu_get_be64s(f, &s->next_transition_time);
	446	qemu_get_timer(f, s->irq_timer);
	447	}
	448	}
	449	return 0;
	450	}
	451
d7d02e3c	452	static void pit_reset(void *opaque)
80cabfad	453	{
d7d02e3c	454	PITState *pit = opaque;
80cabfad FB	455	PITChannelState *s;
	456	int i;
	457
	458	for(i = 0;i < 3; i++) {
ec844b96	459	s = &pit->channels[i];
80cabfad FB	460	s->mode = 3;
	461	s->gate = (i != 2);
	462	pit_load_count(s, 0);
	463	}
d7d02e3c FB	464	}
d7d02e3c FB	465
d537cf6c	466	PITState *pit_init(int base, qemu_irq irq)
d7d02e3c FB	467	{
	468	PITState *pit = &pit_state;
	469	PITChannelState *s;
	470
	471	s = &pit->channels[0];
	472	/* the timer 0 is connected to an IRQ */
	473	s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
	474	s->irq = irq;
80cabfad	475
ec844b96	476	register_savevm("i8254", base, 1, pit_save, pit_load, pit);
b0a21b53	477
d7d02e3c	478	qemu_register_reset(pit_reset, pit);
ec844b96 FB	479	register_ioport_write(base, 4, 1, pit_ioport_write, pit);
ec844b96 FB	480	register_ioport_read(base, 3, 1, pit_ioport_read, pit);
d7d02e3c FB	481
	482	pit_reset(pit);
	483
ec844b96	484	return pit;
80cabfad	485	}